MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 * * 2 * * * * Low Supply Voltage Range: 1.8 V to 3.6 V Ultralow Power Consumption - Active Mode (AM): All System Clocks Active: 270 A/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical) - Standby Mode (LPM3): Watchdog With Crystal, and Supply Supervisor Operational, Full RAM Retention, Fast Wake-Up: 1.8 A at 2.2 V, 2.1 A at 3.0 V (Typical) - Shutdown RTC Mode (LPM3.5): Shutdown Mode, Active Real-Time Clock With Crystal: 1.1 A at 3.0 V (Typical) - Shutdown Mode (LPM4.5): 0.3 A at 3.0 V (Typical) Wake-Up From Standby Mode in 3 s (Typical) 16-Bit RISC Architecture, Extended Memory, up to 20-MHz System Clock Flexible Power Management System - Fully Integrated LDO With Programmable Regulated Core Supply Voltage - Supply Voltage Supervision, Monitoring, and Brownout Unified Clock System - FLL Control Loop for Frequency Stabilization - Low-Power Low-Frequency Internal Clock Source (VLO) - Low-Frequency Trimmed Internal Reference Source (REFO) - 32-kHz Crystals (XT1) - High-Frequency Crystals Up to 32 MHz (XT2) * * * * * * * * * * * * * Four 16-Bit Timer With 3, 5, or 7 Capture/Compare Registers Two Universal Serial Communication Interfaces - USCI_A0 and USCI_A1 Each Support: - Enhanced UART Supports AutoBaudrate Detection - IrDA Encoder and Decoder - Synchronous SPI - USCI_B0 and USCI_B1 Each Support: - I2CTM - Synchronous SPI Full-Speed Universal Serial Bus (USB) - Integrated USB-PHY - Integrated 3.3-V and 1.8-V USB Power System - Integrated USB-PLL - Eight Input and Eight Output Endpoints 12-Bit Analog-to-Digital (A/D) Converter With Internal Shared Reference, Sample-and-Hold, and Autoscan Feature Dual 12-Bit Digital-to-Analog (D/A) Converters With Synchronization Voltage Comparator Integrated LCD Driver With Contrast Control for up to 160 Segments Hardware Multiplier Supporting 32-Bit Operations Serial Onboard Programming, No External Programming Voltage Needed Six-Channel Internal DMA Real-Time Clock Module With Supply Voltage Backup Switch Family Members are Summarized in Table 1 For Complete Module Descriptions, See the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com DESCRIPTION The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3 s (typical). The MSP430F663x series are microcontroller configurations with a high performance 12-bit analog-to-digital (A/D) converter, comparator, two universal serial communication interfaces (USCI), USB 2.0, hardware multiplier, DMA, four 16-bit timers, real-time clock module with alarm capabilities, LCD driver, and up to 74 I/O pins. Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, hand-held meters, etc. Family members available are summarized in Table 1. Table 1. Family Members USCI Device Flash (KB) SRAM (KB) (1) Channel A: UART, IrDA, SPI Timer_A Channel B: SPI, I2C ADC12_A (Ch) DAC12_A (Ch) Comp_B (Ch) I/O Package Type MSP430F6638 256 16 + 2 5, 3, 3 7 2 2 12 ext, 4 int 2 12 74 100 PZ, 113 ZQW MSP430F6637 192 16 + 2 5, 3, 3 7 2 2 12 ext, 4 int 2 12 74 100 PZ, 113 ZQW MSP430F6636 128 16 + 2 5, 3, 3 7 2 2 12 ext, 4 int 2 12 74 100 PZ, 113 ZQW MSP430F6635 256 16 + 2 5, 3, 3 7 2 2 12 ext, 4 int - 12 74 100 PZ, 113 ZQW MSP430F6634 192 16 + 2 5, 3, 3 7 2 2 12 ext, 4 int - 12 74 100 PZ, 113 ZQW MSP430F6633 128 16 + 2 5, 3, 3 7 2 2 12 ext, 4 int - 12 74 100 PZ, 113 ZQW MSP430F6632 256 16 + 2 5, 3, 3 7 2 2 - - 12 74 100 PZ, 113 ZQW MSP430F6631 192 16 + 2 5, 3, 3 7 2 2 - - 12 74 100 PZ, 113 ZQW MSP430F6630 128 16 + 2 5, 3, 3 7 2 2 - - 12 74 100 PZ, 113 ZQW (1) (2) (3) 2 (2) Timer_B (3) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use. Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 2. Ordering Information (1) TA PACKAGED DEVICES (2) PLASTIC 100-PIN TQFP (PZ) PLASTIC 113-BALL BGA (ZQW) MSP430F6638IPZ MSP430F6638IZQW MSP430F6637IPZ MSP430F6637IZQW MSP430F6636IPZ MSP430F6636IZQW MSP430F6635IPZ MSP430F6635IZQW MSP430F6634IPZ MSP430F6634IZQW MSP430F6633IPZ MSP430F6633IZQW MSP430F6632IPZ MSP430F6632IZQW MSP430F6631IPZ MSP430F6631IZQW MSP430F6630IPZ MSP430F6630IZQW -40C to 85C (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/package. Copyright (c) 2010-2012, Texas Instruments Incorporated 3 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Functional Block Diagram, MSP430F6638, MSP430F6637, MSP430F6636 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1.x XT2IN XT2OUT Unified Clock System 16KB RAM ACLK SMCLK 256KB 192KB 128KB Flash MCLK Power Management SYS Watchdog +2KB RAM USB Buffer +8B Backup RAM LDO SVM/SVS Brownout P2 Port Mapping Controller PA P2.x P3.x PB P4.x P5.x PC P6.x I/O Ports P1/P2 2x8 I/Os Interrupt Capability I/O Ports P3/P4 2x8 I/Os Interrupt Capability I/O Ports P5/P6 2x8 I/Os PA 1x16 I/Os PB 1x16 I/Os PC 1x16 I/Os P7.x PD P8.x I/O Ports P7/P8 1x6 I/Os 1x8 I/Os PD 1x14 I/Os P9.x I/O Ports P9 1x8 I/Os PE 1x8 I/Os USCI0,1 Ax: UART, IrDA, SPI USB Full-speed Bx: SPI, I2C CPUXV2 and Working Registers EEM (L: 8+2) DMA TA0 JTAG/ SBW Interface/ MPY32 Port PJ Timer_A 5 CC Registers PJ.x TA1 and TA2 2 Timer_A each with 3 CC Registers ADC12_A RTC_B TB0 Timer_B 7 CC Registers CRC16 Comp_B Battery Backup System 12 Bit 200 KSPS 16 Channels (12 ext/4 int) Autoscan LCD_B DAC12_A REF 12 bit 2 channels voltage out Reference 1.5V, 2.0V, 2.5V 6 Channel 160 Segments Functional Block Diagram, MSP430F6635, MSP430F6634, MSP430F6633 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1.x XT2IN XT2OUT Unified Clock System MCLK ACLK SMCLK 256KB 192KB 128KB Flash 16KB RAM Power Management +2KB RAM USB Buffer +8B Backup RAM SYS Watchdog LDO SVM/SVS Brownout P2 Port Mapping Controller PA P2.x P3.x PB P4.x P5.x PC P6.x I/O Ports P1/P2 2x8 I/Os Interrupt Capability I/O Ports P3/P4 2x8 I/Os Interrupt Capability I/O Ports P5/P6 2x8 I/Os PA 1x16 I/Os PB 1x16 I/Os PC 1x16 I/Os P7.x PD P8.x I/O Ports P7/P8 1x6 I/Os 1x8 I/Os PD 1x14 I/Os P9.x I/O Ports P9 1x8 I/Os PE 1x8 I/Os USCI0,1 Ax: UART, IrDA, SPI USB Full-speed Bx: SPI, I2C CPUXV2 and Working Registers EEM (L: 8+2) JTAG/ SBW Interface/ Port PJ PJ.x 4 DMA TA0 MPY32 Timer_A 5 CC Registers TA1 and TA2 2 Timer_A each with 3 CC Registers ADC12_A LCD_B RTC_B TB0 Timer_B 7 CC Registers CRC16 Battery Backup System Comp_B 12 Bit 200 KSPS 16 Channels (12 ext/4 int) Autoscan REF Reference 1.5V, 2.0V, 2.5V 6 Channel 160 Segments Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Functional Block Diagram, MSP430F6632, MSP430F6631, MSP430F6630 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1.x XT2IN XT2OUT Unified Clock System MCLK ACLK SMCLK 256KB 192KB 128KB Flash 16KB RAM Power Management +2KB RAM USB Buffer +8B Backup RAM SYS Watchdog LDO SVM/SVS Brownout P2 Port Mapping Controller PA P2.x P3.x PB P4.x P5.x PC P6.x I/O Ports P1/P2 2x8 I/Os Interrupt Capability I/O Ports P3/P4 2x8 I/Os Interrupt Capability I/O Ports P5/P6 2x8 I/Os PA 1x16 I/Os PB 1x16 I/Os PC 1x16 I/Os P7.x PD P8.x I/O Ports P7/P8 1x6 I/Os 1x8 I/Os PD 1x14 I/Os P9.x I/O Ports P9 1x8 I/Os PE 1x8 I/Os USCI0,1 Ax: UART, IrDA, SPI USB Full-speed Bx: SPI, I2C CPUXV2 and Working Registers EEM (L: 8+2) JTAG/ SBW Interface/ Port PJ PJ.x DMA TA0 MPY32 Timer_A 5 CC Registers TA1 and TA2 2 Timer_A each with 3 CC Registers Copyright (c) 2010-2012, Texas Instruments Incorporated LCD_B RTC_B REF TB0 Timer_B 7 CC Registers CRC16 Battery Backup System Comp_B Reference 1.5V, 2.0V, 2.5V 6 Channel 160 Segments 5 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MSP430F6638 MSP430F6637 MSP430F6636 PZ PACKAGE (TOP VIEW) P9.7/S0 P9.6/S1 P9.5/S2 P9.4/S3 P9.3/S4 P9.2/S5 P9.1/S6 P9.0/S7 P8.7/S8 P8.6/UCB1SOMI/UCB1SCL/S9 P8.5/UCB1SIMO/UCB1SDA/S10 DVCC2 DVSS2 P8.4/UCB1CLK/UCA1STE/S11 P8.3/UCA1RXD/UCA1SOMI/S12 P8.2/UCA1TXD/UCA1SIMO/S13 P8.1/UCB1STE/UCA1CLK/S14 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P4.6/TB0.6/S17 P4.5/TB0.5/S18 P4.4/TB0.4/S19 P4.3/TB0.3/S20 P4.2/TB0.2/S21 P4.1/TB0.1/S22 P5.2/R23 LCDCAP/R33 COM0 P5.3/COM1/S42 P5.4/COM2/S41 P5.5/COM3/S40 P1.0/TA0CLK/ACLK/S39 P1.1/TA0.0/S38 P1.2/TA0.1/S37 P1.3/TA0.2/S36 P1.4/TA0.3/S35 P1.5/TA0.4/S34 P1.6/TA0.1/S33 P1.7/TA0.2/S32 P3.0/TA1CLK/CBOUT/S31 P3.1/TA1.0/S30 P3.2/TA1.1/S29 P3.3/TA1.2/S28 P3.4/TA2CLK/SMCLK/S27 P3.5/TA2.0/S26 P3.6/TA2.1/S25 P3.7/TA2.2/S24 P4.0/TB0.0/S23 DVSS1 VCORE 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1 P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14/DAC0 P7.7/CB11/A15/DAC1 P5.0/VREF+/VeREF+ P5.1/VREF-/VeREF- AVCC1 AVSS1 XIN XOUT AVSS2 P5.6/ADC12CLK/DMAE0 P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6/R03 P2.7/P2MAP7/LCDREF/R13 DVCC1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P6.3/CB3/A3 P6.2/CB2/A2 P6.1/CB1/A1 P6.0/CB0/A0 RST/NMI/SBWTDIO PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCK DVSS3 DVCC3 P5.7/RTCCLK VBAT VBAK P7.3/XT2OUT P7.2/XT2IN AVSS3 V18 VUSB VBUS PU.1/DM PUR PU.0/DP VSSU Pin Designation, MSP430F6638IPZ, MSP430F6637IPZ, MSP430F6636IPZ CAUTION: LCDCAP/R33 must be connected to DVSS if not used. 6 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MSP430F6635 MSP430F6634 MSP430F6633 PZ PACKAGE (TOP VIEW) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P9.7/S0 P9.6/S1 P9.5/S2 P9.4/S3 P9.3/S4 P9.2/S5 P9.1/S6 P9.0/S7 P8.7/S8 P8.6/UCB1SOMI/UCB1SCL/S9 P8.5/UCB1SIMO/UCB1SDA/S10 DVCC2 DVSS2 P8.4/UCB1CLK/UCA1STE/S11 P8.3/UCA1RXD/UCA1SOMI/S12 P8.2/UCA1TXD/UCA1SIMO/S13 P8.1/UCB1STE/UCA1CLK/S14 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P4.6/TB0.6/S17 P4.5/TB0.5/S18 P4.4/TB0.4/S19 P4.3/TB0.3/S20 P4.2/TB0.2/S21 P4.1/TB0.1/S22 P5.2/R23 LCDCAP/R33 COM0 P5.3/COM1/S42 P5.4/COM2/S41 P5.5/COM3/S40 P1.0/TA0CLK/ACLK/S39 P1.1/TA0.0/S38 P1.2/TA0.1/S37 P1.3/TA0.2/S36 P1.4/TA0.3/S35 P1.5/TA0.4/S34 P1.6/TA0.1/S33 P1.7/TA0.2/S32 P3.0/TA1CLK/CBOUT/S31 P3.1/TA1.0/S30 P3.2/TA1.1/S29 P3.3/TA1.2/S28 P3.4/TA2CLK/SMCLK/S27 P3.5/TA2.0/S26 P3.6/TA2.1/S25 P3.7/TA2.2/S24 P4.0/TB0.0/S23 DVSS1 VCORE 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6 P6.7/CB7/A7 P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14 P7.7/CB11/A15 P5.0/VREF+/VeREF+ P5.1/VREF-/VeREF- AVCC1 AVSS1 XIN XOUT AVSS2 P5.6/ADC12CLK/DMAE0 P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6/R03 P2.7/P2MAP7/LCDREF/R13 DVCC1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P6.3/CB3/A3 P6.2/CB2/A2 P6.1/CB1/A1 P6.0/CB0/A0 RST/NMI/SBWTDIO PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCK DVSS3 DVCC3 P5.7/RTCCLK VBAT VBAK P7.3/XT2OUT P7.2/XT2IN AVSS3 V18 VUSB VBUS PU.1/DM PUR PU.0/DP VSSU Pin Designation, MSP430F6635IPZ, MSP430F6634IPZ, MSP430F6633IPZ CAUTION: LCDCAP/R33 must be connected to DVSS if not used. Copyright (c) 2010-2012, Texas Instruments Incorporated 7 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MSP430F6632 MSP430F6631 MSP430F6630 PZ PACKAGE (TOP VIEW) P9.7/S0 P9.6/S1 P9.5/S2 P9.4/S3 P9.3/S4 P9.2/S5 P9.1/S6 P9.0/S7 P8.7/S8 P8.6/UCB1SOMI/UCB1SCL/S9 P8.5/UCB1SIMO/UCB1SDA/S10 DVCC2 DVSS2 P8.4/UCB1CLK/UCA1STE/S11 P8.3/UCA1RXD/UCA1SOMI/S12 P8.2/UCA1TXD/UCA1SIMO/S13 P8.1/UCB1STE/UCA1CLK/S14 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P4.6/TB0.6/S17 P4.5/TB0.5/S18 P4.4/TB0.4/S19 P4.3/TB0.3/S20 P4.2/TB0.2/S21 P4.1/TB0.1/S22 P5.2/R23 LCDCAP/R33 COM0 P5.3/COM1/S42 P5.4/COM2/S41 P5.5/COM3/S40 P1.0/TA0CLK/ACLK/S39 P1.1/TA0.0/S38 P1.2/TA0.1/S37 P1.3/TA0.2/S36 P1.4/TA0.3/S35 P1.5/TA0.4/S34 P1.6/TA0.1/S33 P1.7/TA0.2/S32 P3.0/TA1CLK/CBOUT/S31 P3.1/TA1.0/S30 P3.2/TA1.1/S29 P3.3/TA1.2/S28 P3.4/TA2CLK/SMCLK/S27 P3.5/TA2.0/S26 P3.6/TA2.1/S25 P3.7/TA2.2/S24 P4.0/TB0.0/S23 DVSS1 VCORE 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P6.4/CB4 P6.5/CB5 P6.6/CB6 P6.7/CB7 P7.4/CB8 P7.5/CB9 P7.6/CB10 P7.7/CB11 P5.0/VREF+/VeREF+ P5.1/VREF-/VeREF- AVCC1 AVSS1 XIN XOUT AVSS2 P5.6/DMAE0 P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6/R03 P2.7/P2MAP7/LCDREF/R13 DVCC1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P6.3/CB3 P6.2/CB2 P6.1/CB1 P6.0/CB0 RST/NMI/SBWTDIO PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCK DVSS3 DVCC3 P5.7/RTCCLK VBAT VBAK P7.3/XT2OUT P7.2/XT2IN AVSS3 V18 VUSB VBUS PU.1/DM PUR PU.0/DP VSSU Pin Designation, MSP430F6632IPZ, MSP430F6631IPZ, MSP430F6630IPZ CAUTION: LCDCAP/R33 must be connected to DVSS if not used. 8 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Pin Designation, MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW, MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW, MSP430F6631IZQW, MSP430F6630IZQW ZQW PACKAGE (TOP VIEW) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C11 C12 D1 D2 D4 D5 D6 D7 D8 D9 D11 D12 E1 E2 E4 E5 E6 E7 E8 E9 E11 E12 F1 F2 F4 F5 F8 F9 F11 F12 G1 G2 G4 G5 G8 G9 G11 G12 H1 H2 H4 H5 H6 H7 H8 H9 H11 H12 J1 J2 J4 J5 J6 J7 J8 J9 J11 J12 K1 K2 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 NOTE: For terminal assignments, see Table 3 Copyright (c) 2010-2012, Texas Instruments Incorporated 9 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 3. Terminal Functions TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P6.4/CB4/A4 1 A1 I/O General-purpose digital I/O Comparator_B input CB4 Analog input A4 - ADC(not available on F6632, F6631, F6630 devices) P6.5/CB5/A5 2 B2 I/O General-purpose digital I/O Comparator_B input CB5 Analog input A5 - ADC(not available on F6632, F6631, F6630 devices) I/O General-purpose digital I/O Comparator_B input CB6 Analog input A6 - ADC (not available on F6632, F6631, F6630 devices) DAC12.0 output (not available on F6635, F6634, F6633, F6632, F6631, F6630 devices) P6.6/CB6/A6/DAC0 3 B1 P6.7/CB7/A7/DAC1 4 C2 I/O General-purpose digital I/O Comparator_B input CB7 Analog input A7 - ADC (not available on F6632, F6631, F6630 devices) DAC12.1 output (not available on F6635, F6634, F6633, F6632, F6631, F6630 devices) P7.4/CB8/A12 5 C1 I/O General-purpose digital I/O Comparator_B input CB8 Analog input A12 -ADC (not available on F6632, F6631, F6630 devices) P7.5/CB9/A13 6 C3 I/O General-purpose digital I/O Comparator_B input CB9 Analog input A13 - ADC (not available on F6632, F6631, F6630 devices) I/O General-purpose digital I/O Comparator_B input CB10 Analog input A14 - ADC (not available on F6632, F6631, F6630 devices) DAC12.0 output (not available on F6635, F6634, F6633, F6632, F6631, F6630 devices) P7.6/CB10/A14/DAC0 7 D2 P7.7/CB11/A15/DAC1 8 D1 I/O General-purpose digital I/O Comparator_B input CB11 Analog input A15 - ADC (not available on F6632, F6631, F6630 devices) DAC12.1 output (not available on F6635, F6634, F6633, F6632, F6631, F6630 devices) P5.0/VREF+/VeREF+ 9 D4 I/O General-purpose digital I/O Output of reference voltage to the ADC Input for an external reference voltage to the ADC P5.1/VREF-/VeREF- 10 E4 I/O General-purpose digital I/O Negative terminal for the ADC's reference voltage for both sources, the internal reference voltage, or an external applied reference voltage AVCC1 11 E1, E2 AVSS1 12 F2 XIN 13 F1 I Input terminal for crystal oscillator XT1 XOUT 14 G1 O Output terminal of crystal oscillator XT1 AVSS2 15 G2 (1) 10 Analog power supply Analog ground supply Analog ground supply I = input, O = output, N/A = not available on this package offering Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P5.6/ADC12CLK/DMAE0 16 H1 I/O General-purpose digital I/O Conversion clock output ADC (not available on F6632, F6631, F6630 devices) DMA external trigger input P2.0/P2MAP0 17 G4 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output P2.1/P2MAP1 18 H2 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data P2.2/P2MAP2 19 J1 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock P2.3/P2MAP3 20 H4 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable P2.4/P2MAP4 21 J2 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out P2.5/P2MAP5 22 K1 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in P2.6/P2MAP6/R03 23 K2 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: no secondary function Input/output port of lowest analog LCD voltage (V5) I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: no secondary function External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) P2.7/P2MAP7/LCDREF/R13 24 DVCC1 25 L1 Digital power supply DVSS1 26 M1 Digital ground supply VCORE (2) 27 M2 Regulated core power supply (internal use only, no external current loading) P5.2/R23 28 L3 I/O General-purpose digital I/O Input/output port of second most positive analog LCD voltage (V2) LCDCAP/R33 29 M3 I/O LCD capacitor connection Input/output port of most positive analog LCD voltage (V1) CAUTION: LCDCAP/R33 must be connected to DVSS if not used. COM0 30 J4 O LCD common output COM0 for LCD backplane P5.3/COM1/S42 31 L4 I/O General-purpose digital I/O LCD common output COM1 for LCD backplane LCD segment output S42 P5.4/COM2/S41 32 M4 I/O General-purpose digital I/O LCD common output COM2 for LCD backplane LCD segment output S41 P5.5/COM3/S40 33 J5 I/O General-purpose digital I/O LCD common output COM3 for LCD backplane LCD segment output S40 (2) L2 VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. Copyright (c) 2010-2012, Texas Instruments Incorporated 11 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME P1.0/TA0CLK/ACLK/S39 P1.1/TA0.0/S38 I/O (1) NO. PZ 34 35 DESCRIPTION ZQW L5 M5 I/O General-purpose digital I/O with port interrupt Timer TA0 clock signal TACLK input ACLK output (divided by 1, 2, 4, 8, 16, or 32) LCD segment output S39 I/O General-purpose digital I/O with port interrupt Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output LCD segment output S38 P1.2/TA0.1/S37 36 J6 I/O General-purpose digital I/O with port interrupt Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output BSL receive input LCD segment output S37 P1.3/TA0.2/S36 37 H6 I/O General-purpose digital I/O with port interrupt Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output LCD segment output S36 P1.4/TA0.3/S35 38 M6 I/O General-purpose digital I/O with port interrupt Timer TA0 CCR3 capture: CCI3A input compare: Out3 output LCD segment output S35 P1.5/TA0.4/S34 39 L6 I/O General-purpose digital I/O with port interrupt Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output LCD segment output S34 P1.6/TA0.1/S33 40 J7 I/O General-purpose digital I/O with port interrupt Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output LCD segment output S33 P1.7/TA0.2/S32 41 M7 I/O General-purpose digital I/O with port interrupt Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output LCD segment output S32 P3.0/TA1CLK/CBOUT/S31 42 L7 I/O General-purpose digital I/O with port interrupt Timer TA1 clock input Comparator_B output LCD segment output S31 P3.1/TA1.0/S30 43 H7 I/O General-purpose digital I/O with port interrupt Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S30 P3.2/TA1.1/S29 44 M8 I/O General-purpose digital I/O with port interrupt Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S29 P3.3/TA1.2/S28 45 L8 I/O General-purpose digital I/O with port interrupt Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S28 I/O General-purpose digital I/O with port interrupt Timer TA2 clock input SMCLK output LCD segment output S27 P3.4/TA2CLK/SMCLK/S27 12 46 J8 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P3.5/TA2.0/S26 47 M9 I/O General-purpose digital I/O with port interrupt Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S26 P3.6/TA2.1/S25 48 L9 I/O General-purpose digital I/O with port interrupt Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S25 P3.7/TA2.2/S24 49 M10 I/O General-purpose digital I/O with port interrupt Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S24 P4.0/TB0.0/S23 50 J9 I/O General-purpose digital I/O with port interrupt Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S23 P4.1/TB0.1/S22 51 M11 I/O General-purpose digital I/O with port interrupt Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S22 P4.2/TB0.2/S21 52 L10 I/O General-purpose digital I/O with port interrupt Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S21 P4.3/TB0.3/S20 53 M12 I/O General-purpose digital I/O with port interrupt Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output LCD segment output S20 P4.4/TB0.4/S19 54 L12 I/O General-purpose digital I/O with port interrupt Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output LCD segment output S19 P4.5/TB0.5/S18 55 L11 I/O General-purpose digital I/O with port interrupt Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output LCD segment output S18 P4.6/TB0.6/S17 56 K11 I/O General-purpose digital I/O with port interrupt Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output LCD segment output S17 P4.7/TB0OUTH/SVMOUT/S16 57 K12 I/O General-purpose digital I/O with port interrupt Timer TB0: Switch all PWM outputs high impedance SVM output LCD segment output S16 P8.0/TB0CLK/S15 58 J11 I/O General-purpose digital I/O Timer TB0 clock input LCD segment output S15 P8.1/UCB1STE/UCA1CLK/S14 59 J12 I/O General-purpose digital I/O USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output LCD segment output S14 P8.2/UCA1TXD/UCA1SIMO/S13 60 H11 I/O General-purpose digital I/O USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out LCD segment output S13 Copyright (c) 2010-2012, Texas Instruments Incorporated 13 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P8.3/UCA1RXD/UCA1SOMI/S12 61 H12 I/O General-purpose digital I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in LCD segment output S12 P8.4/UCB1CLK/UCA1STE/S11 62 G11 I/O General-purpose digital I/O USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable LCD segment output S11 DVSS2 63 G12 Digital ground supply DVCC2 64 F12 Digital power supply P8.5/UCB1SIMO/UCB1SDA/S10 65 F11 I/O General-purpose digital I/O USCI_B1 SPI slave in/master out; USCI_B1 I2C data LCD segment output S10 P8.6/UCB1SOMI/UCB1SCL/S9 66 G9 I/O General-purpose digital I/O USCI_B1 SPI slave out/master in; USCI_B1 I2C clock LCD segment output S9 P8.7/S8 67 E12 I/O General-purpose digital I/O LCD segment output S8 P9.0/S7 68 E11 I/O General-purpose digital I/O LCD segment output S7 P9.1/S6 69 F9 I/O General-purpose digital I/O LCD segment output S6 P9.2/S5 70 D12 I/O General-purpose digital I/O LCD segment output S5 P9.3/S4 71 D11 I/O General-purpose digital I/O LCD segment output S4 P9.4/S3 72 E9 I/O General-purpose digital I/O LCD segment output S3 P9.5/S2 73 C12 I/O General-purpose digital I/O LCD segment output S2 P9.6/S1 74 C11 I/O General-purpose digital I/O LCD segment output S1 P9.7/S0 75 D9 I/O General-purpose digital I/O LCD segment output S0 VSSU 76 B11 and B12 PU.0/DP 77 A12 I/O General-purpose digital I/O - controlled by USB control register USB data terminal DP PUR 78 B10 I/O USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to invoke the default USB BSL. Recommended 1-M resistor to ground. See USB BSL for more information. PU.1/DM 79 A11 I/O General-purpose digital I/O - controlled by USB control register USB data terminal DM VBUS 80 A10 USB LDO input (connect to USB power source) VUSB 81 A9 USB LDO output V18 82 B9 USB regulated power (internal use only, no external current loading) 14 USB PHY ground supply Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW AVSS3 83 A8 P7.2/XT2IN 84 B8 I/O General-purpose digital I/O Input terminal for crystal oscillator XT2 P7.3/XT2OUT 85 B7 I/O General-purpose digital I/O Output terminal of crystal oscillator XT2 VBAK 86 A7 Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Recommended Operating Conditions. VBAT 87 D8 Backup or secondary supply voltage. If backup voltage is not supplied, connect to DVCC externally. P5.7/RTCCLK 88 D7 DVCC3 89 A6 Digital power supply DVSS3 90 A5 Digital ground supply TEST/SBWTCK 91 B6 I PJ.0/TDO 92 B5 I/O General-purpose digital I/O Test data output port PJ.1/TDI/TCLK 93 A4 I/O General-purpose digital I/O Test data input or test clock input PJ.2/TMS 94 E7 I/O General-purpose digital I/O Test mode select PJ.3/TCK 95 D6 I/O General-purpose digital I/O Test clock RST/NMI/SBWTDIO 96 A3 I/O Reset input (active low) Non-maskable interrupt input Spy-bi-wire data input/output P6.0/CB0/A0 97 B4 I/O General-purpose digital I/O Comparator_B input CB0 Analog input A0 - ADC (not available on F6632, F6631, F6630 devices) P6.1/CB1/A1 98 B3 I/O General-purpose digital I/O Comparator_B input CB1 Analog input A1 - ADC (not available on F6632, F6631, F6630 devices) P6.2/CB2/A2 99 A2 I/O General-purpose digital I/O Comparator_B input CB2 Analog input A2 - ADC (not available on F6632, F6631, F6630 devices) P6.3/CB3/A3 100 D5 I/O General-purpose digital I/O Comparator_B input CB3 Analog input A3 - ADC (not available on F6632, F6631, F6630 devices) Copyright (c) 2010-2012, Texas Instruments Incorporated Analog ground supply I/O General-purpose digital I/O RTCCLK output Test mode pin; selects digital I/O on JTAG pins Spy-bi-wire input clock 15 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME Reserved 16 NO. PZ ZQW N/A E5, E6, E8, F4, F5, F8, G5, G8, H5, H8, H9 I/O (1) DESCRIPTION Reserved. It is recommended to connect to ground (DVSS, AVSS). Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. General-Purpose Register R10 General-Purpose Register R11 Instruction Set General-Purpose Register R12 The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 4 shows examples of the three types of instruction formats; Table 5 shows the address modes. General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Table 4. Instruction Word Formats INSTRUCTION WORD FORMAT EXAMPLE Dual operands, source-destination ADD Single operands, destination only R4 + R5 R5 R8 PC (TOS), R8 PC CALL Relative jump, un/conditional OPERATION R4,R5 JNE Jump-on-equal bit = 0 Table 5. Address Mode Descriptions (1) ADDRESS MODE S (1) D (1) Register + + MOV Rs,Rd MOV R10,R11 R10 R11 Indexed + + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) M(6+R6) Symbolic (PC relative) + + MOV EDE,TONI Absolute + + MOV &MEM, &TCDAT Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) M(Tab+R6) Indirect auto-increment + MOV @Rn+,Rm MOV @R10+,R11 M(R10) R11 R10 + 2 R10 Immediate + MOV #X,TONI MOV #45,TONI #45 M(TONI) SYNTAX EXAMPLE OPERATION M(EDE) M(TONI) M(MEM) M(TCDAT) S = source, D = destination Copyright (c) 2010-2012, Texas Instruments Incorporated 17 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Operating Modes The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following seven operating modes can be configured by software: * Active mode (AM) - All clocks are active * Low-power mode 0 (LPM0) - CPU is disabled - ACLK and SMCLK remain active, MCLK is disabled - FLL loop control remains active * Low-power mode 1 (LPM1) - CPU is disabled - FLL loop control is disabled - ACLK and SMCLK remain active, MCLK is disabled * Low-power mode 2 (LPM2) - CPU is disabled - MCLK, FLL loop control, and DCOCLK are disabled - DCO's dc generator remains enabled - ACLK remains active * Low-power mode 3 (LPM3) - CPU is disabled - MCLK, FLL loop control, and DCOCLK are disabled - DCO's dc generator is disabled - ACLK remains active * Low-power mode 4 (LPM4) - CPU is disabled - ACLK is disabled - MCLK, FLL loop control, and DCOCLK are disabled - DCO's dc generator is disabled - Crystal oscillator is stopped - Complete data retention * Low-power mode 3.5 (LPM3.5) - Internal regulator disabled - No data retention - RTC enabled and clocked by low-frequency oscillator - Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4 * Low-power mode 4.5 (LPM4.5) - Internal regulator disabled - No data retention - Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4 18 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY System Reset Power-Up, External Reset Watchdog Timeout, Key Violation Flash Memory Key Violation WDTIFG, KEYV (SYSRSTIV) (1) (2) Reset 0FFFEh 63, highest System NMI PMM Vacant Memory Access JTAG Mailbox SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV) (1) (Non)maskable 0FFFCh 62 User NMI NMI Oscillator Fault Flash Memory Access Violation NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV) (1) (2) (Non)maskable 0FFFAh 61 Comp_B Comparator B interrupt flags (CBIV) (1) (3) Maskable 0FFF8h 60 Timer TB0 Maskable 0FFF6h 59 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6, TB0IFG (TBIV) (1) (3) Maskable 0FFF4h 58 Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57 USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3) Maskable 0FFF0h 56 USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (3) Maskable 0FFEEh 55 ADC12_A (4) ADC12IFG0 to ADC12IFG15 (ADC12IV) (1) (3) Maskable 0FFECh 54 Timer TB0 TB0CCR0 CCIFG0 Timer TA0 TA0CCR0 CCIFG0 Maskable 0FFEAh 53 Timer TA0 Maskable 0FFE8h 52 USB_UBM USB interrupts (USBIV) (1) (3) Maskable 0FFE6h 51 DMA DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG, DMA5IFG (DMAIV) (1) (3) Maskable 0FFE4h 50 Timer TA1 TA1CCR0 CCIFG0 (3) Maskable 0FFE2h 49 Timer TA1 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV) (1) (3) Maskable 0FFE0h 48 P1IFG.0 to P1IFG.7 (P1IV) (1) (3) Maskable 0FFDEh 47 USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3) Maskable 0FFDCh 46 USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3) Maskable 0FFDAh 45 Maskable 0FFD8h 44 I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV) (1) (3) LCD_B LCD_B Interrupt Flags (LCDBIV) (1) Maskable 0FFD6h 43 RTC_B RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV) (1) (3) Maskable 0FFD4h 42 DAC12_A (5) DAC12_0IFG, DAC12_1IFG (1) (3) Maskable 0FFD2h 41 Timer TA2 (3) (4) (5) (3) TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV) (1) (3) I/O Port P1 (1) (2) (3) TA2CCR0 CCIFG0 (3) Maskable 0FFD0h 40 Timer TA2 TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2, TA2IFG (TA2IV) (1) (3) Maskable 0FFCEh 39 I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV) (1) (3) Maskable 0FFCCh 38 I/O Port P4 (1) (3) Maskable 0FFCAh 37 P4IFG.0 to P4IFG.7 (P4IV) Multiple source flags A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. Interrupt flags are located in the module. Only on devices with peripheral module ADC12_A, otherwise reserved. Only on devices with peripheral module DAC12_A, otherwise reserved. Copyright (c) 2010-2012, Texas Instruments Incorporated 19 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 6. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations (continued) (6) INTERRUPT SOURCE INTERRUPT FLAG Reserved Reserved (6) SYSTEM INTERRUPT WORD ADDRESS PRIORITY 0FFC8h 36 0FF80h 0, lowest Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatability with other devices, it is recommended to reserve these locations. Memory Organization Table 7. Memory Organization (1) (2) Memory (flash) Main: interrupt vector Main: code memory RAM USB RAM (3) Information memory (flash) Bootstrap loader (BSL) memory (flash) Peripherals (1) (2) (3) 20 MSP430F6636 MSP430F6633 MSP430F6630 MSP430F6637 MSP430F6634 MSP430F6631 MSP430F6638 MSP430F6635 MSP430F6632 128KB 00FFFFh-00FF80h 192KB 00FFFFh-00FF80h 256KB 00FFFFh-00FF80h Bank 3 N/A N/A 64 KB 047FFF-038000h Bank 2 N/A 64 KB 037FFF-028000h 64 KB 037FFF-028000h Bank 1 64 KB 027FFF-018000h 64 KB 027FFF-018000h 64 KB 027FFF-018000h Bank 0 64 KB 017FFF-008000h 64 KB 017FFF-008000h 64 KB 017FFF-008000h Sector 3 4 KB 0063FFh-005400h 4 KB 0063FFh-005400h 4 KB 0063FFh-005400h Sector 2 4 KB 0053FFh-004400h 4 KB 0053FFh-004400h 4 KB 0053FFh-004400h Sector 1 4 KB 0043FFh-003400h 4 KB 0043FFh-003400h 4 KB 0043FFh-003400h Sector 0 4 KB 0033FFh-002400h 4 KB 0033FFh-002400h 4 KB 0033FFh-002400h Size RAM 2KB 0023FFh-001C00h 2KB 0023FFh-001C00h 2KB 0023FFh-001C00h Info A 128 B 0019FFh-001980h 128 B 0019FFh-001980h 128 B 0019FFh-001980h Info B 128 B 00197Fh-001900h 128 B 00197Fh-001900h 128 B 00197Fh-001900h Info C 128 B 0018FFh-001880h 128 B 0018FFh-001880h 128 B 0018FFh-001880h Info D 128 B 00187Fh-001800h 128 B 00187Fh-001800h 128 B 00187Fh-001800h BSL 3 512 B 0017FFh-001600h 512 B 0017FFh-001600h 512 B 0017FFh-001600h BSL 2 512 B 0015FFh-001400h 512 B 0015FFh-001400h 512 B 0015FFh-001400h BSL 1 512 B 0013FFh-001200h 512 B 0013FFh-001200h 512 B 0013FFh-001200h BSL 0 512 B 0011FFh-001000h 512 B 0011FFh-001000h 512 B 0011FFh-001000h Size 4KB 000FFFh-000000h 4KB 000FFFh-000000h 4KB 000FFFh-000000h Total Size N/A = Not available. Backup RAM is accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. USB RAM can be used as general purpose RAM when not used for USB operation. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the device memory via the BSL is protected by an user-defined password. For complete description of the features of the BSL and its implementation, see MSP430 Programming Via the Bootstrap Loader (BSL) (SLAU319). USB BSL All devices come pre-programmed with the USB BSL. Use of the USB BSL requires external access to the six pins shown in Table 8. In addition to these pins, the application must support external components necessary for normal USB operation; for example, the proper crystal on XT2IN and XT2OUT or proper decoupling. Table 8. USB BSL Pin Requirements and Functions DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entry sequence signal PU.0/DP USB data terminal DP PU.1/DM USB data terminal DM PUR USB pullup resistor terminal VBUS USB bus power supply VSSU USB ground supply NOTE The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is pulled high externally, then the BSL is invoked. Therefore, unless the application is invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. Applying a 1-M resistor to ground is recommended. UART BSL A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the preprogrammed, factory supplied, USB BSL. Use of the UART BSL requires external access to the six pins shown in Table 9. Table 9. UART BSL Pin Requirements and Functions DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entry sequence signal TEST/SBWTCK Entry sequence signal P1.1 Data transmit P1.2 Data receive VCC Power supply VSS Ground supply JTAG Operation JTAG Standard Interface The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 10. For further details on interfacing to development tools and device programmers, see the MSP430(tm) Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320). Copyright (c) 2010-2012, Texas Instruments Incorporated 21 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 10. JTAG Pin Requirements and Functions DEVICE SIGNAL DIRECTION FUNCTION PJ.3/TCK IN JTAG clock input PJ.2/TMS IN JTAG state control PJ.1/TDI/TCLK IN JTAG data input, TCLK input PJ.0/TDO OUT JTAG data output TEST/SBWTCK IN Enable JTAG pins RST/NMI/SBWTDIO IN External reset VCC Power supply VSS Ground supply Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 11. For further details on interfacing to development tools and device programmers, see the MSP430(tm) Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320). Table 11. Spy-Bi-Wire Pin Requirements and Functions DEVICE SIGNAL DIRECTION FUNCTION TEST/SBWTCK IN Spy-Bi-Wire clock input RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output VCC Power supply VSS Ground supply Flash Memory The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: * Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size. * Segments 0 to n may be erased in one step, or each segment may be individually erased. * Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. * Segment A can be locked separately. RAM Memory The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage, however all data is lost. Features of the RAM memory include: * RAM memory has n sectors. The size of a sector can be found in Memory Organization. * Each sector 0 to n can be complete disabled, however data retention is lost. * Each sector 0 to n automatically enters low power retention mode when possible. * For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required. Backup RAM Memory The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during operation from a backup supply if the Battery Backup System module is implemented. There are 8 bytes of Backup RAM available on MSP430F663x. It can be wordwise accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. 22 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Digital I/O There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete, and port PJ contains four individual I/O ports. * All individual I/O bits are independently programmable. * Any combination of input, output, and interrupt conditions is possible. * Programmable pullup or pulldown on all ports. * Programmable drive strength on all ports. * Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4. * Read/write access to port-control registers is supported by all instructions. * Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD). Port Mapping Controller The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2. Table 12. Port Mapping, Mnemonics and Functions VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION 0 PM_NONE None DVSS Comparator_B output 1 2 PM_CBOUT - PM_TB0CLK Timer TB0 clock input - PM_ADC12CLK - ADC12CLK PM_DMAE0 DMAE0 Input - PM_SVMOUT - SVM output PM_TB0OUTH Timer TB0 high impedance input TB0OUTH - 4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0 5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1 6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2 7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3 8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4 9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5 10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6 3 11 12 13 14 15 16 PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input) PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI) PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output) PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI) PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI) PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input) PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI) PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI) PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI) PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI) PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI) PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input) 17 PM_MCLK - 18 Reserved Reserved for test purposes. Do not use this setting. Copyright (c) 2010-2012, Texas Instruments Incorporated MCLK 23 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 12. Port Mapping, Mnemonics and Functions (continued) VALUE PxMAPy MNEMONIC 19 Reserved 20-30 31 (0FFh) (1) INPUT PIN FUNCTION Reserved (1) OUTPUT PIN FUNCTION Reserved for test purposes. Do not use this setting. None DVSS Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals. PM_ANALOG The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored, which results in a read out value of 31. Table 13. Default Mapping PIN PxMAPy MNEMONIC P2.0/P2MAP0 PM_UCB0STE, PM_UCA0CLK USCI_B0 SPI slave transmit enable (direction controlled by USCI - input), USCI_A0 clock input/output (direction controlled by USCI) P2.1/P2MAP1 PM_UCB0SIMO, PM_UCB0SDA USCI_B0 SPI slave in master out (direction controlled by USCI), USCI_B0 I2C data (open drain and direction controlled by USCI) P2.2/P2MAP2 PM_UCB0SOMI, PM_UCB0SCL USCI_B0 SPI slave out master in (direction controlled by USCI), USCI_B0 I2C clock (open drain and direction controlled by USCI) P2.3/P2MAP3 PM_UCB0CLK, PM_UCA0STE USCI_B0 clock input/output (direction controlled by USCI), USCI_A0 SPI slave transmit enable (direction controlled by USCI - input) P2.4/P2MAP4 PM_UCA0TXD, PM_UCA0SIMO USCI_A0 UART TXD (direction controlled by USCI - output), USCI_A0 SPI slave in master out (direction controlled by USCI) P2.5/P2MAP5 PM_UCA0RXD, PM_UCA0SOMI USCI_A0 UART RXD (direction controlled by USCI - input), USCI_A0 SPI slave out master in (direction controlled by USCI) P2.6/P2MAP6/R03 PM_NONE - DVSS P2.7/P2MAP7/LCDREF/R13 PM_NONE - DVSS INPUT PIN FUNCTION OUTPUT PIN FUNCTION Oscillator and System Clock The clock system in the MSP430F663x family of devices is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in 3 s (typical). The UCS module provides the following clock signals: * Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitallycontrolled oscillator DCO. * Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to ACLK. * Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources available to ACLK. * ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32. Power Management Module (PMM) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply. 24 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. Real-Time Clock (RTC_B) The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes, hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in LPM3.5 mode and operation from a backup supply. Watchdog Timer (WDT_A) The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. System Module (SYS) The SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap loader entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange mechanism via JTAG called a JTAG mailbox that can be used in the application. Table 14. System Module Interrupt Vector Registers INTERRUPT VECTOR REGISTER INTERRUPT EVENT WORD ADDRESS OFFSET No interrupt pending 00h Brownout (BOR) 02h RST/NMI (BOR) 04h DoBOR (BOR) 06h LPM3.5 or LPM4.5 wakeup (BOR) 08h Security violation (BOR) 0Ah SVSL (POR) 0Ch SVSH (POR) 0Eh SVML_OVP (POR) SYSRSTIV, System Reset SVMH_OVP (POR) 019Eh Highest 10h 12h DoPOR (POR) 14h WDT timeout (PUC) 16h WDT key violation (PUC) 18h KEYV flash key violation (PUC) 1Ah Reserved 1Ch Peripheral area fetch (PUC) 1Eh PMM key violation (PUC) 20h Reserved 22h to 3Eh Copyright (c) 2010-2012, Texas Instruments Incorporated PRIORITY Lowest 25 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 14. System Module Interrupt Vector Registers (continued) INTERRUPT VECTOR REGISTER INTERRUPT EVENT WORD ADDRESS No interrupt pending 00h SVMLIFG 02h SVMHIFG 04h DLYLIFG 06h DLYHIFG SYSSNIV, System NMI SYSUNIV, User NMI SYSBERRIV, Bus Error VMAIFG 0Ch 0Eh SVMLVLRIFG 10h SVMHVLRIFG 12h Reserved 14h to 1Eh No interrupt pending 00h NMIFG 02h OFIFG 019Ah Highest 06h 08h Reserved 0Ah to 1Eh No interrupt pending 00h 0198h Lowest 04h BUSIFG USB wait state timeout Highest 0Ah JMBINIFG ACCVIFG PRIORITY 08h 019Ch JMBOUTIFG Reserved 26 OFFSET Lowest 02h Highest 04h to 1Eh Lowest Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments described in Table 15. Table 15. DMA Trigger Assignments (1) Trigger Channel 0 1 DMAREQ 1 TA0CCR0 CCIFG 2 TA0CCR2 CCIFG 3 TA1CCR0 CCIFG 4 TA1CCR2 CCIFG 5 TA2CCR0 CCIFG 6 TA2CCR2 CCIFG 7 TBCCR0 CCIFG 8 TBCCR2 CCIFG 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 UCA0RXIFG 17 UCA0TXIFG 18 UCB0RXIFG 19 UCB0TXIFG 20 UCA1RXIFG 21 UCA1TXIFG 22 UCB1RXIFG 23 UCB1TXIFG 24 ADC12IFGx (2) 25 DAC12_0IFG (3) 26 DAC12_1IFG (3) 27 USB FNRXD 28 USB ready 29 MPY ready DMA5IFG DMA0IFG 31 (2) (3) 3 0 30 (1) 2 DMA1IFG DMA2IFG 4 5 DMA3IFG DMA4IFG DMAE0 Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not cause any DMA trigger event when selected. Only on devices with peripheral module ADC12_A. Reserved on devices without ADC. Only on devices with peripheral module DAC12_A. Reserved on devices without DAC. Copyright (c) 2010-2012, Texas Instruments Incorporated 27 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Universal Serial Communication Interface (USCI) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions, A and B. The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C. The MSP430F663x series includes two complete USCI modules (n = 0 to 1). Timer TA0 Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 16. Timer TA0 Signal Connections INPUT PIN NUMBER PZ ZQW DEVICE INPUT SIGNAL 34-P1.0 L5-P1.0 TA0CLK ACLK SMCLK SMCLK L5-P1.0 TA0CLK TACLK 35-P1.1 M5-P1.1 TA0.0 CCI0A DVSS CCI0B DVSS GND MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 TA0 OUTPUT PIN NUMBER PZ ZQW 35-P1.1 M5-P1.1 TA0.0 DVCC VCC 36-P1.2 J6-P1.2 TA0.1 CCI1A 36-P1.2 J6-P1.2 40-P1.6 J7-P1.6 TA0.1 CCI1B 40-P1.6 J7-P1.6 DVSS GND DVCC VCC CCR1 TA1 TA0.1 ADC12_A (internal) (1) ADC12SHSx = {1} 37-P1.3 H6-P1.3 TA0.2 CCI2A 37-P1.3 H6-P1.3 41-P1.7 M7-P1.7 TA0.2 CCI2B 41-P1.7 M7-P1.7 DVSS GND DVCC VCC TA0.3 CCI3A 38-P1.4 M6-P1.4 DVSS CCI3B DVSS GND 39-P1.5 L6-P1.5 39-P1.5 28 TACLK ACLK 34-P1.0 38-P1.4 (1) MODULE INPUT SIGNAL M6-P1.4 L6-P1.5 DVCC VCC TA0.4 CCI4A DVSS CCI4B DVSS GND DVCC VCC CCR2 CCR3 CCR4 TA2 TA3 TA4 TA0.2 TA0.3 TA0.4 Only on devices with peripheral module ADC12_A. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Timer TA1 Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 17. Timer TA1 Signal Connections INPUT PIN NUMBER PZ ZQW DEVICE INPUT SIGNAL 42-P3.0 L7-P3.0 TA1CLK TACLK ACLK ACLK SMCLK SMCLK 42-P3.0 L7-P3.0 TA1CLK TACLK 43-P3.1 H7-P3.1 TA1.0 CCI0A DVSS CCI0B DVSS GND 44-P3.2 45-P3.3 (1) MODULE INPUT SIGNAL M8-P3.2 L8-P3.3 DVCC VCC TA1.1 CCI1A CBOUT (internal) CCI1B DVSS GND DVCC VCC TA1.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 CCR1 TA0 TA1 OUTPUT PIN NUMBER PZ ZQW 43-P3.1 H7-P3.1 44-P3.2 M8-P3.2 TA1.0 TA1.1 DAC12_A (1) DAC12_0, DAC12_1 (internal) 45-P3.3 CCR2 TA2 L8-P3.3 TA1.2 Only on devices with peripheral module DAC12_A. Copyright (c) 2010-2012, Texas Instruments Incorporated 29 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Timer TA2 Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 18. Timer TA2 Signal Connections INPUT PIN NUMBER PZ ZQW DEVICE INPUT SIGNAL 46-P3.4 J8-P3.4 TA2CLK TACLK ACLK ACLK SMCLK SMCLK 46-P3.4 J8-P3.4 TA2CLK TACLK 47-P3.5 M9-P3.5 TA2.0 CCI0A DVSS CCI0B DVSS GND 48-P3.6 49-P3.7 30 MODULE INPUT SIGNAL L9-P3.6 M10-P3.7 DVCC VCC TA2.1 CCI1A CBOUT (internal) CCI1B DVSS GND DVCC VCC TA2.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA CCR0 CCR1 CCR2 TA0 TA1 TA2 OUTPUT PIN NUMBER PZ ZQW 47-P3.5 M9-P3.5 48-P3.6 L9-P3.6 49-P3.7 M10-P3.7 TA2.0 TA2.1 TA2.2 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Timer TB0 Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 19. Timer TB0 Signal Connections INPUT PIN NUMBER PZ ZQW 58-P8.0 P2MAPx (1) J11-P8.0 P2MAPx (1) DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TB0CLK TB0CLK MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer NA NA OUTPUT PIN NUMBER PZ ZQW ACLK ACLK SMCLK SMCLK J11-P8.0 P2MAPx (1) TB0CLK TB0CLK 50-P4.0 J9-P4.0 TB0.0 CCI0A 50-P4.0 J9-P4.0 P2MAPx (1) P2MAPx (1) TB0.0 CCI0B P2MAPx (1) P2MAPx (1) DVSS GND 58-P8.0 P2MAPx (1) CCR0 TB0 TB0.0 ADC12 (internal) (2) ADC12SHSx = {2} DVCC VCC 51-P4.1 M11-P4.1 TB0.1 CCI1A 51-P4.1 M11-P4.1 P2MAPx (1) P2MAPx (1) TB0.1 CCI1B P2MAPx (1) P2MAPx (1) DVSS GND DVCC VCC CCR1 TB1 TB0.1 ADC12 (internal) (2) ADC12SHSx = {3} 52-P4.2 L10-P4.2 TB0.2 CCI2A 52-P4.2 L10-P4.2 P2MAPx (1) P2MAPx (1) TB0.2 CCI2B P2MAPx (1) P2MAPx (1) DVSS GND 53-P4.3 P2MAPx (1) 54-P4.4 P2MAPx (1) M12-P4.3 P2MAPx (1) L12-P4.4 P2MAPx (1) DVCC VCC TB0.3 CCI3A TB0.3 CCI3B DVSS GND DVCC VCC TB0.4 CCI4A TB0.4 CCI4B DVSS GND DVCC VCC CCR2 TB2 TB0.2 DAC12_A (3) DAC12_0, DAC12_1 (internal) 53-P4.3 CCR3 TB3 TB0.3 P2MAPx (1) 54-P4.4 CCR4 TB4 TB0.4 P2MAPx (1) M12-P4.3 P2MAPx (1) L12-P4.4 P2MAPx (1) 55-P4.5 L11-P4.5 TB0.5 CCI5A 55-P4.5 L11-P4.5 P2MAPx (1) P2MAPx (1) TB0.5 CCI5B P2MAPx (1) P2MAPx (1) DVSS GND CCR5 TB5 TB0.5 DVCC VCC 56-P4.6 K11-P4.6 TB0.6 CCI6A 56-P4.6 K11-P4.6 P2MAPx (1) P2MAPx (1) TB0.6 CCI6B P2MAPx (1) P2MAPx (1) DVSS GND DVCC VCC (1) (2) (3) CCR6 TB6 TB0.6 Timer functions selectable via the port mapping controller. Only on devices with peripheral module ADC12_A. Only on devices with peripheral module DAC12_A. Copyright (c) 2010-2012, Texas Instruments Incorporated 31 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Comparator_B The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC12_A The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. DAC12_A The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules are present, they may be grouped together for synchronous operation. CRC16 The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. REF Voltage Reference The reference module (REF) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. LCD_B The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by software. The module also provides an automatic blinking capability for individual segments. USB Universal Serial Bus The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO, PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock frequencies. USB RAM, when not used for USB communication, can be used by the system. Embedded Emulation Module (EEM) The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM implemented on these devices has the following features: * Eight hardware triggers/breakpoints on memory access * Two hardware triggers/breakpoints on CPU register write access * Up to ten hardware triggers can be combined to form complex triggers/breakpoints * Two cycle counters * Sequencer * State storage * Clock control on module level 32 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Peripheral File Map Table 20. Peripherals (1) MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE (1) Special Functions (see Table 21) 0100h 000h - 01Fh PMM (see Table 22) 0120h 000h - 00Fh Flash Control (see Table 23) 0140h 000h - 00Fh CRC16 (see Table 24) 0150h 000h - 007h RAM Control (see Table 25) 0158h 000h - 001h Watchdog (see Table 26) 015Ch 000h - 001h UCS (see Table 27) 0160h 000h - 01Fh SYS (see Table 28) 0180h 000h - 01Fh Shared Reference (see Table 29) 01B0h 000h - 001h Port Mapping Control (see Table 30) 01C0h 000h - 003h Port Mapping Port P2 (see Table 30) 01D0h 000h - 007h Port P1/P2 (see Table 31) 0200h 000h - 01Fh Port P3/P4 (see Table 32) 0220h 000h - 01Fh Port P5/P6 (see Table 33) 0240h 000h - 00Bh Port P7/P8 (see Table 34) 0260h 000h - 00Bh Port P9 (see Table 35) 0280h 000h - 00Bh Port PJ (see Table 36) 0320h 000h - 01Fh Timer TA0 (see Table 37) 0340h 000h - 02Eh Timer TA1 (see Table 38) 0380h 000h - 02Eh Timer TB0 (see Table 39) 03C0h 000h - 02Eh Timer TA2 (see Table 40) 0400h 000h - 02Eh Battery Backup (see Table 41) 0480h 000h - 01Fh RTC_B (see Table 42) 04A0h 000h - 01Fh 32-bit Hardware Multiplier (see Table 43) 04C0h 000h - 02Fh DMA General Control (see Table 44) 0500h 000h - 00Fh DMA Channel 0 (see Table 44) 0510h 000h - 00Ah DMA Channel 1 (see Table 44) 0520h 000h - 00Ah DMA Channel 2 (see Table 44) 0530h 000h - 00Ah DMA Channel 3 (see Table 44) 0540h 000h - 00Ah DMA Channel 4 (see Table 44) 0550h 000h - 00Ah DMA Channel 5 (see Table 44) 0560h 000h - 00Ah USCI_A0 (see Table 45) 05C0h 000h - 01Fh USCI_B0 (see Table 46) 05E0h 000h - 01Fh USCI_A1 (see Table 47) 0600h 000h - 01Fh USCI_B1 (see Table 48) 0620h 000h - 01Fh ADC12_A (see Table 49) 0700h 000h - 03Fh DAC12_A (see Table 50) 0780h 000h - 01Fh Comparator_B (see Table 51) 08C0h 000h - 00Fh USB configuration (see Table 52) 0900h 000h - 014h USB control (see Table 53) 0920h 000h - 01Fh LCD_B control (see Table 54) 0A00h 000h - 05Fh For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Copyright (c) 2010-2012, Texas Instruments Incorporated 33 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 21. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 22. PMM Registers (Base Address: 0120h) REGISTER DESCRIPTION REGISTER OFFSET PMM Control 0 PMMCTL0 00h PMM control 1 PMMCTL1 02h SVS high side control SVSMHCTL 04h SVS low side control SVSMLCTL 06h PMM interrupt flags PMMIFG 0Ch PMM interrupt enable PMMIE 0Eh Table 23. Flash Control Registers (Base Address: 0140h) REGISTER DESCRIPTION REGISTER OFFSET Flash control 1 FCTL1 00h Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h Table 24. CRC16 Registers (Base Address: 0150h) REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC result CRC16INIRES 04h Table 25. RAM Control Registers (Base Address: 0158h) REGISTER DESCRIPTION RAM control 0 REGISTER RCCTL0 OFFSET 00h Table 26. Watchdog Registers (Base Address: 015Ch) REGISTER DESCRIPTION Watchdog timer control REGISTER WDTCTL OFFSET 00h Table 27. UCS Registers (Base Address: 0160h) REGISTER DESCRIPTION REGISTER OFFSET UCS control 0 UCSCTL0 00h UCS control 1 UCSCTL1 02h UCS control 2 UCSCTL2 04h UCS control 3 UCSCTL3 06h UCS control 4 UCSCTL4 08h UCS control 5 UCSCTL5 0Ah UCS control 6 UCSCTL6 0Ch UCS control 7 UCSCTL7 0Eh UCS control 8 UCSCTL8 10h 34 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 28. SYS Registers (Base Address: 0180h) REGISTER DESCRIPTION REGISTER OFFSET System control SYSCTL 00h Bootstrap loader configuration area SYSBSLC 02h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh Bus Error vector generator SYSBERRIV 18h User NMI vector generator SYSUNIV 1Ah System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh Table 29. Shared Reference Registers (Base Address: 01B0h) REGISTER DESCRIPTION Shared reference control REGISTER REFCTL OFFSET 00h Table 30. Port Mapping Registers (Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h) REGISTER DESCRIPTION REGISTER OFFSET Port mapping password register PMAPPWD 00h Port mapping control register PMAPCTL 02h Port P2.0 mapping register P2MAP0 00h Port P2.1 mapping register P2MAP1 01h Port P2.2 mapping register P2MAP2 02h Port P2.3 mapping register P2MAP3 03h Port P2.4 mapping register P2MAP4 04h Port P2.5 mapping register P2MAP5 05h Port P2.6 mapping register P2MAP6 06h Port P2.7 mapping register P2MAP7 07h Table 31. Port P1/P2 Registers (Base Address: 0200h) REGISTER DESCRIPTION REGISTER OFFSET Port P1 input P1IN 00h Port P1 output P1OUT 02h Port P1 direction P1DIR 04h Port P1 pullup/pulldown enable P1REN 06h Port P1 drive strength P1DS 08h Port P1 selection P1SEL 0Ah Port P1 interrupt vector word P1IV 0Eh Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable P1IE 1Ah Port P1 interrupt flag P1IFG 1Ch Port P2 input P2IN 01h Port P2 output P2OUT 03h Port P2 direction P2DIR 05h Port P2 pullup/pulldown enable P2REN 07h Port P2 drive strength P2DS 09h Copyright (c) 2010-2012, Texas Instruments Incorporated 35 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 31. Port P1/P2 Registers (Base Address: 0200h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Port P2 selection P2SEL 0Bh Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh Table 32. Port P3/P4 Registers (Base Address: 0220h) REGISTER DESCRIPTION REGISTER OFFSET Port P3 input P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 pullup/pulldown enable P3REN 06h Port P3 drive strength P3DS 08h Port P3 selection P3SEL 0Ah Port P3 interrupt vector word P3IV 0Eh Port P3 interrupt edge select P3IES 18h Port P3 interrupt enable P3IE 1Ah Port P3 interrupt flag P3IFG 1Ch Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 pullup/pulldown enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 selection P4SEL 0Bh Port P4 interrupt vector word P4IV 1Eh Port P4 interrupt edge select P4IES 19h Port P4 interrupt enable P4IE 1Bh Port P4 interrupt flag P4IFG 1Dh Table 33. Port P5/P6 Registers (Base Address: 0240h) REGISTER DESCRIPTION REGISTER OFFSET Port P5 input P5IN 00h Port P5 output P5OUT 02h Port P5 direction P5DIR 04h Port P5 pullup/pulldown enable P5REN 06h Port P5 drive strength P5DS 08h Port P5 selection P5SEL 0Ah Port P6 input P6IN 01h Port P6 output P6OUT 03h Port P6 direction P6DIR 05h Port P6 pullup/pulldown enable P6REN 07h Port P6 drive strength P6DS 09h Port P6 selection P6SEL 0Bh 36 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 34. Port P7/P8 Registers (Base Address: 0260h) REGISTER DESCRIPTION REGISTER OFFSET Port P7 input P7IN 00h Port P7 output P7OUT 02h Port P7 direction P7DIR 04h Port P7 pullup/pulldown enable P7REN 06h Port P7 drive strength P7DS 08h Port P7 selection P7SEL 0Ah Port P8 input P8IN 01h Port P8 output P8OUT 03h Port P8 direction P8DIR 05h Port P8 pullup/pulldown enable P8REN 07h Port P8 drive strength P8DS 09h Port P8 selection P8SEL 0Bh Table 35. Port P9 Register (Base Address: 0280h) REGISTER DESCRIPTION REGISTER OFFSET Port P9 input P9IN 00h Port P9 output P9OUT 02h Port P9 direction P9DIR 04h Port P9 pullup/pulldown enable P9REN 06h Port P9 drive strength P9DS 08h Port P9 selection P9SEL 0Ah Table 36. Port J Registers (Base Address: 0320h) REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ pullup/pulldown enable PJREN 06h Port PJ drive strength PJDS 08h Table 37. TA0 Registers (Base Address: 0340h) REGISTER DESCRIPTION REGISTER OFFSET TA0 control TA0CTL 00h Capture/compare control 0 TA0CCTL0 02h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 2 TA0CCTL2 06h Capture/compare control 3 TA0CCTL3 08h Capture/compare control 4 TA0CCTL4 0Ah TA0 counter register TA0R 10h Capture/compare register 0 TA0CCR0 12h Capture/compare register 1 TA0CCR1 14h Capture/compare register 2 TA0CCR2 16h Capture/compare register 3 TA0CCR3 18h Capture/compare register 4 TA0CCR4 1Ah TA0 expansion register 0 TA0EX0 20h TA0 interrupt vector TA0IV 2Eh Copyright (c) 2010-2012, Texas Instruments Incorporated 37 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 38. TA1 Registers (Base Address: 0380h) REGISTER DESCRIPTION REGISTER OFFSET TA1 control TA1CTL 00h Capture/compare control 0 TA1CCTL0 02h Capture/compare control 1 TA1CCTL1 04h Capture/compare control 2 TA1CCTL2 06h TA1 counter register TA1R 10h Capture/compare register 0 TA1CCR0 12h Capture/compare register 1 TA1CCR1 14h Capture/compare register 2 TA1CCR2 16h TA1 expansion register 0 TA1EX0 20h TA1 interrupt vector TA1IV 2Eh Table 39. TB0 Registers (Base Address: 03C0h) REGISTER DESCRIPTION REGISTER OFFSET TB0 control TB0CTL 00h Capture/compare control 0 TB0CCTL0 02h Capture/compare control 1 TB0CCTL1 04h Capture/compare control 2 TB0CCTL2 06h Capture/compare control 3 TB0CCTL3 08h Capture/compare control 4 TB0CCTL4 0Ah Capture/compare control 5 TB0CCTL5 0Ch Capture/compare control 6 TB0CCTL6 0Eh TB0 register TB0R 10h Capture/compare register 0 TB0CCR0 12h Capture/compare register 1 TB0CCR1 14h Capture/compare register 2 TB0CCR2 16h Capture/compare register 3 TB0CCR3 18h Capture/compare register 4 TB0CCR4 1Ah Capture/compare register 5 TB0CCR5 1Ch Capture/compare register 6 TB0CCR6 1Eh TB0 expansion register 0 TB0EX0 20h TB0 interrupt vector TB0IV 2Eh Table 40. TA2 Registers (Base Address: 0400h) REGISTER DESCRIPTION REGISTER OFFSET TA2 control TA2CTL 00h Capture/compare control 0 TA2CCTL0 02h Capture/compare control 1 TA2CCTL1 04h Capture/compare control 2 TA2CCTL2 06h TA2 counter register TA2R 10h Capture/compare register 0 TA2CCR0 12h Capture/compare register 1 TA2CCR1 14h Capture/compare register 2 TA2CCR2 16h TA2 expansion register 0 TA2EX0 20h TA2 interrupt vector TA2IV 2Eh 38 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 41. Battery Backup Registers (Base Address: 0480h) REGISTER DESCRIPTION REGISTER OFFSET Battery Backup Memory 0 BAKMEM0 00h Battery Backup Memory 1 BAKMEM1 02h Battery Backup Memory 2 BAKMEM2 04h Battery Backup Memory 3 BAKMEM3 06h Battery Backup Control BAKCTL 1Ch Battery Charger Control BAKCHCTL 1Eh Table 42. Real-Time Clock Registers (Base Address: 04A0h) REGISTER DESCRIPTION REGISTER OFFSET RTC control register 0 RTCCTL0 00h RTC control register 1 RTCCTL1 01h RTC control register 2 RTCCTL2 02h RTC control register 3 RTCCTL3 03h RTC prescaler 0 control register RTCPS0CTL 08h RTC prescaler 1 control register RTCPS1CTL 0Ah RTC prescaler 0 RTCPS0 0Ch RTC prescaler 1 RTCPS1 0Dh RTC interrupt vector word RTCIV 0Eh RTC seconds RTCSEC 10h RTC minutes RTCMIN 11h RTC hours RTCHOUR 12h RTC day of week RTCDOW 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Binary-to-BCD conversion register BIN2BCD 1Ch BCD-to-binary conversion register BCD2BIN 1Eh Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) REGISTER DESCRIPTION REGISTER OFFSET 16-bit operand 1 - multiply MPY 00h 16-bit operand 1 - signed multiply MPYS 02h 16-bit operand 1 - multiply accumulate MAC 04h 16-bit operand 1 - signed multiply accumulate MACS 06h 16-bit operand 2 OP2 08h 16 x 16 result low word RESLO 0Ah 16 x 16 result high word RESHI 0Ch 16 x 16 sum extension register SUMEXT 0Eh 32-bit operand 1 - multiply low word MPY32L 10h 32-bit operand 1 - multiply high word MPY32H 12h 32-bit operand 1 - signed multiply low word MPYS32L 14h 32-bit operand 1 - signed multiply high word MPYS32H 16h Copyright (c) 2010-2012, Texas Instruments Incorporated 39 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) (continued) REGISTER DESCRIPTION REGISTER OFFSET 32-bit operand 1 - multiply accumulate low word MAC32L 18h 32-bit operand 1 - multiply accumulate high word MAC32H 1Ah 32-bit operand 1 - signed multiply accumulate low word MACS32L 1Ch 32-bit operand 1 - signed multiply accumulate high word MACS32H 1Eh 32-bit operand 2 - low word OP2L 20h 32-bit operand 2 - high word OP2H 22h 32 x 32 result 0 - least significant word RES0 24h 32 x 32 result 1 RES1 26h 32 x 32 result 2 RES2 28h 32 x 32 result 3 - most significant word RES3 2Ah MPY32 control register 0 MPY32CTL0 2Ch Table 44. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA Channel 4: 0550h, DMA Channel 5: 0560h) REGISTER DESCRIPTION REGISTER OFFSET DMA General Control: DMA module control 0 DMACTL0 00h DMA General Control: DMA module control 1 DMACTL1 02h DMA General Control: DMA module control 2 DMACTL2 04h DMA General Control: DMA module control 3 DMACTL3 06h DMA General Control: DMA module control 4 DMACTL4 08h DMA General Control: DMA interrupt vector DMAIV 0Ah DMA Channel 0 control DMA0CTL 00h DMA Channel 0 source address low DMA0SAL 02h DMA Channel 0 source address high DMA0SAH 04h DMA Channel 0 destination address low DMA0DAL 06h DMA Channel 0 destination address high DMA0DAH 08h DMA Channel 0 transfer size DMA0SZ 0Ah DMA Channel 1 control DMA1CTL 00h DMA Channel 1 source address low DMA1SAL 02h DMA Channel 1 source address high DMA1SAH 04h DMA Channel 1 destination address low DMA1DAL 06h DMA Channel 1 destination address high DMA1DAH 08h DMA Channel 1 transfer size DMA1SZ 0Ah DMA Channel 2 control DMA2CTL 00h DMA Channel 2 source address low DMA2SAL 02h DMA Channel 2 source address high DMA2SAH 04h DMA Channel 2 destination address low DMA2DAL 06h DMA Channel 2 destination address high DMA2DAH 08h DMA Channel 2 transfer size DMA2SZ 0Ah DMA Channel 3 control DMA3CTL 00h DMA Channel 3 source address low DMA3SAL 02h DMA Channel 3 source address high DMA3SAH 04h DMA Channel 3 destination address low DMA3DAL 06h DMA Channel 3 destination address high DMA3DAH 08h DMA Channel 3 transfer size DMA3SZ 0Ah DMA Channel 4 control DMA4CTL 00h DMA Channel 4 source address low DMA4SAL 02h 40 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 44. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA Channel 4: 0550h, DMA Channel 5: 0560h) (continued) REGISTER DESCRIPTION REGISTER OFFSET DMA Channel 4 source address high DMA4SAH 04h DMA Channel 4 destination address low DMA4DAL 06h DMA Channel 4 destination address high DMA4DAH 08h DMA Channel 4 transfer size DMA4SZ 0Ah DMA Channel 5 control DMA5CTL 00h DMA Channel 5 source address low DMA5SAL 02h DMA Channel 5 source address high DMA5SAH 04h DMA Channel 5 destination address low DMA5DAL 06h DMA Channel 5 destination address high DMA5DAH 08h DMA Channel 5 transfer size DMA5SZ 0Ah Table 45. USCI_A0 Registers (Base Address: 05C0h) REGISTER DESCRIPTION REGISTER OFFSET USCI control 0 UCA0CTL0 00h USCI control 1 UCA0CTL1 01h USCI baud rate 0 UCA0BR0 06h USCI baud rate 1 UCA0BR1 07h USCI modulation control UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receive buffer UCA0RXBUF 0Ch USCI transmit buffer UCA0TXBUF 0Eh USCI LIN control UCA0ABCTL 10h USCI IrDA transmit control UCA0IRTCTL 12h USCI IrDA receive control UCA0IRRCTL 13h USCI interrupt enable UCA0IE 1Ch USCI interrupt flags UCA0IFG 1Dh USCI interrupt vector word UCA0IV 1Eh Table 46. USCI_B0 Registers (Base Address: 05E0h) REGISTER DESCRIPTION REGISTER OFFSET USCI synchronous control 0 UCB0CTL0 00h USCI synchronous control 1 UCB0CTL1 01h USCI synchronous bit rate 0 UCB0BR0 06h USCI synchronous bit rate 1 UCB0BR1 07h USCI synchronous status UCB0STAT 0Ah USCI synchronous receive buffer UCB0RXBUF 0Ch USCI synchronous transmit buffer UCB0TXBUF 0Eh USCI I2C own address UCB0I2COA 10h USCI I2C slave address UCB0I2CSA 12h USCI interrupt enable UCB0IE 1Ch USCI interrupt flags UCB0IFG 1Dh USCI interrupt vector word UCB0IV 1Eh Copyright (c) 2010-2012, Texas Instruments Incorporated 41 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 47. USCI_A1 Registers (Base Address: 0600h) REGISTER DESCRIPTION REGISTER OFFSET USCI control 0 UCA1CTL0 00h USCI control 1 UCA1CTL1 01h USCI baud rate 0 UCA1BR0 06h USCI baud rate 1 UCA1BR1 07h USCI modulation control UCA1MCTL 08h USCI status UCA1STAT 0Ah USCI receive buffer UCA1RXBUF 0Ch USCI transmit buffer UCA1TXBUF 0Eh USCI LIN control UCA1ABCTL 10h USCI IrDA transmit control UCA1IRTCTL 12h USCI IrDA receive control UCA1IRRCTL 13h USCI interrupt enable UCA1IE 1Ch USCI interrupt flags UCA1IFG 1Dh USCI interrupt vector word UCA1IV 1Eh Table 48. USCI_B1 Registers (Base Address: 0620h) REGISTER DESCRIPTION REGISTER OFFSET USCI synchronous control 0 UCB1CTL0 00h USCI synchronous control 1 UCB1CTL1 01h USCI synchronous bit rate 0 UCB1BR0 06h USCI synchronous bit rate 1 UCB1BR1 07h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address UCB1I2CSA 12h USCI interrupt enable UCB1IE 1Ch USCI interrupt flags UCB1IFG 1Dh USCI interrupt vector word UCB1IV 1Eh Table 49. ADC12_A Registers (Base Address: 0700h) REGISTER DESCRIPTION REGISTER OFFSET Control register 0 ADC12CTL0 00h Control register 1 ADC12CTL1 02h Control register 2 ADC12CTL2 04h Interrupt-flag register ADC12IFG 0Ah Interrupt-enable register ADC12IE 0Ch Interrupt-vector-word register ADC12IV 0Eh ADC memory-control register 0 ADC12MCTL0 10h ADC memory-control register 1 ADC12MCTL1 11h ADC memory-control register 2 ADC12MCTL2 12h ADC memory-control register 3 ADC12MCTL3 13h ADC memory-control register 4 ADC12MCTL4 14h ADC memory-control register 5 ADC12MCTL5 15h ADC memory-control register 6 ADC12MCTL6 16h ADC memory-control register 7 ADC12MCTL7 17h ADC memory-control register 8 ADC12MCTL8 18h 42 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 49. ADC12_A Registers (Base Address: 0700h) (continued) REGISTER DESCRIPTION REGISTER OFFSET ADC memory-control register 9 ADC12MCTL9 19h ADC memory-control register 10 ADC12MCTL10 1Ah ADC memory-control register 11 ADC12MCTL11 1Bh ADC memory-control register 12 ADC12MCTL12 1Ch ADC memory-control register 13 ADC12MCTL13 1Dh ADC memory-control register 14 ADC12MCTL14 1Eh ADC memory-control register 15 ADC12MCTL15 1Fh Conversion memory 0 ADC12MEM0 20h Conversion memory 1 ADC12MEM1 22h Conversion memory 2 ADC12MEM2 24h Conversion memory 3 ADC12MEM3 26h Conversion memory 4 ADC12MEM4 28h Conversion memory 5 ADC12MEM5 2Ah Conversion memory 6 ADC12MEM6 2Ch Conversion memory 7 ADC12MEM7 2Eh Conversion memory 8 ADC12MEM8 30h Conversion memory 9 ADC12MEM9 32h Conversion memory 10 ADC12MEM10 34h Conversion memory 11 ADC12MEM11 36h Conversion memory 12 ADC12MEM12 38h Conversion memory 13 ADC12MEM13 3Ah Conversion memory 14 ADC12MEM14 3Ch Conversion memory 15 ADC12MEM15 3Eh Table 50. DAC12_A Registers (Base Address: 0780h) REGISTER DESCRIPTION REGISTER OFFSET DAC12_A channel 0 control register 0 DAC12_0CTL0 00h DAC12_A channel 0 control register 1 DAC12_0CTL1 02h DAC12_A channel 0 data register DAC12_0DAT 04h DAC12_A channel 0 calibration control register DAC12_0CALCTL 06h DAC12_A channel 0 calibration data register DAC12_0CALDAT 08h DAC12_A channel 1 control register 0 DAC12_1CTL0 10h DAC12_A channel 1 control register 1 DAC12_1CTL1 12h DAC12_A channel 1 data register DAC12_1DAT 14h DAC12_A channel 1 calibration control register DAC12_1CALCTL 16h DAC12_A channel 1 calibration data register DAC12_1CALDAT 18h DAC12_A interrupt vector word DAC12IV 1Eh Table 51. Comparator_B Registers (Base Address: 08C0h) REGISTER DESCRIPTION REGISTER OFFSET Comp_B control register 0 CBCTL0 00h Comp_B control register 1 CBCTL1 02h Comp_B control register 2 CBCTL2 04h Comp_B control register 3 CBCTL3 06h Comp_B interrupt register CBINT 0Ch Comp_B interrupt vector word CBIV 0Eh Copyright (c) 2010-2012, Texas Instruments Incorporated 43 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 52. USB Configuration Registers (Base Address: 0900h) REGISTER DESCRIPTION REGISTER OFFSET USB key/ID USBKEYID 00h USB module configuration USBCNF 02h USB PHY control USBPHYCTL 04h USB power control USBPWRCTL 08h USB power voltage setting USBPWRVSR 0Ah USB PLL control USBPLLCTL 10h USB PLL divider USBPLLDIV 12h USB PLL interrupts USBPLLIR 14h Table 53. USB Control Registers (Base Address: 0920h) REGISTER DESCRIPTION REGISTER OFFSET Input endpoint#0 configuration IEPCNF_0 00h Input endpoint #0 byte count IEPCNT_0 01h Output endpoint#0 configuration OEPCNF_0 02h Output endpoint #0 byte count OEPCNT_0 03h Input endpoint interrupt enables IEPIE 0Eh Output endpoint interrupt enables OEPIE 0Fh Input endpoint interrupt flags IEPIFG 10h Output endpoint interrupt flags OEPIFG 11h USB interrupt vector USBIV 12h USB maintenance MAINT 16h Time stamp TSREG 18h USB frame number USBFN 1Ah USB control USBCTL 1Ch USB interrupt enables USBIE 1Dh USB interrupt flags USBIFG 1Eh Function address FUNADR 1Fh Table 54. LCD_B Registers (Base Address: 0A00h) REGISTER DESCRIPTION REGISTER OFFSET LCD_B control register 0 LCDBCTL0 000h LCD_B control register 1 LCDBCTL1 002h LCD_B blinking control register LCDBBLKCTL 004h LCD_B memory control register LCDBMEMCTL 006h LCD_B voltage control register LCDBVCTL 008h LCD_B port control register 0 LCDBPCTL0 00Ah LCD_B port control register 1 LCDBPCTL1 00Ch LCD_B port control register 2 LCDBPCTL2 00Eh LCD_B charge pump control register LCDBCTL0 012h LCD_B interrupt vector word LCDBIV 01Eh LCD_B memory 1 LCDM1 020h LCD_B memory 2 LCDM2 021h LCD_B memory 22 LCDM22 035h LCD_B blinking memory 1 LCDBM1 040h LCD_B blinking memory 2 LCDBM2 041h 44 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 54. LCD_B Registers (Base Address: 0A00h) (continued) REGISTER DESCRIPTION LCD_B blinking memory 22 Copyright (c) 2010-2012, Texas Instruments Incorporated REGISTER LCDBM22 OFFSET 055h 45 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (excluding VCORE, VBUS, V18) (2) -0.3 V to VCC + 0.3 V Diode current at any device pin 2 mA Storage temperature range, Tstg (3) -55C to 150C Maximum junction temperature, TJ 95C (1) (2) (3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. VCORE is for internal device use only. No external dc loading or voltage should be applied. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Thermal Packaging Characteristics PARAMETER JA Junction-to-ambient thermal resistance, still air (1) JC(TOP) Junction-to-case (top) thermal resistance (2) JB Junction-to-board thermal resistance (3) (1) (2) (3) VALUE QFP (PZ) 122 BGA (ZQW) 108 QFP (PZ) 83 BGA (ZQW) 72 QFP (PZ) 98 BGA (ZQW) 76 UNIT C/W C/W C/W The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. Recommended Operating Conditions MIN Supply voltage during program execution and flash programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 = DVCC = VCC) (1) (2) VCC Supply voltage during USB operation, USB PLL disabled (USB_EN = 1, UPLLEN = 0) VCC,USB Supply voltage during USB operation, USB PLL enabled (3) (USB_EN = 1, UPLLEN = 1) VSS Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS) VBAT,RTC Backup-supply voltage with RTC operational VBAT,MEM TA NOM MAX PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 3.6 PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 3.6 PMMCOREVx = 2 2.2 3.6 PMMCOREVx = 2, 3 2.4 3.6 0 UNIT V V V TA = 0C to 85C 1.55 3.6 TA = -40C to 85C 1.70 3.6 Backup-supply voltage with backup memory retained. TA = -40C to 85C 1.20 3.6 V Operating free-air temperature I version -40 85 C TJ Operating junction temperature I version -40 CBAK Capacitance at pin VBAK (1) (2) (3) 46 1 4.7 V 85 C 10 nF It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation. The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold parameters for the exact values and further details. USB operation with USB PLL enabled requires PMMCOREVx 2 for proper operation. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Recommended Operating Conditions (continued) MIN CVCORE Capacitor at VCORE CDVCC/ CVCORE Capacitor ratio of DVCC to VCORE fSYSTEM UNIT nF 10 Processor frequency (maximum MCLK frequency) (4) (5) (see Figure 1) Minimum processor frequency for USB operation USB_wait Wait state cycles during USB operation (5) MAX 470 fSYSTEM_USB (4) NOM PMMCOREVx = 0, 1.8 V VCC 3.6 V (default condition) 0 8.0 PMMCOREVx = 1, 2 V VCC 3.6 V 0 12.0 PMMCOREVx = 2, 2.2 V VCC 3.6 V 0 16.0 PMMCOREVx = 3, 2.4 V VCC 3.6 V 0 20.0 1.5 MHz MHz 16 cycles The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency. Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. 25 System Frequency - MHz 20 3 16 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 1. Frequency vs Supply Voltage Copyright (c) 2010-2012, Texas Instruments Incorporated 47 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER EXECUTION MEMORY VCC PMMCOREVx 1 MHz TYP IAM, IAM, (1) (2) (3) 48 Flash RAM Flash RAM 3V 3V 8 MHz MAX 0.36 TYP 2.1 12 MHz MAX TYP 0 0.32 1 0.36 2.4 3.6 2 0.37 2.5 3.8 3 0.39 0 0.18 1 0.20 1.2 1.7 2 0.22 1.3 2.0 3 0.23 1.4 2.1 1.0 MAX TYP UNIT MAX 2.4 2.7 0.21 20 MHz 4.0 4.0 mA 6.6 1.2 1.9 mA 3.6 All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0). fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER ILPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) VLO,WDT ILPM4 ILPM3.5, RTC,VCC ILPM3.5, RTC,VBAT ILPM3.5, RTC,TOT Low-power mode 4 (8) (4) 85C 0 71 75 87 81 85 99 3V 3 78 83 98 89 94 108 2.2 V 0 6.3 6.7 9.9 9.0 11 16 3V 3 6.6 7.0 11 10 12 18 0 1.6 1.8 2.4 4.7 6.5 10.5 1 1.6 1.9 4.8 6.6 2 1.7 2.0 4.9 6.7 0 1.9 2.1 5.0 6.8 1 1.9 2.1 5.1 7.0 2 2.0 2.2 5.2 7.1 3 2.0 2.2 2.9 5.4 7.3 12.6 0 0.9 1.2 1.9 4.0 5.9 10.3 1 0.9 1.2 4.1 6.0 2 1.0 1.3 4.2 6.1 3 1.0 1.3 2.2 4.3 6.3 11.3 0 0.9 1.1 1.8 3.9 5.8 10 1 0.9 1.1 4.0 5.9 2 1.0 1.2 4.1 6.1 3 1.0 1.2 4.2 6.2 11 3V ILPM3, 60C 2.2 V Low-power mode 3, crystal mode (6) (4) Low-power mode 3, VLO mode, Watchdog enabled (7) (4) 25C PMMCOREVx 2.2 V ILPM3,XT1LF -40C VCC 3V 3V TYP MAX TYP MAX 2.7 2.1 TYP MAX TYP MAX 10.8 UNIT A A A A A Low-power mode 3.5 (LPM3.5) current with active RTC into primary supply pin DVCC (9) 3V 0.5 0.8 1.4 A Low-power mode 3.5 (LPM3.5) current with active RTC into backup supply pin VBAT (10) 3V 0.6 0.8 1.4 A Total low-power mode 3.5 (LPM3.5) current with active RTC (11) 3V 1.6 2.8 A 1.0 1.1 1.3 (1) (2) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF. (3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). (4) Current for brownout included. Low side supervisor and monitors disabled (SVSL, SVML). High side supervisor and monitor disabled (SVSH, SVMH). RAM retention enabled. (5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled. USB disabled (VUSBEN = 0, SLDOEN = 0). (6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). (7) Current for watchdog timer clocked by VLO included. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fMCLK = fSMCLK = fDCO = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). (8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). (9) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active (10) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK (11) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK Copyright (c) 2010-2012, Texas Instruments Incorporated 49 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2) PARAMETER ILPM4.5 Low-power mode 4.5 (LPM4.5) (12) VCC PMMCOREVx -40C TYP 3V MAX 0.2 25C TYP 60C MAX 0.3 TYP 0.6 85C MAX TYP 0.7 MAX 0.9 1.4 UNIT A (12) Internal regulator disabled. No data retention. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) Temperature (TA) PARAMETER VCC PMMCOREVx -40C TYP ILPM3, LCD, ext. bias ILPM3, LCD, int. bias Low-power mode 3 (LPM3) current, LCD 4mux mode, external biasing (3) (4) Low-power mode 3 (LPM3) current, LCD 4mux mode, internal biasing, charge pump disabled (3) (5) 3V 3V 2.2 V ILPM3 LCD,CP (1) (2) (3) (4) (5) (6) Low-power mode 3 (LPM3) current, LCD 4mux mode, internal biasing, charge pump enabled (3) (6) 3V MAX 25C TYP 0 2.3 2.7 1 2.3 2 60C MAX TYP MAX TYP UNIT MAX 5.4 7.4 2.7 5.6 7.5 2.4 2.8 5.8 7.7 3 2.4 2.8 3.5 5.9 7.9 13.2 0 2.7 3.2 3.8 5.9 7.9 12.2 1 2.7 3.2 6.1 8.1 2 2.8 3.3 6.2 8.3 3 2.8 3.3 6.4 8.4 0 3.8 1 3.9 2 4.0 0 4.0 1 4.1 2 4.2 3 4.2 3.1 85C 4.9 11.5 A A 13.7 A A All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF. Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz Current for brownout included. Low side supervisor and monitors disabled (SVSL, SVML). High side supervisor and monitor disabled (SVSH, SVMH). RAM retention enabled. LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz) Current through external resistors not included (voltage levels are supplied by test equipment). Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load. LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz) Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load. LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump enabled), VLCDx = 1000 (VLCD = 3 V, typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz) Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load. Schmitt-Trigger Inputs - General Purpose I/O (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ (1) 50 Positive-going input threshold voltage TEST CONDITIONS VCC MIN TYP MAX 1.8 V 0.80 1.40 3V 1.50 2.10 UNIT V Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Schmitt-Trigger Inputs - General Purpose I/O(1) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT- Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT-) RPull Pullup or pulldown resistor For pullup: VIN = VSS For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC VCC MIN TYP 1.8 V 0.45 1.00 3V 0.75 1.65 1.8 V 0.3 0.8 3V 0.4 1.0 20 35 MAX UNIT V V 50 k 5 pF Inputs - Ports P1, P2, P3, and P4 (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) (2) External interrupt timing TEST CONDITIONS (2) VCC Port P1, P2, P3, P4: P1.x to P4.x, External trigger pulse duration to set interrupt flag MIN 2.2 V, 3 V MAX UNIT 20 ns Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). Leakage Current - General Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.x) (1) (2) TEST CONDITIONS VCC (1) (2) High-impedance leakage current MIN 1.8 V, 3 V MAX UNIT 50 nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. Outputs - General Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = -3 mA VOH High-level output voltage I(OHmax) = -10 mA (2) I(OHmax) = -5 mA (1) I(OHmax) = -15 mA (2) I(OLmax) = 3 mA (1) VOL Low-level output voltage I(OLmax) = 10 mA (2) I(OLmax) = 5 mA (2) 1.8 V 3V 1.8 V (1) I(OLmax) = 15 mA (2) (1) VCC (1) 3V MIN MAX VCC - 0.25 VCC VCC - 0.60 VCC VCC - 0.25 VCC VCC - 0.60 VCC UNIT V VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 V VSS VSS + 0.60 The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed 48 mA to hold the maximum voltage drop specified. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed 100 mA to hold the maximum voltage drop specified. Copyright (c) 2010-2012, Texas Instruments Incorporated 51 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Outputs - General Purpose I/O (Reduced Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS I(OHmax) = -1 mA VOH High-level output voltage 1.8 V I(OHmax) = -3 mA (3) I(OHmax) = -2 mA (2) 3V I(OHmax) = -6 mA (3) I(OLmax) = 1 mA VOL Low-level output voltage (3) MIN MAX VCC - 0.25 VCC VCC - 0.60 VCC VCC - 0.25 VCC VCC - 0.60 VCC (2) 1.8 V I(OLmax) = 3 mA (3) I(OLmax) = 2 mA (2) 3V I(OLmax) = 6 mA (3) (1) (2) VCC (2) UNIT V VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 V VSS VSS + 0.60 Selecting reduced drive strength may reduce EMI. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed 100 mA to hold the maximum voltage drop specified. Output Frequency - Ports P1, P2, and P3 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fPx.y fPort_CLK (1) (2) (3) 52 TEST CONDITIONS Port output frequency (with load) P3.4/TA2CLK/SMCLK/S27 CL = 20 pF, RL = 1 k (1) or 3.2 k (2) (3) Clock output frequency P1.0/TA0CLK/ACLK/S39 P3.4/TA2CLK/SMCLK/S27 P2.0/P2MAP0 (P2MAP0 = PM_MCLK ) CL = 20 pF (3) MIN MAX VCC = 1.8 V PMMCOREVx = 0 8 VCC = 3 V PMMCOREVx = 3 20 VCC = 1.8 V PMMCOREVx = 0 8 VCC = 3 V PMMCOREVx = 3 20 UNIT MHz MHz Full drive strength of port: A resistive divider with 2 x 0.5 k between VCC and VSS is used as load. The output is connected to the center tap of the divider. Reduced drive strength of port: A resistive divider with 2 x 1.6 k between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V P3.2 IOL - Typical Low-Level Output Current - mA IOL - Typical Low-Level Output Current - mA 25.0 TA = 25C 20.0 TA = 85C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 7.0 TA = 85C 5.0 4.0 3.0 2.0 1.0 0.5 1.0 1.5 Figure 2. Figure 3. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 0.0 IOH - Typical High-Level Output Current - mA VCC = 3.0 V P3.2 -5.0 -10.0 -15.0 -20.0 -25.0 0.0 2.0 VOL - Low-Level Output Voltage - V VOL - Low-Level Output Voltage - V IOH - Typical High-Level Output Current - mA TA = 25C 6.0 0.0 0.0 3.5 VCC = 1.8 V P3.2 TA = 85C TA = 25C 0.5 1.0 1.5 2.0 2.5 3.0 VOH - High-Level Output Voltage - V Figure 4. Copyright (c) 2010-2012, Texas Instruments Incorporated 3.5 -1.0 VCC = 1.8 V P3.2 -2.0 -3.0 -4.0 -5.0 TA = 85C -6.0 TA = 25C -7.0 -8.0 0.0 0.5 1.0 1.5 VOH - High-Level Output Voltage - V 2.0 Figure 5. 53 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 3.0 V P3.2 55.0 IOL - Typical Low-Level Output Current - mA IOL - Typical Low-Level Output Current - mA 60.0 TA = 25C 50.0 TA = 85C 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 24 16 8 4 0.5 1.0 1.5 Figure 7. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 VCC = 3.0 V P3.2 IOH - Typical High-Level Output Current - mA -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0 TA = 85C -55.0 -60.0 0.0 2.0 VOL - Low-Level Output Voltage - V Figure 6. 0.0 IOH - Typical High-Level Output Current - mA TA = 85C 12 VOL - Low-Level Output Voltage - V TA = 25C 0.5 1.0 1.5 2.0 2.5 3.0 VOH - High-Level Output Voltage - V Figure 8. 54 TA = 25C 20 0 0.0 3.5 VCC = 1.8 V P3.2 3.5 VCC = 1.8 V P3.2 -4 -8 -12 TA = 85C -16 TA = 25C -20 0.0 0.5 1.0 1.5 2.0 VOH - High-Level Output Voltage - V Figure 9. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25C IDVCC,LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25C 0.170 32768 XTS = 0, XT1BYPASS = 0 fXT1,LF,SW XT1 oscillator logic-level squarewave input frequency, LF mode XTS = 0, XT1BYPASS = 1 (2) OALF 3V 0.290 XT1 oscillator crystal frequency, LF mode (3) 10 CL,eff fFault,LF tSTART,LF (1) (2) (3) (4) (5) (6) (7) (8) 32.768 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, fXT1,LF = 32768 Hz, CL,eff = 6 pF 210 XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, fXT1,LF = 32768 Hz, CL,eff = 12 pF UNIT 300 A Hz 50 kHz k XTS = 0, XCAPx = 0 (6) Integrated effective load capacitance, LF mode (5) MAX 0.075 fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25C fXT1,LF0 Oscillation allowance for LF crystals (4) TYP 2 XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 12.0 pF Duty cycle, LF mode XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz 30 70 % Oscillator fault frequency, LF mode (7) XTS = 0 (8) 10 10000 Hz Startup time, LF mode fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, TA = 25C, CL,eff = 6 pF fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25C, CL,eff = 12 pF 1000 3V ms 500 To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. Maximum frequency of operation of the entire device cannot be exceeded. Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: (a) For XT1DRIVEx = 0, CL,eff 6 pF. (b) For XT1DRIVEx = 1, 6 pF CL,eff 9 pF. (c) For XT1DRIVEx = 2, 6 pF CL,eff 10 pF. (d) For XT1DRIVEx = 3, CL,ef f 6 pF. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Copyright (c) 2010-2012, Texas Instruments Incorporated 55 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Crystal Oscillator, XT2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25C IDVCC,XT2 XT2 oscillator crystal current consumption fOSC = 12 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 1, TA = 25C fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25C (2) TYP MAX UNIT 200 260 3V A 325 fOSC = 32 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25C 450 fXT2,HF0 XT2 oscillator crystal frequency, mode 0 XT2DRIVEx = 0, XT2BYPASS = 0 (3) 4 8 MHz fXT2,HF1 XT2 oscillator crystal frequency, mode 1 XT2DRIVEx = 1, XT2BYPASS = 0 (3) 8 16 MHz fXT2,HF2 XT2 oscillator crystal frequency, mode 2 XT2DRIVEx = 2, XT2BYPASS = 0 (3) 16 24 MHz fXT2,HF3 XT2 oscillator crystal frequency, mode 3 XT2DRIVEx = 3, XT2BYPASS = 0 (3) 24 32 MHz fXT2,HF,SW XT2 oscillator logic-level squarewave input frequency XT2BYPASS = 1 (4) 0.7 32 MHz OAHF tSTART,HF CL,eff fFault,HF (1) (2) (3) (4) (5) (6) (7) (8) 56 Oscillation allowance for HF crystals (5) Startup time Integrated effective load capacitance, HF mode (6) (3) XT2DRIVEx = 0, XT2BYPASS = 0, fXT2,HF0 = 6 MHz, CL,eff = 15 pF 450 XT2DRIVEx = 1, XT2BYPASS = 0, fXT2,HF1 = 12 MHz, CL,eff = 15 pF 320 XT2DRIVEx = 2, XT2BYPASS = 0, fXT2,HF2 = 20 MHz, CL,eff = 15 pF 200 XT2DRIVEx = 3, XT2BYPASS = 0, fXT2,HF3 = 32 MHz, CL,eff = 15 pF 200 fOSC = 6 MHz XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25C, CL,eff = 15 pF 0.5 fOSC = 20 MHz XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25C, CL,eff = 15 pF 3V ms 0.3 1 (1) Duty cycle Measured at ACLK, fXT2,HF2 = 20 MHz 40 Oscillator fault frequency (7) XT2BYPASS = 1 (8) 30 50 pF 60 % 300 kHz Requires external capacitors at both terminals. Values are specified by crystal manufacturers. To improve EMI on the XT2 oscillator the following guidelines should be observed. (a) Keep the traces between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT. (d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Maximum frequency of operation of the entire device cannot be exceeded. When XT2BYPASS is set, the XT2 circuit is automatically powered down. Oscillation allowance is based on a safety factor of 5 for recommended crystals. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V Measured at ACLK (2) 1.8 V to 3.6 V Measured at ACLK 1.8 V to 3.6 V dfVLO/dVCC VLO frequency supply voltage drift Duty cycle (1) (2) MIN TYP MAX 6 9.4 14 0.5 kHz %/C 4 40 UNIT %/V 50 60 TYP MAX % Calculated using the box method: (MAX(-40 to 85C) - MIN(-40 to 85C)) / MIN(-40 to 85C) / (85C - (-40C)) Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V - 1.8 V) Internal Reference, Low-Frequency Oscillator (REFO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN UNIT REFO oscillator current consumption TA = 25C 1.8 V to 3.6 V 3 A REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz REFO absolute tolerance calibrated Full temperature range 1.8 V to 3.6 V 3.5 3V 1.5 dfREFO/dT REFO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V 0.01 %/C dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK (2) 1.8 V to 3.6 V 1.0 %/V Duty cycle Measured at ACLK 1.8 V to 3.6 V REFO startup time 40%/60% duty cycle 1.8 V to 3.6 V IREFO fREFO tSTART (1) (2) TA = 25C 40 50 25 60 % % % s Calculated using the box method: (MAX(-40 to 85C) - MIN(-40 to 85C)) / MIN(-40 to 85C) / (85C - (-40C)) Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V - 1.8 V) Copyright (c) 2010-2012, Texas Instruments Incorporated 57 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz fDCO(1,0) DCO frequency (1, 0) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz fDCO(1,31) DCO frequency (1, 31) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz fDCO(2,0) DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz fDCO(2,31) DCO frequency (2, 31) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz fDCO(3,0) DCO frequency (3, 0) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz fDCO(3,31) DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz fDCO(4,0) DCO frequency (4, 0) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz fDCO(4,31) DCO frequency (4, 31) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz fDCO(5,0) DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz fDCO(5,31) DCO frequency (5, 31) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz fDCO(6,0) DCO frequency (6, 0) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz fDCO(6,31) DCO frequency (6, 31) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz fDCO(7,0) DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz fDCO(7,31) DCO frequency (7, 31) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz SDCORSEL Frequency step between range DCORSEL and DCORSEL + 1 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio SDCO Frequency step between tap DCO and DCO + 1 SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio Duty cycle Measured at SMCLK dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz, 0.1 %/C dfDCO/dVCC DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V 40 50 60 % Typical DCO Frequency, VCC = 3.0 V, TA = 25C 100 fDCO - MHz 10 DCOx = 31 1 0.1 DCOx = 0 0 1 2 3 4 5 6 7 DCORSEL Figure 10. Typical DCO frequency 58 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 PMM, Brown-Out Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS V(DVCC_BOR_IT-) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s V(DVCC_BOR_hys) BORH hysteresis tRESET Pulse length required at RST/NMI pin to accept a reset MIN 0.80 TYP 1.30 60 MAX UNIT 1.45 V 1.50 V 250 mV 2 s PMM, Core Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V DVCC 3.6 V, 0 mA I(VCORE) 21 mA 1.90 V VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V DVCC 3.6 V, 0 mA I(VCORE) 21 mA 1.80 V VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2 V DVCC 3.6 V, 0 mA I(VCORE) 17 mA 1.60 V VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V DVCC 3.6 V, 0 mA I(VCORE) 13 mA 1.40 V VCORE3(LPM) Core voltage, low-current 2.4 V DVCC 3.6 V, 0 A I(VCORE) 30 A mode, PMMCOREV = 3 1.94 V VCORE2(LPM) Core voltage, low-current 2.2 V DVCC 3.6 V, 0 A I(VCORE) 30 A mode, PMMCOREV = 2 1.84 V VCORE1(LPM) Core voltage, low-current 2 V DVCC 3.6 V, 0 A I(VCORE) 30 A mode, PMMCOREV = 1 1.64 V VCORE0(LPM) Core voltage, low-current 1.8 V DVCC 3.6 V, 0 A I(VCORE) 30 A mode, PMMCOREV = 0 1.44 V PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.6 V I(SVSH) V(SVSH_IT-) V(SVSH_IT+) (1) SVS current consumption SVSH on voltage level (1) SVSH off voltage level (1) TYP MAX 0 UNIT nA SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200 nA SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 2.0 A SVSHE = 1, SVSHRVL = 0 1.59 1.64 1.69 SVSHE = 1, SVSHRVL = 1 1.79 1.84 1.91 SVSHE = 1, SVSHRVL = 2 1.98 2.04 2.11 SVSHE = 1, SVSHRVL = 3 2.10 2.16 2.23 SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.81 SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.01 SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.21 SVSHE = 1, SVSMHRRL = 3 2.20 2.26 2.33 SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.48 SVSHE = 1, SVSMHRRL = 5 2.56 2.70 2.84 SVSHE = 1, SVSMHRRL = 6 2.85 3.00 3.15 SVSHE = 1, SVSMHRRL = 7 2.85 3.00 3.15 V V The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage. Copyright (c) 2010-2012, Texas Instruments Incorporated 59 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com PMM, SVS High Side (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tpd(SVSH) SVSH propagation delay t(SVSH) SVSH on/off delay time dVDVCC/dt DVCC rise time MIN TYP SVSHE = 1, dVDVCC/dt = 10 mV/s, SVSHFP = 1 2.5 SVSHE = 1, dVDVCC/dt = 1 mV/s, SVSHFP = 0 20 SVSHE = 01, SVSHFP = 1 12.5 SVSHE = 01, SVSHFP = 0 100 0 MAX UNIT s s 1000 V/s MAX UNIT PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMHE = 0, DVCC = 3.6 V I(SVMH) V(SVMH) SVMH current consumption SVMH on or off voltage level (1) 0 nA SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200 nA SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 2.0 A SVMHE = 1, SVSMHRRL = 0 1.65 1.74 1.86 SVMHE = 1, SVSMHRRL = 1 1.85 1.94 2.02 SVMHE = 1, SVSMHRRL = 2 2.02 2.14 2.22 SVMHE = 1, SVSMHRRL = 3 2.18 2.26 2.35 SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.48 SVMHE = 1, SVSMHRRL = 5 2.56 2.70 2.84 SVMHE = 1, SVSMHRRL = 6 2.85 3.00 3.15 SVMHE = 1, SVSMHRRL = 7 2.85 3.00 3.15 SVMHE = 1, SVMHOVPE = 1 tpd(SVMH) t(SVMH) (1) SVMH propagation delay SVMH on or off delay time TYP V 3.75 SVMHE = 1, dVDVCC/dt = 10 mV/s, SVMHFP = 1 SVMHE = 1, dVDVCC/dt = 1 mV/s, SVMHFP = 0 2.5 s 20 s SVMHE = 01, SVSMFP = 1 12.5 s SVMHE = 01, SVMHFP = 0 100 s The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage. PMM, SVS Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSLE = 0, PMMCOREV = 2 I(SVSL) SVSL current consumption tpd(SVSL) SVSL propagation delay t(SVSL) SVSL on/off delay time TYP MAX 0 UNIT nA SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 nA SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 2.0 A SVSLE = 1, dVCORE/dt = 10 mV/s, SVSLFP = 1 2.5 SVSLE = 1, dVCORE/dt = 1 mV/s, SVSLFP = 0 20 SVSLE = 01, SVSLFP = 1 12.5 SVSLE = 01, SVSLFP = 0 100 s s PMM, SVM Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMLE = 0, PMMCOREV = 2 I(SVML) 60 SVML current consumption TYP MAX UNIT 0 nA SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 nA SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 2.0 A Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 PMM, SVM Low Side (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tpd(SVML) SVML propagation delay t(SVML) SVML on/off delay time TEST CONDITIONS MIN TYP SVMLE = 1, dVCORE/dt = 10 mV/s, SVMLFP = 1 2.5 SVMLE = 1, dVCORE/dt = 1 mV/s, SVMLFP = 0 20 SVMLE = 01, SVMLFP = 1 12.5 SVMLE = 01, SVMLFP = 0 100 MAX UNIT s s Wake-Up From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TYP MAX fMCLK 4 MHz MIN 3 6.5 UNIT 1 MHz < fMCLK < 4 MHz 4 8.0 150 165 s tWAKE-UP-FAST Wake-up time from LPM2, LPM3, or LPM4 to active mode (1) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 1 tWAKE-UP-SLOW Wake-up time from LPM2, LPM3 or LPM4 to active mode (2) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 0 tWAKE-UP-LPM5 Wake-up time from LPM3.5 or LPM4.5 to active mode (3) 2 3 ms tWAKE-UP-RESET Wake-up time from RST or BOR event to active mode (3) 2 3 ms (1) (2) (3) s This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low-side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low-side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). This value represents the time from the wakeup event to the reset vector execution. Timer_A, Timers TA0, TA1, and TA2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fTA Timer_A input clock frequency Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% 10% 1.8 V, 3 V tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V, 3 V MIN TYP MAX UNIT 20 MHz 20 ns Timer_B, Timer TB0 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTB Timer_B input clock frequency Internal: SMCLK, ACLK External: TBCLK Duty cycle = 50% 10% tTB,cap Timer_B capture timing All capture inputs, Minimum pulse duration required for capture Copyright (c) 2010-2012, Texas Instruments Incorporated VCC 1.8 V, 3 V 1.8 V, 3 V MIN 20 TYP MAX UNIT 20 MHz ns 61 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Battery Backup over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VBAT = 1.7 V, DVCC not connected, RTC running IVBAT Current into VBAT terminal in VBAT = 2.2 V, case no primary battery is DVCC not connected, connected. RTC running VBAT = 3 V, DVCC not connected, RTC running VCC MIN TYP TA = -40C 0.43 TA = 25C 0.52 TA = 60C 0.58 TA = 85C 0.64 TA = -40C 0.50 TA = 25C 0.59 TA = 60C 0.64 TA = 85C 0.71 TA = -40C 0.68 TA = 25C 0.75 TA = 60C 0.79 TA = 85C VSWITCH RON_VBAT On-resistance of switch between VBAT and VBAK VBAT3 VBAT to ADC input channel 12: VBAT divide, VBAT3 VBAT /3 tSample,VBA CVCC = 4.7 F A 1.59 1.69 SVSHRL = 1 1.79 1.91 SVSHRL = 2 1.98 2.11 SVSHRL = 3 2.10 2.23 0.35 1 1.8 V 0.6 5% 3V 1.0 5% 3.6 V 1.2 5% 0V VBAT to ADC: Sampling time ADC12ON = 1, required if VBAT3 selected Error of conversion result 1 LSB 1000 VCHVx Charger end voltage 2.65 Charge limiting resistor A VSVSH_IT- T3 RCHARGE A SVSHRL = 0 VBAT = 1.8 V UNIT 0.86 General Switch-over level (VCC to VBAT) MAX CHVx = 2 V k V ns 2.7 2.9 CHCx = 1 5 CHCx = 2 10 CHCx = 3 20 V k USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) t UART receive deglitch time (1) (1) 62 TEST CONDITIONS VCC MIN Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% 10% TYP MAX UNIT fSYSTEM MHz 1 MHz 2.2 V 50 600 3V 50 600 ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 11 and ) PARAMETER fUSCI TEST CONDITIONS VCC USCI input clock frequency PMMCOREV = 0 tSU,MI SOMI input data setup time PMMCOREV = 3 PMMCOREV = 0 tHD,MI SOMI input data hold time PMMCOREV = 3 tVALID,MO SIMO output data valid time (2) SIMO output data hold time (2) (3) 55 3V 38 2.4 V 30 3V 25 1.8 V 0 3V 0 2.4 V 0 3V 0 MAX UNIT fSYSTEM MHz ns ns ns ns 1.8 V 20 3V 18 UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 3 2.4 V 16 3V 15 1.8 V -10 3V -8 2.4 V -10 3V -8 (3) CL = 20 pF, PMMCOREV = 3 (1) 1.8 V TYP UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 0 CL = 20 pF, PMMCOREV = 0 tHD,MO MIN SMCLK, ACLK, Duty cycle = 50% 10% ns ns ns ns fUCxCLK = 1/2tLO/HI with tLO/HI max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 11 and . Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 11 and . 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 11. SPI Master Mode, CKPH = 0 Copyright (c) 2010-2012, Texas Instruments Incorporated 63 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,MI tSU,MI SOMI tHD,MO tVALID,MO SIMO Figure 12. SPI Master Mode, CKPH = 1 64 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 13 and Figure 14) PARAMETER TEST CONDITIONS PMMCOREV = 0 tSTE,LEAD STE lead time, STE low to clock PMMCOREV = 3 PMMCOREV = 0 tSTE,LAG STE lag time, Last clock to STE high PMMCOREV = 3 PMMCOREV = 0 tSTE,ACC STE access time, STE low to SOMI data out PMMCOREV = 3 PMMCOREV = 0 tSTE,DIS STE disable time, STE high to SOMI high impedance PMMCOREV = 3 PMMCOREV = 0 tSU,SI SIMO input data setup time PMMCOREV = 3 PMMCOREV = 0 tHD,SI SIMO input data hold time PMMCOREV = 3 tVALID,SO tHD,SO (1) (2) (3) SOMI output data valid time (2) SOMI output data hold time (3) VCC MIN 1.8 V 11 3V 8 2.4 V 7 3V 6 1.8 V 3 3V 3 2.4 V 3 3V 3 TYP MAX ns ns ns ns 1.8 V 66 3V 50 2.4 V 36 3V 30 1.8 V 30 3V 23 2.4 V 16 3V 13 1.8 V 5 3V 5 2.4 V 2 3V 2 1.8 V 5 3V 5 2.4 V 5 3V 5 UNIT ns ns ns ns ns ns ns ns UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 0 1.8 V 76 3V 60 UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 3 2.4 V 44 3V 40 CL = 20 pF, PMMCOREV = 0 1.8 V 18 3V 12 CL = 20 pF, PMMCOREV = 3 2.4 V 10 3V 8 ns ns ns ns fUCxCLK = 1/2tLO/HI with tLO/HI max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)). For the master's parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 13 and Figure 14. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 13 and Figure 14. Copyright (c) 2010-2012, Texas Instruments Incorporated 65 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 13. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 14. SPI Slave Mode, CKPH = 1 66 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15) PARAMETER TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% 10% MAX UNIT fSYSTEM MHz 400 kHz fUSCI USCI input clock frequency fSCL SCL clock frequency tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 2.2 V, 3 V 0 ns tSU,DAT Data setup time 2.2 V, 3 V 250 ns 2.2 V, 3 V fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz tSU,STO Setup time for STOP tSP Pulse width of spikes suppressed by input filter fSCL > 100 kHz tSU,STA tHD,STA 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V 0 4.0 s 0.6 4.7 s 0.6 4.0 s 0.6 2.2 V 50 600 3V 50 600 tHD,STA ns tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 15. I2C Mode Timing Copyright (c) 2010-2012, Texas Instruments Incorporated 67 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com LCD_B, Recommended Operating Conditions PARAMETER CONDITIONS MIN NOM MAX UNIT Supply voltage range, charge pump enabled, VLCD 3.6 V LCDCPEN = 1, 0000 < VLCDx 1111 (charge pump enabled, VLCD 3.6 V) 2.2 3.6 V Supply voltage range, charge pump enabled, VLCD 3.3 V LCDCPEN = 1, 0000 < VLCDx 1100 (charge pump enabled, VLCD 3.3 V) 2.0 3.6 V VCC,LCD_B, int. bias Supply voltage range, internal biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V VCC,LCD_B, Supply voltage range, external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V Supply voltage range, external LCD voltage, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.0 3.6 V VLCDCAP/R33 External LCD voltage at LCDCAP/R33, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.4 3.6 V CLCDCAP Capacitor on LCDCAP when charge pump enabled LCDCPEN = 1, VLCDx > 0000 (charge pump enabled) 4.7 10 F fFrame LCD frame frequency range fLCD = 2 x mux x fFRAME (mux = 1 (static), 2, 3, 4) 100 Hz fACLK,in ACLK input frequency range CPanel Panel capacitance VCC,LCD_B, CP en,3.6 VCC,LCD_B, CP en,3.3 ext. bias VCC,LCD_B, VLCDEXT 4.7 0 40 kHz 100-Hz frame frequency 30 32 10000 pF VCC + 0.2 V VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 VR23,1/3bias Analog input voltage at R23 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR13 VR03 + 2/3 x (VR33-VR03) VR33 V VR13,1/3bias Analog input voltage at R13 with 1/3 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR03 VR03 + 1/3 x (VR33-VR03) VR23 V VR13,1/2bias Analog input voltage at R13 with 1/2 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1 VR03 VR03 + 1/2 x (VR33-VR03) VR33 V VR03 Analog input voltage at R03 R0EXT = 1 VLCD-VR03 Voltage difference between VLCD and R03 VLCDREF/R13 External LCD reference voltage applied VLCDREFx = 01 at LCDREF/R13 68 LCDCPEN = 0, R0EXT = 1 2.4 VSS V 2.4 0.8 1.2 VCC+0 .2 V 1.5 V Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 LCD_B, Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VLCD LCD voltage TEST CONDITIONS VCC MIN TYP MAX UNIT VLCDx = 0000, VLCDEXT = 0 2.4 V - 3.6 V VCC V LCDCPEN = 1, VLCDx = 0001 2 V - 3.6 V 2.60 V LCDCPEN = 1, VLCDx = 0010 2 V - 3.6 V 2.66 V LCDCPEN = 1, VLCDx = 0011 2 V - 3.6 V 2.72 V LCDCPEN = 1, VLCDx = 0100 2 V - 3.6 V 2.79 V LCDCPEN = 1, VLCDx = 0101 2 V - 3.6 V 2.85 V LCDCPEN = 1, VLCDx = 0110 2 V - 3.6 V 2.92 V LCDCPEN = 1, VLCDx = 0111 2 V - 3.6 V 2.98 V LCDCPEN = 1, VLCDx = 1000 2 V - 3.6 V 3.05 V LCDCPEN = 1, VLCDx = 1001 2 V - 3.6 V 3.10 V LCDCPEN = 1, VLCDx = 1010 2 V - 3.6 V 3.17 V LCDCPEN = 1, VLCDx = 1011 2 V - 3.6 V 3.24 V LCDCPEN = 1, VLCDx = 1100 2 V - 3.6 V 3.30 V LCDCPEN = 1, VLCDx = 1101 2.2 V - 3.6 V 3.36 V LCDCPEN = 1, VLCDx = 1110 2.2 V - 3.6 V 3.42 LCDCPEN = 1, VLCDx = 1111 2.2 V - 3.6 V 3.48 V 3.6 V ICC,Peak,CP Peak supply currents due to charge pump activities LCDCPEN = 1, VLCDx = 1111 2.2 V 400 A tLCD,CP,on Time to charge CLCD when discharged CLCD = 4.7 F, LCDCPEN = 01, VLCDx = 1111 2.2 V 100 ICP,Load Maximum charge pump load current LCDCPEN = 1, VLCDx = 1111 2.2 V RLCD,Seg LCD driver output impedance, segment lines LCDCPEN = 1, VLCDx = 1000, ILOAD = 10 A 2.2 V 10 k RLCD,COM LCD driver output impedance, common lines LCDCPEN = 1, VLCDx = 1000, ILOAD = 10 A 2.2 V 10 k MAX UNIT 500 ms 50 A 12-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V V(Ax) Analog input voltage range (2) All ADC12 analog input pins Ax IADC12_A Operating supply current into AVCC terminal (3) fADC12CLK = 5 MHz (4) CI Input capacitance Only one terminal Ax can be selected at one time RI Input MUX ON resistance 0 V VIN V(AVCC) (1) (2) (3) (4) VCC MIN TYP 2.2 0 3.6 V AVCC V 2.2 V 150 200 3V 150 250 2.2 V 20 25 pF 200 1900 10 A The leakage current is specified by the digital I/O input leakage. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. If the reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are required. See REF, External Reference and REF, Built-In Reference. The internal reference supply current is not included in current consumption parameter IADC12. ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0 Copyright (c) 2010-2012, Texas Instruments Incorporated 69 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com 12-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC For specified performance of ADC12 linearity parameters using an external reference voltage or AVCC as reference (1) fADC12CLK ADC conversion clock For specified performance of ADC12 linearity parameters using the internal reference (2) 2.2 V, 3 V For specified performance of ADC12 linearity parameters using the internal reference (3) fADC12OSC tCONVERT tSample (1) (2) (3) (4) (5) (6) Internal ADC12 oscillator (4) Conversion time MIN TYP MAX 0.45 4.8 5.0 0.45 2.4 4.0 0.45 2.4 2.7 4.8 5.4 ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 REFON = 0, Internal oscillator, ADC12OSC used for ADC conversion clock 2.2 V, 3 V 2.4 RS = 400 , RI = 200 , CI = 20 pF, = [RS + RI] x CI (6) MHz MHz 3.1 s External fADC12CLK from ACLK, MCLK or SMCLK, ADC12SSEL 0 Sampling time UNIT (5) 2.2 V, 3 V 1000 ns REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0, SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5 MHz. SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1 SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC divided by 2. The ADC12OSC is sourced directly from MODOSC inside the UCS. 13 x ADC12DIV x 1/fADC12CLK Approximately ten Tau () are needed to get an error of less than 0.5 LSB: tSample = ln(2n+1) x (RS + RI) x CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance 12-Bit ADC, Linearity Parameters Using an External Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER EI Integral linearity error (1) ED Differential linearity error (1) EO Offset error (3) EG Gain error (3) ET (1) (2) (3) Total unadjusted error TEST CONDITIONS 1.4 V dVREF 1.6 V (2) 1.6 V < dVREF VCC MIN TYP 2 2.2 V, 3 V (2) (2) MAX 1.7 2.2 V, 3 V 1 (2) 2.2 V, 3 V 3 5.6 dVREF > 2.2 V (2) 2.2 V, 3 V 1.5 3.5 (2) 2.2 V, 3 V 1 2.5 dVREF 2.2 V (2) 2.2 V, 3 V 3.5 7.1 dVREF > 2.2 V (2) 2.2 V, 3 V 2 5 dVREF 2.2 V UNIT LSB LSB LSB LSB LSB Parameters are derived using the histogram method. The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-. VR+ < AVCC. VR-> AVSS. Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 , and two decoupling capacitors, 10 F and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the MSP430F5xx and MSP430F6xx Family User's Guide (SLAU208). Parameters are derived using a best fit curve. 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER (1) EI Integral linearity error ED Differential linearity error (1) (1) (2) 70 TEST CONDITIONS See (2) See (2) VCC MIN TYP MAX UNIT 2.2 V, 3 V 1.7 LSB 2.2 V, 3 V 1 LSB Parameters are derived using the histogram method. AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EO Offset error See (2) 2.2 V, 3 V 1 2 LSB EG Gain error (3) See (2) 2.2 V, 3 V 2 4 LSB ET Total unadjusted error See (2) 2.2 V, 3 V 2 5 LSB TYP MAX UNIT (3) (3) Parameters are derived using a best fit curve. 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS (1) PARAMETER EI Integral linearity error (2) ED Differential linearity error (2) EO Offset error (3) EG Gain error (3) ET Total unadjusted error (1) (2) (3) (4) ADC12SR = 0, REFOUT = 1 fADC12CLK 4.0 MHz ADC12SR = 0, REFOUT = 0 fADC12CLK 2.7 MHz ADC12SR = 0, REFOUT = 1 fADC12CLK 4.0 MHz ADC12SR = 0, REFOUT = 1 fADC12CLK 2.7 MHz ADC12SR = 0, REFOUT = 0 fADC12CLK 2.7 MHz ADC12SR = 0, REFOUT = 1 fADC12CLK 4.0 MHz ADC12SR = 0, REFOUT = 0 fADC12CLK 2.7 MHz ADC12SR = 0, REFOUT = 1 fADC12CLK 4.0 MHz ADC12SR = 0, REFOUT = 0 fADC12CLK 2.7 MHz ADC12SR = 0, REFOUT = 1 fADC12CLK 4.0 MHz ADC12SR = 0, REFOUT = 0 fADC12CLK 2.7 MHz VCC MIN 1.7 2.2 V, 3 V 2.5 -1 +1.5 -1 +2.5 2.2 V, 3 V 1 2.2 V, 3 V 2.2 V, 3 V 2 4 2 4 1 2.5 2.2 V, 3 V LSB LSB LSB (4) VREF 5 LSB 1% 2 LSB 1% (4) VREF The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = VR+ - VR-. Parameters are derived using the histogram method. Parameters are derived using a best fit curve. The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this mode the reference voltage used by the ADC12_A is not available on a pin. 12-Bit ADC, Temperature Sensor and Built-In VMID over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VSENSOR See (1) TCSENSOR TEST CONDITIONS ADC12ON = 1, INCH = 0Ah, TA = 0C ADC12ON = 1, INCH = 0Ah VCC MIN TYP 2.2 V 680 3V 680 2.2 V 2.25 3V 2.25 MAX mV mV/C tSENSOR(sample) Sample time required if channel 10 is selected (2) (3) ADC12ON = 1, INCH = 0Ah, Error of conversion result 1 LSB 2.2 V 100 3V 100 VMID AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh, VMID is approximately 0.5 x VAVCC 2.2 V 1.06 1.1 1.14 3V 1.46 1.5 1.54 tVMID(sample) Sample time required if channel 11 is selected (4) ADC12ON = 1, INCH = 0Bh, Error of conversion result 1 LSB 2.2 V, 3 V 1000 (1) (2) (3) (4) UNIT s V ns The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of the temperature sensor. The temperature sensor offset can be significant. A single-point calibration is recommended to minimize the offset error of the built-in temperature sensor. The TLV structure contains calibration values for 30C 3C and 85C 3C for each of the available reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR x (Temperature,C) + VSENSOR, where TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's Guide (SLAU208). The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on). The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. Copyright (c) 2010-2012, Texas Instruments Incorporated 71 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Typical Temperature Sensor Voltage - mV 1000 950 900 850 800 750 700 650 600 550 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Ambient Temperature - C Figure 16. Typical Temperature Sensor Voltage REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER VeREF+ Positive external reference voltage input VREF-/VeREF- VeREF+ - VREF-/VeREF- IVeREF+, IVREF-/VeREF- CVREF+/(1) (2) (3) (4) (5) 72 TEST CONDITIONS MAX UNIT 1.4 AVCC V (3) 0 1.2 V (4) 1.4 AVCC V VeREF+ > VREF-/VeREF- (2) Negative external reference voltage input VeREF+ > VREF-/VeREF- Differential external reference voltage input VeREF+ > VREF-/VeREF- Static input current Capacitance at VREF+/terminal (5) VCC MIN TYP 1.4 V VeREF+ VAVCC , VeREF- = 0 V, fADC12CLK = 5 MHz, ADC12SHTx = 1h, Conversion rate 200 ksps 2.2 V, 3 V -26 26 A 1.4 V VeREF+ VAVCC , VeREF- = 0 V, fADC12CLK = 5 MHZ, ADC12SHTx = 8h, Conversion rate 20 ksps 2.2 V, 3 V -1.2 +1.2 A 10 F The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Two decoupling capacitors, 10 F and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS REFVSEL = {2} for 2.5 V, REFON = REFOUT = 1 , IVREF+ = 0 A VREF+ REFVSEL = {1} for 2 V, Positive built-in reference REFON = REFOUT = 1, voltage output IVREF+ = 0 A REFVSEL = {0} for 1.5 V, REFON = REFOUT = 1, IVREF+ = 0 A AVCC(min) IREF+ VCC TYP MAX 3V 2.5 1% 3V 2.0 1% 2.2 V, 3 V 1.5 1% REFVSEL = {0} for 1.5 V AVCC minimum voltage, Positive built-in reference REFVSEL = {1} for 2 V active REFVSEL = {2} for 2.5 V Operating supply current into AVCC terminal (2) (3) MIN UNIT V 2.2 2.3 V 2.8 ADC12SR = 1 (4), REFON = 1, REFOUT = 0, REFBURST = 0 3V 70 100 A ADC12SR = 1 (4), REFON = 1, REFOUT = 1, REFBURST = 0 3V 0.45 0.75 mA ADC12SR = 0 (4), REFON = 1, REFOUT = 0, REFBURST = 0 3V 210 310 A ADC12SR = 0 (4), REFON = 1, REFOUT = 1, REFBURST = 0 3V 0.95 1.7 mA IL(VREF+) Load-current regulation, VREF+ terminal (5) REFVSEL = {0, 1, 2} IVREF+ = +10 A / -1000 A AVCC = AVCC(min) for each reference level, REFVSEL = {0, 1, 2}, REFON = REFOUT = 1 CVREF+ Capacitance at VREF+ terminal REFON = REFOUT = 1, (6) 0 mA IVREF+ IVREF+(max) TCREF+ Temperature coefficient of built-in reference (7) IVREF+ is a constant in the range of 0 mA IVREF+ -1 mA REFOUT = 0 2.2 V, 3 V 20 TCREF+ Temperature coefficient of built-in reference (7) IVREF+ is a constant in the range of 0 mA IVREF+ -1 mA REFOUT = 1 2.2 V, 3 V 20 50 ppm/ C PSRR_DC Power supply rejection ratio (dc) AVCC = AVCC(min) - AVCC(max), TA = 25C, REFVSEL = {0, 1, 2}, REFON = 1, REFOUT = 0 or 1 120 300 V/V PSRR_AC Power supply rejection ratio (ac) AVCC = AVCC(min) - AVCC(max), TA = 25C, REFVSEL = {0, 1, 2}, REFON = 1, REFOUT = 0 or 1 1 (1) (2) (3) (4) (5) (6) (7) 1500 2.2 V, 3 V 20 2500 V/mA 100 pF ppm/ C mV/V The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as, used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference for the conversion and utilizes the smaller buffer. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without external load. The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with REFON = 1 and REFOUT = 0. For devices without the ADC12, the parametric with ADC12SR = 0 are applicable. Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or other external factors. Two decoupling capacitors, 10 F and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Calculated using the box method: (MAX(-40 to 85C) - MIN(-40 to 85C)) / MIN(-40 to 85C)/(85C - (-40C)). Copyright (c) 2010-2012, Texas Instruments Incorporated 73 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com REF, Built-In Reference (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCC MIN AVCC = AVCC(min) - AVCC(max), REFVSEL = {0, 1, 2}, REFOUT = 0, REFON = 0 1 tSETTLE (8) TYP MAX UNIT 75 Settling time of reference AVCC = AVCC(min) - AVCC(max), voltage (8) CVREF = CVREF(max), REFVSEL = {0, 1, 2}, REFOUT = 1, REFON = 0 1 s 75 The condition is that the error in a conversion started after tREFON is less than 0.5 LSB. The settling time depends on the external capacitive load when REFOUT = 1. 12-Bit DAC, Supply Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER AVCC TEST CONDITIONS Analog supply voltage DAC12AMPx = 2, DAC12IR = 0, DAC12IOG = 1, DAC12_xDAT = 0800h, VeREF+ = VREF+ = 1.5 V Supply current, single DAC channel (1) IDD VCC AVCC = DVCC, AVSS = DVSS = 0 V (2) MIN 3V DAC12AMPx = 2, DAC12IR = 1, DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC PSRR (1) (2) (3) (4) Power supply rejection ratio (3) (4) DAC12_xDAT = 800h, VeREF+ = 1.5 V or 2.5 V, AVCC = 100 mV MAX UNIT 3.60 V 65 110 125 165 A 2.2 V, 3 V DAC12AMPx = 7, DAC12IR = 1, DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC DAC12_xDAT = 800h, VeREF+ = 1.5 V, AVCC = 100 mV TYP 2.20 250 350 750 1100 2.2 V 70 3V 70 dB No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications. PSRR = 20 log (AVCC / VDAC12_xOUT) The internal reference is not used. 12-Bit DAC, Linearity Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17) PARAMETER TEST CONDITIONS TYP MAX 2.2 V 2 4 (2) VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3V 2 4 VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V 0.4 1 (2) VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3V 0.4 1 Resolution 12-bit monotonic INL Integral nonlinearity (1) VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 DNL Differential nonlinearity (1) (1) VCC MIN 12 UNIT bits LSB LSB (2) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) x (VeREF+/4095) x DAC12_xDAT, DAC12IR = 1. This parameter is not production tested. 74 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 12-Bit DAC, Linearity Specifications (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17) PARAMETER TEST CONDITIONS Without calibration (1) EO (3) Offset voltage With calibration dE(O)/dT Offset error temperature coefficient (1) EG Gain error dE(G)/dT Gain temperature coefficient (1) tOffset_Cal Time for offset calibration (4) (1) (3) VCC VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3V VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3V MIN TYP UNIT 21 (2) 21 mV 1.5 (2) 1.5 With calibration 2.2 V, 3 V 10 VeREF+ = 1.5 V 2.2 V 2.5 VeREF+ = 2.5 V 3V 2.5 2.2 V, 3 V V/C %FSR ppm of FSR/ C 10 DAC12AMPx = 2 165 DAC12AMPx = 3, 5 2.2 V, 3 V 66 DAC12AMPx = 4, 6, 7 (3) (4) MAX ms 16.5 The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect accuracy and is not recommended. DAC VOUT DAC Output VR+ RLoad = Ideal transfer function AVCC 2 CLoad = 100 pF Offset Error Positive Negative Gain Error DAC Code Figure 17. Linearity Test Load Conditions and Gain/Offset Definition Copyright (c) 2010-2012, Texas Instruments Incorporated 75 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com 12-Bit DAC, Output Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC No load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 No load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 Output voltage range (1) (see Figure 18) VO TYP MAX 0 0.005 AVCC - 0.05 AVCC 2.2 V, 3 V RLoad = 3 k, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 RLoad = 3 k, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 CL(DAC12) Maximum DAC12 load capacitance 2.2 V, 3 V IL(DAC12) DAC12AMPx = 2, DAC12xDAT = 0FFFh, Maximum DAC12 VO/P(DAC12) > AVCC - 0.3 load current DAC12AMPx = 2, DAC12xDAT = 0h, VO/P(DAC12) < 0.3 V 2.2 V, 3 V V 0 0.1 AVCC - 0.13 AVCC 100 pF mA 1 Output resistance RLoad = 3 k, VO/P(DAC12) > AVCC - 0.3 V, (see Figure 18) DAC12_xDAT = 0FFFh 2.2 V, 3 V 150 250 150 250 RLoad = 3 k, 0.3 V VO/P(DAC12) AVCC - 0.3 V (1) UNIT -1 RLoad = 3 k, VO/P(DAC12) < 0.3 V, DAC12AMPx = 2, DAC12_xDAT = 0h RO/P(DAC12) MIN 6 Data is valid after the offset calibration of the output amplifier. RO/P(DAC12_x) ILoad Max RLoad AVCC DAC12 2 O/P(DAC12_x) CLoad = 100 pF Min 0.3 AVCC - 0.3 V VOUT AVCC Figure 18. DAC12_x Output Resistance Tests 76 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 12-Bit DAC, Reference Input Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS DAC12IR = 0 (1) Reference input voltage range VeREF+ VCC (2) 2.2 V, 3 V DAC12IR = 1 (3) (4) DAC12_0 IR = DAC12_1 IR = 0 Ri(VREF+), Ri(VeREF+) MIN (6) AVCC /3 AVCC + 0.2 AVCC AVCC + 0.2 UNIT V M 48 2.2 V, 3 V DAC12_0 IR = 0, DAC12_1 IR = 1 48 DAC12_0 IR = DAC12_1 IR = 1, DAC12_0 SREFx = DAC12_1 SREFx (6) (1) (2) (3) (4) (5) MAX 20 DAC12_0 IR = 1, DAC12_1 IR = 0 Reference input resistance (5) TYP k 24 For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / [3 x (1 + EG)]. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC). The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / (1 + EG). This impedance depends on tradeoff in power savings. Current devices have 48 k for each channel when divide is enabled. Can be increased if performance can be maintained. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance. 12-Bit DAC, Dynamic Specifications VREF = VCC, DAC12IR = 1 (see Figure 19 and Figure 20), over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tON DAC12 on time TEST CONDITIONS DAC12_xDAT = 800h, ErrorV(O) < 0.5 LSB (1) (see Figure 19) VCC MIN DAC12AMPx = 0 {2, 3, 4} DAC12AMPx = 0 {5, 6} 2.2 V, 3 V DAC12AMPx = 0 7 DAC12AMPx = 2 tS(FS) Settling time, full scale DAC12_xDAT = 80h F7Fh 80h DAC12AMPx = 3, 5 2.2 V, 3 V DAC12AMPx = 4, 6, 7 tS(C-C) Settling time, code to code DAC12_xDAT = 3F8h 408h 3F8h, BF8h C08h BF8h DAC12AMPx = 2 DAC12AMPx = 3, 5 Slew rate DAC12_xDAT = 80h F7Fh 80h (2) 2.2 V, 3 V Glitch energy DAC12_xDAT = 800h 7FFh 800h (1) (2) 15 30 6 12 100 200 40 80 15 30 UNIT s s s 1 2.2 V, 3 V DAC12AMPx = 4, 6, 7 DAC12AMPx = 7 120 2 DAC12AMPx = 4, 6, 7 DAC12AMPx = 3, 5 MAX 60 5 DAC12AMPx = 2 SR TYP 0.05 0.35 0.35 1.10 1.50 5.20 2.2 V, 3 V 35 V/s nV-s RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 19. Slew rate applies to output voltage steps 200 mV. Conversion 1 VOUT DAC Output ILoad RLoad = 3 kW Conversion 2 Conversion 3 1/2 LSB Glitch Energy AVCC 2 RO/P(DAC12.x) 1/2 LSB CLoad = 100 pF tsettleLH tsettleHL Figure 19. Settling Time and Glitch Energy Testing Copyright (c) 2010-2012, Texas Instruments Incorporated 77 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRHL tSRLH Figure 20. Slew Rate Testing 12-Bit DAC, Dynamic Specifications (Continued) over recommended ranges of supply voltage and TA = 25C (unless otherwise noted) PARAMETER BW-3dB TEST CONDITIONS 3-dB bandwidth, VDC = 1.5 V, VAC = 0.1 VPP (see Figure 21) MIN TYP MAX UNIT 40 DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h 2.2 V, 3 V 180 DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h kHz 550 DAC12_0DAT = 800h, No load, DAC12_1DAT = 80h F7Fh, RLoad = 3 k, fDAC12_0OUT = 10 kHz at 50/50 duty cycle Channel-to-channel crosstalk (1) (see Figure 22) (1) VCC DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h -80 2.2 V, 3 V DAC12_0DAT = 80h F7Fh, RLoad = 3 k, DAC12_1DAT = 800h, No load, fDAC12_0OUT = 10 kHz at 50/50 duty cycle dB -80 RLoad = 3 k, CLoad = 100 pF RLoad = 3 kW ILoad VeREF+ AVCC DAC12_x 2 DACx AC CLoad = 100 pF DC Figure 21. Test Conditions for 3-dB Bandwidth Specification RLoad ILoad AVCC DAC12_0 2 DAC0 DAC12_xDAT 080h 7F7h 080h 7F7h 080h VOUT CLoad = 100 pF VREF+ VDAC12_yOUT RLoad ILoad AVCC DAC12_1 VDAC12_xOUT 2 DAC1 fToggle CLoad = 100 pF Figure 22. Crosstalk Test Conditions 78 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC Supply voltage MIN TYP 1.8 3.6 1.8 V IAVCC_COMP Comparator operating supply current into AVCC terminal, Excludes reference resistor ladder IAVCC_REF Quiescent current of local reference voltage amplifier into AVCC terminal VIC Common mode input range VOFFSET Input offset voltage CIN Input capacitance RSIN tPD tPD,filter Series input resistance Propagation delay, response time Propagation delay with filter active CBPWRMD = 00 MAX V 40 2.2 V 30 50 3V 40 65 CBPWRMD = 01 2.2 V, 3 V 10 30 CBPWRMD = 10 2.2 V, 3 V 0.1 0.5 CBREFACC = 1, CBREFLx = 01 0 A VCC - 1 V 20 CBPWRMD = 01, 10 10 5 ON - switch closed 3 A 22 CBPWRMD = 00 OFF - switch opened UNIT mV pF 4 50 k M CBPWRMD = 00, CBF = 0 450 ns CBPWRMD = 01, CBF = 0 600 ns CBPWRMD = 10, CBF = 0 50 s CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 00 0.35 0.6 1.0 s CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 01 0.6 1.0 1.8 s CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 10 1.0 1.8 3.4 s CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 11 1.8 3.4 6.5 s tEN_CMP Comparator enable time, settling time CBON = 0 to CBON = 1 CBPWRMD = 00, 01, 10 1 2 s tEN_REF Resistor reference enable time CBON = 0 to CBON = 1 0.3 1.5 s VCB_REF Reference voltage for a given tap VIN = reference into resistor ladder, n = 0 to 31 VIN x (n+1) / 32 VIN x (n+1.5) / 32 V Copyright (c) 2010-2012, Texas Instruments Incorporated VIN x (n+0.5) / 32 79 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Ports PU.0 and PU.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH High-level output voltage VUSB = 3.3 V 10%, IOH = -25 mA VOL Low-level output voltage VUSB = 3.3 V 10%, IOL = 25 mA VIH High-level input voltage VUSB = 3.3 V 10% VIL Low-level input voltage VUSB = 3.3 V 10% MIN TYP MAX 2.4 UNIT V 0.4 2.0 V V 0.8 V USB Output Ports DP and DM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH D+, D- single ended USB 2.0 load conditions VOL D+, D- single ended USB 2.0 load conditions Z(DRV) D+, D- impedance Including external series resistor of 27 tRISE Rise time tFALL Fall time MIN TYP MAX 2.8 3.6 UNIT V 0 0.3 V 28 44 Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 4 20 ns Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 4 20 ns MAX UNIT USB Input Ports DP and DM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP V(CM) Differential input common mode range 0.8 2.5 V Z(IN) Input impedance 300 VCRS Crossover voltage 1.3 VIL Static SE input logic low level 0.8 VIH Static SE input logic high level 2.0 V VDI Differential input voltage 0.2 V k 2.0 V V USB-PWR (USB Power System) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VLAUNCH VBUS detection threshold VBUS USB bus voltage VUSB USB LDO output voltage TEST CONDITIONS Normal operation MIN TYP 3.76 3.3 (1) MAX UNIT 3.75 V 5.5 V 9% V V18 Internal USB voltage IUSB_EXT Maximum external current from VUSB terminal (2) IDET USB LDO current overload detection (3) ISUSPEND Operating supply current into VBUS terminal. (4) CBUS VBUS terminal recommended capacitance 4.7 F CUSB VUSB terminal recommended capacitance 220 nF C18 V18 terminal recommended capacitance 220 nF tENABLE Settling time VUSB and V18 RPUR Pullup resistance of PUR terminal (1) (2) (3) (4) 80 1.8 USB LDO is on 60 USB LDO is on, USB PLL disabled Within 2%, recommended capacitances 70 110 V 12 mA 100 mA 250 A 2 ms 150 This voltage is for internal use only. No external dc loading should be applied. This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB operation. A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value. Does not include current contribution of Rpu and Rpd as outlined in the USB specification. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 USB-PLL (USB Phase-Locked Loop) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IPLL Operating supply current fPLL PLL frequency fUPD PLL reference frequency tLOCK PLL lock time tJitter PLL jitter TEST CONDITIONS VCC MIN TYP MAX 7 48 1.5 UNIT mA MHz 3 MHz 2 ms 1000 ps Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS DVCC(PGM/ERASE) Program and erase supply voltage IPGM Average supply current from DVCC during program IERASE Average supply current from DVCC during erase IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase tCPT Cumulative program time MIN TYP 1.8 3.6 3 See (1) 4 Program and erase endurance 10 MAX UNIT V 5 mA 2.5 mA 2 mA 16 ms 5 10 cycles tRetention Data retention duration TJ = 25C 100 tWord Word or byte program time See (2) 64 85 years s 0 Block program time for first byte or word See (2) 49 65 s tBlock, 1-(N-1) Block program time for each additional byte or word, except for last byte or word See (2) 37 49 s tBlock, N Block program time for last byte or word See (2) 55 73 s tSeg Erase Erase time for segment, mass erase, and bank erase when available See (2) 23 32 ms fMCLK,MGR MCLK frequency in marginal read mode (FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1) 0 1 MHz tBlock, (1) (2) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word or byte write and block write modes. These values are hardwired into the flash controller's state machine. JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 s tSBW, Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.2 V, 3 V 1 s En tSBW,Rst Spy-Bi-Wire return to normal operation time fTCK TCK input frequency (4-wire JTAG) (2) Rinternal Internal pulldown resistance on TEST (1) (2) 2.2 V 15 100 0 5 MHz 10 MHz 80 k 3V 0 2.2 V, 3 V 45 60 s Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. fTCK may be restricted to meet the timing requirements of the module selected. Copyright (c) 2010-2012, Texas Instruments Incorporated 81 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic S32...S39 LCDS32...LCDS39 P1REN.x P1DIR.x 0 0 Module X OUT 1 0 DVCC 1 P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x Bus Keeper EN Module X IN 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TA0CLK/ACLK/S39 P1.1/TA0.0/S38 P1.2/TA0.1/S37 P1.3/TA0.2/S36 P1.4/TA0.3/S35 P1.5/TA0.4/S34 P1.6/TA0.1/S33 P1.7/TA0.2/S32 D P1IE.x EN P1IRQ.x Q P1IFG.x P1SEL.x P1IES.x 82 Set Interrupt Edge Select Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 55. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) x P1.0/TA0CLK/ACLK/ S39 0 P1.1/TA0.0/S38 1 FUNCTION P1.0 (I/O) 2 3 P1.5/TA0.4/S34 P1.6/TA0.1/S33 4 5 6 0 0 1 0 ACLK 1 1 0 S39 X X 1 P1.1 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI0A capture input 0 1 0 Timer TA0.0 output 1 1 0 P1.2 (I/O) 7 X 1 0 0 0 1 0 1 1 0 S37 X X 1 I: 0; O: 1 0 0 0 1 0 P1.3 (I/O) Timer TA0.2 output 1 1 0 S36 X X 1 I: 0; O: 1 0 0 Timer TA0.CCI3A capture input 0 1 0 Timer TA0.3 output 1 1 0 S35 X X 1 P1.4 (I/O) P1.5 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI4A capture input 0 1 0 Timer TA0.4 output 1 1 0 S34 X X 1 P1.6 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI1B capture input 0 1 0 Timer TA0.1 output 1 1 0 P1.7 (I/O) Timer TA0.CCI2B capture input (1) X I: 0; O: 1 Timer TA0.1 output S33 P1.7/TA0.2/S32 LCDS32...39 0 Timer TA0.CCI2A capture input P1.4/TA0.3/S35 P1SEL.x I: 0; O: 1 Timer TA0.CCI1A capture input P1.3/TA0.2/S36 P1DIR.x Timer TA0.TA0CLK S38 P1.2/TA0.1/S37 CONTROL BITS/SIGNALS (1) X X 1 I: 0; O: 1 0 0 0 1 0 Timer TA0.2 output 1 1 0 S32 X X 1 X = Don't care Copyright (c) 2010-2012, Texas Instruments Incorporated 83 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic to LCD_B from LCD_B P2REN.x P2DIR.x 0 From Port Mapping 1 P2OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x From Port Mapping P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6/R03 P2.7/P2MAP7/LCDREF/R13 EN To Port Mapping D P2IE.x EN P2IRQ.x Q P2IFG.x P2SEL.x P2IES.x 84 Set Interrupt Edge Select Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 56. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/P2MAP0 x 0 FUNCTION P2.0 (I/O) Mapped secondary digital function P2.1/P2MAP1 1 P2.1 (I/O) Mapped secondary digital function P2.2/P2MAP2 2 P2.2 (I/O) Mapped secondary digital function P2.3/P2MAP3 3 P2.4/P2MAP4 4 P2.3 (I/O) Mapped secondary digital function P2.4 (I/O) Mapped secondary digital function P2.5/P2MAP5 5 P2.5 (I/O Mapped secondary digital function P2.6/P2MAP6/R03 6 P2.6 (I/O) Mapped secondary digital function R03 P2.7/P2MAP7/ LCDREF/R13 (1) 7 CONTROL BITS/SIGNALS (1) P2DIR.x P2SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 P2MAPx 19 19 19 19 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 19 = 31 19 19 X 1 I: 0; O: 1 0 Mapped secondary digital function X 1 19 LCDREF/R13 X 1 = 31 P2.7 (I/O) X = Don't care Copyright (c) 2010-2012, Texas Instruments Incorporated 85 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger Pad Logic S24...S31 LCDS24...LCDS31 P3REN.x P3DIR.x 0 0 Module X OUT 1 0 DVCC 1 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x Bus Keeper EN Module X IN 1 Direction 0: Input 1: Output 1 P3OUT.x DVSS P3.0/TA1CLK/CBOUT/S31 P3.1/TA1.0/S30 P3.2/TA1.1/S29 P3.3/TA1.2/S28 P3.4/TA2CLK/SMCLK/S27 P3.5/TA2.0/S26 P3.6/TA2.1/S25 P3.7/TA2.2/S24 D P3IE.x EN P3IRQ.x Q P3IFG.x P3SEL.x P3IES.x 86 Set Interrupt Edge Select Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 57. Port P3 (P3.0 to P3.7) Pin Functions PIN NAME (P3.x) x P3.0/TA1CLK/CBOUT/ S31 0 P3.1/TA1.0/S30 1 FUNCTION P3.0 (I/O) 2 3 P3.5/TA2.0/S26 P3.6/TA2.1/S25 4 5 6 0 0 1 0 CBOUT 1 1 0 S31 X X 1 P3.1 (I/O) I: 0; O: 1 0 0 Timer TA1.CCI0A capture input 0 1 0 Timer TA1.0 output 1 1 0 P3.2 (I/O) 7 X 1 0 0 0 1 0 1 1 0 S29 X X 1 I: 0; O: 1 0 0 0 1 0 P3.3 (I/O) Timer TA1.2 output 1 1 0 S28 X X 1 I: 0; O: 1 0 0 Timer TA2.TA2CLK 0 1 0 SMCLK 1 1 0 S27 X X 1 P3.4 (I/O) P3.5 (I/O) I: 0; O: 1 0 0 Timer TA2.CCI0A capture input 0 1 0 Timer TA2.0 output 1 1 0 S26 X X 1 P3.6 (I/O) I: 0; O: 1 0 0 Timer TA2.CCI1A capture input 0 1 0 Timer TA2.1 output 1 1 1 P3.7 (I/O) Timer TA2.CCI2A capture input (1) X I: 0; O: 1 Timer TA1.1 output S25 P3.7/TA2.2/S24 LCDS24...31 0 Timer TA1.CCI2A capture input P3.4/TA2CLK/SMCLK/ S27 P3SEL.x I: 0; O: 1 Timer TA1.CCI1A capture input P3.3/TA1.2/S28 P3DIR.x Timer TA1.TA1CLK S30 P3.2/TA1.1/S29 CONTROL BITS/SIGNALS (1) X X 1 I: 0; O: 1 0 0 0 1 0 Timer TA2.2 output 1 1 0 S24 X X 1 X = Don't care Copyright (c) 2010-2012, Texas Instruments Incorporated 87 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic S16...S23 LCDS16...LCDS23 P4REN.x P4DIR.x 0 0 Module X OUT 1 0 DVCC 1 P4DS.x 0: Low drive 1: High drive P4SEL.x P4IN.x Bus Keeper EN Module X IN 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS P4.0/TB0.0/S23 P4.1/TB0.1/S22 P4.2/TB0.2/S21 P4.3/TB0.3/S20 P4.4/TB0.4/S19 P4.5/TB0.5/S18 P4.6/TB0.6/S17 P4.7/TB0OUTH/SVMOUT/S16 D P4IE.x EN P4IRQ.x Q P4IFG.x P4SEL.x P4IES.x 88 Set Interrupt Edge Select Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 58. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) P4.0/TB0.0/S23 P4.1/TB0.1/S22 x 0 1 FUNCTION P4.0 (I/O) 2 0 0 1 0 Timer TB0.0 output (2) 1 1 0 S23 X X 1 P4.1 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI1A capture input 0 1 0 Timer TB0.1 output (2) 1 1 0 P4.2 (I/O) (2) S21 P4.3 (I/O) Timer TB0.CCI3A capture input Timer TB0.3 output (2) P4.5/TB0.5/S18 P4.6/TB0.6/S17 4 5 6 (1) (2) 7 X 1 0 0 0 1 0 1 1 0 X X 1 I: 0; O: 1 0 0 0 1 0 1 1 0 X 1 I: 0; O: 1 0 0 Timer TB0.CCI4A capture input 0 1 0 Timer TB0.4 output (2) 1 1 0 S19 X X 1 P4.4 (I/O) P4.5 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI5A capture input 0 1 0 Timer TB0.5 output (2) 1 1 0 S18 X X 1 P4.6 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI6A capture input 0 1 0 Timer TB0.6 output (2) 1 1 0 S17 P4.7/TB0OUTH/ SVMOUT/S16 X I: 0; O: 1 X S20 P4.4/TB0.4/S19 LCDS16...23 0 Timer TB0.2 output 3 P4SEL.x I: 0; O: 1 Timer TB0.CCI2A capture input P4.3/TB0.3/S20 P4DIR.x Timer TB0.CCI0A capture input S22 P4.2/TB0.2/S21 CONTROL BITS/SIGNALS (1) P4.7 (I/O) Timer TB0.TB0OUTH X X 1 I: 0; O: 1 0 0 0 1 0 SVMOUT 1 1 0 S16 X X 1 X = Don't care Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance. Copyright (c) 2010-2012, Texas Instruments Incorporated 89 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Pad Logic To/From Reference P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 Module X OUT 1 P5.0/VREF+/VeREF+ P5.1/VREF-/VeREF- P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x Bus Keeper EN Module X IN D Table 59. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/VREF+/VeREF+ x 0 FUNCTION P5DIR.x P5SEL.x REFOUT I: 0; O: 1 0 X X 1 0 X 1 1 P5.1 (I/O) (2) I: 0; O: 1 0 X VeREF- (5) X 1 0 VREF- (6) X 1 1 P5.0 (I/O) (2) VeREF+ (3) VREF+ (4) P5.1/VREF-/VeREF- (1) (2) (3) (4) (5) (6) 90 1 CONTROL BITS/SIGNALS (1) X = Don't care Default condition Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or DAC12_A. Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF+ reference is available at the pin. Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or DAC12_A. Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF- reference is available at the pin. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger Pad Logic S40...S42 LCDS40...LCDS42 P5REN.x P5DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5OUT.x DVSS P5.2/R23 P5.3/COM1/S42 P5.4/COM2/S41 P5.5/COM3/S40 P5.6/ADC12CLK/DMAE0 P5.7/RTCCLK P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x Bus Keeper EN Module X IN D Table 60. Port P5 (P5.2 to P5.7) Pin Functions PIN NAME (P5.x) P5.2/R23 x 2 FUNCTION P5.2 (I/O) R23 P5.3/COM1/S42 3 P5.3 (I/O) COM1 S42 P5.4/COM2/S41 4 P5.4 (I/O) COM2 S41 P5.5/COM3/S40 5 P5.5 (I/O) COM3 S40 P5.6/ADC12CLK/DMAE0 P5.7/RTCCLK (1) 6 7 CONTROL BITS/SIGNALS (1) P5DIR.x P5SEL.x LCDS40...42 I: 0; O: 1 0 na X 1 na I: 0; O: 1 0 0 X 1 X 1 X 0 I: 0; O: 1 0 0 X 1 X 1 X 0 I: 0; O: 1 0 0 X 1 X X 0 1 I: 0; O: 1 0 na ADC12CLK 1 1 na DMAE0 0 1 na P5.7 (I/O) I: 0; O: 1 0 na RTCCLK 1 1 na P5.6 (I/O) X = Don't care Copyright (c) 2010-2012, Texas Instruments Incorporated 91 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y 0 Dvss 1 From DAC12_A 2 0 if DAC12AMPx=0 1 if DAC12AMPx=1 2 if DAC12AMPx>1 To Comparator_B From Comparator_B CBPD.x DAC12AMPx>0 DAC12OPS P6REN.x DVSS 0 DVCC 1 1 P6DIR.x P6OUT.x P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x Bus Keeper 92 P6.0/CB0/A0 P6.1/CB1/A1 P6.2/CB2/A2 P6.3/CB3/A3 P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 61. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) P6.0/CB0/A0 x 0 FUNCTION P6.0 (I/O) CB0 A0 (2) P6.1/CB1/A1 1 (3) P6.1 (I/O) CB1 A1 (2) P6.2/CB2/A2 2 (3) P6.2 (I/O) CB2 A2 (2) P6.3/CB3/A3 3 (3) P6.3 (I/O) CB3 A3 (2) P6.4/CB4/A4 4 (3) P6.4 (I/O) CB4 A4 P6.5/CB5/A5 5 (2) (3) P6.5 (I/O) CB5 A5 P6.6/CB6/A6/DAC0 6 (4) (2) (3) P6.6 (I/O) CB6 A6 (2) (3) DAC0 P6.7/CB7/A7/DAC1 7 P6.7 (I/O) CB7 A7 (2) (3) DAC1 (1) (2) (3) (4) CONTROL BITS/SIGNALS (1) P6DIR.x P6SEL.x CBPD.x DAC12OPS DAC12AMPx I: 0; O: 1 0 0 n/a n/a X X 1 n/a n/a X 1 X n/a n/a I: 0; O: 1 0 0 n/a n/a X X 1 n/a n/a X 1 X n/a n/a I: 0; O: 1 0 0 n/a n/a X X 1 n/a n/a X 1 X n/a n/a I: 0; O: 1 0 0 n/a n/a X X 1 n/a n/a X 1 X n/a n/a I: 0; O: 1 0 0 n/a n/a X X 1 n/a n/a X 1 X n/a n/a I: 0; O: 1 0 0 n/a n/a X X 1 n/a n/a X 1 X n/a n/a I: 0; O: 1 0 0 X 0 X X 1 X 0 X 1 X X 0 X X X 0 >1 I: 0; O: 1 0 0 X 0 X X 1 X 0 X 1 X X 0 X X X 0 >1 X = Don't care Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits. X = Don't care Copyright (c) 2010-2012, Texas Instruments Incorporated 93 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P7, P7.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P7REN.2 P7DIR.2 DVSS 0 DVCC 1 1 0 1 P7OUT.2 P7DS.2 0: Low drive 1: High drive P7SEL.2 P7.2/XT2IN P7IN.2 Bus Keeper 94 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Port P7, P7.3, Input/Output With Schmitt Trigger Pad Logic To XT2 P7REN.3 P7DIR.3 DVSS 0 DVCC 1 1 0 1 P7OUT.3 P7.3/XT2OUT P7DS.3 0: Low drive 1: High drive P7SEL.3 P7IN.3 Bus Keeper Table 62. Port P7 (P7.2 and P7.3) Pin Functions PIN NAME (P5.x) P7.2/XT2IN P7.3/XT2OUT (1) (2) (3) x 2 3 FUNCTION P7.2 (I/O) CONTROL BITS/SIGNALS (1) P7DIR.x P7SEL.2 P7SEL.3 XT2BYPASS I: 0; O: 1 0 X X XT2IN crystal mode (2) X 1 X 0 XT2IN bypass mode (2) X 1 X 1 I: 0; O: 1 0 X X XT2OUT crystal mode (3) X 1 X 0 P7.3 (I/O) (3) X 1 X 1 P7.3 (I/O) X = Don't care Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal mode or bypass mode. Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as general-purpose I/O. Copyright (c) 2010-2012, Texas Instruments Incorporated 95 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger 0 Dvss 1 From DAC12_A 2 Pad Logic 0 if DAC12AMPx=0 1 if DAC12AMPx=1 2 if DAC12AMPx>1 To ADC12 INCHx = y To Comparator_B From Comparator_B CBPD.x DAC12AMPx>0 DAC12OPS P7REN.x DVSS 0 DVCC 1 1 P7DIR.x P7OUT.x P7DS.x 0: Low drive 1: High drive P7SEL.x P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14/DAC0 P7.7/CB11/A15/DAC1 P7IN.x Bus Keeper 96 Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 63. Port P7 (P7.4 to P7.7) Pin Functions PIN NAME (P7.x) P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14/DAC0 x 4 5 6 FUNCTION P7.4 (I/O) 7 (3) P7SEL.x CBPD.x DAC12OPS DAC12AMPx I: 0; O: 1 0 0 n/a n/a X X 1 n/a n/a A12 (2) X 1 X n/a n/a I: 0; O: 1 0 0 n/a n/a Comparator_B input CB9 X X 1 n/a n/a A13 (2) X 1 X n/a n/a I: 0; O: 1 0 0 X 0 Comparator_B input CB10 X X 1 X 0 A14 (2) X 1 X X 0 X X X 1 >1 (3) P7.5 (I/O) (3) P7.6 (I/O) (3) P7.7 (I/O) I: 0; O: 1 0 0 X 0 Comparator_B input CB11 X X 1 X 0 A15 (2) X 1 X X 0 X X X 1 >1 (3) DAC12_A output DAC1 (1) (2) P7DIR.x Comparator_B input CB8 DAC12_A output DAC0 P7.7/CB11/A15/DAC1 CONTROL BITS/SIGNALS (1) X = Don't care Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits. Copyright (c) 2010-2012, Texas Instruments Incorporated 97 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger Pad Logic S8...S15 LCDS8...LCDS15 P8REN.x P8DIR.x 0 From module 1 P8OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P8DS.x 0: Low drive 1: High drive P8SEL.x P8IN.x EN Module X IN 98 1 Bus Keeper P8.0/TB0CLK/S15 P8.1/UCB1STE/UCA1CLK/S14 P8.2/UCA1TXD/UCA1SIMO/S13 P8.3/UCA1RXD/UCA1SOMI/S12 P8.4/UCB1CLK/UCA1STE/S11 P8.5/UCB1SIMO//UCB1SDA/S10 P8.6/UCB1SOMI/UCB1SCL/S9 P8.7/S8 D Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Table 64. Port P8 (P8.0 to P8.7) Pin Functions PIN NAME (P9.x) P8.0/TB0CLK/S15 P8.1/UCB1STE/UCA1CLK/S14 P8.2/UCA1TXD/UCA1SIMO/S13 P8.3/UCA1RXD/UCA1SOMI/S12 P8.4/UCB1CLK/UCA1STE/S11 x 0 1 2 3 4 FUNCTION P8.0 (I/O) 0 0 1 0 S15 X X 1 I: 0; O: 1 0 0 P8.1 (I/O) UCB1STE/UCA1CLK X 1 0 S14 X X 1 I: 0; O: 1 0 0 P8.2 (I/O) UCA1TXD/UCA1SIMO X 1 0 S13 X X 1 I: 0; O: 1 0 0 P8.3 (I/O) UCA1RXD/UCA1SOMI X 1 0 S12 X X 1 I: 0; O: 1 0 0 X 1 0 P8.4 (I/O) P8.5 (I/O) S10 6 P8.6 (I/O) UCB1SOMI/UCB1SCL S9 P8.7/S8 7 P8.7 (I/O) S8 (1) LCDS8...16 0 UCB1SIMO/UCB1SDA P8.6/UCB1SOMI/UCB1SCL/S9 P8SEL.x I: 0; O: 1 S11 5 P8DIR.x Timer TB0.TB0CLK clock input UCB1CLK/UCA1STE P8.5/UCB1SIMO/UCB1SDA/S10 CONTROL BITS/SIGNALS (1) X X 1 I: 0; O: 1 0 0 X 1 0 X X 1 I: 0; O: 1 0 0 X 1 0 X X 1 I: 0; O: 1 0 0 X X 1 X = Don't care Copyright (c) 2010-2012, Texas Instruments Incorporated 99 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger Pad Logic S0...S7 LCDS0...LCDS7 P9REN.x DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P9DIR.x P9OUT.x P9.0/S7 P9.1/S6 P9.2/S5 P9.3/S4 P9.4/S3 P9.5/S2 P9.6/S1 P9.7/S0 P9DS.x 0: Low drive 1: High drive P9IN.x Bus Keeper Table 65. Port P9 (P9.0 to P9.7) Pin Functions PIN NAME (P9.x) P9.0/S7 x 0 FUNCTION P9.0 (I/O) S7 P9.1/S6 1 P9.1 (I/O) S6 P9.2/S5 2 P9.2 (I/O) S5 P9.3/S4 3 P9.4/S3 4 P9.3 (I/O) S4 P9.4 (I/O) S3 P9.5/S2 5 P9.5 (I/O) S2 P9.6/S1 6 P9.6 (I/O) S1 P9.7/S0 7 P9.7 (I/O) S0 (1) 100 CONTROL BITS/SIGNALS (1) P9DIR.x P9SEL.x LCDS0...7 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 X = Don't care Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Port PU.0/DP, PU.1/DM, PUR USB Ports PUSEL PUOPE VUSB Pad Logic 0 USB output enable VSSU 1 PUOUT0 0 USB DP output PU.0/ DP 1 PUIN0 USB DP input PUIPE . PUIN1 USB DM input PUOUT1 0 USB DM output 1 PU.1/ DM VUSB VSSU Pad Logic PUREN PUR "1" PUSEL PURIN Table 66. Port PU.0/DP, PU.1/DM Output Functions CONTROL BITS PIN NAME FUNCTION PUSEL PUDIR PUOUT1 PUOUT0 PU.1/DM PU.0/DP 0 0 X X Hi-Z Hi-Z Outputs off 0 1 0 0 0 0 Outputs enabled 0 1 0 1 0 1 Outputs enabled 0 1 1 0 1 0 Outputs enabled 0 1 1 1 1 1 Outputs enabled 1 X X X DM DP Direction set by USB module Table 67. Port PUR Input Functions CONTROL BITS PUSEL PUREN 0 0 Copyright (c) 2010-2012, Texas Instruments Incorporated FUNCTION Input disabled Pullup disabled 101 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 67. Port PUR Input Functions (continued) CONTROL BITS 102 FUNCTION PUSEL PUREN 0 1 Input disabled Pullup enabled 1 0 Input enabled Pullup disabled 1 1 Input enabled Pullup enabled Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 1 PJ.0/TDO PJDS.0 0: Low drive 1: High drive From JTAG PJIN.0 EN D Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.x 0 From JTAG 1 DVSS 0 DVCC 1 PJDS.x 0: Low drive 1: High drive From JTAG 1 PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK PJIN.x EN To JTAG D Copyright (c) 2010-2012, Texas Instruments Incorporated 103 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com Table 68. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS/ SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 (2) I: 0; O: 1 PJ.1 (I/O) (2) I: 0; O: 1 PJ.0 (I/O) TDO (3) PJ.1/TDI/TCLK 1 X TDI/TCLK (3) PJ.2/TMS 2 PJ.2 (I/O) TMS (3) PJ.3/TCK 3 (1) (2) (3) (4) 104 X I: 0; O: 1 (4) PJ.3 (I/O) TCK (3) (4) (2) X (2) I: 0; O: 1 (4) X X = Don't care Default condition The pin direction is controlled by the JTAG module. In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care. Copyright (c) 2010-2012, Texas Instruments Incorporated MSP430F663x www.ti.com SLAS566C - JUNE 2010 - REVISED AUGUST 2012 DEVICE DESCRIPTORS Table 69 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 69. MSP430F663x Device Descriptor Table (1) Info Block Die Record ADC12 Calibration (1) Description Address Size bytes F6638 F6637 F6636 F6635 F6634 F6633 F6632 F6631 F6630 Value Value Value Value Value Value Value Value Value Info length 01A00h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h CRC length 01A01h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h CRC value 01A02h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit Device ID 01A04h 2 801Ch 801Ah 8018h 8016h 804Eh 804Ch 804Ah 8048h 8046h Hardware revision 01A06h 1 per unit per unit per unit per unit per unit per unit per unit per unit per unit Firmware revision 01A07h 1 per unit per unit per unit per unit per unit per unit per unit per unit per unit Die Record Tag 01A08h 1 08h 08h 08h 08h 08h 08h 08h 08h 08h Die Record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah Lot/Wafer ID 01A0Ah 4 per unit per unit per unit per unit per unit per unit per unit per unit per unit Die X position 01A0Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit Die Y position 01A10h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit Test results 01A12h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit ADC12 Calibration Tag 01A14h 1 11h 11h 11h 11h 11h 11h 05h 05h 05h ADC12 Calibration length 01A15h 1 10h 10h 10h 10h 10h 10h 10h 10h 10h ADC Gain Factor 01A16h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A ADC Offset 01A18h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A ADC 1.5-V Reference Temp. Sensor 30C 01A1Ah 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A ADC 1.5-V Reference Temp. Sensor 85C 01A1Ch 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A ADC 2.0-V Reference Temp. Sensor 30C 01A1Eh 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A ADC 2.0-V Reference Temp. Sensor 85C 01A20h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A ADC 2.5-V Reference Temp. Sensor 30C 01A22h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A ADC 2.5-V Reference Temp. Sensor 85C 01A24h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A NA = Not applicable Copyright (c) 2010-2012, Texas Instruments Incorporated 105 MSP430F663x SLAS566C - JUNE 2010 - REVISED AUGUST 2012 www.ti.com REVISION HISTORY REVISION SLAS566 COMMENTS Product Preview release SLAS566A Updated Product Preview including electrical specifications SLAS566B Production Data release SLAS566C Changed description of ACLK and PUR in Terminal Functions. Changed typos to Interrupt Flag names on Timer TA2 rows in Table 6. Changed SYSRSTIV, System Reset offset 1Ch to Reserved in Table 14. Corrected names of SVMLVLRIFG and SVMHVLRIFG bits in Table 14. Added note regarding evaluation of PUR in USB BSL. Changed notes on REF, Built-In Reference. Changed tSENSOR(sample) MIN to 100 s in 12-Bit ADC, Temperature Sensor and Built-In VMID. Changed note (2) in 12-Bit ADC, Temperature Sensor and Built-In VMID. Editorial changes throughout. 106 Copyright (c) 2010-2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 2-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) MSP430F6630IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6630IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6630IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green (RoHS & no Sb/Br) SNAGCU MSP430F6630ZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 100 TBD Call TI MSP430F6631IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6631IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6631IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green (RoHS & no Sb/Br) SNAGCU MSP430F6631ZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 100 TBD Call TI MSP430F6632IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6632IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6632IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green (RoHS & no Sb/Br) SNAGCU MSP430F6632ZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 100 TBD Call TI MSP430F6633IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6633IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Addendum-Page 1 Samples Level-3-260C-168 HR Call TI Level-3-260C-168 HR Call TI Level-3-260C-168 HR Call TI PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 2-May-2012 Status (1) Package Type Package Drawing Pins Package Qty 2500 Eco Plan (2) Lead/ Ball Finish Green (RoHS & no Sb/Br) SNAGCU TBD Call TI MSL Peak Temp (3) MSP430F6633IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 MSP430F6633ZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 100 MSP430F6634IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6634IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6634IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green (RoHS & no Sb/Br) SNAGCU MSP430F6634ZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 100 TBD Call TI MSP430F6635IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6635IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6635IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green (RoHS & no Sb/Br) SNAGCU MSP430F6635ZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 100 TBD Call TI MSP430F6636IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6636IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6636IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green (RoHS & no Sb/Br) SNAGCU MSP430F6636ZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 100 TBD Call TI Addendum-Page 2 Samples (Requires Login) Level-3-260C-168 HR Call TI Level-3-260C-168 HR Call TI Level-3-260C-168 HR Call TI Level-3-260C-168 HR Call TI PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 2-May-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) MSP430F6637IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6637IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6637IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR MSP430F6637IZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 113 250 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR MSP430F6638CY ACTIVE Green (RoHS & no Sb/Br) Call TI N / A for Pkg Type MSP430F6638CYS ACTIVE WAFERSALE YS 0 1 TBD Call TI Call TI MSP430F6638IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6638IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F6638IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR MSP430F6638IZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 113 250 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2012 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430F6632IPZR MSP430F6633IPZR Package Package Pins Type Drawing LQFP Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 MSP430F6633IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430F6634IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 MSP430F6635IPZR LQFP SPQ LQFP MSP430F6635IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430F6636IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430F6637IZQWT BGA MI CROSTA R JUNI ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OR MSP430F6638IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 MSP430F6638IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430F6638IZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F6632IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F6633IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F6633IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430F6634IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430F6635IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F6635IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2012 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F6636IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430F6637IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336.6 336.6 28.6 MSP430F6638IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F6638IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430F6638IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336.6 336.6 28.6 Pack Materials-Page 3 MECHANICAL DATA MTQF013A - OCTOBER 1994 - REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0- 7 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. 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