MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
MIXED SIGNAL MICROCONTROLLER
1FEATURES
2• Low Supply Voltage Range: 1.8 V to 3.6 V • Four 16-Bit Timer With 3, 5, or 7
Capture/Compare Registers
• Ultralow Power Consumption • Two Universal Serial Communication
– Active Mode (AM): Interfaces
All System Clocks Active:
270 µA/MHz at 8 MHz, 3.0 V, Flash Program – USCI_A0 and USCI_A1 Each Support:
Execution (Typical) – Enhanced UART Supports Auto-
– Standby Mode (LPM3): Baudrate Detection
Watchdog With Crystal, and Supply – IrDA Encoder and Decoder
Supervisor Operational, Full RAM – Synchronous SPI
Retention, Fast Wake-Up: – USCI_B0 and USCI_B1 Each Support:
1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) – I2CTM
– Shutdown RTC Mode (LPM3.5): – Synchronous SPI
Shutdown Mode, Active Real-Time Clock
With Crystal: • Full-Speed Universal Serial Bus (USB)
1.1 µA at 3.0 V (Typical) – Integrated USB-PHY
– Shutdown Mode (LPM4.5): – Integrated 3.3-V and 1.8-V USB Power
0.3 µA at 3.0 V (Typical) System
• Wake-Up From Standby Mode in 3 µs (Typical) – Integrated USB-PLL
• 16-Bit RISC Architecture, Extended Memory, – Eight Input and Eight Output Endpoints
up to 20-MHz System Clock • 12-Bit Analog-to-Digital (A/D) Converter With
• Flexible Power Management System Internal Shared Reference, Sample-and-Hold,
– Fully Integrated LDO With Programmable and Autoscan Feature
Regulated Core Supply Voltage • Dual 12-Bit Digital-to-Analog (D/A) Converters
– Supply Voltage Supervision, Monitoring, With Synchronization
and Brownout • Voltage Comparator
• Unified Clock System • Integrated LCD Driver With Contrast Control
– FLL Control Loop for Frequency for up to 160 Segments
Stabilization • Hardware Multiplier Supporting 32-Bit
– Low-Power Low-Frequency Internal Clock Operations
Source (VLO) • Serial Onboard Programming, No External
– Low-Frequency Trimmed Internal Reference Programming Voltage Needed
Source (REFO) • Six-Channel Internal DMA
– 32-kHz Crystals (XT1) • Real-Time Clock Module With Supply Voltage
– High-Frequency Crystals Up to 32 MHz Backup Switch
(XT2) • Family Members are Summarized in Table 1
• For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3 µs (typical).
The MSP430F663x series are microcontroller configurations with a high performance 12-bit analog-to-digital
(A/D) converter, comparator, two universal serial communication interfaces (USCI), USB 2.0, hardware multiplier,
DMA, four 16-bit timers, real-time clock module with alarm capabilities, LCD driver, and up to 74 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
Family members available are summarized in Table 1.
Table 1. Family Members
USCI
Flash SRAM ADC12_A DAC12_A Comp_B Package
Channel A: Channel B:
Device Timer_A(2) Timer_B(3) I/O
(KB) (KB)(1) (Ch) (Ch) (Ch) Type
UART, SPI, I2C
IrDA, SPI
12 ext, 100 PZ,
MSP430F6638 256 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6637 192 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6636 128 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6635 256 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6634 192 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6633 128 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
100 PZ,
MSP430F6632 256 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
100 PZ,
MSP430F6631 192 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
100 PZ,
MSP430F6630 128 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
2Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 2. Ordering Information(1)
PACKAGED DEVICES(2)
TAPLASTIC 100-PIN TQFP (PZ) PLASTIC 113-BALL BGA (ZQW)
MSP430F6638IPZ MSP430F6638IZQW
MSP430F6637IPZ MSP430F6637IZQW
MSP430F6636IPZ MSP430F6636IZQW
MSP430F6635IPZ MSP430F6635IZQW
–40°C to 85°C MSP430F6634IPZ MSP430F6634IZQW
MSP430F6633IPZ MSP430F6633IZQW
MSP430F6632IPZ MSP430F6632IZQW
MSP430F6631IPZ MSP430F6631IZQW
MSP430F6630IPZ MSP430F6630IZQW
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/package.
Copyright © 2010–2012, Texas Instruments Incorporated 3
Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
SBW
Interface/
Port PJ
PA PB PC PD
DMA
6 Channel
XT2IN
XT2OUT
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
ADC12_A
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
12 Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
LCD_B
160
Segments
USB
Full-speed
Comp_B
PJ.x
RTC_B
Battery
Backup
System
Unified
Clock
System
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
SBW
Interface/
Port PJ
PA PB PC PD
DMA
6 Channel
XT2IN
XT2OUT
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_B
Battery
Backup
System
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
ADC12_A
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
12 Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
DAC12_A
12 bit
2 channels
voltage out
LCD_B
160
Segments
USB
Full-speed
Comp_B
PJ.x
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
256KB
192KB
128KB
Flash
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Functional Block Diagram, MSP430F6638, MSP430F6637, MSP430F6636
Functional Block Diagram, MSP430F6635, MSP430F6634, MSP430F6633
4Copyright © 2010–2012, Texas Instruments Incorporated
Unified
Clock
System
256KB
192KB
128KB
Flash
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
SBW
Interface/
Port PJ
PA PB PC PD
DMA
6 Channel
XT2IN
XT2OUT
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
LCD_B
160
Segments
USB
Full-speed
Comp_B
PJ.x
RTC_B
Battery
Backup
System
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Functional Block Diagram, MSP430F6632, MSP430F6631, MSP430F6630
Copyright © 2010–2012, Texas Instruments Incorporated 5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F6638
MSP430F6637
MSP430F6636
PZPACKAGE
(TOP VIEW)
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P7.3/XT2OUT
P7.2/XT2IN
VBUS
VUSB
PU.1/DM
PUR
PU.0/DP
VSSU
V18
AVSS3
P1.3/TA0.2/S36
P1.4/TA0.3/S35
AVSS2
P5.6/ADC12CLK/DMAE0
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.5/TA0.4/S34
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P8.4 /S11/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC3
DVSS3
VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Pin Designation, MSP430F6638IPZ, MSP430F6637IPZ, MSP430F6636IPZ
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
6Copyright © 2010–2012, Texas Instruments Incorporated
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14
P7.7/CB11/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F6635
MSP430F6634
MSP430F6633
PZPACKAGE
(TOP VIEW)
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P7.3/XT2OUT
P7.2/XT2IN
VBUS
VUSB
PU.1/DM
PUR
PU.0/DP
VSSU
V18
AVSS3
P1.3/TA0.2/S36
P1.4/TA0.3/S35
AVSS2
P5.6/ADC12CLK/DMAE0
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.5/TA0.4/S34
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P8.4 /S11/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC3
DVSS3
VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Pin Designation, MSP430F6635IPZ, MSP430F6634IPZ, MSP430F6633IPZ
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Copyright © 2010–2012, Texas Instruments Incorporated 7
1
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4
5
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8
9
10
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13
14
15
16
17
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19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P7.4/CB8
P7.5/CB9
P7.6/CB10
P7.7/CB11
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F6632
MSP430F6631
MSP430F6630
PZPACKAGE
(TOP VIEW)
P6.3/CB3
P6.2/CB2
P6.1/CB1
P6.0/CB0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P7.3/XT2OUT
P7.2/XT2IN
VBUS
VUSB
PU.1/DM
PUR
PU.0/DP
VSSU
V18
AVSS3
P1.3/TA0.2/S36
P1.4/TA0.3/S35
AVSS2
P5.6/DMAE0
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.5/TA0.4/S34
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P8.4 /S11/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC3
DVSS3
VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Pin Designation, MSP430F6632IPZ, MSP430F6631IPZ, MSP430F6630IPZ
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
8Copyright © 2010–2012, Texas Instruments Incorporated
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
C1 C2 C3 C11 C12
D1 D2 D4 D5 D6 D7 D8 D9 D11 D12
E1 E2 E4 E5 E6 E7 E8 E9 E11 E12
F1 F2 F4 F5 F8 F9 F11 F12
G1 G2 G4 G5 G8 G9 G11 G12
J1 J2 J4 J5 J6 J7 J8 J9 J11 J12
H1 H2 H4 H5 H6 H7 H8 H9 H11 H12
K1 K2 K11 K12
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12
M4
ZQWPACKAGE
(TOP VIEW)
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Pin Designation, MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW,
MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW,
MSP430F6631IZQW, MSP430F6630IZQW
NOTE: For terminal assignments, see Table 3
Copyright © 2010–2012, Texas Instruments Incorporated 9
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Table 3. Terminal Functions
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4
Analog input A4 – ADC(not available on F6632, F6631, F6630 devices)
General-purpose digital I/O
P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5
Analog input A5 – ADC(not available on F6632, F6631, F6630 devices)
General-purpose digital I/O
Comparator_B input CB6
P6.6/CB6/A6/DAC0 3 B1 I/O Analog input A6 – ADC (not available on F6632, F6631, F6630 devices)
DAC12.0 output (not available on F6635, F6634, F6633, F6632, F6631, F6630
devices)
General-purpose digital I/O
Comparator_B input CB7
P6.7/CB7/A7/DAC1 4 C2 I/O Analog input A7 – ADC (not available on F6632, F6631, F6630 devices)
DAC12.1 output (not available on F6635, F6634, F6633, F6632, F6631, F6630
devices)
General-purpose digital I/O
P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8
Analog input A12 –ADC (not available on F6632, F6631, F6630 devices)
General-purpose digital I/O
P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9
Analog input A13 – ADC (not available on F6632, F6631, F6630 devices)
General-purpose digital I/O
Comparator_B input CB10
P7.6/CB10/A14/DAC0 7 D2 I/O Analog input A14 – ADC (not available on F6632, F6631, F6630 devices)
DAC12.0 output (not available on F6635, F6634, F6633, F6632, F6631, F6630
devices)
General-purpose digital I/O
Comparator_B input CB11
P7.7/CB11/A15/DAC1 8 D1 I/O Analog input A15 – ADC (not available on F6632, F6631, F6630 devices)
DAC12.1 output (not available on F6635, F6634, F6633, F6632, F6631, F6630
devices)
General-purpose digital I/O
P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O
P5.1/VREF-/VeREF- 10 E4 I/O Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
E1,
AVCC1 11 Analog power supply
E2
AVSS1 12 F2 Analog ground supply
XIN 13 F1 I Input terminal for crystal oscillator XT1
XOUT 14 G1 O Output terminal of crystal oscillator XT1
AVSS2 15 G2 Analog ground supply
(1) I = input, O = output, N/A = not available on this package offering
10 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC (not available on F6632, F6631, F6630 devices)
DMA external trigger input
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/P2MAP0 17 G4 I/O Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and mappable secondary function
P2.1/P2MAP1 18 H2 I/O Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function
P2.2/P2MAP2 19 J1 I/O Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function
P2.3/P2MAP3 20 H4 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and mappable secondary function
P2.4/P2MAP4 21 J2 I/O Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
General-purpose digital I/O with port interrupt and mappable secondary function
P2.5/P2MAP5 22 K1 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
General-purpose digital I/O with port interrupt and mappable secondary function
P2.6/P2MAP6/R03 23 K2 I/O Default mapping: no secondary function
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
P2.7/P2MAP7/LCDREF/R13 24 L2 I/O External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
DVCC1 25 L1 Digital power supply
DVSS1 26 M1 Digital ground supply
VCORE(2) 27 M2 Regulated core power supply (internal use only, no external current loading)
General-purpose digital I/O
P5.2/R23 28 L3 I/O Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
LCDCAP/R33 29 M3 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
COM0 30 J4 O LCD common output COM0 for LCD backplane
General-purpose digital I/O
P5.3/COM1/S42 31 L4 I/O LCD common output COM1 for LCD backplane
LCD segment output S42
General-purpose digital I/O
P5.4/COM2/S41 32 M4 I/O LCD common output COM2 for LCD backplane
LCD segment output S41
General-purpose digital I/O
P5.5/COM3/S40 33 J5 I/O LCD common output COM3 for LCD backplane
LCD segment output S40
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Copyright © 2010–2012, Texas Instruments Incorporated 11
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O with port interrupt
Timer TA0 clock signal TACLK input
P1.0/TA0CLK/ACLK/S39 34 L5 I/O ACLK output (divided by 1, 2, 4, 8, 16, or 32)
LCD segment output S39
General-purpose digital I/O with port interrupt
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.1/TA0.0/S38 35 M5 I/O BSL transmit output
LCD segment output S38
General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
P1.2/TA0.1/S37 36 J6 I/O BSL receive input
LCD segment output S37
General-purpose digital I/O with port interrupt
P1.3/TA0.2/S36 37 H6 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output S36
General-purpose digital I/O with port interrupt
P1.4/TA0.3/S35 38 M6 I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
LCD segment output S35
General-purpose digital I/O with port interrupt
P1.5/TA0.4/S34 39 L6 I/O Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
LCD segment output S34
General-purpose digital I/O with port interrupt
P1.6/TA0.1/S33 40 J7 I/O Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
LCD segment output S33
General-purpose digital I/O with port interrupt
P1.7/TA0.2/S32 41 M7 I/O Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
LCD segment output S32
General-purpose digital I/O with port interrupt
Timer TA1 clock input
P3.0/TA1CLK/CBOUT/S31 42 L7 I/O Comparator_B output
LCD segment output S31
General-purpose digital I/O with port interrupt
P3.1/TA1.0/S30 43 H7 I/O Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S30
General-purpose digital I/O with port interrupt
P3.2/TA1.1/S29 44 M8 I/O Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S29
General-purpose digital I/O with port interrupt
P3.3/TA1.2/S28 45 L8 I/O Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S28
General-purpose digital I/O with port interrupt
Timer TA2 clock input
P3.4/TA2CLK/SMCLK/S27 46 J8 I/O SMCLK output
LCD segment output S27
12 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O with port interrupt
P3.5/TA2.0/S26 47 M9 I/O Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S26
General-purpose digital I/O with port interrupt
P3.6/TA2.1/S25 48 L9 I/O Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S25
General-purpose digital I/O with port interrupt
P3.7/TA2.2/S24 49 M10 I/O Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S24
General-purpose digital I/O with port interrupt
P4.0/TB0.0/S23 50 J9 I/O Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S23
General-purpose digital I/O with port interrupt
P4.1/TB0.1/S22 51 M11 I/O Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S22
General-purpose digital I/O with port interrupt
P4.2/TB0.2/S21 52 L10 I/O Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S21
General-purpose digital I/O with port interrupt
P4.3/TB0.3/S20 53 M12 I/O Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
LCD segment output S20
General-purpose digital I/O with port interrupt
P4.4/TB0.4/S19 54 L12 I/O Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
LCD segment output S19
General-purpose digital I/O with port interrupt
P4.5/TB0.5/S18 55 L11 I/O Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
LCD segment output S18
General-purpose digital I/O with port interrupt
P4.6/TB0.6/S17 56 K11 I/O Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
LCD segment output S17
General-purpose digital I/O with port interrupt
Timer TB0: Switch all PWM outputs high impedance
P4.7/TB0OUTH/SVMOUT/S16 57 K12 I/O SVM output
LCD segment output S16
General-purpose digital I/O
P8.0/TB0CLK/S15 58 J11 I/O Timer TB0 clock input
LCD segment output S15
General-purpose digital I/O
P8.1/UCB1STE/UCA1CLK/S14 59 J12 I/O USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output
LCD segment output S14
General-purpose digital I/O
P8.2/UCA1TXD/UCA1SIMO/S13 60 H11 I/O USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out
LCD segment output S13
Copyright © 2010–2012, Texas Instruments Incorporated 13
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P8.3/UCA1RXD/UCA1SOMI/S12 61 H12 I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in
LCD segment output S12
General-purpose digital I/O
P8.4/UCB1CLK/UCA1STE/S11 62 G11 I/O USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable
LCD segment output S11
DVSS2 63 G12 Digital ground supply
DVCC2 64 F12 Digital power supply
General-purpose digital I/O
P8.5/UCB1SIMO/UCB1SDA/S10 65 F11 I/O USCI_B1 SPI slave in/master out; USCI_B1 I2C data
LCD segment output S10
General-purpose digital I/O
P8.6/UCB1SOMI/UCB1SCL/S9 66 G9 I/O USCI_B1 SPI slave out/master in; USCI_B1 I2C clock
LCD segment output S9
General-purpose digital I/O
P8.7/S8 67 E12 I/O LCD segment output S8
General-purpose digital I/O
P9.0/S7 68 E11 I/O LCD segment output S7
General-purpose digital I/O
P9.1/S6 69 F9 I/O LCD segment output S6
General-purpose digital I/O
P9.2/S5 70 D12 I/O LCD segment output S5
General-purpose digital I/O
P9.3/S4 71 D11 I/O LCD segment output S4
General-purpose digital I/O
P9.4/S3 72 E9 I/O LCD segment output S3
General-purpose digital I/O
P9.5/S2 73 C12 I/O LCD segment output S2
General-purpose digital I/O
P9.6/S1 74 C11 I/O LCD segment output S1
General-purpose digital I/O
P9.7/S0 75 D9 I/O LCD segment output S0
B11
VSSU 76 and USB PHY ground supply
B12
General-purpose digital I/O - controlled by USB control register
PU.0/DP 77 A12 I/O USB data terminal DP
USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to
PUR 78 B10 I/O invoke the default USB BSL. Recommended 1-MΩresistor to ground. See USB
BSL for more information.
General-purpose digital I/O - controlled by USB control register
PU.1/DM 79 A11 I/O USB data terminal DM
VBUS 80 A10 USB LDO input (connect to USB power source)
VUSB 81 A9 USB LDO output
V18 82 B9 USB regulated power (internal use only, no external current loading)
14 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
AVSS3 83 A8 Analog ground supply
General-purpose digital I/O
P7.2/XT2IN 84 B8 I/O Input terminal for crystal oscillator XT2
General-purpose digital I/O
P7.3/XT2OUT 85 B7 I/O Output terminal of crystal oscillator XT2
Capacitor for backup subsystem. Do not load this pin externally. For capacitor
VBAK 86 A7 values, see CBAK in Recommended Operating Conditions.
Backup or secondary supply voltage. If backup voltage is not supplied, connect to
VBAT 87 D8 DVCC externally.
General-purpose digital I/O
P5.7/RTCCLK 88 D7 I/O RTCCLK output
DVCC3 89 A6 Digital power supply
DVSS3 90 A5 Digital ground supply
Test mode pin; selects digital I/O on JTAG pins
TEST/SBWTCK 91 B6 I Spy-bi-wire input clock
General-purpose digital I/O
PJ.0/TDO 92 B5 I/O Test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK 93 A4 I/O Test data input or test clock input
General-purpose digital I/O
PJ.2/TMS 94 E7 I/O Test mode select
General-purpose digital I/O
PJ.3/TCK 95 D6 I/O Test clock
Reset input (active low)
RST/NMI/SBWTDIO 96 A3 I/O Non-maskable interrupt input
Spy-bi-wire data input/output
General-purpose digital I/O
P6.0/CB0/A0 97 B4 I/O Comparator_B input CB0
Analog input A0 – ADC (not available on F6632, F6631, F6630 devices)
General-purpose digital I/O
P6.1/CB1/A1 98 B3 I/O Comparator_B input CB1
Analog input A1 – ADC (not available on F6632, F6631, F6630 devices)
General-purpose digital I/O
P6.2/CB2/A2 99 A2 I/O Comparator_B input CB2
Analog input A2 – ADC (not available on F6632, F6631, F6630 devices)
General-purpose digital I/O
P6.3/CB3/A3 100 D5 I/O Comparator_B input CB3
Analog input A3 – ADC (not available on F6632, F6631, F6630 devices)
Copyright © 2010–2012, Texas Instruments Incorporated 15
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
E5,
E6,
E8,
F4,
F5,
Reserved N/A F8, Reserved. It is recommended to connect to ground (DVSS, AVSS).
G5,
G8,
H5,
H8,
H9
16 Copyright © 2010–2012, Texas Instruments Incorporated
Program Counter PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register R4
General-Purpose Register R5
General-Purpose Register R6
General-Purpose Register R7
General-Purpose Register R8
General-Purpose Register R9
General-Purpose Register R10
General-Purpose Register R11
General-Purpose Register R12
General-Purpose Register R13
General-Purpose Register R15
General-Purpose Register R14
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Instruction Set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 4 shows examples of the three
types of instruction formats; Table 5 shows the
address modes.
Table 4. Instruction Word Formats
INSTRUCTION WORD FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 →R5
Single operands, destination only CALL R8 PC →(TOS), R8 →PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0
Table 5. Address Mode Descriptions
ADDRESS MODE S(1) D(1) SYNTAX EXAMPLE OPERATION
Register + + MOV Rs,Rd MOV R10,R11 R10 →R11
Indexed + + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) →M(6+R6)
Symbolic (PC relative) + + MOV EDE,TONI M(EDE) →M(TONI)
Absolute + + MOV &MEM, &TCDAT M(MEM) →M(TCDAT)
Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) →M(Tab+R6)
M(R10) →R11
Indirect auto-increment + MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 →R10
Immediate + MOV #X,TONI MOV #45,TONI #45 →M(TONI)
(1) S = source, D = destination
Copyright © 2010–2012, Texas Instruments Incorporated 17
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Operating Modes
The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No data retention
– RTC enabled and clocked by low-frequency oscillator
– Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4
18 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up, External Reset WDTIFG, KEYV (SYSRSTIV)(1)(2) Reset 0FFFEh 63, highest
Watchdog Timeout, Key Violation
Flash Memory Key Violation
System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access JMBOUTIFG (SYSSNIV)(1)
JTAG Mailbox
User NMI
NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG (Non)maskable 0FFFAh 61
Oscillator Fault (SYSUNIV)(1)(2)
Flash Memory Access Violation
Comp_B Comparator B interrupt flags (CBIV)(1)(3) Maskable 0FFF8h 60
Timer TB0 TB0CCR0 CCIFG0(3) Maskable 0FFF6h 59
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
Timer TB0 Maskable 0FFF4h 58
TB0IFG (TBIV)(1) (3)
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(3) Maskable 0FFF0h 56
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)(1)(3) Maskable 0FFEEh 55
ADC12_A(4) ADC12IFG0 to ADC12IFG15 (ADC12IV)(1)(3) Maskable 0FFECh 54
Timer TA0 TA0CCR0 CCIFG0(3) Maskable 0FFEAh 53
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
Timer TA0 Maskable 0FFE8h 52
TA0IFG (TA0IV)(1)(3)
USB_UBM USB interrupts (USBIV)(1)(3) Maskable 0FFE6h 51
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA Maskable 0FFE4h 50
DMA4IFG, DMA5IFG (DMAIV)(1)(3)
Timer TA1 TA1CCR0 CCIFG0(3) Maskable 0FFE2h 49
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
Timer TA1 Maskable 0FFE0h 48
TA1IFG (TA1IV)(1)(3)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) (3) Maskable 0FFDEh 47
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(3) Maskable 0FFDCh 46
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(3) Maskable 0FFDAh 45
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (3) Maskable 0FFD8h 44
LCD_B LCD_B Interrupt Flags (LCDBIV)(1) Maskable 0FFD6h 43
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_B Maskable 0FFD4h 42
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1)(3)
DAC12_A(5) DAC12_0IFG, DAC12_1IFG(1)(3) Maskable 0FFD2h 41
Timer TA2 TA2CCR0 CCIFG0(3) Maskable 0FFD0h 40
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
Timer TA2 Maskable 0FFCEh 39
TA2IFG (TA2IV)(1)(3)
I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)(1)(3) Maskable 0FFCCh 38
I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)(1)(3) Maskable 0FFCAh 37
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with peripheral module ADC12_A, otherwise reserved.
(5) Only on devices with peripheral module DAC12_A, otherwise reserved.
Copyright © 2010–2012, Texas Instruments Incorporated 19
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
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Table 6. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations (continued)
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
0FFC8h 36
Reserved Reserved(6) ⋮ ⋮
0FF80h 0, lowest
(6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatability with other devices, it is recommended to reserve these locations.
Memory Organization
Table 7. Memory Organization(1)(2)
MSP430F6636 MSP430F6637 MSP430F6638
MSP430F6633 MSP430F6634 MSP430F6635
MSP430F6630 MSP430F6631 MSP430F6632
Memory (flash) Total Size 128KB 192KB 256KB
Main: interrupt vector 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
Bank 3 N/A N/A 64 KB
047FFF-038000h
Bank 2 N/A 64 KB 64 KB
037FFF-028000h 037FFF-028000h
Main: code memory Bank 1 64 KB 64 KB 64 KB
027FFF-018000h 027FFF-018000h 027FFF-018000h
Bank 0 64 KB 64 KB 64 KB
017FFF-008000h 017FFF-008000h 017FFF-008000h
Sector 3 4 KB 4 KB 4 KB
0063FFh–005400h 0063FFh–005400h 0063FFh–005400h
Sector 2 4 KB 4 KB 4 KB
0053FFh–004400h 0053FFh–004400h 0053FFh–004400h
RAM Sector 1 4 KB 4 KB 4 KB
0043FFh–003400h 0043FFh–003400h 0043FFh–003400h
Sector 0 4 KB 4 KB 4 KB
0033FFh–002400h 0033FFh–002400h 0033FFh–002400h
Size 2KB 2KB 2KB
USB RAM(3) RAM 0023FFh-001C00h 0023FFh-001C00h 0023FFh-001C00h
Info A 128 B 128 B 128 B
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
Info B 128 B 128 B 128 B
00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
Information memory
(flash) Info C 128 B 128 B 128 B
0018FFh–001880h 0018FFh–001880h 0018FFh–001880h
Info D 128 B 128 B 128 B
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
BSL 3 512 B 512 B 512 B
0017FFh–001600h 0017FFh–001600h 0017FFh–001600h
BSL 2 512 B 512 B 512 B
0015FFh–001400h 0015FFh–001400h 0015FFh–001400h
Bootstrap loader (BSL)
memory (flash) BSL 1 512 B 512 B 512 B
0013FFh–001200h 0013FFh–001200h 0013FFh–001200h
BSL 0 512 B 512 B 512 B
0011FFh–001000h 0011FFh–001000h 0011FFh–001000h
Size 4KB 4KB 4KB
Peripherals 000FFFh–000000h 000FFFh–000000h 000FFFh–000000h
(1) N/A = Not available.
(2) Backup RAM is accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
(3) USB RAM can be used as general purpose RAM when not used for USB operation.
20 Copyright © 2010–2012, Texas Instruments Incorporated
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Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory via the BSL is protected by an user-defined password. For complete description of the features of
the BSL and its implementation, see MSP430 Programming Via the Bootstrap Loader (BSL) (SLAU319).
USB BSL
All devices come pre-programmed with the USB BSL. Use of the USB BSL requires external access to the six
pins shown in Table 8. In addition to these pins, the application must support external components necessary for
normal USB operation; for example, the proper crystal on XT2IN and XT2OUT or proper decoupling.
Table 8. USB BSL Pin Requirements and Functions
DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
PU.0/DP USB data terminal DP
PU.1/DM USB data terminal DM
PUR USB pullup resistor terminal
VBUS USB bus power supply
VSSU USB ground supply
NOTE
The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is
pulled high externally, then the BSL is invoked. Therefore, unless the application is
invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or
USB is never used. Applying a 1-MΩresistor to ground is recommended.
UART BSL
A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the pre-
programmed, factory supplied, USB BSL. Use of the UART BSL requires external access to the six pins shown
in Table 9.
Table 9. UART BSL Pin Requirements and Functions
DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.1 Data transmit
P1.2 Data receive
VCC Power supply
VSS Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 10. For further
details on interfacing to development tools and device programmers, see the MSP430(tm) Hardware Tools
User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).
Copyright © 2010–2012, Texas Instruments Incorporated 21
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Table 10. JTAG Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input, TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 11. For further details on interfacing to development tools and
device programmers, see the MSP430(tm) Hardware Tools User's Guide (SLAU278). For a complete description
of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).
Table 11. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
VCC Power supply
VSS Ground supply
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A can be locked separately.
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in Memory Organization.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
• For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
Backup RAM Memory
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the Battery Backup System module is implemented.
There are 8 bytes of Backup RAM available on MSP430F663x. It can be wordwise accessed via the control
registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
22 Copyright © 2010–2012, Texas Instruments Incorporated
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Digital I/O
There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete, and port PJ contains four
individual I/O ports.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).
Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.
Table 12. Port Mapping, Mnemonics and Functions
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
PM_CBOUT - Comparator_B output
1PM_TB0CLK Timer TB0 clock input -
PM_ADC12CLK - ADC12CLK
2PM_DMAE0 DMAE0 Input -
PM_SVMOUT - SVM output
3Timer TB0 high impedance input
PM_TB0OUTH -
TB0OUTH
4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0
5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1
6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2
7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3
8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4
9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5
10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6
PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)
11 PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)
12 PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
13 PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
14 PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
15 PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
16 PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
17 PM_MCLK - MCLK
18 Reserved Reserved for test purposes. Do not use this setting.
Copyright © 2010–2012, Texas Instruments Incorporated 23
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Table 12. Port Mapping, Mnemonics and Functions (continued)
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
19 Reserved Reserved for test purposes. Do not use this setting.
20-30 Reserved None DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
31 (0FFh)(1) PM_ANALOG when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
which results in a read out value of 31.
Table 13. Default Mapping
PxMAPy
PIN INPUT PIN FUNCTION OUTPUT PIN FUNCTION
MNEMONIC
PM_UCB0STE, USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),
P2.0/P2MAP0 PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0SIMO, USCI_B0 SPI slave in master out (direction controlled by USCI),
P2.1/P2MAP1 PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0SOMI, USCI_B0 SPI slave out master in (direction controlled by USCI),
P2.2/P2MAP2 PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0CLK, USCI_B0 clock input/output (direction controlled by USCI),
P2.3/P2MAP3 PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCA0TXD, USCI_A0 UART TXD (direction controlled by USCI - output),
P2.4/P2MAP4 PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0RXD, USCI_A0 UART RXD (direction controlled by USCI - input),
P2.5/P2MAP5 PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
P2.6/P2MAP6/R03 PM_NONE - DVSS
P2.7/P2MAP7/LCDREF/R13 PM_NONE - DVSS
Oscillator and System Clock
The clock system in the MSP430F663x family of devices is supported by the Unified Clock System (UCS)
module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not
supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency
oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal
oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power
consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a
digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The
internal DCO provides a fast turn-on clock source and stabilizes in 3 µs (typical). The UCS module provides the
following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally-
controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to
ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
24 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
Real-Time Clock (RTC_B)
The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes,
hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which
compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports
flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in
LPM3.5 mode and operation from a backup supply.
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset and
power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap
loader entry mechanisms, and configuration management (device descriptors). SYS also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 14. System Module Interrupt Vector Registers
INTERRUPT VECTOR INTERRUPT EVENT WORD ADDRESS OFFSET PRIORITY
REGISTER
No interrupt pending 00h
Brownout (BOR) 02h Highest
RST/NMI (BOR) 04h
DoBOR (BOR) 06h
LPM3.5 or LPM4.5 wakeup (BOR) 08h
Security violation (BOR) 0Ah
SVSL (POR) 0Ch
SVSH (POR) 0Eh
SVML_OVP (POR) 10h
SYSRSTIV, System Reset 019Eh
SVMH_OVP (POR) 12h
DoPOR (POR) 14h
WDT timeout (PUC) 16h
WDT key violation (PUC) 18h
KEYV flash key violation (PUC) 1Ah
Reserved 1Ch
Peripheral area fetch (PUC) 1Eh
PMM key violation (PUC) 20h
Reserved 22h to 3Eh Lowest
Copyright © 2010–2012, Texas Instruments Incorporated 25
MSP430F663x
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Table 14. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR INTERRUPT EVENT WORD ADDRESS OFFSET PRIORITY
REGISTER
No interrupt pending 00h
SVMLIFG 02h Highest
SVMHIFG 04h
DLYLIFG 06h
DLYHIFG 08h
SYSSNIV, System NMI VMAIFG 019Ch 0Ah
JMBINIFG 0Ch
JMBOUTIFG 0Eh
SVMLVLRIFG 10h
SVMHVLRIFG 12h
Reserved 14h to 1Eh Lowest
No interrupt pending 00h
NMIFG 02h Highest
OFIFG 04h
SYSUNIV, User NMI 019Ah
ACCVIFG 06h
BUSIFG 08h
Reserved 0Ah to 1Eh Lowest
No interrupt pending 00h
SYSBERRIV, Bus Error USB wait state timeout 0198h 02h Highest
Reserved 04h to 1Eh Lowest
26 Copyright © 2010–2012, Texas Instruments Incorporated
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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments described in
Table 15.
Table 15. DMA Trigger Assignments(1)
Channel
Trigger 0 1 2 3 4 5
0 DMAREQ
1 TA0CCR0 CCIFG
2 TA0CCR2 CCIFG
3 TA1CCR0 CCIFG
4 TA1CCR2 CCIFG
5 TA2CCR0 CCIFG
6 TA2CCR2 CCIFG
7 TBCCR0 CCIFG
8 TBCCR2 CCIFG
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 UCA0RXIFG
17 UCA0TXIFG
18 UCB0RXIFG
19 UCB0TXIFG
20 UCA1RXIFG
21 UCA1TXIFG
22 UCB1RXIFG
23 UCB1TXIFG
24 ADC12IFGx(2)
25 DAC12_0IFG(3)
26 DAC12_1IFG(3)
27 USB FNRXD
28 USB ready
29 MPY ready
30 DMA5IFG DMA0IFG DMA1IFG DMA2IFG DMA3IFG DMA4IFG
31 DMAE0
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not
cause any DMA trigger event when selected.
(2) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC.
(3) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC.
Copyright © 2010–2012, Texas Instruments Incorporated 27
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
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Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C.
The MSP430F663x series includes two complete USCI modules (n = 0 to 1).
Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 16. Timer TA0 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
PZ ZQW PZ ZQW
SIGNAL SIGNAL SIGNAL SIGNAL
34-P1.0 L5-P1.0 TA0CLK TACLK
ACLK ACLK Timer NA NA
SMCLK SMCLK
34-P1.0 L5-P1.0 TA0CLK TACLK
35-P1.1 M5-P1.1 TA0.0 CCI0A 35-P1.1 M5-P1.1
DVSS CCI0B CCR0 TA0 TA0.0
DVSS GND
DVCC VCC
36-P1.2 J6-P1.2 TA0.1 CCI1A 36-P1.2 J6-P1.2
40-P1.6 J7-P1.6 TA0.1 CCI1B 40-P1.6 J7-P1.6
CCR1 TA1 TA0.1 ADC12_A (internal)(1)
DVSS GND ADC12SHSx = {1}
DVCC VCC
37-P1.3 H6-P1.3 TA0.2 CCI2A 37-P1.3 H6-P1.3
41-P1.7 M7-P1.7 TA0.2 CCI2B 41-P1.7 M7-P1.7
CCR2 TA2 TA0.2
DVSS GND
DVCC VCC
38-P1.4 M6-P1.4 TA0.3 CCI3A 38-P1.4 M6-P1.4
DVSS CCI3B CCR3 TA3 TA0.3
DVSS GND
DVCC VCC
39-P1.5 L6-P1.5 TA0.4 CCI4A 39-P1.5 L6-P1.5
DVSS CCI4B CCR4 TA4 TA0.4
DVSS GND
DVCC VCC
(1) Only on devices with peripheral module ADC12_A.
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Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 17. Timer TA1 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
PZ ZQW PZ ZQW
SIGNAL SIGNAL SIGNAL SIGNAL
42-P3.0 L7-P3.0 TA1CLK TACLK
ACLK ACLK Timer NA NA
SMCLK SMCLK
42-P3.0 L7-P3.0 TA1CLK TACLK
43-P3.1 H7-P3.1 TA1.0 CCI0A 43-P3.1 H7-P3.1
DVSS CCI0B CCR0 TA0 TA1.0
DVSS GND
DVCC VCC
44-P3.2 M8-P3.2 TA1.1 CCI1A 44-P3.2 M8-P3.2
DAC12_A(1)
CBOUT CCI1B DAC12_0, DAC12_1
(internal) CCR1 TA1 TA1.1 (internal)
DVSS GND
DVCC VCC
45-P3.3 L8-P3.3 TA1.2 CCI2A 45-P3.3 L8-P3.3
ACLK CCI2B
(internal) CCR2 TA2 TA1.2
DVSS GND
DVCC VCC
(1) Only on devices with peripheral module DAC12_A.
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Timer TA2
Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 18. Timer TA2 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
PZ ZQW PZ ZQW
SIGNAL SIGNAL SIGNAL SIGNAL
46-P3.4 J8-P3.4 TA2CLK TACLK
ACLK ACLK Timer NA NA
SMCLK SMCLK
46-P3.4 J8-P3.4 TA2CLK TACLK
47-P3.5 M9-P3.5 TA2.0 CCI0A 47-P3.5 M9-P3.5
DVSS CCI0B CCR0 TA0 TA2.0
DVSS GND
DVCC VCC
48-P3.6 L9-P3.6 TA2.1 CCI1A 48-P3.6 L9-P3.6
CBOUT CCI1B
(internal) CCR1 TA1 TA2.1
DVSS GND
DVCC VCC
49-P3.7 M10-P3.7 TA2.2 CCI2A 49-P3.7 M10-P3.7
ACLK CCI2B
(internal) CCR2 TA2 TA2.2
DVSS GND
DVCC VCC
30 Copyright © 2010–2012, Texas Instruments Incorporated
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Timer TB0
Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It supports multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 19. Timer TB0 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
PZ ZQW PZ ZQW
SIGNAL SIGNAL SIGNAL SIGNAL
58-P8.0 J11-P8.0 TB0CLK TB0CLK
P2MAPx(1) P2MAPx(1)
ACLK ACLK Timer NA NA
SMCLK SMCLK
58-P8.0 J11-P8.0 TB0CLK TB0CLK
P2MAPx(1) P2MAPx(1)
50-P4.0 J9-P4.0 TB0.0 CCI0A 50-P4.0 J9-P4.0
P2MAPx(1) P2MAPx(1) TB0.0 CCI0B P2MAPx(1) P2MAPx(1)
CCR0 TB0 TB0.0 ADC12 (internal) (2)
DVSS GND ADC12SHSx = {2}
DVCC VCC
51-P4.1 M11-P4.1 TB0.1 CCI1A 51-P4.1 M11-P4.1
P2MAPx(1) P2MAPx(1) TB0.1 CCI1B P2MAPx(1) P2MAPx(1)
CCR1 TB1 TB0.1 ADC12 (internal) (2)
DVSS GND ADC12SHSx = {3}
DVCC VCC
52-P4.2 L10-P4.2 TB0.2 CCI2A 52-P4.2 L10-P4.2
P2MAPx(1) P2MAPx(1) TB0.2 CCI2B P2MAPx(1) P2MAPx(1)
DAC12_A(3)
CCR2 TB2 TB0.2
DVSS GND DAC12_0, DAC12_1
(internal)
DVCC VCC
53-P4.3 M12-P4.3 TB0.3 CCI3A 53-P4.3 M12-P4.3
P2MAPx(1) P2MAPx(1) TB0.3 CCI3B P2MAPx(1) P2MAPx(1)
CCR3 TB3 TB0.3
DVSS GND
DVCC VCC
54-P4.4 L12-P4.4 TB0.4 CCI4A 54-P4.4 L12-P4.4
P2MAPx(1) P2MAPx(1) TB0.4 CCI4B P2MAPx(1) P2MAPx(1)
CCR4 TB4 TB0.4
DVSS GND
DVCC VCC
55-P4.5 L11-P4.5 TB0.5 CCI5A 55-P4.5 L11-P4.5
P2MAPx(1) P2MAPx(1) TB0.5 CCI5B P2MAPx(1) P2MAPx(1)
CCR5 TB5 TB0.5
DVSS GND
DVCC VCC
56-P4.6 K11-P4.6 TB0.6 CCI6A 56-P4.6 K11-P4.6
P2MAPx(1) P2MAPx(1) TB0.6 CCI6B P2MAPx(1) P2MAPx(1)
CCR6 TB6 TB0.6
DVSS GND
DVCC VCC
(1) Timer functions selectable via the port mapping controller.
(2) Only on devices with peripheral module ADC12_A.
(3) Only on devices with peripheral module DAC12_A.
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Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
ADC12_A
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-
and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU
intervention.
DAC12_A
The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12-bit
mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules are present,
they may be grouped together for synchronous operation.
CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
REF Voltage Reference
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device.
LCD_B
The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal display
(LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and
segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is
possible to control the level of the LCD voltage, and thus contrast, by software. The module also provides an
automatic blinking capability for individual segments.
USB Universal Serial Bus
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,
PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock frequencies. USB RAM,
when not used for USB communication, can be used by the system.
Embedded Emulation Module (EEM)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM
implemented on these devices has the following features:
• Eight hardware triggers/breakpoints on memory access
• Two hardware triggers/breakpoints on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers/breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level
32 Copyright © 2010–2012, Texas Instruments Incorporated
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Peripheral File Map
Table 20. Peripherals
MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE(1)
Special Functions (see Table 21) 0100h 000h - 01Fh
PMM (see Table 22) 0120h 000h - 00Fh
Flash Control (see Table 23) 0140h 000h - 00Fh
CRC16 (see Table 24) 0150h 000h - 007h
RAM Control (see Table 25) 0158h 000h - 001h
Watchdog (see Table 26) 015Ch 000h - 001h
UCS (see Table 27) 0160h 000h - 01Fh
SYS (see Table 28) 0180h 000h - 01Fh
Shared Reference (see Table 29) 01B0h 000h - 001h
Port Mapping Control (see Table 30) 01C0h 000h - 003h
Port Mapping Port P2 (see Table 30) 01D0h 000h - 007h
Port P1/P2 (see Table 31) 0200h 000h - 01Fh
Port P3/P4 (see Table 32) 0220h 000h - 01Fh
Port P5/P6 (see Table 33) 0240h 000h - 00Bh
Port P7/P8 (see Table 34) 0260h 000h - 00Bh
Port P9 (see Table 35) 0280h 000h - 00Bh
Port PJ (see Table 36) 0320h 000h - 01Fh
Timer TA0 (see Table 37) 0340h 000h - 02Eh
Timer TA1 (see Table 38) 0380h 000h - 02Eh
Timer TB0 (see Table 39) 03C0h 000h - 02Eh
Timer TA2 (see Table 40) 0400h 000h - 02Eh
Battery Backup (see Table 41) 0480h 000h - 01Fh
RTC_B (see Table 42) 04A0h 000h - 01Fh
32-bit Hardware Multiplier (see Table 43) 04C0h 000h - 02Fh
DMA General Control (see Table 44) 0500h 000h - 00Fh
DMA Channel 0 (see Table 44) 0510h 000h - 00Ah
DMA Channel 1 (see Table 44) 0520h 000h - 00Ah
DMA Channel 2 (see Table 44) 0530h 000h - 00Ah
DMA Channel 3 (see Table 44) 0540h 000h - 00Ah
DMA Channel 4 (see Table 44) 0550h 000h - 00Ah
DMA Channel 5 (see Table 44) 0560h 000h - 00Ah
USCI_A0 (see Table 45) 05C0h 000h - 01Fh
USCI_B0 (see Table 46) 05E0h 000h - 01Fh
USCI_A1 (see Table 47) 0600h 000h - 01Fh
USCI_B1 (see Table 48) 0620h 000h - 01Fh
ADC12_A (see Table 49) 0700h 000h - 03Fh
DAC12_A (see Table 50) 0780h 000h - 01Fh
Comparator_B (see Table 51) 08C0h 000h - 00Fh
USB configuration (see Table 52) 0900h 000h - 014h
USB control (see Table 53) 0920h 000h - 01Fh
LCD_B control (see Table 54) 0A00h 000h - 05Fh
(1) For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
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Table 21. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h
Table 22. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION REGISTER OFFSET
PMM Control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high side control SVSMHCTL 04h
SVS low side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
Table 23. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION REGISTER OFFSET
Flash control 1 FCTL1 00h
Flash control 3 FCTL3 04h
Flash control 4 FCTL4 06h
Table 24. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC result CRC16INIRES 04h
Table 25. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION REGISTER OFFSET
RAM control 0 RCCTL0 00h
Table 26. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION REGISTER OFFSET
Watchdog timer control WDTCTL 00h
Table 27. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION REGISTER OFFSET
UCS control 0 UCSCTL0 00h
UCS control 1 UCSCTL1 02h
UCS control 2 UCSCTL2 04h
UCS control 3 UCSCTL3 06h
UCS control 4 UCSCTL4 08h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh
UCS control 8 UCSCTL8 10h
34 Copyright © 2010–2012, Texas Instruments Incorporated
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 28. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootstrap loader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus Error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh
Table 29. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION REGISTER OFFSET
Shared reference control REFCTL 00h
Table 30. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)
REGISTER DESCRIPTION REGISTER OFFSET
Port mapping password register PMAPPWD 00h
Port mapping control register PMAPCTL 02h
Port P2.0 mapping register P2MAP0 00h
Port P2.1 mapping register P2MAP1 01h
Port P2.2 mapping register P2MAP2 02h
Port P2.3 mapping register P2MAP3 03h
Port P2.4 mapping register P2MAP4 04h
Port P2.5 mapping register P2MAP5 05h
Port P2.6 mapping register P2MAP6 06h
Port P2.7 mapping register P2MAP7 07h
Table 31. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pullup/pulldown enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 pullup/pulldown enable P2REN 07h
Port P2 drive strength P2DS 09h
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Table 31. Port P1/P2 Registers (Base Address: 0200h) (continued)
REGISTER DESCRIPTION REGISTER OFFSET
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh
Table 32. Port P3/P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 pullup/pulldown enable P3REN 06h
Port P3 drive strength P3DS 08h
Port P3 selection P3SEL 0Ah
Port P3 interrupt vector word P3IV 0Eh
Port P3 interrupt edge select P3IES 18h
Port P3 interrupt enable P3IE 1Ah
Port P3 interrupt flag P3IFG 1Ch
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 pullup/pulldown enable P4REN 07h
Port P4 drive strength P4DS 09h
Port P4 selection P4SEL 0Bh
Port P4 interrupt vector word P4IV 1Eh
Port P4 interrupt edge select P4IES 19h
Port P4 interrupt enable P4IE 1Bh
Port P4 interrupt flag P4IFG 1Dh
Table 33. Port P5/P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 pullup/pulldown enable P5REN 06h
Port P5 drive strength P5DS 08h
Port P5 selection P5SEL 0Ah
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 pullup/pulldown enable P6REN 07h
Port P6 drive strength P6DS 09h
Port P6 selection P6SEL 0Bh
36 Copyright © 2010–2012, Texas Instruments Incorporated
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 34. Port P7/P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 pullup/pulldown enable P7REN 06h
Port P7 drive strength P7DS 08h
Port P7 selection P7SEL 0Ah
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 pullup/pulldown enable P8REN 07h
Port P8 drive strength P8DS 09h
Port P8 selection P8SEL 0Bh
Table 35. Port P9 Register (Base Address: 0280h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P9 input P9IN 00h
Port P9 output P9OUT 02h
Port P9 direction P9DIR 04h
Port P9 pullup/pulldown enable P9REN 06h
Port P9 drive strength P9DS 08h
Port P9 selection P9SEL 0Ah
Table 36. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION REGISTER OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ pullup/pulldown enable PJREN 06h
Port PJ drive strength PJDS 08h
Table 37. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
Capture/compare control 3 TA0CCTL3 08h
Capture/compare control 4 TA0CCTL4 0Ah
TA0 counter register TA0R 10h
Capture/compare register 0 TA0CCR0 12h
Capture/compare register 1 TA0CCR1 14h
Capture/compare register 2 TA0CCR2 16h
Capture/compare register 3 TA0CCR3 18h
Capture/compare register 4 TA0CCR4 1Ah
TA0 expansion register 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh
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Table 38. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION REGISTER OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
Capture/compare control 2 TA1CCTL2 06h
TA1 counter register TA1R 10h
Capture/compare register 0 TA1CCR0 12h
Capture/compare register 1 TA1CCR1 14h
Capture/compare register 2 TA1CCR2 16h
TA1 expansion register 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh
Table 39. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION REGISTER OFFSET
TB0 control TB0CTL 00h
Capture/compare control 0 TB0CCTL0 02h
Capture/compare control 1 TB0CCTL1 04h
Capture/compare control 2 TB0CCTL2 06h
Capture/compare control 3 TB0CCTL3 08h
Capture/compare control 4 TB0CCTL4 0Ah
Capture/compare control 5 TB0CCTL5 0Ch
Capture/compare control 6 TB0CCTL6 0Eh
TB0 register TB0R 10h
Capture/compare register 0 TB0CCR0 12h
Capture/compare register 1 TB0CCR1 14h
Capture/compare register 2 TB0CCR2 16h
Capture/compare register 3 TB0CCR3 18h
Capture/compare register 4 TB0CCR4 1Ah
Capture/compare register 5 TB0CCR5 1Ch
Capture/compare register 6 TB0CCR6 1Eh
TB0 expansion register 0 TB0EX0 20h
TB0 interrupt vector TB0IV 2Eh
Table 40. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION REGISTER OFFSET
TA2 control TA2CTL 00h
Capture/compare control 0 TA2CCTL0 02h
Capture/compare control 1 TA2CCTL1 04h
Capture/compare control 2 TA2CCTL2 06h
TA2 counter register TA2R 10h
Capture/compare register 0 TA2CCR0 12h
Capture/compare register 1 TA2CCR1 14h
Capture/compare register 2 TA2CCR2 16h
TA2 expansion register 0 TA2EX0 20h
TA2 interrupt vector TA2IV 2Eh
38 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 41. Battery Backup Registers (Base Address: 0480h)
REGISTER DESCRIPTION REGISTER OFFSET
Battery Backup Memory 0 BAKMEM0 00h
Battery Backup Memory 1 BAKMEM1 02h
Battery Backup Memory 2 BAKMEM2 04h
Battery Backup Memory 3 BAKMEM3 06h
Battery Backup Control BAKCTL 1Ch
Battery Charger Control BAKCHCTL 1Eh
Table 42. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION REGISTER OFFSET
RTC control register 0 RTCCTL0 00h
RTC control register 1 RTCCTL1 01h
RTC control register 2 RTCCTL2 02h
RTC control register 3 RTCCTL3 03h
RTC prescaler 0 control register RTCPS0CTL 08h
RTC prescaler 1 control register RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds RTCSEC 10h
RTC minutes RTCMIN 11h
RTC hours RTCHOUR 12h
RTC day of week RTCDOW 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year low RTCYEARL 16h
RTC year high RTCYEARH 17h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh
Binary-to-BCD conversion register BIN2BCD 1Ch
BCD-to-binary conversion register BCD2BIN 1Eh
Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION REGISTER OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension register SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
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Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION REGISTER OFFSET
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control register 0 MPY32CTL0 2Ch
Table 44. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION REGISTER OFFSET
DMA General Control: DMA module control 0 DMACTL0 00h
DMA General Control: DMA module control 1 DMACTL1 02h
DMA General Control: DMA module control 2 DMACTL2 04h
DMA General Control: DMA module control 3 DMACTL3 06h
DMA General Control: DMA module control 4 DMACTL4 08h
DMA General Control: DMA interrupt vector DMAIV 0Ah
DMA Channel 0 control DMA0CTL 00h
DMA Channel 0 source address low DMA0SAL 02h
DMA Channel 0 source address high DMA0SAH 04h
DMA Channel 0 destination address low DMA0DAL 06h
DMA Channel 0 destination address high DMA0DAH 08h
DMA Channel 0 transfer size DMA0SZ 0Ah
DMA Channel 1 control DMA1CTL 00h
DMA Channel 1 source address low DMA1SAL 02h
DMA Channel 1 source address high DMA1SAH 04h
DMA Channel 1 destination address low DMA1DAL 06h
DMA Channel 1 destination address high DMA1DAH 08h
DMA Channel 1 transfer size DMA1SZ 0Ah
DMA Channel 2 control DMA2CTL 00h
DMA Channel 2 source address low DMA2SAL 02h
DMA Channel 2 source address high DMA2SAH 04h
DMA Channel 2 destination address low DMA2DAL 06h
DMA Channel 2 destination address high DMA2DAH 08h
DMA Channel 2 transfer size DMA2SZ 0Ah
DMA Channel 3 control DMA3CTL 00h
DMA Channel 3 source address low DMA3SAL 02h
DMA Channel 3 source address high DMA3SAH 04h
DMA Channel 3 destination address low DMA3DAL 06h
DMA Channel 3 destination address high DMA3DAH 08h
DMA Channel 3 transfer size DMA3SZ 0Ah
DMA Channel 4 control DMA4CTL 00h
DMA Channel 4 source address low DMA4SAL 02h
40 Copyright © 2010–2012, Texas Instruments Incorporated
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Table 44. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h) (continued)
REGISTER DESCRIPTION REGISTER OFFSET
DMA Channel 4 source address high DMA4SAH 04h
DMA Channel 4 destination address low DMA4DAL 06h
DMA Channel 4 destination address high DMA4DAH 08h
DMA Channel 4 transfer size DMA4SZ 0Ah
DMA Channel 5 control DMA5CTL 00h
DMA Channel 5 source address low DMA5SAL 02h
DMA Channel 5 source address high DMA5SAH 04h
DMA Channel 5 destination address low DMA5DAL 06h
DMA Channel 5 destination address high DMA5DAH 08h
DMA Channel 5 transfer size DMA5SZ 0Ah
Table 45. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI control 0 UCA0CTL0 00h
USCI control 1 UCA0CTL1 01h
USCI baud rate 0 UCA0BR0 06h
USCI baud rate 1 UCA0BR1 07h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh
Table 46. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 0 UCB0CTL0 00h
USCI synchronous control 1 UCB0CTL1 01h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous bit rate 1 UCB0BR1 07h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh
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Table 47. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI control 0 UCA1CTL0 00h
USCI control 1 UCA1CTL1 01h
USCI baud rate 0 UCA1BR0 06h
USCI baud rate 1 UCA1BR1 07h
USCI modulation control UCA1MCTL 08h
USCI status UCA1STAT 0Ah
USCI receive buffer UCA1RXBUF 0Ch
USCI transmit buffer UCA1TXBUF 0Eh
USCI LIN control UCA1ABCTL 10h
USCI IrDA transmit control UCA1IRTCTL 12h
USCI IrDA receive control UCA1IRRCTL 13h
USCI interrupt enable UCA1IE 1Ch
USCI interrupt flags UCA1IFG 1Dh
USCI interrupt vector word UCA1IV 1Eh
Table 48. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 0 UCB1CTL0 00h
USCI synchronous control 1 UCB1CTL1 01h
USCI synchronous bit rate 0 UCB1BR0 06h
USCI synchronous bit rate 1 UCB1BR1 07h
USCI synchronous status UCB1STAT 0Ah
USCI synchronous receive buffer UCB1RXBUF 0Ch
USCI synchronous transmit buffer UCB1TXBUF 0Eh
USCI I2C own address UCB1I2COA 10h
USCI I2C slave address UCB1I2CSA 12h
USCI interrupt enable UCB1IE 1Ch
USCI interrupt flags UCB1IFG 1Dh
USCI interrupt vector word UCB1IV 1Eh
Table 49. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION REGISTER OFFSET
Control register 0 ADC12CTL0 00h
Control register 1 ADC12CTL1 02h
Control register 2 ADC12CTL2 04h
Interrupt-flag register ADC12IFG 0Ah
Interrupt-enable register ADC12IE 0Ch
Interrupt-vector-word register ADC12IV 0Eh
ADC memory-control register 0 ADC12MCTL0 10h
ADC memory-control register 1 ADC12MCTL1 11h
ADC memory-control register 2 ADC12MCTL2 12h
ADC memory-control register 3 ADC12MCTL3 13h
ADC memory-control register 4 ADC12MCTL4 14h
ADC memory-control register 5 ADC12MCTL5 15h
ADC memory-control register 6 ADC12MCTL6 16h
ADC memory-control register 7 ADC12MCTL7 17h
ADC memory-control register 8 ADC12MCTL8 18h
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Table 49. ADC12_A Registers (Base Address: 0700h) (continued)
REGISTER DESCRIPTION REGISTER OFFSET
ADC memory-control register 9 ADC12MCTL9 19h
ADC memory-control register 10 ADC12MCTL10 1Ah
ADC memory-control register 11 ADC12MCTL11 1Bh
ADC memory-control register 12 ADC12MCTL12 1Ch
ADC memory-control register 13 ADC12MCTL13 1Dh
ADC memory-control register 14 ADC12MCTL14 1Eh
ADC memory-control register 15 ADC12MCTL15 1Fh
Conversion memory 0 ADC12MEM0 20h
Conversion memory 1 ADC12MEM1 22h
Conversion memory 2 ADC12MEM2 24h
Conversion memory 3 ADC12MEM3 26h
Conversion memory 4 ADC12MEM4 28h
Conversion memory 5 ADC12MEM5 2Ah
Conversion memory 6 ADC12MEM6 2Ch
Conversion memory 7 ADC12MEM7 2Eh
Conversion memory 8 ADC12MEM8 30h
Conversion memory 9 ADC12MEM9 32h
Conversion memory 10 ADC12MEM10 34h
Conversion memory 11 ADC12MEM11 36h
Conversion memory 12 ADC12MEM12 38h
Conversion memory 13 ADC12MEM13 3Ah
Conversion memory 14 ADC12MEM14 3Ch
Conversion memory 15 ADC12MEM15 3Eh
Table 50. DAC12_A Registers (Base Address: 0780h)
REGISTER DESCRIPTION REGISTER OFFSET
DAC12_A channel 0 control register 0 DAC12_0CTL0 00h
DAC12_A channel 0 control register 1 DAC12_0CTL1 02h
DAC12_A channel 0 data register DAC12_0DAT 04h
DAC12_A channel 0 calibration control register DAC12_0CALCTL 06h
DAC12_A channel 0 calibration data register DAC12_0CALDAT 08h
DAC12_A channel 1 control register 0 DAC12_1CTL0 10h
DAC12_A channel 1 control register 1 DAC12_1CTL1 12h
DAC12_A channel 1 data register DAC12_1DAT 14h
DAC12_A channel 1 calibration control register DAC12_1CALCTL 16h
DAC12_A channel 1 calibration data register DAC12_1CALDAT 18h
DAC12_A interrupt vector word DAC12IV 1Eh
Table 51. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION REGISTER OFFSET
Comp_B control register 0 CBCTL0 00h
Comp_B control register 1 CBCTL1 02h
Comp_B control register 2 CBCTL2 04h
Comp_B control register 3 CBCTL3 06h
Comp_B interrupt register CBINT 0Ch
Comp_B interrupt vector word CBIV 0Eh
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MSP430F663x
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Table 52. USB Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION REGISTER OFFSET
USB key/ID USBKEYID 00h
USB module configuration USBCNF 02h
USB PHY control USBPHYCTL 04h
USB power control USBPWRCTL 08h
USB power voltage setting USBPWRVSR 0Ah
USB PLL control USBPLLCTL 10h
USB PLL divider USBPLLDIV 12h
USB PLL interrupts USBPLLIR 14h
Table 53. USB Control Registers (Base Address: 0920h)
REGISTER DESCRIPTION REGISTER OFFSET
Input endpoint#0 configuration IEPCNF_0 00h
Input endpoint #0 byte count IEPCNT_0 01h
Output endpoint#0 configuration OEPCNF_0 02h
Output endpoint #0 byte count OEPCNT_0 03h
Input endpoint interrupt enables IEPIE 0Eh
Output endpoint interrupt enables OEPIE 0Fh
Input endpoint interrupt flags IEPIFG 10h
Output endpoint interrupt flags OEPIFG 11h
USB interrupt vector USBIV 12h
USB maintenance MAINT 16h
Time stamp TSREG 18h
USB frame number USBFN 1Ah
USB control USBCTL 1Ch
USB interrupt enables USBIE 1Dh
USB interrupt flags USBIFG 1Eh
Function address FUNADR 1Fh
Table 54. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION REGISTER OFFSET
LCD_B control register 0 LCDBCTL0 000h
LCD_B control register 1 LCDBCTL1 002h
LCD_B blinking control register LCDBBLKCTL 004h
LCD_B memory control register LCDBMEMCTL 006h
LCD_B voltage control register LCDBVCTL 008h
LCD_B port control register 0 LCDBPCTL0 00Ah
LCD_B port control register 1 LCDBPCTL1 00Ch
LCD_B port control register 2 LCDBPCTL2 00Eh
LCD_B charge pump control register LCDBCTL0 012h
LCD_B interrupt vector word LCDBIV 01Eh
LCD_B memory 1 LCDM1 020h
LCD_B memory 2 LCDM2 021h
⋮ ⋮ ⋮
LCD_B memory 22 LCDM22 035h
LCD_B blinking memory 1 LCDBM1 040h
LCD_B blinking memory 2 LCDBM2 041h
⋮ ⋮ ⋮
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Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS –0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2) –0.3 V to VCC + 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range, Tstg(3) –55°C to 150°C
Maximum junction temperature, TJ95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external dc loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics
PARAMETER VALUE UNIT
QFP (PZ) 122
θJA Junction-to-ambient thermal resistance, still air(1) °C/W
BGA (ZQW) 108
QFP (PZ) 83
θJC(TOP) Junction-to-case (top) thermal resistance(2) °C/W
BGA (ZQW) 72
QFP (PZ) 98
θJB Junction-to-board thermal resistance(3) °C/W
BGA (ZQW) 76
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Recommended Operating Conditions MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6
Supply voltage during program execution and flash PMMCOREVx = 0, 1 2.0 3.6
VCC programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 = V
PMMCOREVx = 0, 1, 2 2.2 3.6
DVCC = VCC)(1)(2)
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
PMMCOREVx = 0 1.8 3.6
PMMCOREVx = 0, 1 2.0 3.6
Supply voltage during USB operation, USB PLL disabled
(USB_EN = 1, UPLLEN = 0) PMMCOREVx = 0, 1, 2 2.2 3.6
VCC,USB V
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
PMMCOREVx = 2 2.2 3.6
Supply voltage during USB operation, USB PLL enabled(3)
(USB_EN = 1, UPLLEN = 1) PMMCOREVx = 2, 3 2.4 3.6
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =
VSS 0 V
DVSS2 = DVSS3 = VSS)TA= 0°C to 85°C 1.55 3.6
VBAT,RTC Backup-supply voltage with RTC operational V
TA= –40°C to 85°C 1.70 3.6
VBAT,MEM Backup-supply voltage with backup memory retained. TA= –40°C to 85°C 1.20 3.6 V
TAOperating free-air temperature I version –40 85 °C
TJOperating junction temperature I version –40 85 °C
CBAK Capacitance at pin VBAK 1 4.7 10 nF
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) USB operation with USB PLL enabled requires PMMCOREVx ≥2 for proper operation.
46 Copyright © 2010–2012, Texas Instruments Incorporated
2.01.8
8
0
12
20
25
SystemFrequency-MHz
SupplyVoltage-V
ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.
2.2 2.4 3.6
0,1,2,30,1,20,10
1,2,3
1,2
1
2,3
3
2
16
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Recommended Operating Conditions (continued) MIN NOM MAX UNIT
CVCORE Capacitor at VCORE 470 nF
CDVCC/Capacitor ratio of DVCC to VCORE 10
CVCORE PMMCOREVx = 0,
1.8 V ≤VCC ≤3.6 V 0 8.0
(default condition)
PMMCOREVx = 1, 0 12.0
Processor frequency (maximum MCLK frequency)(4)(5) 2 V ≤VCC ≤3.6 V
fSYSTEM MHz
(see Figure 1)PMMCOREVx = 2, 0 16.0
2.2 V ≤VCC ≤3.6 V
PMMCOREVx = 3, 0 20.0
2.4 V ≤VCC ≤3.6 V
fSYSTEM_USB Minimum processor frequency for USB operation 1.5 MHz
USB_wait Wait state cycles during USB operation 16 cycles
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Figure 1. Frequency vs Supply Voltage
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
EXECUTION
PARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz UNIT
MEMORY TYP MAX TYP MAX TYP MAX TYP MAX
0 0.32 0.36 2.1 2.4
1 0.36 2.4 3.6 4.0
IAM, Flash Flash 3 V mA
2 0.37 2.5 3.8
3 0.39 2.7 4.0 6.6
0 0.18 0.21 1.0 1.2
1 0.20 1.2 1.7 1.9
IAM, RAM RAM 3 V mA
2 0.22 1.3 2.0
3 0.23 1.4 2.1 3.6
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
-40°C 25°C 60°C 85°C
PARAMETER VCC PMMCOREVx UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V 0 71 75 87 81 85 99
ILPM0,1MHz Low-power mode 0(3)(4) µA
3 V 3 78 83 98 89 94 108
2.2 V 0 6.3 6.7 9.9 9.0 11 16
ILPM2 Low-power mode 2(5)(4) µA
3 V 3 6.6 7.0 11 10 12 18
0 1.6 1.8 2.4 4.7 6.5 10.5
2.2 V 1 1.6 1.9 4.8 6.6
2 1.7 2.0 4.9 6.7
Low-power mode 3,
ILPM3,XT1LF 0 1.9 2.1 2.7 5.0 6.8 10.8 µA
crystal mode(6)(4) 1 1.9 2.1 5.1 7.0
3 V 2 2.0 2.2 5.2 7.1
3 2.0 2.2 2.9 5.4 7.3 12.6
0 0.9 1.2 1.9 4.0 5.9 10.3
Low-power mode 3, 1 0.9 1.2 4.1 6.0
ILPM3, VLO mode, Watchdog 3 V µA
VLO,WDT 2 1.0 1.3 4.2 6.1
enabled(7)(4)
3 1.0 1.3 2.2 4.3 6.3 11.3
0 0.9 1.1 1.8 3.9 5.8 10
1 0.9 1.1 4.0 5.9
ILPM4 Low-power mode 4(8)(4) 3 V µA
2 1.0 1.2 4.1 6.1
3 1.0 1.2 2.1 4.2 6.2 11
Low-power mode 3.5
ILPM3.5, (LPM3.5) current with 3 V 0.5 0.8 1.4 µA
RTC,VCC active RTC into primary
supply pin DVCC (9)
Low-power mode 3.5
ILPM3.5, (LPM3.5) current with 3 V 0.6 0.8 1.4 µA
RTC,VBAT active RTC into backup
supply pin VBAT(10)
Total low-power mode
ILPM3.5, 3.5 (LPM3.5) current 3 V 1.0 1.1 1.3 1.6 2.8 µA
RTC,TOT with active RTC(11)
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(4) Current for brownout included. Low side supervisor and monitors disabled (SVSL, SVML). High side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO
setting = 1 MHz operation, DCO bias generator enabled.
USB disabled (VUSBEN = 0, SLDOEN = 0).
(6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(7) Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(9) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active
(10) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no
current drawn on VBAK
(11) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
-40°C 25°C 60°C 85°C
PARAMETER VCC PMMCOREVx UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
Low-power mode 4.5
ILPM4.5 3 V 0.2 0.3 0.6 0.7 0.9 1.4 µA
(LPM4.5)(12)
(12) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
Temperature (TA)
PARAMETER VCC PMMCOREVx -40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
0 2.3 2.7 3.1 5.4 7.4 11.5
Low-power mode 3
ILPM3, 1 2.3 2.7 5.6 7.5
(LPM3) current, LCD 4-
LCD, 3 V µA
mux mode, external 2 2.4 2.8 5.8 7.7
ext. bias biasing(3) (4) 3 2.4 2.8 3.5 5.9 7.9 13.2
0 2.7 3.2 3.8 5.9 7.9 12.2
Low-power mode 3
ILPM3, (LPM3) current, LCD 4- 1 2.7 3.2 6.1 8.1
LCD, mux mode, internal 3 V µA
2 2.8 3.3 6.2 8.3
int. bias biasing, charge pump
disabled(3)(5) 3 2.8 3.3 4.9 6.4 8.4 13.7
0 3.8
2.2 V 1 3.9 µA
Low-power mode 3 2 4.0
(LPM3) current, LCD 4-
ILPM3 mux mode, internal 0 4.0
LCD,CP biasing, charge pump 1 4.1
enabled(3)(6) 3 V µA
2 4.2
3 4.2
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout included. Low side supervisor and monitors disabled (SVSL, SVML). High side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
(4) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
(5) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
(6) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
Schmitt-Trigger Inputs – General Purpose I/O(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 0.80 1.40
VIT+ Positive-going input threshold voltage V
3 V 1.50 2.10
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
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Schmitt-Trigger Inputs – General Purpose I/O(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 0.45 1.00
VIT– Negative-going input threshold voltage V
3 V 0.75 1.65
1.8 V 0.3 0.8
Vhys Input voltage hysteresis (VIT+ – VIT–) V
3 V 0.4 1.0
For pullup: VIN = VSS
RPull Pullup or pulldown resistor 20 35 50 kΩ
For pulldown: VIN = VCC
CIInput capacitance VIN = VSS or VCC 5 pF
Inputs – Ports P1, P2, P3, and P4(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Port P1, P2, P3, P4: P1.x to P4.x,
t(int) External interrupt timing(2) 2.2 V, 3 V 20 ns
External trigger pulse duration to set interrupt flag
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Leakage Current – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.x) High-impedance leakage current (1)(2) 1.8 V, 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Outputs – General Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
I(OHmax) = –3 mA(1) VCC – 0.25 VCC
1.8 V
I(OHmax) = –10 mA(2) VCC – 0.60 VCC
VOH High-level output voltage V
I(OHmax) = –5 mA(1) VCC – 0.25 VCC
3 V
I(OHmax) = –15 mA(2) VCC – 0.60 VCC
I(OLmax) = 3 mA(1) VSS VSS + 0.25
1.8 V
I(OLmax) = 10 mA(2) VSS VSS + 0.60
VOL Low-level output voltage V
I(OLmax) = 5 mA(1) VSS VSS + 0.25
3 V
I(OLmax) = 15 mA(2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
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MSP430F663x
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Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
I(OHmax) = –1 mA(2) VCC – 0.25 VCC
1.8 V
I(OHmax) = –3 mA(3) VCC – 0.60 VCC
VOH High-level output voltage V
I(OHmax) = –2 mA(2) VCC – 0.25 VCC
3 V
I(OHmax) = –6 mA(3) VCC – 0.60 VCC
I(OLmax) = 1 mA(2) VSS VSS + 0.25
1.8 V
I(OLmax) = 3 mA(3) VSS VSS + 0.60
VOL Low-level output voltage V
I(OLmax) = 2 mA(2) VSS VSS + 0.25
3 V
I(OLmax) = 6 mA(3) VSS VSS + 0.60
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – Ports P1, P2, and P3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC = 1.8 V 8
PMMCOREVx = 0
Port output frequency P3.4/TA2CLK/SMCLK/S27
fPx.y MHz
(with load) CL= 20 pF, RL= 1 kΩ(1) or 3.2 kΩ(2)(3) VCC = 3 V 20
PMMCOREVx = 3
VCC = 1.8 V
P1.0/TA0CLK/ACLK/S39 8
PMMCOREVx = 0
P3.4/TA2CLK/SMCLK/S27
fPort_CLK Clock output frequency MHz
P2.0/P2MAP0 (P2MAP0 = PM_MCLK ) VCC = 3 V 20
CL= 20 pF(3) PMMCOREVx = 3
(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩbetween VCC and VSS is used as load. The output is connected to the
center tap of the divider.
(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩbetween VCC and VSS is used as load. The output is connected to the
center tap of the divider.
(3) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
52 Copyright © 2010–2012, Texas Instruments Incorporated
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V
P3.2
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
−8.0
−7.0
−6.0
−5.0
−4.0
−3.0
−2.0
−1.0
0.0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V
P3.2
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
0.0
5.0
10.0
15.0
20.0
25.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V
P3.2
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V
P3.2
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
MSP430F663x
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Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
Figure 2. Figure 3.
TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs vs
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
Figure 4. Figure 5.
Copyright © 2010–2012, Texas Instruments Incorporated 53
−20
−16
−12
−8
−4
0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V
P3.2
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
−60.0
−55.0
−50.0
−45.0
−40.0
−35.0
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V
P3.2
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
60.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V
P3.2
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
0
4
8
12
16
20
24
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V
P3.2
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
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Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
Figure 6. Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs vs
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
Figure 8. Figure 9.
54 Copyright © 2010–2012, Texas Instruments Incorporated
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1, 0.075
TA= 25°C
Differential XT1 oscillator crystal fOSC = 32768 Hz, XTS = 0,
ΔIDVCC,LF current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2, 3 V 0.170 µA
drive setting, LF mode TA= 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3, 0.290
TA= 25°C
XT1 oscillator crystal frequency,
fXT1,LF0 XTS = 0, XT1BYPASS = 0 32768 Hz
LF mode
XT1 oscillator logic-level square-
fXT1,LF,SW XTS = 0, XT1BYPASS = 1(2) (3) 10 32.768 50 kHz
wave input frequency, LF mode XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0, 210
fXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
OALF kΩ
LF crystals(4) XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1, 300
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0(6) 2
XTS = 0, XCAPx = 1 5.5
Integrated effective load
CL,eff pF
capacitance, LF mode(5) XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 12.0
XTS = 0, Measured at ACLK,
Duty cycle, LF mode 30 70 %
fXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF XTS = 0(8) 10 10000 Hz
LF mode(7)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0, 1000
TA= 25°C,
CL,eff = 6 pF
tSTART,LF Startup time, LF mode 3 V ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3, 500
TA= 25°C,
CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,eff ≤6 pF.
(b) For XT1DRIVEx = 1, 6 pF ≤CL,eff ≤9 pF.
(c) For XT1DRIVEx = 2, 6 pF ≤CL,eff ≤10 pF.
(d) For XT1DRIVEx = 3, CL,ef f ≥6 pF.
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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MSP430F663x
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Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0, 200
TA= 25°C
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1, 260
TA= 25°C
XT2 oscillator crystal current
IDVCC,XT2 3 V µA
consumption fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2, 325
TA= 25°C
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3, 450
TA= 25°C
XT2 oscillator crystal frequency,
fXT2,HF0 XT2DRIVEx = 0, XT2BYPASS = 0(3) 4 8 MHz
mode 0
XT2 oscillator crystal frequency,
fXT2,HF1 XT2DRIVEx = 1, XT2BYPASS = 0(3) 8 16 MHz
mode 1
XT2 oscillator crystal frequency,
fXT2,HF2 XT2DRIVEx = 2, XT2BYPASS = 0(3) 16 24 MHz
mode 2
XT2 oscillator crystal frequency,
fXT2,HF3 XT2DRIVEx = 3, XT2BYPASS = 0(3) 24 32 MHz
mode 3
XT2 oscillator logic-level square-
fXT2,HF,SW XT2BYPASS = 1(4) (3) 0.7 32 MHz
wave input frequency XT2DRIVEx = 0, XT2BYPASS = 0, 450
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
XT2DRIVEx = 1, XT2BYPASS = 0, 320
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
Oscillation allowance for
OAHF Ω
HF crystals(5) XT2DRIVEx = 2, XT2BYPASS = 0, 200
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
XT2DRIVEx = 3, XT2BYPASS = 0, 200
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz
XT2BYPASS = 0, XT2DRIVEx = 0, 0.5
TA= 25°C, CL,eff = 15 pF
tSTART,HF Startup time 3 V ms
fOSC = 20 MHz
XT2BYPASS = 0, XT2DRIVEx = 3, 0.3
TA= 25°C, CL,eff = 15 pF
Integrated effective load
CL,eff 1 pF
capacitance, HF mode(6) (1)
Duty cycle Measured at ACLK, fXT2,HF2 = 20 MHz 40 50 60 %
fFault,HF Oscillator fault frequency(7) XT2BYPASS = 1(8) 30 300 kHz
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz
dfVLO/dTVLO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.5 %/°C
dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 4 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 %
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
REFO oscillator current
IREFO TA= 25°C 1.8 V to 3.6 V 3 µA
consumption
REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz
fREFO Full temperature range 1.8 V to 3.6 V ±3.5 %
REFO absolute tolerance
calibrated TA= 25°C 3 V ±1.5 %
dfREFO/dTREFO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.01 %/°C
REFO frequency supply voltage
dfREFO/dVCC Measured at ACLK(2) 1.8 V to 3.6 V 1.0 %/V
drift
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 %
tSTART REFO startup time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Copyright © 2010–2012, Texas Instruments Incorporated 57
01 2 34567
Typical DCO Frequency, V = 3.0 V, T = 25°C
CC A
DCORSEL
100
10
1
0.1
f – MHz
DCO
DCOx = 31
DCOx = 0
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz
fDCO(0,31) DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz
fDCO(1,0) DCO frequency (1, 0) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz
fDCO(1,31) DCO frequency (1, 31) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz
fDCO(2,0) DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz
fDCO(2,31) DCO frequency (2, 31) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz
fDCO(3,0) DCO frequency (3, 0) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz
fDCO(3,31) DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz
fDCO(4,0) DCO frequency (4, 0) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz
fDCO(4,31) DCO frequency (4, 31) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz
fDCO(5,0) DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz
fDCO(5,31) DCO frequency (5, 31) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz
fDCO(6,0) DCO frequency (6, 0) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz
fDCO(6,31) DCO frequency (6, 31) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz
fDCO(7,0) DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz
fDCO(7,31) DCO frequency (7, 31) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz
Frequency step between range
SDCORSEL SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio
DCORSEL and DCORSEL + 1
Frequency step between tap
SDCO SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio
DCO and DCO + 1
Duty cycle Measured at SMCLK 40 50 60 %
dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz, 0.1 %/°C
dfDCO/dVCC DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V
Figure 10. Typical DCO frequency
58 Copyright © 2010–2012, Texas Instruments Incorporated
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PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BORHon voltage,
V(DVCC_BOR_IT–) | dDVCC/dt| < 3 V/s 1.45 V
DVCC falling level
BORHoff voltage,
V(DVCC_BOR_IT+) | dDVCC/dt| < 3 V/s 0.80 1.30 1.50 V
DVCC rising level
V(DVCC_BOR_hys) BORHhysteresis 60 250 mV
Pulse length required at
tRESET RST/NMI pin to accept a 2 µs
reset
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Core voltage, active
VCORE3(AM) 2.4 V ≤DVCC ≤3.6 V, 0 mA ≤I(VCORE)≤21 mA 1.90 V
mode, PMMCOREV = 3
Core voltage, active
VCORE2(AM) 2.2 V ≤DVCC ≤3.6 V, 0 mA ≤I(VCORE)≤21 mA 1.80 V
mode, PMMCOREV = 2
Core voltage, active
VCORE1(AM) 2 V ≤DVCC ≤3.6 V, 0 mA ≤I(VCORE)≤17 mA 1.60 V
mode, PMMCOREV = 1
Core voltage, active
VCORE0(AM) 1.8 V ≤DVCC ≤3.6 V, 0 mA ≤I(VCORE)≤13 mA 1.40 V
mode, PMMCOREV = 0
Core voltage, low-current
VCORE3(LPM) 2.4 V ≤DVCC ≤3.6 V, 0 µA ≤I(VCORE)≤30 µA 1.94 V
mode, PMMCOREV = 3
Core voltage, low-current
VCORE2(LPM) 2.2 V ≤DVCC ≤3.6 V, 0 µA ≤I(VCORE)≤30 µA 1.84 V
mode, PMMCOREV = 2
Core voltage, low-current
VCORE1(LPM) 2 V ≤DVCC ≤3.6 V, 0 µA ≤I(VCORE)≤30 µA 1.64 V
mode, PMMCOREV = 1
Core voltage, low-current
VCORE0(LPM) 1.8 V ≤DVCC ≤3.6 V, 0 µA ≤I(VCORE)≤30 µA 1.44 V
mode, PMMCOREV = 0
PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVSHE = 0, DVCC = 3.6 V 0 nA
I(SVSH) SVS current consumption SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200 nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 2.0 µA
SVSHE = 1, SVSHRVL = 0 1.59 1.64 1.69
SVSHE = 1, SVSHRVL = 1 1.79 1.84 1.91
V(SVSH_IT–) SVSHon voltage level(1) V
SVSHE = 1, SVSHRVL = 2 1.98 2.04 2.11
SVSHE = 1, SVSHRVL = 3 2.10 2.16 2.23
SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.81
SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.01
SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.21
SVSHE = 1, SVSMHRRL = 3 2.20 2.26 2.33
V(SVSH_IT+) SVSHoff voltage level(1) V
SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.48
SVSHE = 1, SVSMHRRL = 5 2.56 2.70 2.84
SVSHE = 1, SVSMHRRL = 6 2.85 3.00 3.15
SVSHE = 1, SVSMHRRL = 7 2.85 3.00 3.15
(1) The SVSHsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.
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PMM, SVS High Side (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5
tpd(SVSH) SVSHpropagation delay µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20
SVSHE = 0→1, SVSHFP = 1 12.5
t(SVSH) SVSHon/off delay time µs
SVSHE = 0→1, SVSHFP = 0 100
dVDVCC/dt DVCC rise time 0 1000 V/s
PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVMHE = 0, DVCC = 3.6 V 0 nA
I(SVMH) SVMHcurrent consumption SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200 nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 2.0 µA
SVMHE = 1, SVSMHRRL = 0 1.65 1.74 1.86
SVMHE = 1, SVSMHRRL = 1 1.85 1.94 2.02
SVMHE = 1, SVSMHRRL = 2 2.02 2.14 2.22
SVMHE = 1, SVSMHRRL = 3 2.18 2.26 2.35
V(SVMH) SVMHon or off voltage level(1) SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.48 V
SVMHE = 1, SVSMHRRL = 5 2.56 2.70 2.84
SVMHE = 1, SVSMHRRL = 6 2.85 3.00 3.15
SVMHE = 1, SVSMHRRL = 7 2.85 3.00 3.15
SVMHE = 1, SVMHOVPE = 1 3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5 µs
tpd(SVMH) SVMHpropagation delay SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20 µs
SVMHE = 0→1, SVSMFP = 1 12.5 µs
t(SVMH) SVMHon or off delay time SVMHE = 0→1, SVMHFP = 0 100 µs
(1) The SVMHsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.
PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVSLE = 0, PMMCOREV = 2 0 nA
I(SVSL) SVSLcurrent consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 2.0 µA
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5
tpd(SVSL) SVSLpropagation delay µs
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20
SVSLE = 0→1, SVSLFP = 1 12.5
t(SVSL) SVSLon/off delay time µs
SVSLE = 0→1, SVSLFP = 0 100
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVMLE = 0, PMMCOREV = 2 0 nA
I(SVML) SVMLcurrent consumption SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 2.0 µA
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PMM, SVM Low Side (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5
tpd(SVML) SVMLpropagation delay µs
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20
SVMLE = 0→1, SVMLFP = 1 12.5
t(SVML) SVMLon/off delay time µs
SVMLE = 0→1, SVMLFP = 0 100
Wake-Up From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMCLK ≥4 MHz 3 6.5
PMMCOREV = SVSMLRRL = n
Wake-up time from LPM2,
tWAKE-UP-FAST LPM3, or LPM4 to active (where n = 0, 1, 2, or 3), µs
1 MHz < fMCLK <4 8.0
mode(1) SVSLFP = 1 4 MHz
PMMCOREV = SVSMLRRL = n
Wake-up time from LPM2, (where n = 0, 1, 2, or 3),
tWAKE-UP-SLOW LPM3 or LPM4 to active 150 165 µs
mode(2) SVSLFP = 0
Wake-up time from LPM3.5 or
tWAKE-UP-LPM5 2 3 ms
LPM4.5 to active mode(3)
Wake-up time from RST or
tWAKE-UP-RESET 2 3 ms
BOR event to active mode(3)
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low-side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVMLin full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low-side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVMLare in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
(3) This value represents the time from the wakeup event to the reset vector execution.
Timer_A, Timers TA0, TA1, and TA2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fTA Timer_A input clock frequency External: TACLK 1.8 V, 3 V 20 MHz
Duty cycle = 50% ± 10%
All capture inputs,
tTA,cap Timer_A capture timing Minimum pulse duration required for 1.8 V, 3 V 20 ns
capture
Timer_B, Timer TB0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fTB Timer_B input clock frequency External: TBCLK 1.8 V, 3 V 20 MHz
Duty cycle = 50% ± 10%
All capture inputs,
tTB,cap Timer_B capture timing Minimum pulse duration required for 1.8 V, 3 V 20 ns
capture
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Battery Backup
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
TA= -40°C 0.43
VBAT = 1.7 V, TA= 25°C 0.52
DVCC not connected, µA
TA= 60°C 0.58
RTC running TA= 85°C 0.64
TA= -40°C 0.50
Current into VBAT terminal in VBAT = 2.2 V, TA= 25°C 0.59
IVBAT case no primary battery is DVCC not connected, µA
TA= 60°C 0.64
connected. RTC running TA= 85°C 0.71
TA= -40°C 0.68
VBAT = 3 V, TA= 25°C 0.75
DVCC not connected, µA
TA= 60°C 0.79
RTC running TA= 85°C 0.86
General VSVSH_IT-
SVSHRL = 0 1.59 1.69
Switch-over level (VCC to
VSWITCH CVCC = 4.7 µF SVSHRL = 1 1.79 1.91 V
VBAT) SVSHRL = 2 1.98 2.11
SVSHRL = 3 2.10 2.23
On-resistance of switch 0.35 1
RON_VBAT VBAT = 1.8 V 0 V kΩ
between VBAT and VBAK
VBAT to ADC input channel 1.8 V 0.6 ±5%
12: 3 V 1.0 ±5%
VBAT3 V
VBAT divide, 1.2 ±5%
3.6 V
VBAT3 ≠VBAT /3
tSample,VBA VBAT to ADC: Sampling time ADC12ON = 1, 1000 ns
T3 required if VBAT3 selected Error of conversion result ≤1 LSB
VCHVx Charger end voltage CHVx = 2 2.65 2.7 2.9 V
CHCx = 1 5
RCHARGE Charge limiting resistor CHCx = 2 10 kΩ
CHCx = 3 20
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
fBITCLK 1 MHz
(equals baud rate in MBaud) 2.2 V 50 600
tτUART receive deglitch time(1) ns
3 V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
62 Copyright © 2010–2012, Texas Instruments Incorporated
tSU,MI
tHD,MI
UCLK
SOMI
SIMO
tVALID,MO
tHD,MO
CKPL =0
CKPL =1
tLO/HI tLO/HI
1/fUCxCLK
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USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 11 and )
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SMCLK, ACLK,
fUSCI USCI input clock frequency fSYSTEM MHz
Duty cycle = 50% ± 10% 1.8 V 55
PMMCOREV = 0 ns
3 V 38
tSU,MI SOMI input data setup time 2.4 V 30
PMMCOREV = 3 ns
3 V 25
1.8 V 0
PMMCOREV = 0 ns
3 V 0
tHD,MI SOMI input data hold time 2.4 V 0
PMMCOREV = 3 ns
3 V 0
UCLK edge to SIMO valid, 1.8 V 20
CL= 20 pF, ns
3 V 18
PMMCOREV = 0
tVALID,MO SIMO output data valid time(2) 2.4 V 16
UCLK edge to SIMO valid, ns
CL= 20 pF, PMMCOREV = 3 3 V 15
1.8 V -10
CL= 20 pF, PMMCOREV = 0 ns
3 V -8
tHD,MO SIMO output data hold time(3) 2.4 V -10
CL= 20 pF, PMMCOREV = 3 ns
3 V -8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 11 and .
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 11 and .
Figure 11. SPI Master Mode, CKPH = 0
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USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 13 and Figure 14)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 11
PMMCOREV = 0 ns
3 V 8
tSTE,LEAD STE lead time, STE low to clock 2.4 V 7
PMMCOREV = 3 ns
3 V 6
1.8 V 3
PMMCOREV = 0 ns
3 V 3
tSTE,LAG STE lag time, Last clock to STE high 2.4 V 3
PMMCOREV = 3 ns
3 V 3
1.8 V 66
PMMCOREV = 0 ns
3 V 50
tSTE,ACC STE access time, STE low to SOMI data out 2.4 V 36
PMMCOREV = 3 ns
3 V 30
1.8 V 30
PMMCOREV = 0 ns
3 V 23
STE disable time, STE high to SOMI high
tSTE,DIS impedance 2.4 V 16
PMMCOREV = 3 ns
3 V 13
1.8 V 5
PMMCOREV = 0 ns
3 V 5
tSU,SI SIMO input data setup time 2.4 V 2
PMMCOREV = 3 ns
3 V 2
1.8 V 5
PMMCOREV = 0 ns
3 V 5
tHD,SI SIMO input data hold time 2.4 V 5
PMMCOREV = 3 ns
3 V 5
UCLK edge to SOMI valid, 1.8 V 76
CL= 20 pF, ns
3 V 60
PMMCOREV = 0
tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid, 2.4 V 44
CL= 20 pF, ns
3 V 40
PMMCOREV = 3 1.8 V 18
CL= 20 pF, ns
PMMCOREV = 0 3 V 12
tHD,SO SOMI output data hold time(3) 2.4 V 10
CL= 20 pF, ns
PMMCOREV = 3 3 V 8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 13 and Figure 14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 13
and Figure 14.
Copyright © 2010–2012, Texas Instruments Incorporated 65
STE
UCLK
CKPL =0
CKPL =1
SOMI
SIMO
tSU,SI
tHD,SI
tVALID,SO
tSTE,LEAD
1/fUCxCLK
tSTE,LAG
tSTE,DIS
tSTE,ACC
tHD,MO
tLO/HI tLO/HI
STE
UCLK
CKPL =0
CKPL =1
SOMI
SIMO
tSU,SI
tHD,SI
tVALID,SO
tSTE,LEAD
1/fUCxCLK
tLO/HI tLO/HI
tSTE,LAG
tSTE,DIS
tSTE,ACC
tHD,SO
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Figure 13. SPI Slave Mode, CKPH = 0
Figure 14. SPI Slave Mode, CKPH = 1
66 Copyright © 2010–2012, Texas Instruments Incorporated
SDA
SCL
tHD,DAT
tSU,DAT
tHD,STA
tHIGH
tLOW
tBUF
tHD,STA
tSU,STA
tSP
tSU,STO
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ± 10%
fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz
fSCL ≤100 kHz 4.0
tHD,STA Hold time (repeated) START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
fSCL ≤100 kHz 4.7
tSU,STA Setup time for a repeated START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2.2 V, 3 V 0 ns
tSU,DAT Data setup time 2.2 V, 3 V 250 ns
fSCL ≤100 kHz 4.0
tSU,STO Setup time for STOP 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
2.2 V 50 600
tSP Pulse width of spikes suppressed by input filter ns
3 V 50 600
Figure 15. I2C Mode Timing
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LCD_B, Recommended Operating Conditions
PARAMETER CONDITIONS MIN NOM MAX UNIT
VCC,LCD_B, Supply voltage range, charge pump LCDCPEN = 1, 0000 < VLCDx ≤1111 2.2 3.6 V
CP en,3.6 enabled, VLCD ≤3.6 V (charge pump enabled, VLCD ≤3.6 V)
VCC,LCD_B, Supply voltage range, charge pump LCDCPEN = 1, 0000 < VLCDx ≤1100 2.0 3.6 V
CP en,3.3 enabled, VLCD ≤3.3 V (charge pump enabled, VLCD ≤3.3 V)
Supply voltage range, internal biasing,
VCC,LCD_B, int. bias LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V
charge pump disabled
VCC,LCD_B, Supply voltage range, external biasing, LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V
ext. bias charge pump disabled
Supply voltage range, external LCD
VCC,LCD_B, voltage, internal or external biasing, LCDCPEN = 0, VLCDEXT = 1 2.0 3.6 V
VLCDEXT charge pump disabled
External LCD voltage at LCDCAP/R33,
VLCDCAP/R33 internal or external biasing, charge LCDCPEN = 0, VLCDEXT = 1 2.4 3.6 V
pump disabled
Capacitor on LCDCAP when charge LCDCPEN = 1, VLCDx > 0000
CLCDCAP 4.7 4.7 10 µF
pump enabled (charge pump enabled)
fLCD = 2 × mux × fFRAME
fFrame LCD frame frequency range 0 100 Hz
(mux = 1 (static), 2, 3, 4)
fACLK,in ACLK input frequency range 30 32 40 kHz
CPanel Panel capacitance 100-Hz frame frequency 10000 pF
VCC +
VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 2.4 V
0.2
LCDREXT = 1, LCDEXTBIAS = 1, VR03 + 2/3 ×
VR23,1/3bias Analog input voltage at R23 VR13 VR33 V
LCD2B = 0 (VR33-VR03)
Analog input voltage at R13 with 1/3 LCDREXT = 1, LCDEXTBIAS = 1, VR03 + 1/3 ×
VR13,1/3bias VR03 VR23 V
biasing LCD2B = 0 (VR33-VR03)
Analog input voltage at R13 with 1/2 LCDREXT = 1, LCDEXTBIAS = 1, VR03 + 1/2 ×
VR13,1/2bias VR03 VR33 V
biasing LCD2B = 1 (VR33-VR03)
VR03 Analog input voltage at R03 R0EXT = 1 VSS V
Voltage difference between VLCD and VCC+0
VLCD-VR03 LCDCPEN = 0, R0EXT = 1 2.4 V
R03 .2
External LCD reference voltage applied
VLCDREF/R13 VLCDREFx = 01 0.8 1.2 1.5 V
at LCDREF/R13
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LCD_B, Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VLCD LCD voltage VLCDx = 0000, VLCDEXT = 0 2.4 V - 3.6 V VCC V
LCDCPEN = 1, VLCDx = 0001 2 V - 3.6 V 2.60 V
LCDCPEN = 1, VLCDx = 0010 2 V - 3.6 V 2.66 V
LCDCPEN = 1, VLCDx = 0011 2 V - 3.6 V 2.72 V
LCDCPEN = 1, VLCDx = 0100 2 V - 3.6 V 2.79 V
LCDCPEN = 1, VLCDx = 0101 2 V - 3.6 V 2.85 V
LCDCPEN = 1, VLCDx = 0110 2 V - 3.6 V 2.92 V
LCDCPEN = 1, VLCDx = 0111 2 V - 3.6 V 2.98 V
LCDCPEN = 1, VLCDx = 1000 2 V - 3.6 V 3.05 V
LCDCPEN = 1, VLCDx = 1001 2 V - 3.6 V 3.10 V
LCDCPEN = 1, VLCDx = 1010 2 V - 3.6 V 3.17 V
LCDCPEN = 1, VLCDx = 1011 2 V - 3.6 V 3.24 V
LCDCPEN = 1, VLCDx = 1100 2 V - 3.6 V 3.30 V
LCDCPEN = 1, VLCDx = 1101 2.2 V - 3.6 V 3.36 V
LCDCPEN = 1, VLCDx = 1110 2.2 V - 3.6 V 3.42 V
LCDCPEN = 1, VLCDx = 1111 2.2 V - 3.6 V 3.48 3.6 V
ICC,Peak,CP Peak supply currents due to LCDCPEN = 1, VLCDx = 1111 2.2 V 400 µA
charge pump activities
tLCD,CP,on Time to charge CLCD when CLCD = 4.7 µF, 2.2 V 100 500 ms
discharged LCDCPEN = 0→1,
VLCDx = 1111
ICP,Load Maximum charge pump load LCDCPEN = 1, VLCDx = 1111 2.2 V 50 µA
current
RLCD,Seg LCD driver output impedance, LCDCPEN = 1, VLCDx = 1000, 2.2 V 10 kΩ
segment lines ILOAD = ±10 µA
RLCD,COM LCD driver output impedance, LCDCPEN = 1, VLCDx = 1000, 2.2 V 10 kΩ
common lines ILOAD = ±10 µA
12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC and DVCC are connected together,
AVCC Analog supply voltage AVSS and DVSS are connected together, 2.2 3.6 V
V(AVSS) = V(DVSS) = 0 V
V(Ax) Analog input voltage range(2) All ADC12 analog input pins Ax 0 AVCC V
2.2 V 150 200
Operating supply current into
IADC12_A fADC12CLK = 5 MHz(4) µA
AVCC terminal(3) 3 V 150 250
Only one terminal Ax can be selected at one
CIInput capacitance 2.2 V 20 25 pF
time
RIInput MUX ON resistance 0 V ≤VIN ≤V(AVCC) 10 200 1900 Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are
required. See REF, External Reference and REF, Built-In Reference.
(3) The internal reference supply current is not included in current consumption parameter IADC12.
(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0
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12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
For specified performance of ADC12 linearity
parameters using an external reference voltage or 0.45 4.8 5.0
AVCC as reference(1)
fADC12CLK ADC conversion clock For specified performance of ADC12 linearity 2.2 V, 3 V MHz
0.45 2.4 4.0
parameters using the internal reference(2)
For specified performance of ADC12 linearity 0.45 2.4 2.7
parameters using the internal reference(3)
Internal ADC12
fADC12OSC ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz
oscillator(4)
REFON = 0, Internal oscillator, 2.2 V, 3 V 2.4 3.1
ADC12OSC used for ADC conversion clock
tCONVERT Conversion time µs
External fADC12CLK from ACLK, MCLK or SMCLK, (5)
ADC12SSEL ≠0
RS= 400 Ω, RI= 200 Ω, CI= 20 pF,
tSample Sampling time 2.2 V, 3 V 1000 ns
τ= [RS+ RI] × CI(6)
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) 13 × ADC12DIV × 1/fADC12CLK
(6) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS+ RI) × CI+ 800 ns, where n = ADC resolution = 12, RS= external source resistance
12-Bit ADC, Linearity Parameters Using an External Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.4 V ≤dVREF ≤1.6 V(2) ±2
Integral
EI2.2 V, 3 V LSB
linearity error(1) 1.6 V < dVREF (2) ±1.7
Differential
ED(2) 2.2 V, 3 V ±1 LSB
linearity error(1)
dVREF ≤2.2 V(2) 2.2 V, 3 V ±3 ±5.6
EOOffset error(3) LSB
dVREF > 2.2 V(2) 2.2 V, 3 V ±1.5 ±3.5
EGGain error(3) (2) 2.2 V, 3 V ±1 ±2.5 LSB
dVREF ≤2.2 V(2) 2.2 V, 3 V ±3.5 ±7.1
Total unadjusted
ETLSB
error dVREF > 2.2 V(2) 2.2 V, 3 V ±2 ±5
(1) Parameters are derived using the histogram method.
(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-. VR+ < AVCC. VR-> AVSS.
Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling capacitors,
10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the MSP430F5xx and
MSP430F6xx Family User's Guide (SLAU208).
(3) Parameters are derived using a best fit curve.
12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
EIIntegral linearity error(1) See (2) 2.2 V, 3 V ±1.7 LSB
EDDifferential linearity error(1) See (2) 2.2 V, 3 V ±1 LSB
(1) Parameters are derived using the histogram method.
(2) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.
70 Copyright © 2010–2012, Texas Instruments Incorporated
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12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
EOOffset error(3) See (2) 2.2 V, 3 V ±1 ±2 LSB
EGGain error(3) See (2) 2.2 V, 3 V ±2 ±4 LSB
ETTotal unadjusted error See (2) 2.2 V, 3 V ±2 ±5 LSB
(3) Parameters are derived using a best fit curve.
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) VCC MIN TYP MAX UNIT
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤4.0 MHz ±1.7
Integral
EI2.2 V, 3 V LSB
linearity error(2) ADC12SR = 0, REFOUT = 0 fADC12CLK ≤2.7 MHz ±2.5
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤4.0 MHz -1 +1.5
Differential
EDADC12SR = 0, REFOUT = 1 fADC12CLK ≤2.7 MHz 2.2 V, 3 V ±1 LSB
linearity error(2) ADC12SR = 0, REFOUT = 0 fADC12CLK ≤2.7 MHz -1 +2.5
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤4.0 MHz ±2 ±4
EOOffset error(3) 2.2 V, 3 V LSB
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤2.7 MHz ±2 ±4
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤4.0 MHz ±1 ±2.5 LSB
EGGain error(3) 2.2 V, 3 V
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤2.7 MHz ±1%(4) VREF
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤4.0 MHz ±2 ±5 LSB
Total unadjusted
ET2.2 V, 3 V
error ADC12SR = 0, REFOUT = 0 fADC12CLK ≤2.7 MHz ±1%(4) VREF
(1) The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = VR+ - VR-.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
(4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In
this mode the reference voltage used by the ADC12_A is not available on a pin.
12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2.2 V 680
ADC12ON = 1, INCH = 0Ah,
VSENSOR See (1) mV
TA= 0°C 3 V 680
2.2 V 2.25
TCSENSOR ADC12ON = 1, INCH = 0Ah mV/°C
3 V 2.25
2.2 V 100
Sample time required if ADC12ON = 1, INCH = 0Ah,
tSENSOR(sample) µs
channel 10 is selected(2)(3) Error of conversion result ≤1 LSB 3 V 100
2.2 V 1.06 1.1 1.14
ADC12ON = 1, INCH = 0Bh,
VMID AVCC divider at channel 11 V
VMID is approximately 0.5 × VAVCC 3 V 1.46 1.5 1.54
Sample time required if ADC12ON = 1, INCH = 0Bh,
tVMID(sample) 2.2 V, 3 V 1000 ns
channel 11 is selected(4) Error of conversion result ≤1 LSB
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
(2) The temperature sensor offset can be significant. A single-point calibration is recommended to minimize the offset error of the built-in
temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available reference
voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and
VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's
Guide (SLAU208).
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Copyright © 2010–2012, Texas Instruments Incorporated 71
500
550
600
650
700
750
800
850
900
950
1000
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Typical Temperature Sensor Voltage - mV
AmbientTemperature- ˚C
MSP430F663x
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Figure 16. Typical Temperature Sensor Voltage
REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Positive external
VeREF+ VeREF+ > VREF–/VeREF– (2) 1.4 AVCC V
reference voltage input
Negative external
VREF–/VeREF– VeREF+ > VREF–/VeREF– (3) 0 1.2 V
reference voltage input
VeREF+ – Differential external VeREF+ > VREF–/VeREF– (4) 1.4 AVCC V
VREF–/VeREF– reference voltage input 1.4 V ≤VeREF+ ≤VAVCC , VeREF– = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 1h, 2.2 V, 3 V -26 26 µA
Conversion rate 200 ksps
IVeREF+,Static input current
IVREF–/VeREF– 1.4 V ≤VeREF+ ≤VAVCC , VeREF– = 0 V,
fADC12CLK = 5 MHZ, ADC12SHTx = 8h, 2.2 V, 3 V -1.2 +1.2 µA
Conversion rate 20 ksps
Capacitance at VREF+/-
CVREF+/- 10 µF
terminal(5)
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
72 Copyright © 2010–2012, Texas Instruments Incorporated
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REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
REFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1 , 3 V 2.5 ±1%
IVREF+ = 0 A
REFVSEL = {1} for 2 V,
Positive built-in reference
VREF+ REFON = REFOUT = 1, 3 V 2.0 ±1% V
voltage output IVREF+ = 0 A
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, 2.2 V, 3 V 1.5 ±1%
IVREF+ = 0 A
REFVSEL = {0} for 1.5 V 2.2
AVCC minimum voltage,
AVCC(min) Positive built-in reference REFVSEL = {1} for 2 V 2.3 V
active REFVSEL = {2} for 2.5 V 2.8
ADC12SR = 1(4), REFON = 1, REFOUT = 0, 3 V 70 100 µA
REFBURST = 0
ADC12SR = 1(4), REFON = 1, REFOUT = 1, 3 V 0.45 0.75 mA
REFBURST = 0
Operating supply current
IREF+ into AVCC terminal (2) (3) ADC12SR = 0(4), REFON = 1, REFOUT = 0, 3 V 210 310 µA
REFBURST = 0
ADC12SR = 0(4), REFON = 1, REFOUT = 1, 3 V 0.95 1.7 mA
REFBURST = 0
REFVSEL = {0, 1, 2}
Load-current regulation, IVREF+ = +10 µA / -1000 µA
IL(VREF+) 1500 2500 µV/mA
VREF+ terminal(5) AVCC = AVCC(min) for each reference level,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
Capacitance at VREF+ REFON = REFOUT = 1, (6)
CVREF+ 2.2 V, 3 V 20 100 pF
terminal 0 mA ≤IVREF+ ≤IVREF+(max)
Temperature coefficient IVREF+ is a constant in the range ppm/
TCREF+ REFOUT = 0 2.2 V, 3 V 20
of built-in reference(7) of 0 mA ≤IVREF+ ≤–1 mA °C
Temperature coefficient IVREF+ is a constant in the range ppm/
TCREF+ REFOUT = 1 2.2 V, 3 V 20 50
of built-in reference(7) of 0 mA ≤IVREF+ ≤–1 mA °C
AVCC = AVCC(min) - AVCC(max),
Power supply rejection
PSRR_DC TA= 25°C, REFVSEL = {0, 1, 2}, REFON = 1, 120 300 µV/V
ratio (dc) REFOUT = 0 or 1
AVCC = AVCC(min) - AVCC(max),
Power supply rejection
PSRR_AC TA= 25°C, REFVSEL = {0, 1, 2}, REFON = 1, 1 mV/V
ratio (ac) REFOUT = 0 or 1
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and utilizes the smaller buffer.
(2) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with
REFON = 1 and REFOUT = 0.
(4) For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.
(5) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or other
external factors.
(6) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
(7) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
Copyright © 2010–2012, Texas Instruments Incorporated 73
MSP430F663x
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REF, Built-In Reference (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC = AVCC(min) - AVCC(max),
REFVSEL = {0, 1, 2}, REFOUT = 0, 75
REFON = 0 →1
Settling time of reference
tSETTLE µs
AVCC = AVCC(min) - AVCC(max),
voltage(8) CVREF = CVREF(max), 75
REFVSEL = {0, 1, 2}, REFOUT = 1,
REFON = 0 →1
(8) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC = DVCC, AVSS = DVSS = 0 V 2.20 3.60 V
DAC12AMPx = 2, DAC12IR = 0,
DAC12IOG = 1, 3 V 65 110
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = 1.5 V
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h, 125 165
VeREF+ = VREF+ = AVCC
IDD Supply current, single DAC channel(1) (2) µA
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h, 2.2 V, 3 V 250 350
VeREF+ = VREF+ = AVCC
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h, 750 1100
VeREF+ = VREF+ = AVCC
DAC12_xDAT = 800h, 2.2 V 70
VeREF+ = 1.5 V, ΔAVCC = 100 mV
PSRR Power supply rejection ratio(3) (4) dB
DAC12_xDAT = 800h,
VeREF+ = 1.5 V or 2.5 V, 3 V 70
ΔAVCC = 100 mV
(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications.
(3) PSRR = 20 log (ΔAVCC /ΔVDAC12_xOUT)
(4) The internal reference is not used.
12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Resolution 12-bit monotonic 12 bits
VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V ±2 ±4(2)
Integral
INL LSB
nonlinearity(1) VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3 V ±2 ±4
VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V ±0.4 ±1(2)
Differential
DNL LSB
nonlinearity(1) VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3 V ±0.4 ±1
(1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of
the first-order equation: y = a + bx. VDAC12_xOUT = EO+(1+EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
(2) This parameter is not production tested.
74 Copyright © 2010–2012, Texas Instruments Incorporated
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
R =
Load ¥
AVCC
C = 100 pF
Load
2
DAC Output
Positive
Negative
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
12-Bit DAC, Linearity Specifications (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VeREF+ = 1.5 V,
DAC12AMPx = 7, 2.2 V ±21(2)
DAC12IR = 1
Without calibration(1) (3) VeREF+ = 2.5 V,
DAC12AMPx = 7, 3 V ±21
DAC12IR = 1
EOOffset voltage mV
VeREF+ = 1.5 V,
DAC12AMPx = 7, 2.2 V ±1.5(2)
DAC12IR = 1
With calibration(1) (3) VeREF+ = 2.5 V,
DAC12AMPx = 7, 3 V ±1.5
DAC12IR = 1
Offset error
dE(O)/dTtemperature With calibration 2.2 V, 3 V ±10 µV/°C
coefficient(1)
VeREF+ = 1.5 V 2.2 V ±2.5
EGGain error %FSR
VeREF+ = 2.5 V 3 V ±2.5 ppm
Gain temperature of
dE(G)/dT2.2 V, 3 V 10
coefficient(1) FSR/
°C
DAC12AMPx = 2 165
Time for offset
tOffset_Cal DAC12AMPx = 3, 5 2.2 V, 3 V 66 ms
calibration(4) DAC12AMPx = 4, 6, 7 16.5
(3) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
(4) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect
accuracy and is not recommended.
Figure 17. Linearity Test Load Conditions and Gain/Offset Definition
Copyright © 2010–2012, Texas Instruments Incorporated 75
RO/P(DAC12_x)
Max
0.3
AVCC
AV – 0.3 V
CC VOUT
Min
RLoad
AVCC
C = 100 pF
Load
2
ILoad
DAC12
O/P(DAC12_x)
MSP430F663x
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12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
No load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1, 0 0.005
DAC12AMPx = 7
No load, VeREF+ = AVCC,AVCC –
DAC12_xDAT = 0FFFh, DAC12IR = 1, AVCC
0.05
Output voltage DAC12AMPx = 7
VOrange(1) (see 2.2 V, 3 V V
RLoad = 3 kΩ, VeREF+ = AVCC,
Figure 18)DAC12_xDAT = 0h, DAC12IR = 1, 0 0.1
DAC12AMPx = 7
RLoad = 3 kΩ, VeREF+ = AVCC,AVCC –
DAC12_xDAT = 0FFFh, DAC12IR = 1, AVCC
0.13
DAC12AMPx = 7
Maximum DAC12
CL(DAC12) 2.2 V, 3 V 100 pF
load capacitance DAC12AMPx = 2, DAC12xDAT = 0FFFh, –1
VO/P(DAC12) > AVCC – 0.3
Maximum DAC12
IL(DAC12) 2.2 V, 3 V mA
load current DAC12AMPx = 2, DAC12xDAT = 0h, 1
VO/P(DAC12) < 0.3 V
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V, 150 250
DAC12AMPx = 2, DAC12_xDAT = 0h
Output resistance RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V,
RO/P(DAC12) 2.2 V, 3 V 150 250 Ω
(see Figure 18) DAC12_xDAT = 0FFFh
RLoad = 3 kΩ,6
0.3 V ≤VO/P(DAC12) ≤AVCC – 0.3 V
(1) Data is valid after the offset calibration of the output amplifier.
Figure 18. DAC12_x Output Resistance Tests
76 Copyright © 2010–2012, Texas Instruments Incorporated
R = 3 k
Load W
AVCC
C = 100 pF
Load
2
DAC Output
RO/P(DAC12.x)
ILoad
Conversion 1 Conversion 2
VOUT
Conversion 3
Glitch
Energy
±1/2 LSB
±1/2 LSB
tsettleLH tsettleHL
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12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC AVCC
DAC12IR = 0(1) (2) / 3 + 0.2
Reference input voltage
VeREF+ 2.2 V, 3 V V
range AVCC
DAC12IR = 1(3) (4) AVCC + 0.2
DAC12_0 IR = DAC12_1 IR = 0 20 MΩ
DAC12_0 IR = 1, DAC12_1 IR = 0 48
Ri(VREF+),Reference input resistance(5) 2.2 V, 3 V
DAC12_0 IR = 0, DAC12_1 IR = 1 48
Ri(VeREF+) kΩ
DAC12_0 IR = DAC12_1 IR = 1, 24
DAC12_0 SREFx = DAC12_1 SREFx(6)
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
(5) This impedance depends on tradeoff in power savings. Current devices have 48 kΩfor each channel when divide is enabled. Can be
increased if performance can be maintained.
(6) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-Bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 19 and Figure 20), over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
DAC12AMPx = 0 →{2, 3, 4} 60 120
DAC12_xDAT = 800h,
tON DAC12 on time ErrorV(O) < ±0.5 LSB(1) DAC12AMPx = 0 →{5, 6} 2.2 V, 3 V 15 30 µs
(see Figure 19)DAC12AMPx = 0 →7 6 12
DAC12AMPx = 2 100 200
DAC12_xDAT =
tS(FS) Settling time, full scale DAC12AMPx = 3, 5 2.2 V, 3 V 40 80 µs
80h →F7Fh →80h DAC12AMPx = 4, 6, 7 15 30
DAC12AMPx = 2 5
DAC12_xDAT =
Settling time, code to
tS(C-C) 3F8h →408h →3F8h, DAC12AMPx = 3, 5 2.2 V, 3 V 2 µs
code BF8h →C08h →BF8h DAC12AMPx = 4, 6, 7 1
DAC12AMPx = 2 0.05 0.35
DAC12_xDAT =
SR Slew rate DAC12AMPx = 3, 5 2.2 V, 3 V 0.35 1.10 V/µs
80h →F7Fh →80h(2) DAC12AMPx = 4, 6, 7 1.50 5.20
DAC12_xDAT =
Glitch energy DAC12AMPx = 7 2.2 V, 3 V 35 nV-s
800h →7FFh →800h
(1) RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 19.
(2) Slew rate applies to output voltage steps ≥200 mV.
Figure 19. Settling Time and Glitch Energy Testing
Copyright © 2010–2012, Texas Instruments Incorporated 77
DAC12_xDAT 080h
VOUT
foggleT
7F7h
VDAC12_yOUT
080h 7F7h 080h
VDAC12_xOUT
RLoad
AVCC
CLoad =100pF
2
ILoad
DAC12_1
RLoad
AVCC
C =100pF
Load
2
ILoad
DAC12_0
DAC0
DAC1
VREF+
VeREF+
AC
DC
R =3k
Load W
AVCC
C =100pF
Load
2
ILoad
DAC12_x
DACx
Conversion 1 Conversion 2
VOUT
Conversion 3
10%
tSRLH tSRHL
90%
10%
90%
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Figure 20. Slew Rate Testing
12-Bit DAC, Dynamic Specifications (Continued)
over recommended ranges of supply voltage and TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, 40
DAC12IR = 1, DAC12_xDAT = 800h
3-dB bandwidth,
VDC = 1.5 V, DAC12AMPx = {5, 6}, DAC12SREFx = 2,
BW–3dB 2.2 V, 3 V 180 kHz
VAC = 0.1 VPP DAC12IR = 1, DAC12_xDAT = 800h
(see Figure 21)DAC12AMPx = 7, DAC12SREFx = 2, 550
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔F7Fh, RLoad = 3 kΩ, –80
Channel-to-channel fDAC12_0OUT = 10 kHz at 50/50 duty cycle
crosstalk(1) (see 2.2 V, 3 V dB
DAC12_0DAT = 80h ↔F7Fh, RLoad = 3 kΩ,
Figure 22)DAC12_1DAT = 800h, No load, –80
fDAC12_0OUT = 10 kHz at 50/50 duty cycle
(1) RLoad = 3 kΩ, CLoad = 100 pF
Figure 21. Test Conditions for 3-dB Bandwidth Specification
Figure 22. Crosstalk Test Conditions
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Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC Supply voltage 1.8 3.6 V
1.8 V 40
Comparator operating supply CBPWRMD = 00 2.2 V 30 50
current into AVCC terminal,
IAVCC_COMP 3 V 40 65 µA
Excludes reference resistor CBPWRMD = 01 2.2 V, 3 V 10 30
ladder CBPWRMD = 10 2.2 V, 3 V 0.1 0.5
Quiescent current of local
IAVCC_REF reference voltage amplifier CBREFACC = 1, CBREFLx = 01 22 µA
into AVCC terminal
VIC Common mode input range 0 VCC - 1 V
CBPWRMD = 00 ±20
VOFFSET Input offset voltage mV
CBPWRMD = 01, 10 ±10
CIN Input capacitance 5 pF
ON - switch closed 3 4 kΩ
RSIN Series input resistance OFF - switch opened 50 MΩ
CBPWRMD = 00, CBF = 0 450 ns
Propagation delay, response
tPD CBPWRMD = 01, CBF = 0 600 ns
time CBPWRMD = 10, CBF = 0 50 µs
CBPWRMD = 00, CBON = 1, CBF = 1, 0.35 0.6 1.0 µs
CBFDLY = 00
CBPWRMD = 00, CBON = 1, CBF = 1, 0.6 1.0 1.8 µs
CBFDLY = 01
Propagation delay with filter
tPD,filter active CBPWRMD = 00, CBON = 1, CBF = 1, 1.0 1.8 3.4 µs
CBFDLY = 10
CBPWRMD = 00, CBON = 1, CBF = 1, 1.8 3.4 6.5 µs
CBFDLY = 11
Comparator enable time, CBON = 0 to CBON = 1
tEN_CMP 1 2 µs
settling time CBPWRMD = 00, 01, 10
Resistor reference enable
tEN_REF CBON = 0 to CBON = 1 0.3 1.5 µs
time VIN × VIN × VIN ×
Reference voltage for a given VIN = reference into resistor ladder,
VCB_REF (n+0.5) (n+1) (n+1.5) V
tap n = 0 to 31 / 32 / 32 / 32
Copyright © 2010–2012, Texas Instruments Incorporated 79
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
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Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH High-level output voltage VUSB = 3.3 V ± 10%, IOH = -25 mA 2.4 V
VOL Low-level output voltage VUSB = 3.3 V ± 10%, IOL = 25 mA 0.4 V
VIH High-level input voltage VUSB = 3.3 V ± 10% 2.0 V
VIL Low-level input voltage VUSB = 3.3 V ± 10% 0.8 V
USB Output Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH D+, D- single ended USB 2.0 load conditions 2.8 3.6 V
VOL D+, D- single ended USB 2.0 load conditions 0 0.3 V
Z(DRV) D+, D- impedance Including external series resistor of 27 Ω28 44 Ω
tRISE Rise time Full speed, differential, CL= 50 pF, 10%/90%, Rpu on D+ 4 20 ns
tFALL Fall time Full speed, differential, CL= 50 pF, 10%/90%, Rpu on D+ 4 20 ns
USB Input Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(CM) Differential input common mode range 0.8 2.5 V
Z(IN) Input impedance 300 kΩ
VCRS Crossover voltage 1.3 2.0 V
VIL Static SE input logic low level 0.8 V
VIH Static SE input logic high level 2.0 V
VDI Differential input voltage 0.2 V
USB-PWR (USB Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VLAUNCH VBUS detection threshold 3.75 V
VBUS USB bus voltage Normal operation 3.76 5.5 V
VUSB USB LDO output voltage 3.3 ±9% V
V18 Internal USB voltage(1) 1.8 V
IUSB_EXT Maximum external current from VUSB terminal(2) USB LDO is on 12 mA
IDET USB LDO current overload detection(3) 60 100 mA
USB LDO is on,
ISUSPEND Operating supply current into VBUS terminal.(4) 250 µA
USB PLL disabled
CBUS VBUS terminal recommended capacitance 4.7 µF
CUSB VUSB terminal recommended capacitance 220 nF
C18 V18 terminal recommended capacitance 220 nF
Within 2%,
tENABLE Settling time VUSB and V18 2 ms
recommended capacitances
RPUR Pullup resistance of PUR terminal 70 110 150 Ω
(1) This voltage is for internal use only. No external dc loading should be applied.
(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
(3) A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
(4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
80 Copyright © 2010–2012, Texas Instruments Incorporated
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
USB-PLL (USB Phase-Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IPLL Operating supply current 7 mA
fPLL PLL frequency 48 MHz
fUPD PLL reference frequency 1.5 3 MHz
tLOCK PLL lock time 2 ms
tJitter PLL jitter 1000 ps
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage 1.8 3.6 V
IPGM Average supply current from DVCC during program 3 5 mA
IERASE Average supply current from DVCC during erase 2.5 mA
Average supply current from DVCC during mass erase or bank
IMERASE, IBANK 2 mA
erase
tCPT Cumulative program time See (1) 16 ms
Program and erase endurance 104105cycles
tRetention Data retention duration TJ= 25°C 100 years
tWord Word or byte program time See (2) 64 85 µs
tBlock, 0 Block program time for first byte or word See (2) 49 65 µs
Block program time for each additional byte or word, except for last
tBlock, 1–(N–1) See (2) 37 49 µs
byte or word
tBlock, N Block program time for last byte or word See (2) 55 73 µs
Erase time for segment, mass erase, and bank erase when
tSeg Erase See (2) 23 32 ms
available
MCLK frequency in marginal read mode
fMCLK,MGR 0 1 MHz
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
tSBW, En 2.2 V, 3 V 1 µs
edge)(1)
tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs
2.2 V 0 5 MHz
fTCK TCK input frequency (4-wire JTAG)(2) 3 V 0 10 MHz
Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
Copyright © 2010–2012, Texas Instruments Incorporated 81
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
Direction
0:Input
1:Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
EN
ModuleXIN
1
0
ModuleXOUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
1
0
DVSS
DVCC
P1REN.x
PadLogic
1
P1DS.x
0:Lowdrive
1:Highdrive
D
Bus
Keeper
S32...S39
LCDS32...LCDS39
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
82 Copyright © 2010–2012, Texas Instruments Incorporated
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 55. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x LCDS32...39
P1.0/TA0CLK/ACLK/ 0 P1.0 (I/O) I: 0; O: 1 0 0
S39 Timer TA0.TA0CLK 0 1 0
ACLK 1 1 0
S39 X X 1
P1.1/TA0.0/S38 1 P1.1 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI0A capture input 0 1 0
Timer TA0.0 output 1 1 0
S38 X X 1
P1.2/TA0.1/S37 2 P1.2 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI1A capture input 0 1 0
Timer TA0.1 output 1 1 0
S37 X X 1
P1.3/TA0.2/S36 3 P1.3 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI2A capture input 0 1 0
Timer TA0.2 output 1 1 0
S36 X X 1
P1.4/TA0.3/S35 4 P1.4 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI3A capture input 0 1 0
Timer TA0.3 output 1 1 0
S35 X X 1
P1.5/TA0.4/S34 5 P1.5 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI4A capture input 0 1 0
Timer TA0.4 output 1 1 0
S34 X X 1
P1.6/TA0.1/S33 6 P1.6 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI1B capture input 0 1 0
Timer TA0.1 output 1 1 0
S33 X X 1
P1.7/TA0.2/S32 7 P1.7 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI2B capture input 0 1 0
Timer TA0.2 output 1 1 0
S32 X X 1
(1) X = Don't care
Copyright © 2010–2012, Texas Instruments Incorporated 83
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
Direction
0:Input
1:Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
EN
ToPortMapping
1
0
FromPortMapping
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
1
0
DVSS
DVCC
P2REN.x
PadLogic
1
P2DS.x
0:Lowdrive
1:Highdrive
D
FromPortMapping
toLCD_B
fromLCD_B
FromPortMapping
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
84 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 56. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.x P2MAPx
P2.0/P2MAP0 0 P2.0 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤19
P2.1/P2MAP1 1 P2.1 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤19
P2.2/P2MAP2 2 P2.2 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤19
P2.3/P2MAP3 3 P2.3 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤19
P2.4/P2MAP4 4 P2.4 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤19
P2.5/P2MAP5 5 P2.5 (I/O I: 0; O: 1 0
Mapped secondary digital function X 1 ≤19
P2.6/P2MAP6/R03 6 P2.6 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤19
R03 X 1 = 31
P2.7/P2MAP7/ 7 P2.7 (I/O) I: 0; O: 1 0
LCDREF/R13 Mapped secondary digital function X 1 ≤19
LCDREF/R13 X 1 = 31
(1) X = Don't care
Copyright © 2010–2012, Texas Instruments Incorporated 85
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
Direction
0:Input
1:Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
EN
ModuleXIN
1
0
ModuleXOUT
P3OUT.x
1
0
DVSS
DVCC
P3REN.x
PadLogic
1
P3DS.x
0:Lowdrive
1:Highdrive
D
S24...S31
LCDS24...LCDS31
P3IRQ.x
Interrupt
Edge
Select
Q
EN
Set
P3SEL.x
P3IES.x
P3IFG.x
P3IE.x
Bus
Keeper
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
86 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 57. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL.x LCDS24...31
P3.0/TA1CLK/CBOUT/ 0 P3.0 (I/O) I: 0; O: 1 0 0
S31 Timer TA1.TA1CLK 0 1 0
CBOUT 1 1 0
S31 X X 1
P3.1/TA1.0/S30 1 P3.1 (I/O) I: 0; O: 1 0 0
Timer TA1.CCI0A capture input 0 1 0
Timer TA1.0 output 1 1 0
S30 X X 1
P3.2/TA1.1/S29 2 P3.2 (I/O) I: 0; O: 1 0 0
Timer TA1.CCI1A capture input 0 1 0
Timer TA1.1 output 1 1 0
S29 X X 1
P3.3/TA1.2/S28 3 P3.3 (I/O) I: 0; O: 1 0 0
Timer TA1.CCI2A capture input 0 1 0
Timer TA1.2 output 1 1 0
S28 X X 1
P3.4/TA2CLK/SMCLK/ 4 P3.4 (I/O) I: 0; O: 1 0 0
S27 Timer TA2.TA2CLK 0 1 0
SMCLK 1 1 0
S27 X X 1
P3.5/TA2.0/S26 5 P3.5 (I/O) I: 0; O: 1 0 0
Timer TA2.CCI0A capture input 0 1 0
Timer TA2.0 output 1 1 0
S26 X X 1
P3.6/TA2.1/S25 6 P3.6 (I/O) I: 0; O: 1 0 0
Timer TA2.CCI1A capture input 0 1 0
Timer TA2.1 output 1 1 1
S25 X X 1
P3.7/TA2.2/S24 7 P3.7 (I/O) I: 0; O: 1 0 0
Timer TA2.CCI2A capture input 0 1 0
Timer TA2.2 output 1 1 0
S24 X X 1
(1) X = Don't care
Copyright © 2010–2012, Texas Instruments Incorporated 87
P4.0/TB0.0/S23
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
P4.4/TB0.4/S19
P4.5/TB0.5/S18
P4.6/TB0.6/S17
P4.7/TB0OUTH/SVMOUT/S16
Direction
0:Input
1:Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
EN
ModuleXIN
1
0
ModuleXOUT
P4OUT.x
1
0
DVSS
DVCC
P4REN.x
PadLogic
1
P4DS.x
0:Lowdrive
1:Highdrive
D
S16...S23
LCDS16...LCDS23
P4IRQ.x
Interrupt
Edge
Select
Q
EN
Set
P4SEL.x
P4IES.x
P4IFG.x
P4IE.x
Bus
Keeper
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
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Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
88 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 58. Port P4 (P4.0 to P4.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P4.x) x FUNCTION P4DIR.x P4SEL.x LCDS16...23
P4.0/TB0.0/S23 0 P4.0 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI0A capture input 0 1 0
Timer TB0.0 output(2) 1 1 0
S23 X X 1
P4.1/TB0.1/S22 1 P4.1 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI1A capture input 0 1 0
Timer TB0.1 output(2) 1 1 0
S22 X X 1
P4.2/TB0.2/S21 2 P4.2 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI2A capture input 0 1 0
Timer TB0.2 output(2) 1 1 0
S21 X X 1
P4.3/TB0.3/S20 3 P4.3 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI3A capture input 0 1 0
Timer TB0.3 output(2) 1 1 0
S20 X X 1
P4.4/TB0.4/S19 4 P4.4 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI4A capture input 0 1 0
Timer TB0.4 output(2) 1 1 0
S19 X X 1
P4.5/TB0.5/S18 5 P4.5 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI5A capture input 0 1 0
Timer TB0.5 output(2) 1 1 0
S18 X X 1
P4.6/TB0.6/S17 6 P4.6 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI6A capture input 0 1 0
Timer TB0.6 output(2) 1 1 0
S17 X X 1
P4.7/TB0OUTH/ 7 P4.7 (I/O) I: 0; O: 1 0 0
SVMOUT/S16 Timer TB0.TB0OUTH 0 1 0
SVMOUT 1 1 0
S16 X X 1
(1) X = Don't care
(2) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.
Copyright © 2010–2012, Texas Instruments Incorporated 89
P5.0/VREF+/VeREF+
P5.1/VREF–/VeREF–
P5SEL.x
1
0
P5DIR.x
P5IN.x
EN
ModuleXIN
1
0
ModuleXOUT
P5OUT.x
1
0
DVSS
DVCC
P5REN.x
PadLogic
1
P5DS.x
0:Lowdrive
1:Highdrive
D
Bus
Keeper
To/From
Reference
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Table 59. Port P5 (P5.0 and P5.1) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.x REFOUT
P5.0/VREF+/VeREF+ 0 P5.0 (I/O)(2) I: 0; O: 1 0 X
VeREF+(3) X 1 0
VREF+(4) X 1 1
P5.1/VREF–/VeREF– 1 P5.1 (I/O)(2) I: 0; O: 1 0 X
VeREF–(5) X 1 0
VREF–(6) X 1 1
(1) X = Don't care
(2) Default condition
(3) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or
DAC12_A.
(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A, VREF+ reference is available at the pin.
(5) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or
DAC12_A.
(6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A, VREF– reference is available at the pin.
90 Copyright © 2010–2012, Texas Instruments Incorporated
P5.2/R23
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P5.6/ADC12CLK/DMAE0
P5.7/RTCCLK
Direction
0:Input
1:Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
EN
ModuleXIN
1
0
ModuleXOUT
P5OUT.x
1
0
DVSS
DVCC
P5REN.x
PadLogic
1
P5DS.x
0:Lowdrive
1:Highdrive
D
S40...S42
LCDS40...LCDS42
Bus
Keeper
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
Table 60. Port P5 (P5.2 to P5.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.x LCDS40...42
P5.2/R23 2 P5.2 (I/O) I: 0; O: 1 0 na
R23 X 1 na
P5.3/COM1/S42 3 P5.3 (I/O) I: 0; O: 1 0 0
COM1 X 1 X
S42 X 0 1
P5.4/COM2/S41 4 P5.4 (I/O) I: 0; O: 1 0 0
COM2 X 1 X
S41 X 0 1
P5.5/COM3/S40 5 P5.5 (I/O) I: 0; O: 1 0 0
COM3 X 1 X
S40 X 0 1
P5.6/ADC12CLK/DMAE0 6 P5.6 (I/O) I: 0; O: 1 0 na
ADC12CLK 1 1 na
DMAE0 0 1 na
P5.7/RTCCLK 7 P5.7 (I/O) I: 0; O: 1 0 na
RTCCLK 1 1 na
(1) X = Don't care
Copyright © 2010–2012, Texas Instruments Incorporated 91
P6SEL.x
P6DIR.x
P6IN.x
P6OUT.x
1
0
DVSS
DVCC
P6REN.x
PadLogic
1
P6DS.x
0:Lowdrive
1:Highdrive
Bus
Keeper
To ADC12
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
INCHx=y
FromDAC12_A
ToComparator_B
FromComparator_B
CBPD.x
0
1
2
Dvss
0ifDAC12AMPx=0
1ifDAC12AMPx=1
2ifDAC12AMPx>1
DAC12AMPx>0
DAC12OPS
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
92 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 61. Port P6 (P6.0 to P6.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P6.x) x FUNCTION P6DIR.x P6SEL.x CBPD.x DAC12OPS DAC12AMPx
P6.0/CB0/A0 0 P6.0 (I/O) I: 0; O: 1 0 0 n/a n/a
CB0 X X 1 n/a n/a
A0(2) (3) X 1 X n/a n/a
P6.1/CB1/A1 1 P6.1 (I/O) I: 0; O: 1 0 0 n/a n/a
CB1 X X 1 n/a n/a
A1(2) (3) X 1 X n/a n/a
P6.2/CB2/A2 2 P6.2 (I/O) I: 0; O: 1 0 0 n/a n/a
CB2 X X 1 n/a n/a
A2(2) (3) X 1 X n/a n/a
P6.3/CB3/A3 3 P6.3 (I/O) I: 0; O: 1 0 0 n/a n/a
CB3 X X 1 n/a n/a
A3(2) (3) X 1 X n/a n/a
P6.4/CB4/A4 4 P6.4 (I/O) I: 0; O: 1 0 0 n/a n/a
CB4 X X 1 n/a n/a
A4(2) (3) X 1 X n/a n/a
P6.5/CB5/A5 5 P6.5 (I/O) I: 0; O: 1 0 0 n/a n/a
CB5 X X 1 n/a n/a
A5(4) (2) (3) X 1 X n/a n/a
P6.6/CB6/A6/DAC0 6 P6.6 (I/O) I: 0; O: 1 0 0 X 0
CB6 X X 1 X 0
A6(2) (3) X 1 X X 0
DAC0 X X X 0 >1
P6.7/CB7/A7/DAC1 7 P6.7 (I/O) I: 0; O: 1 0 0 X 0
CB7 X X 1 X 0
A7(2) (3) X 1 X X 0
DAC1 X X X 0 >1
(1) X = Don't care
(2) Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.
(4) X = Don't care
Copyright © 2010–2012, Texas Instruments Incorporated 93
P7.3/XT2OUT
P7SEL.3
1
0
P7DIR.3
P7IN.3
P7OUT.3
1
0
DVSS
DVCC
P7REN.3
PadLogic
1
P7DS.3
0:Lowdrive
1:Highdrive
Bus
Keeper
ToXT2
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Port P7, P7.3, Input/Output With Schmitt Trigger
Table 62. Port P7 (P7.2 and P7.3) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P5.x) x FUNCTION P7DIR.x P7SEL.2 P7SEL.3 XT2BYPASS
P7.2/XT2IN 2 P7.2 (I/O) I: 0; O: 1 0 X X
XT2IN crystal mode(2) X 1 X 0
XT2IN bypass mode(2) X 1 X 1
P7.3/XT2OUT 3 P7.3 (I/O) I: 0; O: 1 0 X X
XT2OUT crystal mode(3) X 1 X 0
P7.3 (I/O)(3) X 1 X 1
(1) X = Don't care
(2) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal
mode or bypass mode.
(3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as
general-purpose I/O.
Copyright © 2010–2012, Texas Instruments Incorporated 95
P7SEL.x
P7DIR.x
P7IN.x
P7OUT.x
1
0
DVSS
DVCC
P7REN.x
PadLogic
1
P7DS.x
0:Lowdrive
1:Highdrive
Bus
Keeper
FromDAC12_A
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
INCHx=y
To ADC12
ToComparator_B
FromComparator_B
CBPD.x
0
1
2
Dvss
0ifDAC12AMPx=0
1ifDAC12AMPx=1
2ifDAC12AMPx>1
DAC12AMPx>0
DAC12OPS
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
96 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 63. Port P7 (P7.4 to P7.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P7.x) x FUNCTION P7DIR.x P7SEL.x CBPD.x DAC12OPS DAC12AMPx
P7.4/CB8/A12 4 P7.4 (I/O) I: 0; O: 1 0 0 n/a n/a
Comparator_B input CB8 X X 1 n/a n/a
A12(2) (3) X 1 X n/a n/a
P7.5/CB9/A13 5 P7.5 (I/O) I: 0; O: 1 0 0 n/a n/a
Comparator_B input CB9 X X 1 n/a n/a
A13(2) (3) X 1 X n/a n/a
P7.6/CB10/A14/DAC0 6 P7.6 (I/O) I: 0; O: 1 0 0 X 0
Comparator_B input CB10 X X 1 X 0
A14(2) (3) X 1 X X 0
DAC12_A output DAC0 X X X 1 >1
P7.7/CB11/A15/DAC1 7 P7.7 (I/O) I: 0; O: 1 0 0 X 0
Comparator_B input CB11 X X 1 X 0
A15(2) (3) X 1 X X 0
DAC12_A output DAC1 X X X 1 >1
(1) X = Don't care
(2) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.
Copyright © 2010–2012, Texas Instruments Incorporated 97
P8.0/TB0CLK/S15
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO//UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
P8.7/S8
Direction
0:Input
1:Output
P8SEL.x
1
0
P8DIR.x
P8IN.x
EN
ModuleXIN
1
0
ModuleXOUT
P8OUT.x
1
0
DVSS
DVCC
P8REN.x
PadLogic
1
P8DS.x
0:Lowdrive
1:Highdrive
D
S8...S15
LCDS8...LCDS15
Bus
Keeper
Frommodule
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
98 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 64. Port P8 (P8.0 to P8.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P9.x) x FUNCTION P8DIR.x P8SEL.x LCDS8...16
P8.0/TB0CLK/S15 0 P8.0 (I/O) I: 0; O: 1 0 0
Timer TB0.TB0CLK clock input 0 1 0
S15 X X 1
P8.1/UCB1STE/UCA1CLK/S14 1 P8.1 (I/O) I: 0; O: 1 0 0
UCB1STE/UCA1CLK X 1 0
S14 X X 1
P8.2/UCA1TXD/UCA1SIMO/S13 2 P8.2 (I/O) I: 0; O: 1 0 0
UCA1TXD/UCA1SIMO X 1 0
S13 X X 1
P8.3/UCA1RXD/UCA1SOMI/S12 3 P8.3 (I/O) I: 0; O: 1 0 0
UCA1RXD/UCA1SOMI X 1 0
S12 X X 1
P8.4/UCB1CLK/UCA1STE/S11 4 P8.4 (I/O) I: 0; O: 1 0 0
UCB1CLK/UCA1STE X 1 0
S11 X X 1
P8.5/UCB1SIMO/UCB1SDA/S10 5 P8.5 (I/O) I: 0; O: 1 0 0
UCB1SIMO/UCB1SDA X 1 0
S10 X X 1
P8.6/UCB1SOMI/UCB1SCL/S9 6 P8.6 (I/O) I: 0; O: 1 0 0
UCB1SOMI/UCB1SCL X 1 0
S9 X X 1
P8.7/S8 7 P8.7 (I/O) I: 0; O: 1 0 0
S8 X X 1
(1) X = Don't care
Copyright © 2010–2012, Texas Instruments Incorporated 99
P9.0/S7
P9.1/S6
P9.2/S5
P9.3/S4
P9.4/S3
P9.5/S2
P9.6/S1
P9.7/S0
Direction
0:Input
1:Output
P9DIR.x
P9IN.x
P9OUT.x
1
0
DVSS
DVCC
P9REN.x
PadLogic
1
P9DS.x
0:Lowdrive
1:Highdrive
S0...S7
LCDS0...LCDS7
Bus
Keeper
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
Table 65. Port P9 (P9.0 to P9.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P9.x) x FUNCTION P9DIR.x P9SEL.x LCDS0...7
P9.0/S7 0 P9.0 (I/O) I: 0; O: 1 0 0
S7 X X 1
P9.1/S6 1 P9.1 (I/O) I: 0; O: 1 0 0
S6 X X 1
P9.2/S5 2 P9.2 (I/O) I: 0; O: 1 0 0
S5 X X 1
P9.3/S4 3 P9.3 (I/O) I: 0; O: 1 0 0
S4 X X 1
P9.4/S3 4 P9.4 (I/O) I: 0; O: 1 0 0
S3 X X 1
P9.5/S2 5 P9.5 (I/O) I: 0; O: 1 0 0
S2 X X 1
P9.6/S1 6 P9.6 (I/O) I: 0; O: 1 0 0
S1 X X 1
P9.7/S0 7 P9.7 (I/O) I: 0; O: 1 0 0
S0 X X 1
(1) X = Don't care
100 Copyright © 2010–2012, Texas Instruments Incorporated
PUOPE 0
1
0
1
PUOUT0
PUSEL
PadLogic
PU.0/
DP
VUSB VSSU
PU.1/
DM
0
1
PUOUT1
.
PUIN1
USBDMinput
PUIN0
USBDP input
USBDMoutput
USBDP output
USBoutputenable
PUSEL
PadLogic
PUR
VUSB VSSU
“1”
PUREN
PURIN
PUIPE
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Port PU.0/DP, PU.1/DM, PUR USB Ports
Table 66. Port PU.0/DP, PU.1/DM Output Functions
CONTROL BITS PIN NAME FUNCTION
PUSEL PUDIR PUOUT1 PUOUT0 PU.1/DM PU.0/DP
0 0 X X Hi-Z Hi-Z Outputs off
0 1 0 0 0 0 Outputs enabled
0 1 0 1 0 1 Outputs enabled
0 1 1 0 1 0 Outputs enabled
0 1 1 1 1 1 Outputs enabled
1 X X X DM DP Direction set by USB module
Table 67. Port PUR Input Functions
CONTROL BITS FUNCTION
PUSEL PUREN
Input disabled
0 0 Pullup disabled
Copyright © 2010–2012, Texas Instruments Incorporated 101
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
From JTAG
1
0
PJDIR.x
PJIN.x
EN
1
0
From JTAG
PJOUT.x
1
0
DVSS
DVCC
PJREN.x Pad Logic
1
PJDS.x
0: Low drive
1: High drive
D
DVSS
To JTAG
PJ.0/TDO
From JTAG
1
0
PJDIR.0
PJIN.0
EN
1
0
From JTAG
PJOUT.0
1
0
DVSS
DVCC
PJREN.0 Pad Logic
1
PJDS.0
0: Low drive
1: High drive
D
DVCC
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Copyright © 2010–2012, Texas Instruments Incorporated 103
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Table 68. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/
SIGNALS(1)
PIN NAME (PJ.x) x FUNCTION PJDIR.x
PJ.0/TDO 0 PJ.0 (I/O)(2) I: 0; O: 1
TDO(3) X
PJ.1/TDI/TCLK 1 PJ.1 (I/O)(2) I: 0; O: 1
TDI/TCLK(3) (4) X
PJ.2/TMS 2 PJ.2 (I/O)(2) I: 0; O: 1
TMS(3) (4) X
PJ.3/TCK 3 PJ.3 (I/O)(2) I: 0; O: 1
TCK(3) (4) X
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
104 Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
www.ti.com
SLAS566C –JUNE 2010–REVISED AUGUST 2012
DEVICE DESCRIPTORS
Table 69 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type.
Table 69. MSP430F663x Device Descriptor Table(1)
F6638 F6637 F6636 F6635 F6634 F6633 F6632 F6631 F6630
Size
Description Address bytes Value Value Value Value Value Value Value Value Value
Info Block Info length 01A00h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h
CRC value 01A02h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit
Device ID 01A04h 2 801Ch 801Ah 8018h 8016h 804Eh 804Ch 804Ah 8048h 8046h
Hardware revision 01A06h 1 per unit per unit per unit per unit per unit per unit per unit per unit per unit
Firmware revision 01A07h 1 per unit per unit per unit per unit per unit per unit per unit per unit per unit
Die Record Die Record Tag 01A08h 1 08h 08h 08h 08h 08h 08h 08h 08h 08h
Die Record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/Wafer ID 01A0Ah 4 per unit per unit per unit per unit per unit per unit per unit per unit per unit
Die X position 01A0Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit
Die Y position 01A10h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit
Test results 01A12h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit
ADC12 ADC12 Calibration Tag 01A14h 1 11h 11h 11h 11h 11h 11h 05h 05h 05h
Calibration
ADC12 Calibration 01A15h 1 10h 10h 10h 10h 10h 10h 10h 10h 10h
length
ADC Gain Factor 01A16h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A
ADC Offset 01A18h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A
ADC 1.5-V Reference 01A1Ah 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A
Temp. Sensor 30°C
ADC 1.5-V Reference 01A1Ch 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A
Temp. Sensor 85°C
ADC 2.0-V Reference 01A1Eh 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A
Temp. Sensor 30°C
ADC 2.0-V Reference 01A20h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A
Temp. Sensor 85°C
ADC 2.5-V Reference 01A22h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A
Temp. Sensor 30°C
ADC 2.5-V Reference 01A24h 2 per unit per unit per unit per unit per unit per unit N/A N/A N/A
Temp. Sensor 85°C
(1) NA = Not applicable
Copyright © 2010–2012, Texas Instruments Incorporated 105
MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
REVISION HISTORY
REVISION COMMENTS
SLAS566 Product Preview release
SLAS566A Updated Product Preview including electrical specifications
SLAS566B Production Data release
Changed description of ACLK and PUR in Terminal Functions.
Changed typos to Interrupt Flag names on Timer TA2 rows in Table 6.
Changed SYSRSTIV, System Reset offset 1Ch to Reserved in Table 14.
Corrected names of SVMLVLRIFG and SVMHVLRIFG bits in Table 14.
SLAS566C Added note regarding evaluation of PUR in USB BSL.
Changed notes on REF, Built-In Reference.
Changed tSENSOR(sample) MIN to 100 µs in 12-Bit ADC, Temperature Sensor and Built-In VMID.
Changed note (2) in 12-Bit ADC, Temperature Sensor and Built-In VMID.
Editorial changes throughout.
106 Copyright © 2010–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F6630IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6630IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6630IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6630ZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 100 TBD Call TI Call TI
MSP430F6631IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6631IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6631IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6631ZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 100 TBD Call TI Call TI
MSP430F6632IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6632IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6632IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6632ZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 100 TBD Call TI Call TI
MSP430F6633IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6633IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F6633IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6633ZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 100 TBD Call TI Call TI
MSP430F6634IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6634IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6634IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6634ZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 100 TBD Call TI Call TI
MSP430F6635IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6635IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6635IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6635ZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 100 TBD Call TI Call TI
MSP430F6636IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6636IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6636IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6636ZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 100 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F6637IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6637IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6637IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6637IZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6638CY ACTIVE Green (RoHS
& no Sb/Br) Call TI N / A for Pkg Type
MSP430F6638CYS ACTIVE WAFERSALE YS 0 1 TBD Call TI Call TI
MSP430F6638IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6638IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F6638IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F6638IZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2012
Addendum-Page 4
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F6632IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F6633IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F6633IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430F6634IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430F6635IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F6635IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430F6636IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430F6637IZQWT BGA MI
CROSTA
R JUNI
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OR
MSP430F6638IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F6638IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430F6638IZQWT BGA MI
CROSTA
R JUNI
OR
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F6632IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F6633IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F6633IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
MSP430F6634IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
MSP430F6635IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F6635IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Jul-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F6636IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
MSP430F6637IZQWT BGA MICROSTAR
JUNIOR ZQW 113 250 336.6 336.6 28.6
MSP430F6638IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F6638IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
MSP430F6638IZQWT BGA MICROSTAR
JUNIOR ZQW 113 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Jul-2012
Pack Materials-Page 3
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 11/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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