L99H01QFTR - STMicroelectronics - Datasheet.Directory

This is information on a product in full production.

April 2012 Doc ID 15567 Rev. 4 1/53

L99H01

Motor bridge driver for automotive applications

Datasheet − production data

Features

■Operating supply voltage 6 V to 28 V

■Central 2 stage charge pump

■100% duty cycle

■

Full R

DSon

down to 6 V (normal level MOSFETs)

■Control of reverse battery protection MOSFET

■Charge pump current limited

■PWM operation up to 30 kHz

■SPI interface

■Current sense amplifier / free configurable

■Zero adjust for end of line trimming

■Power management: programmable free

wheeling

■Sensing circuitry of external MOSFETs with

embedded thermal sensors

Applications

■Wiper

■Power door

■Seat belt tensioner

■Seat positioning

■Valve tronic

■Park break

■2H motors

Description

The L99H01 is designed to control 4 external

N-channel MOS transistors in bridge configuration

for DC-motor driving in automotive applications. A

free configurable current sense amplifier is

integrated. The integrated standard serial

peripheral interface (SPI) controls all outputs and

provides diagnostic information. An interface pin

for the thermal sensors of the external MOSFETs

is implemented.

PowerSSO-36

LQFP32

7x7mm

Table 1. Device summary

Package Order codes

Part number (tube) Part number (tape and reel) Part number (tray)

PowerSSO-36 L99H01XP L99H01XPTR —

LQFP32 — L99H01QFTR L99H01QF

www.st.com

Contents L99H01

2/53 Doc ID 15567 Rev. 4

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Pinout PowerSSO-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Pinout LQFP32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2 Standby mode (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3 H-bridge control (DIR, PWM, bit FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4 Resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.5 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.6 Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.8 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 28

3.9 Short-circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . . 28

3.10 Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.11 Current sense amplifier (CSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.12 Thermal sensor interface / H-bridge switch-off input . . . . . . . . . . . . . . . . 29

3.12.1 EXT_TS-bit = low (active off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.12.2 EXT_TS-bit = high (thermal sensor interface) . . . . . . . . . . . . . . . . . . . . 29

3.13 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.2 Serial data input (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

L99H01 Contents

Doc ID 15567 Rev. 4 3/53

4.1.3 Serial data output (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.4 Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2 General data description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2.2 OpCode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3 Device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.1 Control and status (RAM) address map . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.2 Device (ROM) address map (access with OC0 and OC1 set to ‘1’) . . . 34

4.4 Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.4.1 SPI clock monitor and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.5 Detailed byte description of status register (StatReg0) . . . . . . . . . . . . . . 37

4.6 Detailed byte description of application registers (ApplRegX) . . . . . . . . . 38

4.6.1 Description of the data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.7 Read device information (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.3 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.4 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.5 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.6 LQFP32 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

List of tables L99H01

4/53 Doc ID 15567 Rev. 4

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. Packages thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 9. Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 10. Undervoltage detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 11. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 12. Inputs: CSN, CLK, PWM, DIR, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 13. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 14. Gate drivers for external PowerMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 15. Cross current protection time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 16. Drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 17. Thermal sense interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 18. Current sense amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 19. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 20. DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 21. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 22. EN, CSN timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 23. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 24. DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 25. DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 26. Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 27. Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 28. Control and status (RAM) address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 29. Device (ROM) address map (access with OC0 and OC1 set to ‘1’) . . . . . . . . . . . . . . . . . . 34

Table 30. STK_RESET_Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 31. Address 0<00(hex)>:StatReg 0 - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 32. DS_MON - drivers relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 33. Address 1 <01(hex)>:ApplReg1-read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 34. Overvoltage threshold of the Vs monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 35. DIAG monitoring of source voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 36. Address 2 <02(hex)> : ApplReg2 – read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 37. Cross current protection time (tCCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 38. Multiplexer for current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 39. Gain of current sense amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 40. Address 3 <03(hex)> : ApplReg3 – read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 41. External threshold voltage, factor n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 42. External threshold voltage, factor m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 43. Read device information (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 44. Address 0 <00(hex)> : ID-header - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 45. Address 1 <01(hex)>: product ID (LSB) - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 46. Address 2 <02(hex)>: product ID (MSB) - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 47. Address 3 <03(hex)>: SPI frame ID - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 48. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

L99H01 List of tables

Doc ID 15567 Rev. 4 5/53

Table 49. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

List of figures L99H01

6/53 Doc ID 15567 Rev. 4

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Pinning of device in PowerSSO-36 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. Pinning of device in LQFP-32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. Output timing diagram (active free wheeling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5. Output timing diagram (passive free wheeling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7. SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11. Global error flag diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 12. PowerSSO-36 Rthj-amb vs. PCB copper area in open free air condition(1) . . . . . . . . . . . . . 43

Figure 13. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 14. LQFP32 Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . 47

Figure 15. LQFP32 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 16. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 17. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 18. LQFP32 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 19. LQFP32 tray shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

L99H01 Block diagram and pin description

Doc ID 15567 Rev. 4 7/53

1 Block diagram and pin description

Figure 1. Block diagram

1.1 Pinout PowerSSO-36

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&61

&/.

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3:0

63,

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026)(7

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'ATE

$RIVER

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'LDJQRVLV

&RQWURO

'LDJQRVLV

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6+

*/

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&6,

'L II HU HQW L DO &XU U HQ W

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&6,

&6,

&62

&XUUHQW6HQVH08;

3URJUDPPDEOH

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*1'

&3 &3 &3 &3 &3

&HQWUDO6WHS&KDUJH3XPS

9&3

3URJUDPPDEOH

9'67 +W'HD G

*+

6+

*/

6/

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2YHUYROWDJH'HW

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7HPSH UDWXUH3UHZDUQLQJ

7HPSHUDWXUH 6KXWG RZQ

6/

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

9FF

76

$&7B2))

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&

95(*

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OPTIONALCONTROL

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Table 2. Pin definitions and functions

Pin Symbol Function

1 GND Ground. Reference potential, connected to slug.

2 GNDD Digital ground. Reference potential.

CCD

Logic voltage supply 3.3 V/5 V: for this input a ceramic capacitor as

close as possible to GND is recommended.

Analog voltage supply 3.3 V/5 V: for this input a ceramic capacitor as

close as possible to GND is recommended.

5 EN Enable input. The enable input has a pull-down resistor.

6DIR

Direction select input for H-bridge control. This input has a pull-down

current.

7 PWM PWM input for H-bridge control. This input has a pull-down current.

8CSN

Chip select not input: this input is low active and requires CMOS logic

levels. The serial data transfer between L99H01 and microcontroller is

enabled by pulling the input CSN to low-level. This input has a pull-up

current.

Block diagram and pin description L99H01

8/53 Doc ID 15567 Rev. 4

9CLK

Serial clock input: this input controls the internal shift register of the

SPI and requires CMOS logic levels.This input has a pull-down

current.

10 DI

Serial data in: the input requires CMOS logic levels and receives serial

data from the microcontroller. The data is an 8-bit control word and the

most significant bit (MSB, bit 7) is transferred first. This input has a

pull-down current.

11 DO

Serial data out: the diagnosis data is available via the SPI and this

tristate-output. The output remains in tristate, if the chip is not selected

by the input CSN (CSN = high).

12, 14, 19,

20, 22 NC Not connected.

13 CSO Current sense amplifier output: VCC compatible.

15 CSI1+ Current sense amplifier input: positive input 1, multiplexible.

16 CSI1- Current sense amplifier input: negative input 1, multiplexible.

17 CSI2+ Current sense amplifier input: positive input 2, multiplexible.

18 CSI2- Current sense amplifier input: negative input 2, multiplexible.

21 TS/ ACT_OFF Thermal sensor interface or input to switch all driver active off.

23 GL2 Gate driver for PowerMOS low-side switch in halfbridge 2.

24 SL2 Source of low-side switch in halfbridge 2.

25 GH2 Gate driver for PowerMOS high-side switch in halfbridge 2.

26 SH2 Source/drain of halfbridge 2.

27 SL1 Source of low-side switch in halfbridge 1.

28 GL1 Gate driver for PowerMOS low-side switch in halfbridge 1.

29 SH1 Source/drain of halfbridge 1.

30 GH1 Gate driver for PowerMOS high-side switch in halfbridge 1.

31 CP Charge pump output.

32 CP2+ Charge pump pin for capacitor 2, positive side.

33 CP2- Charge pump pin for capacitor 2, negative side.

34 CP1+ Charge pump pin for capacitor 1, positive side.

35 CP1- Charge pump pin for capacitor 1, negative side.

36 VS

Power supply voltage (external reverse protection required).

For EMI reason a ceramic capacitor as close as possible to GND is

recommended.

Table 2. Pin definitions and functions (continued)

Pin Symbol Function

L99H01 Block diagram and pin description

Doc ID 15567 Rev. 4 9/53

Figure 2. Pinning of device in PowerSSO-36 package

1. The slug is connected to pin 1.

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Table 3. Pin definitions and functions

Pin Symbol Function

1 CP2- Charge pump pin for capacitor 2, negative side.

2 CP1+ Charge pump pin for capacitor 1, positive side.

3 CP1- Charge pump pin for capacitor 1, negative side.

Power supply voltage (external reverse protection required).

For EMI reason a ceramic capacitor as close as possible to GND is

recommended.

5 GND Ground. Reference potential, connected to slug.

6 GNDD Digital ground. Reference potential.

CCD

Logic voltage supply 3.3 V/5 V: for this input a ceramic capacitor as

close as possible to GND is recommended.

Analog voltage supply 3.3 V/5 V: for this input a ceramic capacitor as

close as possible to GND is recommended.

9 EN Enable input. The enable input has a pull-down resistor.

Block diagram and pin description L99H01

10/53 Doc ID 15567 Rev. 4

10 DIR Direction select input for H-bridge control. This input has a pull-down

current.

11 PWM PWM input for H-bridge control. This input has a pull-down current.

12 CSN

Chip select not input: this input is low active and requires CMOS logic

levels. The serial data transfer between L99H01 and microcontroller is

enabled by pulling the input CSN to low-level. This input has a pull-up

current.

13 CLK

Serial clock input: this input controls the internal shift register of the

SPI and requires CMOS logic levels.This input has a pull-down

current.

14 DI

Serial data in: the input requires CMOS logic levels and receives serial

data from the microcontroller. The data is an 8-bit control word and the

most significant bit (MSB, bit 7) is transferred first. This input has a

pull-down current.

15 DO

Serial data out: the diagnosis data is available via the SPI and this

tristate-output. The output remains in tristate, if the chip is not selected

by the input CSN (CSN = high).

16 CSO Current sense amplifier output: VCC compatible.

17 CSI1+ Current sense amplifier input: positive input 1, multiplexible.

18 CSI1- Current sense amplifier input: negative input 1, multiplexible.

19 CSI2+ Current sense amplifier input: positive input 2, multiplexible.

20 CSI2- Current sense amplifier input: negative input 2, multiplexible.

21 NC Not connected.

22 TS/ ACT_OFF Thermal sensor interface or external off for all gate drivers.

23 GL2 Gate driver for PowerMOS low-side switch in halfbridge 2.

24 SL2 Source of low-side switch in halfbridge 2.

25 GH2 Gate driver for PowerMOS high-side switch in halfbridge 2.

26 SH2 Source/drain of halfbridge 2.

27 SL1 Source of low-side switch in halfbridge 1.

28 GL1 Gate driver for PowerMOS low-side switch in halfbridge 1.

29 SH1 Source/drain of halfbridge 1.

30 GH1 Gate driver for PowerMOS high-side switch in halfbridge 1.

31 CP Charge pump output.

32 CP2+ Charge pump pin for capacitor 2, positive side.

Table 3. Pin definitions and functions (continued)

Pin Symbol Function

L99H01 Block diagram and pin description

Doc ID 15567 Rev. 4 11/53

Figure 3. Pinning of device in LQFP-32 package

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Ele ctrical specifications L99H01

12/53 Doc ID 15567 Rev. 4

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the Ta ble 4 may cause permanent damage to

the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

2.2 ESD protection

Table 4. Absolute maximum ratings

Item Symbol Parameter Value Unit

4.1.1 VS

Power supply voltage -0,3 to 35 V

4.1.2 Single pulse tmax < 400 ms 40 V

4.2 VCC Stabilished supply voltage -0.3 to 5.5 V

4.3 DI, DO, CLK, CSN,

EN, DIR, PWM Digital input / output voltage -0.3 to VCC + 0.3 V

4.4 CSO, TS Analog input / output voltage -0.3 to VCC + 0.3 V

4.5 CSI1+, CSI1-,

CSI2+, CSI2- HV signal pins -4 to VS + 5V V

4.6 GL2, GH2, GL1,

GH1 (Gxy) HV signal pins Sxy - 1 to Sxy + 10;

VCP +0.3 V

4.7 SL2, SH2, SL1, SH1 HV signal pins -6 to 40 V

4.8 CP2- CP1- HV signal pins -0.3 to VS + 0.3 V

4.9 CP1+ HV signal pins VS- 0.3 to VS+10 V

4.10 CP2+ HV signal pins VS- 0.6 to VS+10 V

4.11 CP Power pin VS- 0.3 to VS+10 V

Table 5. ESD protection

Item Parameter Value Unit

5.1 All pins ± 2 (1)

1. - HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.

- HBM with all unzapped pins grounded.

5.2 VS versus GND ± 4 (1) kV

L99H01 Electrical specifications

Doc ID 15567 Rev. 4 13/53

2.3 Thermal data

2.4 Electrical characteristics

VS = 6 V to 28 V, VCC = 3 V to 5.3 V, Tj = -40°C to 150°C, unless otherwise specified.

The voltages are referred to GND and currents are assumed positive, when the current

flows into the pin.

Table 6. Operating junction temperature

Item Symbol Parameter Value Unit

6.1 TjOperating junction temperature -40 to 150 °C

Table 7. Temperature warning and thermal shutdown

Item Symbol Parameter Min. Typ. Max. Unit

7.1 TjTW ON

Temperature warning threshold

junction temperature Tj135 — 165 °C

7.2 TjSD ON

Thermal shutdown threshold

junction temperature Tj increasing 155 — 185 °C

7.3 TjSD OFF

Thermal shutdown threshold

junction temperature Tj decreasing 150 — 180 °C

Table 8. Packages thermal resistance

Item Symbol Parameter Value Unit

PowerSSO-36 LQFP32

8.1 Rthj-amb

Thermal resistance junction-

ambient (max.) 58(1)

1. Minimum footprint.

80(1) °C/W

Table 9. Supply

Item Symbol Paramete r Test condition Min. Typ. Max. Unit

9.1 VS

Operating supply

voltage range 628V

9.2 VVS_OV1

Overvoltage disable

high threshold 1 SPI: OVT = 1 28 30.5 32 V

9.3 VVS_OV1H

Overvoltage threshold

1 hysteresis 0.57 0.77 1.07 V

9.4 VVS_OV2

Overvoltage disable

high threshold 2 SPI: OVT = 0 18 20 22 V

9.5 VVS_OV2H

Overvoltage threshold

2 hysteresis 0.42 0.62 0.82 V

Ele ctrical specifications L99H01

14/53 Doc ID 15567 Rev. 4

9.6 VVS_UV

Undervoltage disable

low threshold 4.7 4.9 5.1 V

9.7 VVS_UVH

Undervoltage threshold

hysteresis 0.2 0.3 0.4 V

9.8.1

ISVS DC supply current

VS=13V; V

CC =5V;

Active mode; Outputs

floating

4.5 5.5 6.5 mA

9.8.2

VS= 6 V to 28 V;

VCC = 5.0 V; Active

mode; Outputs floating

2.5 18 mA

9.9 ISL

VS quiescent supply

current

VS=13V; V

CC =0V;

Standby mode;

TTes t = -40°C, 25°C;

Outputs floating

5µA

9.10 ICC VCC DC supply current VS=13V; V

CC =5V;

active mode 1.5 1.8 2.5 mA

9.11 ICC

VCC quiescent supply

current

VCC = 5 V; standby

mode 30 70 150 µA

9.12 ICCdVCCd supply current

VS = 13 V;

VCC =V

CCd=5V;

active mode

250 500 750 µA

Table 10. Undervoltage detection

Item Symbol Parameter Test condition Min. Typ. Max. Unit

10.1 VPOR OFF Power-on reset threshold VCC increasing 2.2 2.55 2.8 V

10.2 VPOR ON Power-on reset threshold VCC decreasing 2.0 2.25 2.6 V

10.3 VPOR hyst

Power-on reset

hysteresis VPOR OFF - VPOR ON 0.2 0.3 0.4 V

Table 11. Watchdog

Item Symbol Parameter Test condition Min. Typ. Max. Unit

11.1 TWDTO Watchdog time out — 50 60 100 ms

Table 9. Supply (continued)

Item Symbol Paramete r Test condition Min. Typ. Max. Unit

L99H01 Electrical specifications

Doc ID 15567 Rev. 4 15/53

Table 12. Inputs: CSN, CLK, PWM, DIR, EN and DI

Item Symbol Parameter Test condition Min. Typ. Max. Unit

12.1 Vin L Low-level input voltage 0.3 * VCC 0.4 * VCC V

12.2 Vin H High-level input voltage 0.6 * VCC 0.7 * VCC V

12.3 Vin Hyst Input voltage hysteresis 0.1 * VCC V

12.4 ICSN in Pull-up current at input CSN VCSN =V

CC - 1.5 V -50 -25 -10 µA

12.5 ICLK in

Pull-down current at input

CLK VCLK =1.5V 103550µA

12.6 IDI in Pull-down current at input DI VDI =1.5V 103550µA

12.7 IDIR in Pull-down current at input DIR VDIR =1.5V 103550µA

12.8 IPWM in

Pull-down current at input

PWM VPWM =1.5V 103550µA

12.9 REN in

Pull-down resistance at input

EN VEN = VCC 100 210 480 kΩ

12.10 Cin(1) Input capacitance at input

CSN, CLK, DI, DIR and PWM 0V<V

CC <5.3V 10 15 pF

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 13. Charge pump output

Item Symbol Parameter Test condition Min. Ty p. Max. Unit

13.1.1

VCP

Charge pump output

voltage

VS = 6 V; ICP = 15 mA VS+6 V

S+7 V

S+7.5 V

13.1.2 VS = 10 V; ICP = 15 mA VS+11 V

+12

VS+13.5 V

13.1.3 VS > 12 V; ICP = 15 mA VS+11 V

+12

VS+13.5 V

13.2 ICP

Charge pump output

current

fCP = fSYS_CLK / 32;

VS=14V; V

CP =V

S+10V 26 38 48 mA

13.3 VCP_LOW

Charge pump low

threshold voltage VS+4.5 V

S+5 V

S+5.5 V

13.4.1 fSYS_CLK

Clock frequency

(internal oscillator)

VCC = 5 V 3 4 4.5 MHz

13.4.2 VCC = 3 V 2.4 3.3 3.5 MHz

13.5 TCP

Charge pump low filter

time 64 µs

Ele ctrical specifications L99H01

16/53 Doc ID 15567 Rev. 4

Table 14. Gate drivers for external PowerMOS

Item Symbol Parameter Test condition Min. Typ. Max. Unit

Drivers for external high-side PowerMOS

14.1 IGHx(on)

Turn on current

(SOURCE stage) Tj = 25 °C (1) 0.3 0.5(2) 0.8 A

14.2.1

RGHx

On-resistance of

SINK stage

VSHx = 0 V; IGHx = 50 mA;

Tj = 25°C 34 5Ω

14.2.2 VSHx = 0 V; IGHx = 50 mA;

Tj = 125°C 4.5 5.3 7 Ω

14.3 VGHxH Gate on voltage Outputs floating VSHx +8V V

SHx +10V V

SHx +12V V

14.4 RGSHx

Passive Gate

clamp resistance 11 13 15 kΩ

Drivers for external low-side PowerMOS

14.5 IGLx(on)

Turn on current

(SOURCE stage) Tj = 25°C (1) 0.3 0.5(2) 0.8 A

14.6.1

RGLx

On-resistance of

SINK stage

VSLx = 0 V; IGHx = 50 mA;

Tj = 25°C 34 5Ω

14.6.2 VSLx = 0 V; IGHx = 50 mA;

Tj = 125°C 4.5 5.3 7 Ω

14.7 VGLxH Gate on voltage VSLx +8V V

SLx +10V V

SLx + 12 V V

14.8 RGSLx

Passive gate

clamp resistance 11 13 15 kΩ

Timing of the drivers

14.9 tGHxHL

Propagation delay

time high to low

VVS = 13.5 V; VSHx = 0;

RG=30 Ω; CG=4.7nF 0.8 1.4 1.9 µs

14.10 tGLxHL

Propagation delay

time low to high

VVS = 13.5 V; VSLx = 0;

RG=30 Ω,; CG=4.7nF 0.6 1.2 1.8 µs

14.11 tGHxr2 Rise time VVS = 13.5 V; VSHx = 0;

RG=0 Ω; CG=4.7nF 45 170 ns

14.12 tGHxf2 Fall time VVS = 13.5 V; VSHx = 0;

RG=0 Ω; CG=4.7nF 60 210 ns

14.13 tGLxr2 Rise time VVS = 13.5 V; VSLx = 0;

RG=0 Ω; CG=4.7nF 45 170 ns

14.14 tGLxf2 Fall time VVS = 13.5 V; VSLx = 0;

RG=0 Ω; CG=4.7nF 60 210 ns

1. Indirect measurement, parameter measured dynamically using 100 nF load capacitor and evaluating the slew rate.

2. Average value.

L99H01 Electrical specifications

Doc ID 15567 Rev. 4 17/53

Table 15. Cross current protection time(1)

Item Symbol Parameter Test condition Min. Typ. Max. Unit

15.1 tCCP0 Cross current protection time — — 250(2) —

15.2 tCCP1 Cross current protection time — 250 500 750

15.3 tCCP2 Cross current protection time — 500 750 1000

15.4 tCCP3 Cross current protection time — 700 1000 1300

15.5 tCCP4 Cross current protection time — 950 1250 1570

15.6 tCCP5 Cross current protection time — 1160 1500 1880

15.7 tCCP6 Cross current protection time — 1360 1750 2180

15.8 tCCP7 Cross current protection time — 1560 2000 2480

1. Test conditions: VCC = 5 V, VS = 13.5 V

2. Not tested

Table 16. Drain source monitoring

Item Symbol Parameter Test condition Min. Typ. Max. Unit

16.1 VSCd1 Drain - source threshold voltage — 0.15 0.5 0.7 V

16.2 VSCd2 Drain - source threshold voltage — 0.45 1 1.25 V

16.3 VSCd3 Drain - source threshold voltage — 0.9 1.5 1.8 V

16.4 VSCd4 Drain - source threshold voltage — 1.4 2 2.35 V

16.5 tSCd Drain - source filtertime — 6 µs

Table 17. Thermal sense interface

Item Symbol Parameter Min. Typ. Max. Unit

17.1 ITS_bias Output bias current 200 250 300 µA

17.2 Vth_TS TS threshold voltage

VTS < VCC - 1 V

n = number of diodes

m = programmed level (0 to 7)

n * (0.31 + m * 0.03) V

Table 18. Current sense amplifier(1)

Item Symbol Parameter Test condition Min. Typ. Max. Unit

DC parameters

18.1 VICM

Input voltage range –

common mode -4 VCP -

8V V

18.2 VIOFF50 Input offset voltage Gain = 50 -11 -4 3 mV

18.3 VIOFF20 Input offset voltage Gain = 20 -23 -8 7 mV

18.4 VIOFF10 Input offset voltage Gain = 10 -30 -10 10 mV

18.5 VIOFF-T50/ΔTInput offset voltage drift vs.

temperature Gain = 50 -10(2) µV/°K

Ele ctrical specifications L99H01

18/53 Doc ID 15567 Rev. 4

18.6 VIOFF-T20/ΔTInput offset voltage drift vs.

temperature Gain = 20 -18(2) µV/°K

18.7 VIOFF-T10/ΔTInput offset voltage drift vs.

temperature Gain = 10 -27(2) µV/°K

18.8 VIOFF-O_50

Input offset voltage with offset

compensation Gain = 50 -3.5 -1 1.5 mV

18.9 VIOFF-O_20

Input offset voltage with offset

compensation Gain = 20 -6 -2 4 mV

18.10 VIOFF-O_10

Input offset voltage with offset

compensation Gain = 10 -10 -3 6 mV

18.11 PSRR_50 Power supply rejection ratio Gain = 50 39 dB

18.12 PSRR_20 Power supply rejection ratio Gain = 20 31 dB

18.13 PSRR_10 Power supply rejection ratio Gain = 10 25 dB

18.14 CMRR Input common mode rejection Tj = 25°C, DC 60 dB

18.15 Gain50 Gain 46.75 50 53.25

18.16 Gain20 Gain 19 20 21

18.17 Gain10 Gain 9.5 10 10.5

18.18.1

VCSOh High-level output voltage

IOUT = 2 mA VCC -

250 mV V

18.18.2 IOUT = 200 µA VCC -

50 mV

VCC -

20 mV V

18.19.1 VCSOl Low-level output voltage IOUT = -2 mA 100 250 mV

18.19.2 IOUT = -200 µA 15 50 mV

Dynamic parameters

18.20 SRcso_10 CSO slew rate Gain = 10; RL = 1 kΩ,;

CL = 22 pF 2.8 4 V/µs

18.21 SRcso_20 CSO slew rate Gain = 20; RL = 1 kΩ,;

CL = 22 pF 34.5V/µs

18.22 SRcso_50 CSO slew rate Gain = 50; RL = 1 kΩ,;

CL = 22 pF 4.4 6 V/µs

18.23 ICSI_10 CSI input current Gain = 10 -114 -102 -90 µA

18.24 ICSI_20 CSI input current Gain = 20 -80 -72 -64 µA

18.25 ICSI_50 CSI input current Gain = 50 -39 -33 -27 µA

1. Test conditions: VS = 13 V, VCC = 5 V

2. Not tested, guaranteed by design.

Table 18. Current sense amplifier(1) (continued)

Item Symbol Parameter Test condition Min. Typ. Max. Unit

L99H01 Electrical specifications

Doc ID 15567 Rev. 4 19/53

Figure 4. Output timing diagram (active free wheeling)

Figure 5. Output timing diagram (passive free wheeling)

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Ele ctrical specifications L99H01

20/53 Doc ID 15567 Rev. 4

2.5 SPI - electrical characteristics

VS=6V to 28V, V

CC = 3 V to 5.3 V, Tj= -40°C to 150°C, unless otherwise specified. The

voltages are referred to GND and currents are assumed positive, when the current flows into

the pin.

Table 19. DI timing(1)

1. DI timing parameters tested in production by a passed / failed test:

Tj = -40°C / +25°C: SPI communication @ 2 MHz.

Tj = +125°C: SPI communication @ 1.25 MHz.

Item Symbol Parameter Test condition Min. Typ. Max. Unit

19.1 tCLK Clock period — 1000 — ns

19.2 tCLKH Clock high time — 400 — ns

19.3 tCLKL Clock low time — 400 — ns

19.4 tset CSN

CSN setup time, CSN low

before rising edge of CLK — 400 — ns

19.5 tset CLK

CLK setup time, CLK high

before rising edge of CSN — 400 — ns

19.6 tset DI DI setup time — 200 — ns

19.7 thold DI DI hold time — 200 — ns

19.8 tr in

Rise time of input signal DI,

CLK, CSN ——100ns

19.9 tf in

Fall time of input signal

DI, CLK, CSN ——100ns

Table 20. DO

Item Symbol Parameter Test condition Min. Typ. Max. Unit

20.1 VDOL

Low-level output

voltage ID=-4mA 0.2 0.4 V

20.2 VDOH

High-level output

voltage ID=4mA V

CC -0.4 V

CC -0.2 V

20.3 IDOLK

Tristate leakage

current

VCSN =V

CC;

0V<V

DO <V

-10 10 µA

20.4 CDO(1)

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Tristate input

capacitance

VCSN =V

CC;

0V<V

CC <5.3V 10 15 pF

L99H01 Electrical specifications

Doc ID 15567 Rev. 4 21/53

Table 21. DO timing

Item Symbol Parameter Test condition Min. Typ. Max. Unit

21.1 tr DO DO rise time CL= 100 pF;

Iload =-1mA — 80 140 ns

21.2 tf DO DO fall time CL= 100 pF; Iload = 1 mA — 50 100 ns

21.3 ten DO tri L

DO enable time from

tristate to low-level

CL= 100 pF; Iload =1mA;

pull-up load to VCC

— 100 250 ns

21.4 tdis DO L tri

DO disable time from

low-level to tristate

CL= 100 pF; Iload =4mA;

pull-up load to VCC

— 380 450 ns

21.5 ten DO tri H

DO enable time from

tristate to high-level

CL= 100 pF;

Iload = -1 mA; pull-down load

to GND

— 100 250 ns

21.6 tdis DO H tri

DO disable time from

high-level to tristate

CL= 100 pF;

Iload = -4 mA; pull-down load

to GND

— 380 450 ns

21.7 td DO DO delay time VDO <0.3V

CC;

VDO >0.7V

CC; CL= 100 pF — 50 250 ns

Table 22. EN, CSN timing

Item Symbol Parameter Test condition Min. Typ. Max. Unit

22.1 tr DO DO rise time CL= 100 pF;

Iload =-1mA 80 140 ns

22.2 tf DO DO fall time CL= 100 pF;

Iload =1mA 50 100 ns

22.3

CSN_HI,min

CSN HI time, active

mode:the min high time

between two independent

SPI commands.

Transfer of SPI-

command to input

2µs

Ele ctrical specifications L99H01

22/53 Doc ID 15567 Rev. 4

Figure 6. SPI - transfer timing diagram

Figure 7. SPI - input timing

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L99H01 Electrical specifications

Doc ID 15567 Rev. 4 23/53

Figure 8. SPI - DO valid data delay time and valid time

Figure 9. SPI - DO enable and disable time

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Ele ctrical specifications L99H01

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Figure 10. SPI - timing of status bit 0 (fault condition)

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L99H01 Dev ice descr ipt ion

Doc ID 15567 Rev. 4 25/53

3 Device description

3.1 Dual power supply: VS and VCC

The power supply voltage VS supplies the charge-pump. An internal charge-pump is used to

drive the high-side switches and the low-side switches. The logic supply voltage VCC

(3.3 V / 5 V) is used for the logic part and the SPI of the device. Due to the independent logic

supply voltage the control and status information is not lost, even if the supply voltage VS is

switched-off. In case of power-on (VCC increases from undervoltage to

VPOR OFF = 2.5 V, typical) the circuit is initialized by an internally generated power-on reset

(POR). If the voltage VCC decreases under the minimum threshold (VPOR ON =2.2V,

typical), the outputs are switched-off and the status registers are cleared.

3.2 Standby mode (EN)

The L99H01 is activated with enable input high signal. For enable input floating (not

connected) or VEN = 0 V the device is in standby mode. All latched data are cleared and the

inputs and outputs are switched-off. In the standby mode the current at VS is less than 5 µA

(1 µA) for CSN = high (DO in tristate). If VCC > VPOR OFF and EN = high the device enters

the active mode. In the active mode the charge-pump and the diagnostic functions are

active.

3.3 H-bridge control (DIR, PWM, bit FW)

The DIR and PWM inputs control the drivers of the external H-bridge transistors. The motor

direction can be chosen with the DIR input, the duty cycle and frequency with the PWM

input. With the SPI registers FW and FW-PAS 4 different free wheeling modes (2 active and

2 passive) can be selected using the high-side transistors or the low-side transistors.

Unconnected inputs are defined by internal pull-down current.

Device description L99H01

26/53 Doc ID 15567 Rev. 4

Table 23. Truth table

N° Control pins Control bits Failure bits Output pins SPI DO Comment

EN DIR PWM TS/ACT_OFF FW FW_PAS CP_LOW OV UV SC TSD WDTO GH1 GL1 GH2 GL2 GL_ER

1 0 X X X X X X X X X X X RL RL RL RL T Standby mode

2 1 X X X X X X X X X X X RL RL RL RL 1 Power-on reset

31XX 0 X 0 0 0000 0 LLLL 0EXT_TS = 1 (external

thermal shutdown)

4 1 X X 0 X 0 0 0 0 0 0 0 L L L L 0 EXT_TS = 0 (active Off)

5 1 X X 1 X X 1 0 0 0 0 0 RLRLRLRL 1 Charge pump voltage too

low

6 1 X X 1 X X 0 0 0 0 1 0 RL RL RL RL 1 Internal thermal shutdown

7 1 X X 1 X X 0 1 0 0 0 0 L L L L 1 Overvoltage

8 1 X X 1 X X 0 0 1 0 0 0 L L L L 1 Undervoltage

91X X 1 X X 0 001 0 0 L

(1) L(1) L(1) L(1) 0 Short-circuit(1)

10 1 X X 1 X X 0 0 0 0 0 1 L L L L 1 Watchdog time out

11 1 0 1 1 X X 0 0 0 0 0 0 L H H L 0 -

12 1 X 0 1 0 0 0 0 0 0 0 0 L H L H 0 Act. free wheeling mode LS

13 1 0 0 1 0 1 0 0 0 0 0 0 L H L L 0 Pass. free wheeling mode

14110 1 0 1 0 0000 0 LLLH 0Pass. free wheeling mode

15 1 1 1 1 X X 0 0 0 0 0 0 H L L H 0 -

16 1 X 0 1 1 0 0 0 0 0 0 0 H L H L 0 Act. free wheeling mode

17 1 0 0 1 1 1 0 0 0 0 0 0 L L H L 0 Pass. free wheeling mode

18 1 1 0 1 1 1 0 0 0 0 0 0 H L L L 0 Pass. free wheeling mode

1. Only the halfbridge (low-side and high-side) where one MOSFET is in short-circuit condition is switched-off. Both MOSFET’S of the other halfbridge remain active and driven by DIR and PWM.

L99H01 Dev ice descr ipt ion

Doc ID 15567 Rev. 4 27/53

Symbols:

●x: Don't care

●1: Logic high or active

●0: Logic low or not active

●H: Output in source condition

●L: Output in sink condition

●RL: Resistive low (see Section 3.4)

●T: Tristate

●FW: Free wheeling

●FW_PAS: Free wheeling passive

●CP_LOW: Charge pump low

●OV: Overvoltage

●UV: Undervoltage

●SC: Short-circuit

●TSD: Thermal shutdown

●GL_ER: Global error flag

3.4 Resistive low

The resistive output mode protects the L99H01 and the H-bridge in the standby mode and in

some failure modes (internal and external thermal shutdown (TSD), charge pump low

(CP_LOW), stucked reset (STK_RESET_Q) and power-on reset (PORES). When a gate

driver changes into the resistive output mode due to a failure a sequence is started. In this

sequence the concerning driver is switched in sink condition for 32 µs to 64 µs to ensure a

fast switch-off of the H-bridge transistor. Afterwards the driver is switched in the resistive

output mode (resistive path to source).

3.5 Diagnostic functions

The diagnostic functions (over load, power supply over- and undervoltage, charge pump

low, watchdog, temperature warning and internal/external thermal shutdown) are internally

filtered and the condition has to be valid for at least 64 µs (6 µs for a short-circuit) before the

corresponding status bit in the status registers is set. The filters are used to improve the

noise immunity of the device. The internal temperature warning function is intended for

information purpose and does not change the state of the output drivers. On the contrary,

the over load condition switches the corresponding halfbridge in sink condition. The internal

thermal shutdown condition and charge pump low disable all drivers (resistive low). The

external thermal shutdown, watchdog, over- and undervoltage condition switch all driver in

sink condition. The microcontroller needs to clear the status bits to reactivate the drivers.

3.6 Overvoltage and undervoltage detection

If the power supply voltage VS rises above the overvoltage threshold VVS_OVH

(typical 20 V / 30 V), all gate driver stages are switched in sink condition to protect the

H-bridge and the load, setting the OV bit. Two values for the overvoltage threshold can be

selected with the SPI. When the voltage VS drops below the undervoltage threshold

Device description L99H01

28/53 Doc ID 15567 Rev. 4

VVS_UV

, all gate driver stages are switched in the sink condition to avoid driving the power

devices without sufficient gate driving voltage (increased power dissipation), setting the UV

bit. In both cases, overvoltage and undervoltage detection, the charge pump is disabled. If

the supply voltage VS recovers from UV/OV to normal operating voltage range and if the

OV_UV_RD is set to 0, then the charge pump is automatically enabled. In any case,

regardless of the OV_UV_RD bit value, the microcontroller needs to clear the status register

to reactivate the gate drivers.

3.7 Charge pump

The charge pump uses 2 external capacitors. The output of the charge pump has a current

limitation. In standby mode and after overvoltage, undervoltage or a thermal shutdown has

been triggered the charge pump is disabled. If the charge pump output voltage remains too

low for longer than TCP , all gate drivers are switched-off (resistive output, see Section 3.4).

The CP_LOW bit has to be cleared through a software reset to reactivate the gate drivers.

3.8 Temp erature warning and th erm al shutdo wn

If junction temperature rises above TjTWON the temperature warning flag TW is set and is

detectable via the SPI. If junction temperature increases above the second threshold

TjSDON, the thermal shutdown bit (TSD) is set. The gate drivers and the charge pump are

switched-off to protect the device. The gates of the H-bridge are discharged by the resistive

low mode (see Section 3.4). In order to reactivate the output stages the junction

temperature must decrease below TjSDOFF

and the thermal shutdown bit has to be cleared

by the microcontroller.

3.9 Sho rt-circuit detection / drain source monitoring

The drain - source voltage of each activated external MOSFET of the H-bridge is monitored

by comparators to detect shorts to ground or battery. If the voltage drop over the external

MOSFET exceeds the threshold voltage VSCd for longer than the short current detection

time tSCd the corresponding gate driver switches the external MOSFET off and the

corresponding drain source monitoring flag (DS_MON [3:0]) is set. Until this failure flag is

reseted the corresponding half bridge is in sink condition. The DS_MON bits have to be

cleared through a software reset to reactivate the gate drivers. The drain source monitoring

has a filter time of 6 µs. This monitoring is only active when the corresponding gate driver is

in source condition. The threshold voltage VSCd can be programmed in 4 steps between

0.5 V and 2 V with the SPI.

3.10 Programmable cro ss current protectio n

The external Power MOSFET’s transistors in H-bridge (two halfbridges) configuration are

switched-on with an additional delay time tCCP to prevent cross current in the halfbridge. The

cross current protection time tCCP can be programmed with the SPI.

L99H01 Dev ice descr ipt ion

Doc ID 15567 Rev. 4 29/53

3.11 Current sense amplifier (CSA)

The current sense amplifier (CSA) is specially designed for current shunt automotive

applications. It is a bidirectional, single-supply difference amplifier for amplifying small

differential voltages in a wide common mode voltage range (-4 V to (VCP - 8) V). It supports

the current measurement at two shunts. The result of respective shunt can be multiplexed to

the microcontroller compatible output voltage by a SPI command.

A gain of 50, 20 or 10 is SPI programmable. The inputs (CSI1+ / CSI1- and CSI2+ / CSI2-)

are build as a transconductance stage. Therefore a series resistor (for filtering etc.) should

not exceed 50 Ω to keep the additional gain error below 1%.

The output works at half scale: VCSO0 = (0,5 * VCC) V for VIDIFF = 0 V. An internal offset

measurement is in normal mode available with the "OFF_CAL" SPI-bit. If this bit is set to

logic "1" the input pins are disconnected from the amplifier and a virtual zero input

differential voltage is selected.

3.12 Thermal sensor interface / H-bridge switch-off input

The TS/ACT_OFF pin is configurable by SPI with the EXT_TS bit. This pin could be used as

temperature sensor interface for the H-bridge or external off for all gate drivers. The output

bias current ITS_bias is on for EN = high.

3.12.1 EXT_TS-bit = low (active off)

The TS/ACT_OFF input is used as a logic driver control input, without filter delay and

without latching the information.

Pulling the TS/ACT_OFF pin below the programmed threshold all gate drivers are

switched-off and the OT_EXT bit is set.

Increasing the voltage at TS/ACT_OFF pin above the programmed threshold the device

remains to the status set by DIR and PWM-pins and the OT_EXT bit is reseted.

The threshold is programmable by SPI with the registers EXTTH_5:0.

3.12.2 EXT_TS-bit = high (thermal sensor interface)

With the thermal sensor interface external diodes can be used to control the temperature of

the external H-bridge. When the diode forward voltage decreases below the reference

voltage for longer than the internal filter time (64 µs) the OT_EXT bit is set and the driver

switches in resistive low (see Section 3.4: Resistive low).

In this mode the OT_EXT-status-bit has to be cleared to reactivate the gate drivers.

The threshold is programmable by SPI with the registers EXTTH_5:0.

3.13 Watchdog

The tasks of the watchdog is to monitor the microcontroller during normal operation within a

nominal trigger cycle of 60 ms. The microcontroller has to restart the watchdog timer by

sending the watchdog restart bit via SPI repeatedly within the watchdog time TWDTO. If no

correct watchdog service is sent from the microcontroller, all gate drivers switch in sink

Device description L99H01

30/53 Doc ID 15567 Rev. 4

condition and the watchdog time out bit (WDTO) is set. Once the watchdog times out, the

gate drivers can only be reactivated by sending a software reset.

L99H01 Functional description of the SPI

Doc ID 15567 Rev. 4 31/53

4 Functional description of the SPI

4.1 Signal description

4.1.1 Serial clock (CLK)

This input signal provides the timing of the serial interface. Data present at serial data input

(DI) is latched on the rising edge of serial clock (CLK). Data on Serial Data Out (DO) is

shifted out at the falling edge of serial clock (CLK).

The serial clock CLK must be active only during a frame (CSN low phase). Any other

switching of CLK close to any CSN edge could generate setup/hold violations in the SPI

logic of the device.

4.1.2 Serial data input (DI)

This input is used to transfer data serially into the device. Values are latched on the rising

edge of serial clock (CLK).

4.1.3 Serial data output (DO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of serial clock (CLK).

DO also reflects the status of the <Global Error Flag> (<Global Status Byte>[7]) while CSN

is low and no clock signal is present.

4.1.4 Chip select not (CSN)

When this input signal is high, the communication interface of the device is deselected and

serial data output (DO) is high impedance. Driving this input low enables the

communication. The communication must start and stop on a low-level of serial clock (CLK).

The SPI can be driven by a microcontroller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0.

For timing details and figures refer to Section 2.5.

4.2 General data description

The SPI communication is based on a SPI interface structure using CSN (chip select not),

DI (serial data in), DO (serial data out/error) and CLK (serial clock) signal lines.

Each DI communication frame consists of a <Command Byte> which is followed by 1 <Data

Byte>.

The data returned on DO within the same frame always starts with the <Global Status

Byte>, which provides general status information about the device. This byte is followed by 1

<Data Byte> (‘In-frame-response’).

Functional description of the SPI L99H01

32/53 Doc ID 15567 Rev. 4

4.2.1 Command byte

Each communication frame starts with a command byte. It consists of an operating code

which specifies the type of operation (<Read>, <Write>, <Fault Reset>,

<Read Device Information>) and a 6-bit address.

Comments:

●OCx: Operating code

●Ax: Address

4.2.2 OpCode definition

The <Write Mode> and <Read Mode> operations allow access to the RAM of the device.

The <Clear Status> operation is used to read a status register and subsequently clear its

content.

Table 24. DI

Command byte DI - data byte

1514131211109876543210

OC1 OC0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Table 25. DO

Global Status byte DO - data by te

15 14 13 12 11109 8 76543210

GL_ER FE STK_RESET_Q TSD TW UV OV WDTO D7 D6 D5 D4 D3 D2 D1 D0

Table 26. Command byte

Command byte

MSB LSB

Op code Address

OC1 OC0 A5 A4 A3 A2 A1 A0

Table 27. Operating code definition

OC1 OC0 Meaning

0 0 <Write Mode>

0 1 <Read Mode>

1 0 <Clear Status>

1 1 <Read Device Information>

L99H01 Functional description of the SPI

Doc ID 15567 Rev. 4 33/53

<Read Device Information> allows access to the ROM area which contains device related

information such as <ID-Header>, <Product Code>, <Silicon Version and Category> and

<SPI-frame-ID>.

More detailed descriptions of the device information are available in Section 4.7 .

Functional description of the SPI L99H01

34/53 Doc ID 15567 Rev. 4

4.3 Device memory map

4.3.1 Control and status (RAM) addres s map

4.3.2 Device (ROM) address map (a ccess with OC0 and OC1 set to ‘1’)

Table 28. Control and status (RAM) address map

Name Access Address Content

A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Stat Reg0Read/ Clear000000DS_MON_3DS_MON_2DS_MON_1DS_MON_0 0 0 OT_EXTCP_LOW

Appl Reg1Read/ Write000001 RWD FW_PAS OFF_CALCLK_SPCTR OVT OV_UV_RDDIAG_1 DIAG_0

Appl Reg2Read/ Write000010 RWD COPT_2 COPT_1 COPT_0 FW MCSA GCSA_1GCSA_0

Appl Reg3Read/ Write000011 RWD EXT_TS EXTTH_5 EXTTH_4EXTTH_3EXTTH_2EXTTH_1EXTTH_0

Table 29. Device (ROM) address map (access with OC0 and OC1 set to ‘1’)

Name Access Address Content

A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

ID-Header Read

device 000000 FAM_1 FAM_0 NR_PI_5NR_PI_4NR_PI_3NR_PI_2NR_PI_1NR_PI_0

Product Code 1 Read

device 000001PR_ID_7PR_ID_6PR_ID_5PR_ID_4PR_ID_3PR_ID_2PR_ID_1PR_ID_0

Product Code 2 Read

device 000010PR_ID_15PR_ID_14PR_ID_13PR_ID_12PR_ID_11PR_ID_10PR_ID_9PR_ID_8

SPI-Frame-ID Read

device 000011 BR AR5 AR4 AR3 32 bits 24 bits 16 bits 8 bits

Reserved Read

device 111111

Reserved, accessing this address is recognized as a failure, the device enters a fail-safe state

(see Table 30: STK_RESET_Q).

L99H01 Functional description of the SPI

Doc ID 15567 Rev. 4 35/53

4.4 Global status byte

This byte is shifted out first at DO at every SPI access.

The GL_ER bit is present at DO with the falling edge of CSN.

This byte could be reseted with the command <clear status>.

Comments:

●GL_ER: Global error flag. This signal is a logical OR among all the errors of all the

channels of the device.

●FE: Frame error. If the number of clock pulses within the previous frame is not 16 the

frame is ignored and this bit is set.

●STK_RESET_Q: If a stuck at ‘1’ on SPI_DI during any SPI frame occurs, or if a

power-on reset occurs. STK_RESET_Q is reset (‘1’) with any SPI command.

When STK_RESET_Q is active (‘0’), the gate drivers are switched-off (see Section 3.4:

Resistive low).

After a startup of the circuit the STK_RESET_Q is active because of the POR pulse

and the gate drivers are switched-off. The Gate drivers can only be activated after the

STK_RESET_Q has been reset with a SPI command.

●TSD: Thermal shutdown due to an internal sensor. All the gate drivers and the charge

pump must be switched-off (see Section 3.4: Resistive low). The gate drivers can only

be activated after the TSD has been reset with a SPI command.

●TW: Thermal warning

●UV: Logical OR among the filtered undervoltage signals.

●OV: Logical OR among the filtered overvoltage signals.

●WDTO: Watchdog time out.

Failures of <Global Status Register>[8:14] are always linked to the <Global Error Flag>.

The <Global Error Flag> is generated by an OR combination of all failure events of the

device (<Global Status Register>[8:14]).

The flag is reflected via the DO pin while CSN is held low and no clock signal is available.

The flag remains as long as CSN is low. This operation does not cause the <communication

error> bit in the <Global Status Byte> to be set.

Table 30. STK_RESET_Q

Bit 15 14 13 12 11 10 9 8

Name GL_ER FE STK_RESET_Q TSD TW UV OV WDTO

<default> 0 0 1 0 0 0 0 0

Functional description of the SPI L99H01

36/53 Doc ID 15567 Rev. 4

4.4.1 SPI clock monitor and watchdog

Figure 11. Global error flag diagram

1. Writing a “1” to RWD - bit in ApplRegx restarts the internal watchdog counter.

The clock monitor counts the number of clock pulses during a communication frame (while

CSN is low). If the number of SCK pulses does not correspond with the frame width

indicated in the <SPI-frame-ID> (ROM address 03hex) the frame is ignored and the bit

<frame error> in the <Global Status Byte> is set.

Note: Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is

recommended.

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L99H01 Functional description of the SPI

Doc ID 15567 Rev. 4 37/53

4.5 Detaile d byte description of status register (StatReg0)

The read operation starts always with the command byte followed by 1 data byte. The

content of the send data byte has to be ‘0’. The content of the addressed register is shifted

out at DO within the same frame (‘in-frame response’).

The device uses 1 status register to monitor the state of the device. Tabl e 31 shows the

address and the content of the register.

Comments:

●DS_MON[3:0]: If max drain source voltage exceeds the defined thresholds, the

DS_MON are set and the corresponding drivers go to sink mode. The DS_MON bits

have to be cleared through a software reset to reactivate the drivers.

●OT_EXT: Depending on EXT_TS bit following two meanings exist:

– EXT_TS = low (active off):

TS/ACT_OFF pin is used as input to switch the H-bridge in tristate and back.

Details are discribed in Section 3.12.1.

– EXT_TS = high (thermal sensor interface):

TS/ACT_OFF pin is used as thermal sensor interface for external temperature

diodes. Details are discribed in Section 3.12.2.

●CP_LOW: If a charge pump output voltage low occurs, all gate drivers must be

switched-off (resistive low). The CP_LOW bit has to be cleared through a software

reset to reactivate the gate driver.

Table 31. Address 0<00(hex)>:StatReg 0 - read only(1)

1. The errors of the status register are not linked to the <Global Error Flag>.

Bit 7 6 5 4 3 2 1 0

Name DS_MON_3 DS_MON_2 DS_MON_1 DS_MON_0 X X OT_EXT CP_LOW

<default> 0 0 0 0 0 0 0 0

Table 32. DS_MON - drivers relations

DS_MON_3 High-side 2

DS_MON_2 High-side 1

DS_MON_1 Low-side 2

DS_MON_0 Low-side 1

Functional description of the SPI L99H01

38/53 Doc ID 15567 Rev. 4

4.6 Detailed byte descripti on of application register s (ApplRegX)

The write/read operation starts always with a command byte followed by 1 data byte.

4.6.1 Description of the data byte

The device uses 3 application registers to configure the device. Note that the last row shows

the logic levels during a reset phase.

Comments:

●RWD: Restarts the watchdog counter

●FW_PAS: Enables passive free wheeling according to Ta ble 23

●OFF_CAL: Offset calibration mode for CSA

●OVT: Overvoltage threshold

●CLK_SPCTR: Switch the clock to the charge pump

–0: 125 Khz (50% duty cycle)

–1: pulses train (max = 8 µs, min = 2 µs) to optimize power spectrum

●OV_UV_RD: Over/undervoltage recovery disabled.

– 0: If VS recovers from OV/UV condition to normal operating voltage range, the

charge pump is automatically enabled;

– 1: If VS recovers from OV/UV condition to normal operating voltage range, the

charge pump remains disabled;

In both cases the microcontroller has to clear the status register to enable the gate

drivers

●DIAG[1:0]: Drain source monitoring threshold voltage

Table 33. Address 1 <01(hex)>:ApplReg1-read/write

Bit765 43210

Name RWD FW_PAS OFF_CAL CLK_SPCTR OVT OV_UV_ RD DIAG1 DIAG0

<default> 0 0 0 0 0 0 0 0

Table 34. Overvoltage threshold of the Vs monitoring

OVT Threshold

020 V

129 V

Table 35. DIAG monitoring of source voltages

DIAG[1] DIAG[0] Monitoring threshold volta ge

00 V

SCD1= 0.5 V

01 V

SCD2 = 1 V

10 V

SCD3 = 1.5 V

11 V

SCD4 = 2 V

L99H01 Functional description of the SPI

Doc ID 15567 Rev. 4 39/53

Comments:

●RWD: Restarts the watchdog counter

●COPT[2:0]: Filter time to protect the two external halfbridges against cross current.

●FW: Selects high-side or low-side free wheeling

●MCSA: Multiplexer for current sense amplifier.

●GCSA[1:0]: Gain of the current sense amplifier.

Table 36. Address 2 <02(hex)> : ApplReg2 – read/write

Bit76543210

Name RWD COPT_2 COPT_1 COPT_0 FW MCSA GCSA_1 GCSA_0

<default> 0 0 0 0 0 0 0 0

Table 37. Cross current protection time (tCCP)

COPT_2 COPT_1 COPT_0 Protection time

0 0 0 250 ns

0 0 1 500 ns

0 1 0 750 ns

0 1 1 1000 ns

1 0 0 1250 ns

1 0 1 1500 ns

1 1 0 1750 ns

1 1 1 2000 ns

Table 38. Multiplexer for current sense amplifier

MCSA Selected amplifier

0 CSA2 (CSI2+ / CSI2-)

1 CSA1 (CSI1+ / CSI1-)

Table 39. Gain of current sense amplifier

GCSA_1 GCSA_0 Gain

00 10

01 20

10 50

1 1 Not applicable

Functional description of the SPI L99H01

40/53 Doc ID 15567 Rev. 4

Comments:

●RWD: Restarts the watchdog counter

●EXT_TS: The bit select the mode of the input pin TS/ACT_OFF:

– EXT_TS = low (active off):

TS/ACT_OFF pin is used as input to switch the H-bridge in tristate and back.

Details are discribed in Section 3.12.1.

– EXT_TS = high (thermal sensor interface):

TS/ACT_OFF pin is used as thermal sensor interface for external temperature

diodes. Details are discribed in Section 3.12.2.

●EXTTH[5:0]: Determines the threshold of the external thermal shutdown/warning

Table 40. Address 3 <03(hex)> : ApplReg3 – read/write

Bit76543210

Name RWD EXT_TS EXTTH_5 EXTTH_4 EXTTH_3 EXTTH_2 EXTTH_1 EXTTH_0

<default>00000000

Table 41. External threshold voltage, factor n

EXTTH_5 EXTTH_4 EXTTH_3 n

000 7

001 6

010 5

011 4

100 3

101 2

110 1

111 0

Table 42. External threshold voltage, factor m

EXTTH_2 EXTTH_1 EXTTH_0 m

000 7

001 6

010 5

011 4

100 3

101 2

110 1

111 0

L99H01 Functional description of the SPI

Doc ID 15567 Rev. 4 41/53

Equation 1

Vth = n * (0.31 + m * 0.03) V

The purpose of factor n is to determine the number of external temperature sense diodes (in

series). With factor m the level of the threshold voltage can be fine tuned.

4.7 Read device information (ROM)

The device information is stored at the ROM addresses defined below and is read using the

respective operating code.

The <ID-Header> indicates the product family and specifies how many bytes of device

information are available.

●FAM[1:0]: Family identifier, FAM[1:0] = [0:1] stands for ASSPs.

●NR_PI[5:0]: Number of product information bytes.

The <Product Code 1 and 2> represents a unique identifier of the device and version.

Table 43. Read device information (ROM)

Op code Address Device information

OC1 OC0 Ax

1 1 00H <ID-Header>

1 1 01H <Product Code 1>

1 1 02H <Product Code 2>

1 1 03H <SPI-frame-ID>

1 1 3FH

Reserved, accessing this address is recognized as a failure, the

device enters a fail-safe state (see Table 30: STK_RESET_Q).

Table 44. Address 0 <00(hex)> : ID-header - read only(1)

1. Addressable only through a read device information command.

Bit76543210

Name FAM_1 FAM_0 NR_PI_5 NR_PI_4 NR_PI_3 NR_PI_2 NR_PI_1 NR_PI_0

<default>01000010

Table 45. Address 1 <01(hex)>: product ID (LSB) - read only(1)

1. Addressable only through a read device information command.

Bit76543210

Name PR_ID_7 PR_ID_6 PR_ID_5 PR_ID_4 PR_ID_3 PR_ID_2 PR_ID_1 PR_ID_0

<default> 0 0 0 0 0 0 0 1

Functional description of the SPI L99H01

42/53 Doc ID 15567 Rev. 4

The <SPI-frame-ID> (ROM address 03H) provides information about the register width (1, 2,

3 bytes) and the availability of ‘burst mode read’ option.

Comments:

●BR: Burst mode read. Not supported

●AR5: Address width reduction. Not supported

●AR4: Address width reduction. Not supported

●AR3: Address width reduction. Not supported

●32 bits: 32 bits frame width. Not supported

●24 bits: 24 bits frame width. Not supported

●16 bits: 16 bits frame width, 8 bits command and 8 bits data

●8 bits: 8 bits frame width. Not supported

Table 46. Address 2 <02(hex)>: product ID (MSB) - read only(1)

1. Addressable only through a read device Information command.

Bit76543210

Name

PR_ID_15 PR_ID_14 PR_ID_13 PR_ID_12 PR_ID_11 PR_ID_10 PR_ID_9 PR_ID_8

00101XXX

Table 47. Address 3 <03(hex)>: SPI frame ID - read only(1)

1. Addressable only through a Read Device Information command.

Bit76543210

Name BR AR5 AR4 AR3 32 bits 24 bits 16 bits 8 bits

<default> 0 0 0 0 0 0 1 0

L99H01 Packages thermal data

Doc ID 15567 Rev. 4 43/53

5 Packages thermal data

Figure 12. PowerSSO-36 Rthj-amb vs. PCB copper area in open free air condition(1)

1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias,

FR4 area = 129 mm x 60 mm, PCB thickness =1.6 mm, Cu thickness =70 µm (front and back side),

Copper areas: from minimum pad layout to 8 cm2).

0246810

RTHj_amb(°C/W)

PCB Cu heat sink ar ea (cm ^ 2)

Package and packing information L99H01

44/53 Doc ID 15567 Rev. 4

6 Package and packing information

6.1 ECOPACK®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

L99H01 Package and packing information

Doc ID 15567 Rev. 4 45/53

6.2 PowerSSO-36 package information

Figure 13. PowerSSO-36 package dimensions

("1($'5

Package and packing information L99H01

46/53 Doc ID 15567 Rev. 4

Table 48. PowerSSO-36 mechanical data

Symbol Millimeters

Min. Typ. Max.

A2.15 - 2.45

A2 2.15 - 2.35

a1 0 - 0.1

b0.18-0.36

c0.23-0.32

D(1)

1. “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm

per side (0.006”).

10.10 - 10.50

E(1) 7.4 - 7.6

e-0.5-

e3 - 8.5 -

F-2.3-

G- -0.1

H10.1 - 10.5

h--0.4

k0°-8°

L0.55 -0.85

M-4.3-

N - - 10°

O-1.2-

Q-0.8-

S-2.9-

T-3.65-

U-1-

X 4.1 - 4.7

Y 6.5 - 7.1

L99H01 Package and packing information

Doc ID 15567 Rev. 4 47/53

6.3 Packages thermal data

Figure 14. LQFP32 Rthj-amb vs. PCB copper area in open box free air condition

1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias,

FR4 area = 78 mm x 86 mm, PCB thickness =1.6 mm, Cu thickness =70 µm (front and back side), copper

areas: from minimum pad layout to 8 cm2).

0 0.2 0.4 0.6 0.8 1

RTHj_amb(°C/W)

PCB Cu heat sink ar ea (cm ^ 2)

Package and packing information L99H01

48/53 Doc ID 15567 Rev. 4

6.4 LQFP32 package information

Figure 15. LQFP32 package dimensions

("1($'5

L99H01 Package and packing information

Doc ID 15567 Rev. 4 49/53

Table 49. LQFP32 mechanical data

Dim. Millimeter

Min. Typ. Max.

A 1.60

A1 0.05 0.15

A2(1)

1. LQFP stands for low profile quad flat pachage.

Low profile: Body thickness (A2 = 1.40 mm)

1.35 1.40 1.45

b 0.30 0.37 0.45

c 0.09 0.20

D 8.80 9.00 9.20

D1 6.80 7.00 7.20

D3 5.60

E 8.80 9.00 9.20

E1 6.80 7.00 7.20

E3 5.60

e0.80

L 0.45 0.60 0.75

L1 1.00

K 0°3.5°7°

ccc 0.10

Package and packing information L99H01

50/53 Doc ID 15567 Rev. 4

6.5 PowerSSO-36 packing information

Figure 16. PowerSSO-36 tube shipment (no suffix)

Figure 17. PowerSSO-36 tape and reel shipment (suffix “TR”)

All dimensions are in mm.

Base qty 49

Bulk qty 1225

Tube length (±0.5) 532

A3.5

B13.8

C (±0.1) 0.6

Reel dimensions

Base qty 1000

Bulk qty 1000

A (max) 330

B (min) 1.5

C (±0.2) 13

F20.2

G (+2 / -0) 24.4

N (min) 100

T (max ) 30.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

All dimensions are in mm.

Tape width W 24

Tape hole spacing P0 (±0.1) 4

Component spacing P 12

Hole diameter D (±0.05) 1.55

Hole diameter D1 (min) 1.5

Hole position F (±0. 1) 11.5

Compartmen t de pt h K (max) 2.85

Hole spacing P1 (±0.1) 2

Top

cover

tape

End

Start

No componentsNo components Components

500mm min 500mm min

Empty components pockets

sealed with cover tape.

User direction of feed

L99H01 Package and packing information

Doc ID 15567 Rev. 4 51/53

6.6 LQFP32 pack i ng info r ma t io n

Figure 18. LQFP32 tape and reel shipment (suffix “TR”)

Figure 19. LQFP32 tray shipmen t (no suffix )

Revision history L99H01

52/53 Doc ID 15567 Rev. 4

7 Revision history

Table 50. Document revision history

Date Revision Changes

17-Apr-2009 1 Initial release.

19-Aug-2009 2

Updated corporate template from V3 to V3.1

Updated Figure 4.

Removed items 17.16, 17.18 and 17.20 of the Table 18: Current sense

amplifier.

Added Table 15: Cross current protection time

Table 18: Current sense amplifier.

–V

IOFF50, VIOFF20, VIOFF10: added min/typ/max value,

deleted “Tj = 25 °C“ for test condition

–V

IOFF-T50/ΔT: changed symbol (it was VIOFF-T50), updated whole

row.

–V

IOFF-T20/ΔT: changed symbol (it was VIOFF-T20), updated whole

row.

–V

IOFF-T10/ΔT: changed symbol (it was VIOFF-T10), updated whole

row.

–V

IOFF-50, VIOFF-20, VIOFF-10: added min/typ/max value

–Gain50, Gain20, Gain10: added min/typ/max value

– Setting time: deleted row

Added Figure 5: Output timing diagram (passive free wheeling)

Updated Table 23: Truth table.

Updated Section 3.9, Section 3.11, Section 3.12.1 and Section 3.12.2.

Table 30: STK_RESET_Q: changed title (it was “Global status byte”)

Updated Section 4.4.1 and Section 4.6.1.

Updated Ta b l e 4 3 .

20-Apr-2010 3 Updated the CP value in Table 4: Absolute maximum ratings

30-Apr-2012 4

Ta bl e 9 : S u p p ly :

–VVS_OV1: : changed symbol (it was VVS_OVH1)

–VVS_OV1H: : changed symbol (it was VVS_OVH1)

–VVS_OV2: : changed symbol (it was VVS_OVH2)

–VVS_OV2H: : changed symbol (it was VVS_OVH2)

–VVS_UV: : changed symbol (it was VVS_UVH)

Updated Section 3.6: Overvoltage and undervoltage detection and

Section 3.7: Charge pump

Section 4.6.1: Description of the data byte:

– updated OV_UV_RD bit description

Table 48: PowerSSO-36 mechanical data:

– L: updated values

L99H01

Doc ID 15567 Rev. 4 53/53

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