1. General description
The PCA9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an
enable (EN) input, and is operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5 V
(Vbias(ref)(2)).
The PCA9306 allows bidir ectional vo ltage translations between 1.0 V and 5 V without the
use of a direction pin. The low ON- state resist ance (R on) of the switch allows connections
to be made with minimal prop agation delay. When EN is HIGH, the translator switch is on,
and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,
allowing bidirectional data flow between ports. When EN is LOW, the translator switch is
off, and a high-impedance state exists between ports.
The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level
translation and physically isolates the capacitance to either side of the bus when both
sides are connected. The PCA9306 only isolates both sides when the device is disabled
and provides voltage level translation when active.
The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency
and the other at 100 kHz operating frequency. If the two buses are operating at different
frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other
bus is required. If the master is running at 400 kHz, the maximum system operating
frequency may be less than 400 kHz because of the delays added by the translator.
As with the standard I2C- bu s syst em , pu ll-u p resistors are required to provide the logic
HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector
configuration of the I2C-bus. The size of these pull-up resistors depends on the system,
but each side of the translator must have a pull-up resi stor . The d evice is design ed to work
with Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devices in addition to
SMBus devices. The maximum frequency is dependent on the RC time constant, but
generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the
voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2
channel.
PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Rev. 8 — 22 January 2014 Product data sheet
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 2 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
2-bit bidirectional tran slator for SDA and SCL lines in mixed-mode I2C-bus applications
Standard-mode, Fast-mode, and Fast-mode Plus I2C-bus and SMBus compatible
Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and
Fast-mode I2C-bus devices and multiple masters
Allows voltage level translation between:
1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
1.2 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
1.8 V Vref(1) and 3.3 V or 5 V Vbias(ref)(2)
2.5 V Vref(1) and 5 V Vbias(ref)(2)
3.3 V Vref(1) and 5 V Vbias(ref)(2)
Provides bidirectional voltage translation with no direction pin
Low 3.5 ON-state connection between input and output ports provides less signal
distortion
Open-drain I2C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2)
5V tolerant I
2C-bus I/O ports to support mixed-mode signal operation
High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: SO8, TSSOP8, VSSOP8, XQFN8, XSON8, XSON8U
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 3 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
3. Ordering information
[1] Same footprint and pinout as the Texas Instruments PCA9306DCU.
[2] PCA9306DC1/DG is functionally the same (electrically and mechanically) as the PCA9306DC1 and the Texas Instruments
PCA9306DCT. It is produced in Dark Green (lead-free and halogen/antimony-free) package material, with a unique orderable part
number for customers who desire to order and only receive Dark Green package material.
[3] Also known as MSOP8.
[4] Same footprint and pinout as the Texas Instruments PCA9306DCT.
[5] Low cost, thinner, drop-in replacement for VSSOP8 (SOT765-1) package.
[6] ‘X’ will change based on date code.
3.1 Ordering options
Table 1. Ordering information
Tamb =
40
C to +85
C.
Type number Topside
mark Package
Name Description Version
PCA9306D PCA9306 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9306DC 306C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
PCA9306DC1[1] P06 VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
PCA9306DC1/DG[2] P06 VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
PCA9306DP 306P TSSOP8[3] plastic thin shrink small outline package; 8 leads;
body width 3 mm SOT505-1
PCA9306DP1[4] 306T TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm SOT505-2
PCA9306GD1[5] P06 XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 20.5 mm SOT996-2
PCA9306GF 06 XSON8 extremely thin small outline package; no leads; 8 terminals;
body 1.35 10.5 mm SOT1089
PCA9306GM P6X[6] XQFN8 plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6 1.6 0.5 mm SOT902-2
Table 2. Ordering options
Type number Orderable
part number Package Packing method Minimum
order
quantity
Temperature
PCA9306D PCA9306D,112 SO8 Standard marking *
IC’s tube - DSC bulk pack 2000 Tamb =40 Cto+85C
PCA9306D,118 SO8 Reel 13” Q1/T 1
*standard mark SMD 2500 Tamb =40 Cto+85C
PCA9306DC PCA9306DC,125 VSSOP8 Reel 7” Q3/T4
*standard mark 3000 Tamb =40 Cto+85C
PCA9306DC1 PCA9306DC1,125 VSSOP8 Reel 7” Q3/T4
*standard mark 3000 Tamb =40 Cto+85C
PCA9306DC1/DG PCA9306DC1/DG,125 VSSOP8 Reel 7” Q3/T4
*standard mark 3000 Tamb =40 Cto+85C
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 4 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
4. Functional diagram
PCA9306DP PCA9306DP,118 TSSOP8 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =40 Cto+85C
PCA9306DP1 PCA9306DP1,125 TSSOP8 Reel 7” Q3/T4
*standard mark 3000 Tamb =40 Cto+85C
PCA9306GD1 PCA9306GD1,125 XSON8U Reel 7” Q3/T4
*standard mark 3000 Tamb =40 Cto+85C
PCA9306GF PCA9306GF,115 XSON8 Reel 7” Q1/T1
*standard mark SMD 5000 Tamb =40 Cto+85C
PCA9306GM PCA9306GM,125 XQFN8 Reel 7” Q3/T4
*standard mark 4000 Tamb =40 Cto+85C
Table 2. Ordering options …continued
Type number Orderable
part number Package Packing method Minimum
order
quantity
Temperature
Fig 1. Logic diagram of PCA9306 (positive logic)
002aab844
SCL1
SDA1
VREF1
GND
3
4
VREF2
27
1
6
5
SCL2
SDA2
8EN
SW
SW
PCA9306
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 5 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
5. Pinning information
5.1 Pinning
Fig 2. Pin confi gura tio n for TSSOP8
(DP1) Fig 3. Pin configuration for TSSOP8 (DP)
(MSOP8)
Fig 4. Pin configuration for VSSOP8 (DC) Fig 5. Pin configuration for VSSOP8
(DC1; DC1/DG)
Fig 6. Pin configuration for SO8 Fig 7. Pin configuration for XQFN8
PCA9306DP1
GND EN
VREF1 VREF2
SCL1 SCL2
SDA1 SDA2
002aab842
1
2
3
4
6
5
8
7
PCA9306DP
GND EN
VREF1 VREF2
SCL1 SCL2
SDA1 SDA2
002aac373
1
2
3
4
6
5
8
7
PCA9306DC
VREF1 EN
SCL1 VREF2
SDA1 SCL2
GND SDA2
002aac374
1
2
3
4
6
5
8
7
PCA9306DC1
PCA9306DC1/DG
GND EN
VREF1 VREF2
SCL1 SCL2
SDA1 SDA2
002aab843
1
2
3
4
6
5
8
7
PCA9306D
GND EN
VREF1 VREF2
SCL1 SCL2
SDA1 SDA2
002aac372
1
2
3
4
6
5
8
7
002aac375
SCL2VREF1
VREF2
EN
SDA2
GND
SDA1
SCL1
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
PCA9306GM
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 6 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
5.2 Pin description
Fig 8. Pin confi gurat io n for XSON8 U
(GD1) Fig 9. Pin configuration for XSON8
002aae014
Transparent top view
8
7
6
5
1
2
3
4
GND
VREF1
SCL1
SDA1
EN
VREF2
SCL2
SDA2
PCA9306GD1
002aaf393
4
3
2
1
5
6
7
8
PCA9306GF
Transparent top view
VREF1
GND
SCL1
VREF2
EN
SCL2
SDA1 SDA2
Table 3. Pin description
Symbol Pin Description
SO8,
TSSOP8 (MSOP8),
TSSOP8,
VSSOP8 (DC1),
XQFN8, XSON8,
XSON8U (GD1)
VSSOP8 (DC)
GND 1 4 ground (0 V)
VREF1 2 1 low-voltage side reference supply voltage for
SCL1 and SDA1
SCL1 3 2 serial clock, low-voltage side; connect to
VREF1 through a pull-up resistor
SDA1 4 3 serial data, low-voltage side; connect to VREF1
through a pull-up resistor
SDA2 5 5 serial data, high-voltage side; connect to
VREF2 through a pull-up resistor
SCL2 6 6 serial clock, high-voltage side; connect to
VREF2 through a pull-up resistor
VREF2 7 7 high-voltage side reference supply voltage for
SCL2 and SDA2
EN 8 8 switch enable input; connect to VREF2 and
pull-up through a high resistor
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 7 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
6. Functional description
Refer to Figure 1 “Logic diagr am of PCA9306 (positive logic)”.
6.1 Function table
[1] EN is controlled by the Vbias(ref)(2) logic levels and should be at least 1 V higher than Vref(1) for best
translator operation.
7. Limiting values
[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
8. Recommended operating conditions
[1] Vref(1) Vbias(ref)(2) 1 V for best results in level shifting applications.
Table 4. Function selection (example)
H = HIGH level; L = LOW level.
Input EN[1] Function
H SCL1 = SCL2; SDA1 = SDA2
L disconnect
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Symbol Parameter Conditions Min Max Unit
Vref(1) reference voltage (1) 0.5 +6 V
Vbias(ref)(2) reference bias voltage (2) 0.5 +6 V
VIinput voltage 0.5[1] +6 V
VI/O voltage on an input/output pin 0.5[1] +6 V
Ich channel current (DC) - 128 mA
IIK input clamping current VI<0V - 50 mA
Tstg storage temperature 65 +150 C
Table 6. Operating conditions
Symbol Parameter Conditions Min Max Unit
VI/O voltage on an input/output pin SCL1, SDA1,
SCL2, SDA2 05V
Vref(1)[1] reference volt age (1) VREF1 0 5 V
Vbias(ref)(2)[1] reference bias voltage (2) VREF2 0 5 V
VI(EN) input voltage on pin EN 0 5 V
Isw(pass) pass switch current - 64 mA
Tamb ambient temperature operating in free-air 40 +85 C
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 8 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
9. Static characteristics
[1] All typical values are at Tamb =25C.
[2] Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON-state resistance is determined by the lowest voltage of the two terminals.
[3] Guaranteed by design.
[4] For DC, DC1 (VSSOP8) and GD1 (XSON8U) packages only.
Table 7. Static characteristics
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VIK input clamping voltage II=18 mA; VI(EN) =0V - - 1.2 V
IIH HIGH-level input current VI=5V; V
I(EN) =0V --5A
Ci(EN) input capacitance on pin EN VI= 3 V or 0 V - 7.1 - pF
Cio(off) off-state input/output capacitance SCLn, SDAn;
VO=3Vor0V; V
I(EN) =0V -46pF
Cio(on) on-state input/output capacitance SCLn, SDAn;
VO=3Vor0V; V
I(EN) =3V - 9.3 12.5 pF
Ron ON-state resistance[2] SCLn, SDAn;
VI=0V;I
O=64mA [3]
VI(EN) =4.5V - 2.4 5.0
VI(EN) =3V - 3.0 6.0
VI(EN) =2.3V - 3.8 8.0
VI(EN) = 1.5 V - 15 32
VI(EN) =1.5V [4] -3280
VI=2.4V; I
O=15mA
VI(EN) =4.5V - 4.8 7.5
VI(EN) = 3 V - 46 80
VI=1.7V; I
O=15mA
VI(EN) = 2.3 V - 40 80
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 9 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
10. Dynamic characteristics
Table 8. Dynamic characteristics (translating down)
Tamb =
40
C to +85
C, unless otherwise specified. Values guaranteed by design.
Symbol Parameter Conditions CL=50pF CL=30pF CL=15pF Unit
Min Max Min Max Min Max
VI(EN) = 3.3 V; VIH =3.3V; V
IL =0V; V
M= 1.15 V (see Figure 10)
tPLH LOW to HIGH
propagation delay from (input) SCL2 or SDA2
to (output) SCL1 or SDA1 02.001.200.6ns
tPHL HIGH to LOW
propagation delay from (input) SCL2 or SDA2
to (output) SCL1 or SDA1 02.001.500.75ns
VI(EN) = 2.5 V; VIH =2.5V; V
IL =0V; V
M= 0.75 V (see Figure 10)
tPLH LOW to HIGH
propagation delay from (input) SCL2 or SDA2
to (output) SCL1 or SDA1 02.001.200.6ns
tPHL HIGH to LOW
propagation delay from (input) SCL2 or SDA2
to (output) SCL1 or SDA1 02.501.500.75ns
Table 9. Dynamic characteristics (translating up)
Tamb =
40
C to +85
C, unless otherwise specified. Values guaranteed by design.
Symbol Parameter Conditions CL=50pF CL=30pF CL=15pF Unit
Min Max Min Max Min Max
VI(EN) = 3.3 V; VIH =2.3V; V
IL =0V; V
TT = 3.3 V; VM=1.15V; R
L= 300 (see Figure 10)
tPLH LOW to HIGH
propagation delay from (input) SCL1 or SDA1
to (output) SCL2 or SDA2 01.750 1.0 0 0.5ns
tPHL HIGH to LOW
propagation delay from (input) SCL1 or SDA1
to (output) SCL2 or SDA2 02.7501.650 0.8ns
VI(EN) = 2.5 V; VIH =1.5V; V
IL =0V; V
TT = 2.5 V; VM=0.75V; R
L= 300 (see Figure 10)
tPLH LOW to HIGH
propagation delay from (input) SCL1 or SDA1
to (output) SCL2 or SDA2 01.750 1.0 0 0.5ns
tPHL HIGH to LOW
propagation delay from (input) SCL1 or SDA1
to (output) SCL2 or SDA2 03.302.001.0ns
a. Load circuit b. Ti ming diagram
S1 = translating up; S2 = translating down.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo=50; tr2ns; t
f2ns.
The outputs are measured one at a time, with one transition per measurement.
Fig 10. Load circuit for outputs
002aab846
V
IH
V
IL
V
M
V
M
input
output
V
OH
V
OL
V
M
V
M
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 10 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
11. Application information
(1) The applied voltages at Vref(1) and Vpu(D) should be such that Vbias(ref)(2) is at least 1 V higher than
Vref(1) for best translator operation.
Fig 11. Typical application circuit (switch always enab led)
(1) In the Enabled mode, the applied enable voltage and the applied voltage at Vref(1) sho uld be such
that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation.
Fig 12. Typical application circuit (switch enable control)
002aab847
SCL1
SDA1
VREF1
GND
3
4
VREF2
1
6
5
SCL2
SDA2
8EN
SW
SW
PCA9306
7
200 kΩ
RPU RPU
V
pu(D)
= 3.3 V
(1)
I
2
C-BUS
DEVICE
SCL
SDA
V
CC
GND
2
V
ref(1)
= 1.8 V
(1)
RPU RPU
I
2
C-BUS
MASTER
SCL
SDA
V
CC
GND
002aab848
SCL1
SDA1
VREF1
GND
3
4
VREF2
1
6
5
SCL2
SDA2
8EN
SW
SW
PCA9306
7
200 kΩ
RPU RPU
V
pu(D)
= 3.3 V
I
2
C-BUS
DEVICE
SCL
SDA
V
CC
GND
2
V
ref(1)
= 1.8 V
(1)
RPU RPU
I
2
C-BUS
MASTER
SCL
SDA
V
CC
GND
on
off
3.3 V enable signal
(1)
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 11 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
11.1 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower volt age or lower
voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled
to HIGH side Vpu(D) through a pull-up resistor (typically 200 k). This allows VREF2 to
regulate the EN input. A filter capacitor on VREF2 is recommended. The I2C-bus master
output can be totem pole or open-drain (pull-up resistors may be required) and the
I2C-bus device output can be totem pole or open-drain (pull-up resistors are required to
pull the SCL2 and SDA2 outputs to Vpu(D)). However, if either output is totem pole, data
must be unidirectional or the outputs must be 3-stateable and be controlled by some
direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If
both outputs are open-drain, no direction control is needed.
The reference supply voltage (Vref(1)) is connected to the processor core power supply
voltage. When VREF2 is connected through a 200 k resistor to a 3.3 V to 5.5 V Vpu(D)
power supply, and Vref(1) is set between 1.0 V and (Vpu(D) 1 V), the output of each SCL1
and SDA1 has a maximum output voltage equal to VREF1, and the output of each SCL2
and SDA2 has a maximum output voltage equal to Vpu(D).
[1] All typical values are at Tamb =25C.
11.2 How to size pull-up resistor value
Sizing the pull-up resistor on an open- drain bus is specific to the individual application and
is dependent on the following driver characteristics:
•The driver sink current
•The VOL of driver
•The VIL of the driver
•Frequency of operation
The following tables can be used to estimate the pull-up resistor value in different use
cases so that the minimum resistance for the pull-up resistor can be found.
Table 11, Table 12 and Table 13 contain sugg ested minimum values of pull-up resistors for
the PCA9306 and NVT20xx devices with typical voltage translation levels and drive
currents. The calculated values assume that both drive currents are the same.
VOL =V
IL =0.1VCC and accounts for a 5%V
CC tolerance of the supplies, 1%
resistor values. It should be noted that the resistor chosen in the final application should
be equal to or larger than the values shown in Table 11, Table 12 and Table 13 to ensure
that the pass voltage is less than 10 % of the VCC voltage, and the external driver should
Table 10. Application operating conditions
Refer to Figure 11.
Symbol Parameter Conditions Min Typ[1] Max Unit
Vbias(ref)(2) reference bias voltage (2) Vref(1) +0.6 2.1 5 V
VI(EN) input voltage on pin EN Vref(1) +0.6 2.1 5 V
Vref(1) reference voltage (1) 0 1.5 4.4 V
Isw(pass) pass switch current - 14 - mA
Iref reference current transistor - 5 - A
Tamb ambient temperature operating in
free-air 40 - +85 C
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 12 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
be able to sink the total current from both pull-up resistors. When selecting the minimum
resistor value in Table 11, Table 12 or Table 13, the drive curr ent strength that should be
chosen should be the lowest drive current seen in the application and account for any
drive strength current scaling with output voltage. For the GTL devices, the resistance
table should be recalculated to account for the difference in ON resistance and bias
voltage limitations between VCC(B) and VCC(A).
Table 11. Pull-up resistor minimum values, 3 mA driver sin k current for PCA9306 an d NVT20xx
A-side B-side
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
1.0 V Rpu(A) = 750
Rpu(B) = 750
Rpu(A) =845
Rpu(B) =845
Rpu(A) = 976
Rpu(B) = 976
Rpu(A) = none
Rpu(B) =887
Rpu(A) = none
Rpu(B) =1.18k
Rpu(A) = none
Rpu(B) =1.82k
1.2 V Rpu(A) =931
Rpu(B) =931
Rpu(A) =1.02k
Rpu(B) =1.02k
Rpu(A) = none
Rpu(B) =887
Rpu(A) = none
Rpu(B) =1.18k
Rpu(A) = none
Rpu(B) =1.82k
1.5 V Rpu(A) =1.1k
Rpu(B) =1.1k
Rpu(A) = none
Rpu(B) =866
Rpu(A) = none
Rpu(B) =1.18k
Rpu(A) = none
Rpu(B) =1.78k
1.8 V Rpu(A) =1.47k
Rpu(B) =1.47k
Rpu(A) = none
Rpu(B) =1.15k
Rpu(A) = none
Rpu(B) =1.78k
2.5 V Rpu(A) =1.96k
Rpu(B) =1.96k
Rpu(A) = none
Rpu(B) =1.78k
3.3 V Rpu(A) = none
Rpu(B) =1.74k
Table 12. Pull-up resistor minimum values, 10 mA driver sink current for PCA9306 and NVT20xx
A-side B-side
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
1.0 V Rpu(A) = 221
Rpu(B) = 221
Rpu(A) =255
Rpu(B) =255
Rpu(A) = 287
Rpu(B) = 287
Rpu(A) = none
Rpu(B) =267
Rpu(A) = none
Rpu(B) = 357
Rpu(A) = none
Rpu(B) =549
1.2 V Rpu(A) =274
Rpu(B) =274
Rpu(A) = 309
Rpu(B) = 309
Rpu(A) = none
Rpu(B) =267
Rpu(A) = none
Rpu(B) = 357
Rpu(A) = none
Rpu(B) =549
1.5 V Rpu(A) = 332
Rpu(B) = 332
Rpu(A) = none
Rpu(B) =261
Rpu(A) = none
Rpu(B) = 348
Rpu(A) = none
Rpu(B) =536
1.8 V Rpu(A) =442
Rpu(B) =442
Rpu(A) = none
Rpu(B) = 348
Rpu(A) = none
Rpu(B) =536
2.5 V Rpu(A) = 590
Rpu(B) = 590
Rpu(A) = none
Rpu(B) =523
3.3 V Rpu(A) = none
Rpu(B) =523
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 13 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
11.3 How to design for maximum frequency operation
The maximum frequency is limited by the mi nimum pulse width LOW and HIGH as well as
rise time and fall time. See Equation 1 as an example of the maximum fr equency. The rise
and fall times are shown in Figure 13.
(1)
The rise and fall times are dependent upon translation voltages, the drive strength, the
total node cap acit ance (C L(tot)) and the pull-up resistors (RPU) that are present on the bus.
The node capacitance is the addition of the PCB trace capacitance and the device
capacitance that exists on the bus. Because of the dependency of the external
components, PCB layout and the different device operating states the calculation of rise
and fall times is complex and has several inflection points along the curve.
The main component o f the rise and fall times is the RC time const ant of the bus line when
the device is in its two primary operating states: when device is in the ON state and it is
low-impedance, the other is when the device is OFF isolating the A-side from the B-side.
A description of the fall time applied to either An or Bn ou tp ut goin g from HIGH to LOW is
as follows. Whichever side is asserted first, the B-side down must discharge to the VCC(A)
voltage. The time is determined by the pull-up resistor, pull-down driver strength and the
Table 13. Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx
A-side B-side
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
1.0 V Rpu(A) = 147
Rpu(B) = 147
Rpu(A) =169
Rpu(B) =169
Rpu(A) = 191
Rpu(B) = 191
Rpu(A) = none
Rpu(B) =178
Rpu(A) = none
Rpu(B) = 237
Rpu(A) = none
Rpu(B) =365
1.2 V Rpu(A) =182
Rpu(B) =182
Rpu(A) = 205
Rpu(B) = 205
Rpu(A) = none
Rpu(B) =178
Rpu(A) = none
Rpu(B) = 237
Rpu(A) = none
Rpu(B) =365
1.5 V Rpu(A) = 221
Rpu(B) = 221
Rpu(A) = none
Rpu(B) =174
Rpu(A) = none
Rpu(B) = 232
Rpu(A) = none
Rpu(B) =357
1.8 V Rpu(A) =294
Rpu(B) =294
Rpu(A) = none
Rpu(B) = 232
Rpu(A) = none
Rpu(B) =357
2.5 V Rpu(A) = 392
Rpu(B) = 392
Rpu(A) = none
Rpu(B) =357
3.3 V Rpu(A) = none
Rpu(B) =348
Fig 13. An example waveform for maximum frequency
fmax 1
tLOW min
tHIGH min
tr actual
tf actual
+++
-------------------------------------------------------------------------------------------------------------
=
002aag912
tr(actual) tf(actual)
GND
VOL
VIL
VIH VCC tHIGH(min)
tLOW(min)
1 / fmax
0.9 × VCC
0.1 × VCC
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 14 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
capacitance. As the level moves below the VCC(A) voltage, the channel resistance drops
so that both A and B sides equal. The capacit an ce on both sides is connecte d to form the
total capacitance and the pull-up resistors on both sides combine to the parallel equivalent
resistance. The Ron of the device is small compared to the pull-up resistor values, so its
effect on the pull-up resistance can be neglected and the fall is determined by the driver
pulling the combined capacit ance and pull-up resistor currents. An estimation of the actual
fall time seen by the device is equal to the time it takes for the B-side to fall to the VCC(A)
voltage and the time it takes for both sides to fall from the VCC(A) voltage to the VIL level.
A description of the rise time applied to either An or Bn output going from LOW to HIGH is
as follows. When the signal level is LOW, the Ron is at its minimum, so the A and B sides
are essentially one node. They will rise together with an RC time constant that is the sum
of all the capacitance from both sides and the parallel of the resistance from both sides.
As the signal approaches the V CC(A) voltage, the channel resistance goes up and th e
waveforms separate, with the B side finishing its rise with the RC time constant o f the
B side. The rise to VCC(A) is essentially the same for both sides.
There are some basic guidelines to follow that will help maximize the performance of the
device:
•Keep trace length to a minimum by placing the NVT device close to the processor.
•The signal round trip time on tr ace should be shor ter than the rise or fall time of signal
to reduce reflections.
•The faster the edge of the signal, the higher the chance for ringing.
•The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher
the frequency the device can use.
The system designer must design the pull-up resistor value based on external current
drive strength and limit the node capacitance (minimize the wire, stub, connector and
trace length) to get the desired operation frequency result.
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 15 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
12. Package outline
Fig 14. Package outline SOT96-1 (SO8)
81,7 $
PD[ $
 $
 $
 E
S F '
 (
 
H +
( / /
S 4 =\ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP
LQFKHV
 


  






  
  


 

R
R
 
',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV
1RWHV
3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG
3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG


627
;
Z 0
ș
$
$

$

E
S
'
+
(
/
S
4
GHWDLO;
(
=
H
F
/
Y 0 $
$

$


SLQLQGH[


\
( 06
 


  






  





 


  PP
VFDOH
62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627


PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 16 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 15. Package outline SOT505-1 (TSSOP8)
81,7 $
$
PD[ $ $ ES /+( /S Z \Y
F H' ( = ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP 










  





 
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
1RWHV
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG


627 

Z 0
ES
'
=
H

 
 
ș
$
$ $
/S
$
GHWDLO;
/
+(
(
F
Y 0 $
;
$
\
 PP
VFDOH
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627

SLQLQGH[
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 17 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 16. Package outline SOT505-2 (TSSOP8)
81,7 $
$
PD[ $ $ ES /+( /S Z \Y
F H' ( = ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP 










  





 
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG


627 

Z 0
ES
'
=
H

 
 
ș
$
$
/S
$
GHWDLO;
$
/
+(
(
F
Y 0 $
;
$
\
 PP
VFDOH
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPPOHDGOHQJWKPP 627

SLQLQGH[
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 18 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 17. Package outline SOT765-1 (VSSOP8)
81,7 $
$
PD[ $$ES/+(/SZ\Y
FH' ( = ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP 










  





 
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
1RWHV
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG


4


627 02

Z0
ES
'
=
H


ș
$
$
4
/S
$
GHWDLO;
$
/
+(
(
F
Y0$
;
$
\
 PP
VFDOH
96623SODVWLFYHU\WKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627
SLQLQGH[
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 19 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 18. Package outline SOT902-2 (XQFN8)
5HIHUHQFHV
2XWOLQH
YHUVLRQ
(XURSHDQ
SURMHFWLRQ ,VVXHGDWH
,(& -('(& -(,7$
627 
02

VRWBSR


8QLW
PP
PD[
QRP
PLQ
 







 



 
$
'LPHQVLRQV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
;4)1SODVWLFH[WUHPHO\WKLQTXDGIODWSDFNDJHQROHDGV
WHUPLQDOVERG\[[PP 627
$E



'(HH
/



/YZ

\\

PP
VFDOH
WHUPLQDO
LQGH[DUHD
% $'
(
;
&
\
&
\
WHUPLQDO
LQGH[DUHD
/
/
E
H
H
$&%Y
&Z
PHWDODUHD
QRWIRUVROGHULQJ
$
$
GHWDLO;
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 20 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 19. Package outline SOT1089 (XSON8)
5HIHUHQFHV
2XWOLQH
YHUVLRQ
(XURSHDQ
SURMHFWLRQ ,VVXHGDWH
,(& -('(& -(,7$
627
02
VRWBSR


8QLW
PP
PD[
QRP
PLQ
  





 



$
'LPHQVLRQV
1RWH
,QFOXGLQJSODWLQJWKLFNQHVV
9LVLEOHGHSHQGLQJXSRQXVHGPDQXIDFWXULQJWHFKQRORJ\
;621H[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV
WHUPLQDOVERG\[[PP 627
$E/






'(HH
/
PP
VFDOH
WHUPLQDO
LQGH[DUHD
(
'
GHWDLO;
$
$
/
/
E
H
H
WHUPLQDO
LQGH[DUHD
î
î
;
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 21 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 20. Package outline SOT996-2 (XSON8U)
5HIHUHQFHV
2XWOLQH
YHUVLRQ
(XURSHDQ
SURMHFWLRQ ,VVXHGDWH
,(& -('(& -(,7$
627
VRWBSR


8QLW
PP
PD[
QRP
PLQ













  
$
'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV
;621SODVWLFH[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV
WHUPLQDOVERG\[[PP 627
$E


'(HH
//
/Y

Z\

\

PP
VFDOH
&
\
&
\
;
WHUPLQDO
LQGH[DUHD
% $'
(
GHWDLO;
$$
E


H
H$& %
Y
&Z
/
/
/
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 22 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering proce ss is suitable for th e following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
•Process issues, such as application of adhesive and flux, clinching of leads, boar d
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 23 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
13.4 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperat ures during reflow
soldering, see Figure 21.
Table 14. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 15. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 24 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 25 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
14. Soldering: PCB footprints
Fig 22. PCB footprint for SOT96-1 (SO8); reflow soldering
Fig 23. P CB footprint for SOT96-1 (SO8); wave soldering
VRWBIU
RFFXSLHGDUHD
VROGHUODQGV
'LPHQVLRQVLQPP
SODFHPHQWDFFXUDF\

î
î
 


VRWBIZ
VROGHUUHVLVW
RFFXSLHGDUHD
VROGHUODQGV
'LPHQVLRQVLQPP
ERDUGGLUHFWLRQ
SODFHPHQWDFFXUUDF\



î
î
î
î


HQODUJHGVROGHUODQG
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 26 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 24. PCB footprint for SOT505-1 (TSSOP8); reflow soldering
VRWBIU
RFFXSLHGDUHDVROGHUODQGV 'LPHQVLRQVLQPP










PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 27 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 25. PCB footprint for SOT505-2 (TSSOP8); reflow soldering
',0(16,216LQPP
$\ %\ ' ' *\ +\3 & *[
VRWBIU
+[
627
VROGHUODQG
RFFXSLHGDUHD
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI76623SDFNDJH
$\%\*\
&
+\
+[
*[
3
*HQHULFIRRWSULQWSDWWHUQ
5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW
3
 
''[
3
        
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 28 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 26. PCB footprint for SOT765-1 (VSSOP8); re flow soldering
',0(16,216LQPP
$\ %\ ' ' *\ +\3
   
&
  
*[
 VRWBIU
+[

627)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI96623SDFNDJH
$\%\*\
&
+\
+[
*[
3
*HQHULFIRRWSULQWSDWWHUQ
5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW
3


'
'[
3

VROGHUODQG
RFFXSLHGDUHD

PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 29 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 27. PCB footprint for SOT1089 (XSON8); reflow soldering
VRWBIU
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI;621SDFNDJH 627
VROGHUUHVLVW
RFFXSLHGDUHD
VROGHUSDVWH VROGHUODQG
'LPHQVLRQVLQPP

î

î

î

î

î
 

PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 30 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 28. P CB footprint for SOT996-2 (XSON8U); reflow solder ing
SODFHPHQWDUHD
RFFXSLHGDUHD
VROGHUODQGV
VROGHUSDVWH
'LPHQVLRQVLQPP
VRWBIU



 

SDRD


SDRD

PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 31 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Fig 29. P CB footprint for SOT902-2 (XQFN8); reflo w so ldering
627
',0(16,216LQPP
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI;4)1SDFNDJH
$\ ' 6/[ 6/\
 
&
  
+[ +\
 
RFFXSLHGDUHD
VROGHUODQGSOXVVROGHUSDVWH
VROGHUODQG
VROGHUSDVWHGHSRVLW
VRWBIU
,VVXHGDWH 

'
î 

&î
+\
+[

6/\ 
$\

6/[

PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 32 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
15. Abbreviations
16. Revision history
Table 16. Abbreviations
Acronym Description
CDM Charged-Device Model
ESD ElectroStatic Discharge
GTL Gunning Transceiver Logic
HBM Huma n Body Model
I2C-bus Inter-Integrated Circuit bus
I/O Input/Output
LVTTL Low Voltage Transistor-Transistor Logic
PLL Phase-Locked Loop
PRR Pulse Repetition Rate
RC Resistor-Capacitor network
SMBus System Management Bus
Table 17. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9306 v.8 20140122 Product data sheet - PCA9306 v.7
Modifications: •deleted (old) Section 11.2, “Sizing pull-up resistor”
•added (new) Section 11.2 “How to size pull-up resistor value”
•added (new) Section 11.3 “How to design for maximum frequency operation”
PCA9306 v.7 20130517 Product data sheet - PCA9306 v.6
PCA9306 v.6 20101125 Product data sheet - PCA9306 v.5
PCA9306 v.5 20100319 Product data sheet - PCA9306 v.4
PCA9306 v.4 20091026 Product data sheet - PCA9306 v.3
PCA9306 v.3 20080804 Product data sheet - PCA9306 v.2
PCA9306 v.2 20070221 Product data sheet - PCA9306 v.1
PCA9306 v.1 20061020 Product data sheet - -
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 33 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semico nductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development .
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contain s the product specification.
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 34 of 35
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed produ ct cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
Translations — A non-English (translated) versio n of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
© NXP B.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 January 2014
Document identifier: PCA9306
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Functional description . . . . . . . . . . . . . . . . . . . 7
6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
8 Recommended operating conditions. . . . . . . . 7
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11 Application information. . . . . . . . . . . . . . . . . . 10
11.1 Bidirectional translation . . . . . . . . . . . . . . . . . 11
11.2 How to size pull-up resistor value. . . . . . . . . . 11
11.3 How to design for maximum frequency
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
13 Soldering of SMD packages . . . . . . . . . . . . . . 22
13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 22
13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 22
13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22
13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 23
14 Soldering: PCB footprints. . . . . . . . . . . . . . . . 25
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 32
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 32
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 33
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18 Contact information. . . . . . . . . . . . . . . . . . . . . 34
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35