1
Motorola TMOS Power MOSFET Transistor Device Data
!
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
•On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
•Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
•Avalanche Energy Specified
•IDSS and VDS(on) Specified at Elevated Temperature
•Static Parameters are the Same for both TMOS V and TMOS E–FET
•Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–to–Source V oltage VDSS 60 Vdc
Drain–to–Gate V oltage (RGS = 1.0 MΩ) VDGR 60 Vdc
Gate–to–Source Voltage — Continuous
Gate–to–Source V oltage — Non–repetitive (tp ≤ 10 ms) VGS
VGSM ±15
±25 Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
15
12
53
Adc
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ 25°C(1)
PD60
0.4
2.1
Watts
W/°C
Watts
Operating and Storage Temperature Range TJ, Tstg –55 to 175 °C
Single Pulse Drain–to–Source A valanche Energy — Starting T J = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)EAS 113 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient(1)
RθJC
RθJA
RθJA
2.5
100
71.4
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “W orst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 2
Order this document
by MTD15N06VL/D
SEMICONDUCTOR TECHNICAL DATA
TM
D
S
G
CASE 369A–13, Style 2
DPAK Surface Mount
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.085 OHM
Motorola, Inc. 1997
MTD15N06VL
2Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS 60
——
68 —
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS —
——
—10
100
µAdc
Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 2.0) (3)
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th) 1.0
—1.5
4.0 2.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3)
(VGS = 5.0 Vdc, ID = 7.5 Adc) RDS(on) —0.075 0.085 Ohm
Drain–to–Source On–V oltage
(VGS = 5.0 Vdc, ID = 15 Adc)
(VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150°C)
VDS(on) —
——
—1.5
1.3
Vdc
Forward T ransconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) gFS 8.0 10 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V 25 Vdc V 0 Vdc
Ciss —570 880 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz
)
Coss —180 380
Reverse T ransfer Capacitance
f
=
1
.
0
MHz)
Crss —45 110
SWITCHING CHARACTERISTICS (2)
T urn–On Delay Time
(V 30 Vd I 15 Ad
td(on) —11 50 ns
Rise T ime (VDD = 30 Vdc, ID = 15 Adc,
VGS =50Vdc
tr— 150 210
T urn–Off Delay Time
V
GS =
5
.
0
Vd
c,
RG = 9.1 Ω)td(off) —27 160
Fall T ime
G)
tf— 70 140
Gate Charge
(V 48 Vd I 15 Ad
QT— 12 20 nC
(VDS = 48 Vdc, ID = 15 Adc, Q1— 3.0 —
(DS ,D,
VGS = 5.0 Vdc) Q2— 7.0 —
Q3—11 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1) (IS = 15 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
VSD —
—0.96
0.85 1.6
—
Vdc
Reverse Recovery Time
(I 15 Ad V 0 Vd
trr — 63 — ns
(IS = 15 Adc, VGS = 0 Vdc, ta—42 —
(S,GS ,
dIS/dt = 100 A/µs) tb— 21 —
Reverse Recovery Stored Charge QRR —0.140 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD—
—3.5
4.5 —
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad) LS— 7.5 — nH
(1) Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk = Max limit – Typ
3 x SIGMA
MTD15N06VL
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
024 6810
0
10
20
30
35
VDS, DRAIN–TO–SOURCE VOLT AGE (VOLTS)
Figure 1. On–Region Characteristics
ID, DRAIN CURRENT (AMPS)
9234 8
0
10
20
30
35
ID, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
01020305
0
0.02
0.04
0.06
0.12
RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature Figure 4. On–Resistance versus Drain Current
and Gate Voltage
010203040
0
5
10
100
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLT AGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
IDSS, LEAKAGE (nA)
TJ = 125
°
C
100
°
C
TJ = 25
°C
VDS
≥
5 V TJ = –55
°C
25
°C
100
°C
TJ = 100
°C
25
°C
–55
°C
VGS = 0 V
VGS = 10V
VGS = 5 V
40
5
7 V 6 V
5 V
8 V
9 V
40
5
567
0.08
0.1
35
35
RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
01020304035
0.04
0.08
ID, DRAIN CURRENT (AMPS)
10 V
TJ = 25
°C
VGS = 5 V
0.06
5
RDS(on), DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
–50
0.2
0.4
0.6
0.8
2.0
TJ, JUNCTION TEMPERATURE (
°
C)
–25 0 25 50 75 100 150
VGS = 5 V
ID = 7.5 A
1
1.4
1.6
1.8
125 175
13 579
15
25
15
25
0.14
15 25
0.1
15 25
45
50
45
50
10
0.12
0.14
0.16
0.02
045 50
1.2
15 25 45
MTD15N06VL
4Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
Figure 7. Capacitance Variation
10 0 5 10 15
GATE–TO–SOURCE OR DRAIN–T O–SOURCE VOLTAGE (VOL TS)
C, CAPACITANCE (pF)
VGS VDS
Ciss
Coss
Crss
TJ = 25
°C
VDS = 0 V VGS = 0 V
1600
1000
800
600
400
200
5
020 25
Ciss
Crss
1200
1400
1800
2000
2200
MTD15N06VL
5
Motorola TMOS Power MOSFET Transistor Device Data
VDS, DRAIN–TO–SOURCE VOLT AGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
0.5 0.55 0.6 0.65 0.7 0.75
VSD, SOURCE–TO–DRAIN VOLTAGE (VOL TS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
IS, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1 10 100
t, TIME (ns)
TJ = 25
°
C
ID = 15 A
VDD = 30 V
VGS = 5 V tr
tf
td(off)
td(on)
TJ = 25
°
C
VGS = 0 V
Figure 10. Diode Forward Voltage versus Current
0Qg, TOTAL GA TE CHARGE (nC)
5101520 30
T
J
= 25
°
C
ID = 15 A
VDS
VGS
0
2
4
6
11
1000
100
10
1
9
7
5
0
10
8
6
4
30
15
12
9
6
3
0
3
2
1
25
18
21
24
27
Q2
Q3
QT
Q1
8
13
0.8 0.85 0.9 0.95 1
10
12
14
15
35
1
3
5
7
9
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
MTD15N06VL
6Motorola TMOS Power MOSFET Transistor Device Data
SAFE OPERATING AREA
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAIN–TO–SOURCE VOLT AGE (VOLTS)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
ID, DRAIN CURRENT (AMPS)
Figure 13. Thermal Response
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESIST ANCE
Figure 14. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
0.1 100
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
VGS = 15 V
SINGLE PULSE
TC = 25
°
C
1
1
10
100
0.1
dc
100
µ
s1 ms 10 ms
10
µ
s
R
θ
JC(t) = r(t) R
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) R
θ
JC(t)
P(pk)
t1t2
DUTY CYCLE, D = t1/t2
t, TIME (s)
1.00
0.10
0.01
0.2
D = 0.5
0.05
0.01
SINGLE PULSE
0.1
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
0.02
TJ, STARTING JUNCTION TEMPERATURE (
°
C)
E
AS, SINGLE PULSE DRAIN–TO–SOURCE
AV ALANCHE ENERGY (mJ)
25 50 75 100 125
ID = 15 A
150
0
100
70
60
50
80
40
30
20
10
175
90
110
120
MTD15N06VL
7
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.190
4.826
mm
inches
0.100
2.54 0.063
1.6
0.165
4.191 0.118
3.0
0.243
6.172
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, T A. Using the values provided on the data sheet,
PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T A of 25°C, one can
calculate the power dissipation of the device. For a DPAK
device, PD is calculated as follows.
PD = 175°C – 25°C
71.4°C/W = 2.1 Watts
The 71.4°C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.1 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
RθJA versus drain pad area is shown in Figure 15.
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
1.75 Watts
Board Material = 0.0625
″
G–10/FR–4, 2 oz Copper
80
100
60
40
20 1086420
3.0 W atts
5.0 W atts
TA = 25
°
C
A, AREA (SQUARE INCHES)
TO AMBIENT ( C/W)
°
RJA, THERMAL RESISTANCE, JUNCTION
θ
MTD15N06VL
8Motorola TMOS Power MOSFET Transistor Device Data
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 16 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Figure 16. Typical Stencil for DPAK and
D2PAK Packages
SOLDER PASTE
OPENINGS
STENCIL
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and soldering
should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.
MTD15N06VL
9
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer , the computer remembers
these profiles from one operating session to the next. Figure
17 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK”
STEP 3
HEATING
ZONES 2 & 5
“RAMP”
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT STEP 7
COOLING
200
°
C
150
°
C
100
°
C
50
°
C
TIME (3 TO 7 MINUTES T OTAL) TMAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205
°
TO 219
°
C
PEAK AT
SOLDER JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
100
°
C
150
°
C
160
°
C170
°
C
140
°
C
Figure 17. Typical Solder Heating Profile
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
MTD15N06VL
10 Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
CASE 369A–13
ISSUE Y
D
A
K
B
R
V
S
FL
G
2 PL
M
0.13 (0.005) T
E
C
U
J
H
–T–
SEATING
PLANE
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.250 5.97 6.35
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.027 0.035 0.69 0.88
E0.033 0.040 0.84 1.01
F0.037 0.047 0.94 1.19
G0.180 BSC 4.58 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.102 0.114 2.60 2.89
L0.090 BSC 2.29 BSC
R0.175 0.215 4.45 5.46
S0.020 0.050 0.51 1.27
U0.020 ––– 0.51 –––
V0.030 0.050 0.77 1.27
Z0.138 ––– 3.51 –––
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
123
4
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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