HIP4086 S E M I C O N D U C T O R 80V, 0.5A Three Phase Driver November 1996 Features Description * Independently Drives 6 N-Channel MOSFETs in Three Phase Bridge Configuration The HIP4086 is a Three Phase Bridge N-Channel MOSFET driver IC. The HIP4086 is specifically targeted for PWM motor control. It makes bridge based designs simple and flexible. Like the HIP4081, the HIP4086 has a flexible input protocol for driving every possible switch combination. Unlike the HIP4081, the user can override the shoot-through protection for switched reluctance applications. The HIP4086 has reduced drive current compared to the HIP4081 (0.5A vs 2.5A) and a much wider range of programmable dead times (0.25s to 4.5s) - like the HIP4082. The HIP4086 is suitable for applications requiring DC to 100kHz. Unlike the previous family members, the HIP4086 has a programmable undervoltage set point. * Bootstrap Supply Max Voltage to 95VDC * Bias Supply Operation from 7V to 15V * 1.25A Peak Turn-Off Current * User-Programmable Dead Time (0.25s to 4.5s) * Charge-Pump and Bootstrap Maintain Upper Bias Supplies * Programmable Bootstrap Refresh Time * Drives 1000pF Load with Typical Rise Time of 20ns and Fall Time of 10ns Also refer to the HIP4083, three phase upper only MOSFET driver, for a lower current solution optimized for smaller motors. * DIS (Disable) Overrides Input Control * Input Logic Thresholds Compatible with 5V to 15V Logic Levels Ordering Information * Dead Time Disable Capability PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE * Programmable Undervoltage Set Point Applications HIP4086AB -40 to 125 24 Pin SOIC M24.3 HIP4086AP -40 to 125 24 Pin PDIP E24.3 * Brushless Motors * AC Motor Drives * Switched Reluctance Motor Drives * Battery Powered Vehicles Pinout Application Block Diagram HIP4086 (PDIP, SOIC) TOP VIEW 80V 12V BHB 1 24 BHO BHI 2 23 BHS BLI 3 22 BLO ALI 4 21 ALO AHI 5 20 VDD VSS 6 19 CLO RDEL 7 18 AHS 8 17 AHO RFSH 9 16 AHB DIS 10 15 CHS CLI 11 14 CHO CHI 12 13 CHB UVLO HIP4086 GND GND CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1996 1 File Number 4220.1 HIP4086 Functional Block Diagram (1/3 of HIP4086 ) CHARGE PUMP 16 AHB AHI DRIVER 5 TURN-ON DELAY LEVEL SHIFTER 17 AHO DIS 10 VDD 20 UVLO 8 RFSH 9 UNDERVOLTAGE DETECTOR 10ns DELAY 18 AHS UV DEAD TIME DISABLE UV 20 VDD RFSH PULSE DRIVER TURN-ON DELAY ALI RDEL 21 ALO 4 6 DEAD TIME CURRENT MIRRORS 7 VSS DEAD TIME DISABLE 2s DELAY + 100mV +VSS TRUTH TABLE INPUT OUTPUT ALI, BLI, CLI AHI, BHI, CHI UV DIS RDEL ALO, BLO, CLO AHO, BHO, CHO X X X 1 X 0 0 X X 1 X X 0 0 1 X 0 0 >100mV 1 0 0 0 0 0 X 0 1 0 1 0 0 X 0 0 1 0 0 0 <100mV 1 1 NOTE: X signifies that input can be either a "1" or "0". Typical Application (PWM Mode Switching) +12V 80V +12V RDEL PWM INPUTS RUV (OPTIONAL) CRFSH (OPTIONAL) FROM OPTIONAL OVERCURRENT LATCH 1 BHB BHO 24 2 BHI BHS 23 3 BLI BLO 22 4 ALI ALO 21 5 AHI VDD 20 6 VSS CLO 19 7 RDEL AHS 18 8 UVLO AHO 17 9 RFSH AHB 16 10 DIS CHS 15 11 CLI CHO 14 12 CHI CHB 13 GND 3-PHASE LOAD RDIS 2 HIP4086 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 17 1 13 AHB BHB CHB (xHB) High-Side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin. 5 2 12 AHI BHI CHI (xHI) High-Side Logic Level Inputs. Logic at these three pins controls the three high side output drivers, AHO (Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the dead time is disabled by connecting RDEL ( Pin 7) to ground, the low side input of each phase will override the corresponding high side input on that phase - see Truth Table on previous page. If RDEL is tied to ground, dead time is disabled and the outputs follow the inputs. Care must be taken to avoid shoot-through in this application. DIS (Pin 10) also overrides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold each xHI high if the pins are not driven. 4 3 11 ALI BLI CLI (xLI) Low-Side Logic Level Inputs. Logic at these three pins controls the three low side output drivers ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL (Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold xLI high if these pins are not driven. 6 VSS Ground. Connect the sources of the Low-Side power MOSFETs to this pin. 7 RDEL Dead Time Setting. Connect a resistor from this pin to VDD to set timing current that defines the dead time between drivers - see Figure 17. All drivers turn-off with no adjustable delay, so the RDEL resistor guarantees no shoot-through by delaying the turn-on of all drivers. When RDEL is tied to VSS, both upper and lowers can be commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1F or smaller may be connected between RDEL and VSS. 8 UVLO Undervoltage Setting. A resistor can be connected between this pin and VSS to program the undervoltage set point, see Figure 18. With this pin not connected, the undervoltage disable is typically 6.6V. When this pin is tied to VDD , the undervoltage disable is typically 6.2V. 9 RFSH Refresh Pulse Setting. An external capacitor can be connected from this pin to VSS to increase the length of the start up refresh pulse - see Figure 16. If this pin is not connected, the refresh pulse is typically 1.5s. 10 DIS Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold DIS high if this pin is not driven. 17 24 14 AHO BHO CHO (xHO) High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase. 15 23 15 AHS BHS CHS (xHS) High-Side Source Connection. Connect the sources of the High-Side power MOSFETs to these pins. The negative side of the bootstrap capacitors should also be connected to these pins. 20 VDD Positive Supply. Decouple this pin to VSS (Pin 6). 21 22 19 ALO BLO CLO (xLO) Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins. NOTE: x = A, B and C. 3 HIP4086 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on xHS. . . . . . . . . . -6V (Transient) to 85V (-40oC to 150oC) Voltage on xHB. . . . . . . . . . . . . . . . . . . . .VxHS -0.3V to VxHS +VDD Voltage on xLO . . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V Voltage on xHO . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHB +0.3V Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Storage Temperature Range . . . . . . . . . . . . . . . . . . .-65oC to 150oC Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Operating Ambient Temperature Range . . . . . . . . . .-40oC to 125oC Operating Junction Temperature Range . . . . . . . . . .-40oC to 150oC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . +7V to +15V Voltage on xHB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VxHS + VDD Voltage on xHS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 80V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. All voltages are relative to VSS unless otherwise specified. 3. x = A, B and C. For example, xHS refers to AHS, BHS and CHS. Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20K, RUV = , Gate Capacitance(CGATE ) = 1000pF TJ = -40oC TO 150oC TJ = 25oC PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION VDD Quiescent Current xHI = 5V, xLI = 5V 2.7 3.4 4.2 2.1 4.3 mA VDD Operating Current f = 20kHz, 50% Duty Cycle 6.3 8.25 10.5 5 11 mA xHB On Quiescent Current xHI = 0V - 40 80 - 100 A xHB Off Quiescent Current xHI = VDD 0.6 0.8 1.3 0.5 1.4 mA xHB Operating Current f = 20kHz, 50% Duty Cycle 0.7 0.9 1.3 - 2.0 mA Qpump Output Voltage No Load 11.5 12.5 14 10.5 14.5 V Qpump Output Current VxHS = 12V, VxHB = 22V 50 100 130 - 140 A xHB, xHS Leakage Current VxHS = 80V, VxHB = 93V 7 24 45 - 50 A VDD Rising Undervoltage Threshold RUV open 6.2 7.1 8.0 6.1 8.1 V VDD Falling Undervoltage Threshold RUV open 5.75 6.6 7.5 5.6 7.6 V Minimum Undervoltage Threshold RUV = VDD 5 6.2 6.8 4.9 6.9 V Low Level Input Voltage - - 1.0 - 0.8 V High Level Input Voltage 2.5 - - 2.7 - V Input Voltage Hysteresis - 35 - - - mV INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS Low Level Input Current VIN = 0V 60 100 135 55 140 A High Level Input Current VIN = 5V -1 - +1 -10 +10 A - 100 - - 200 mV GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO Low Level Output Voltage (VOUT - VSS) ISINKING = 30mA Peak Turn-On Current VOUT = 0V 0.3 0.5 0.7 - 1.0 A Peak Turn-Off Current VOUT = 12V 0.7 1.1 1.5 0.5 1.7 A 4 HIP4086 Switching Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, CGATE = 1000pF, RDEL = 10k TJ = -40oC TO 150oC TJ = 25oC MIN TYP MAX MIN MAX UNITS RDEL = 100K 3.8 4.5 6 3 7 s RDEL = 10K 0.38 0.5 0.65 0.3 0.7 s Dead Time Channel Matching RDEL = 10K - 7 15 - 20 % Lower Turn-Off Propagation Delay (xLI-xLO) No Load - 30 45 - 65 ns Upper Turn-Off Propagation Delay (xHI-xHO) No Load - 75 90 - 100 ns Lower Turn-On Propagation Delay (xLI-xLO) No Load - 45 75 - 90 ns Upper Turn-On Propagation Delay (xHI-xHO) No Load - 65 90 - 100 ns Rise Time CGATE = 1000pF - 20 40 - 50 ns Fall Time CGATE = 1000pF - 10 20 - 25 ns Disable Turn-Off Propagation Delay (DIS - Lower Outputs) - 55 80 - 90 ns Disable Turn-Off Propagation Delay (DIS - Upper Outputs) - 80 90 - 100 ns Disable to Lower Turn-On Propagation Delay (DIS - xLO) - 55 80 - 100 ns PARAMETER TEST CONDITIONS TURN-ON DELAY AND PROPAGATION DELAY Dead Time Disable to Upper Enable (DIS - xHO) RDEL = 10K, CRFSH Open - 2.0 - - - s Refresh Pulse Width (xLO) CRFSH Open - 1.5 - - - s 5 HIP4086 Timing Diagrams LOWER TURN-OFF LOWER TURN-ON XLI XHI XLO XHO DEAD TIME DEAD TIME XLO (RDEL = VSS) XHO (RDEL = VSS) UPPER TURN-ON UPPER TURN-OFF FIGURE 1. DISABLE TO LOWER TURN-ON PROP DELAY DIS OR UV DISABLE TURN-OFF PROP DELAY (UPPERS) REFRESH PULSE WIDTH XHI, XLI XLO XHO DISABLE TO UPPER ENABLE FIGURE 2. DISABLE FUNCTION NOTES: 4. X means any "A", "B", or "C" phase. 5. With RDEL resistor tied to VDD, lowers and uppers cannot be turned on at the same time. Low side logic overrides high side logic unless RDEL < 100mV. 6 HIP4086 Typical Performance Curves 30 6 VDD SUPPLY CURRENT (mA) VDD SUPPLY CURRENT (mA) 5 CGATE = 1000pF ALL GATE CONTROL INPUTS = 5V VDD = 16V VDD = 15V VDD = 12V 4 VDD = 10V 3 VDD = 8V 200kHz 25 100kHz 20 50kHz 20kHz 10kHz 15 VDD = 7V 2 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 10 -60 160 FIGURE 3. VDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE 120 140 160 VDD = 15V 1.6 3000 BIAS CURRENT (mA) FLOATING BIAS CURRENT (A) 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 1.8 TJ = 25oC CGATE = 1000pF 2000 1000 CGATE = NO LOAD 0 20 40 60 80 100 120 140 160 SWITCHING FREQUENCY (kHz) 1.4 1.2 VDD = 10V VDD = 8V VDD = 7V 1.0 VDD = 12V 0.8 180 0.6 -60 200 FIGURE 5. FLOATING IXHB BIAS CURRENT -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 140 160 FIGURE 6. OFF-STATE IXHB BIAS CURRENT 14 CHARGE PUMP OUTPUT VOLTAGE (V) 200 VxHB - VxHS = 10V OUTPUT CURRENT (A) -20 FIGURE 4. VDD SUPPLY CURRENT vs SWITCHING FREQUENCY 4000 0 -40 150 100 50 0 -60 -40 -20 0 20 40 60 80 12 JUNCTION TEMPERATURE (oC) VDD = 12V VDD = 10V 11 10 VDD = 8V 9 8 VDD = 7V 7 6 -60 100 120 140 160 VDD = 15V 13 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) FIGURE 7. CHARGE PUMP OUTPUT CURRENT FIGURE 8. CHARGE PUMP OUTPUT VOLTAGE 7 HIP4086 Typical Performance Curves (Continued) 1 2 AVERAGE TURN-OFF CURRENT (A) AVERAGE TURN-ON CURRENT (A) CGATE = 1000pF 0.8 VDD = 15V 0.6 VDD = 12V VDD = 10V 0.4 V DD = 8V VDD = 7V 0.2 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 1.6 VDD = 12V 1.2 VDD = 10V VDD = 8V 0.8 VDD = 7V 0.4 0 -60 160 CGATE = 1000pF VDD = 15V -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 FIGURE 9. AVERAGE TURN-ON CURRENT (0 TO 5V) FIGURE 10. AVERAGE TURN-OFF CURRENT (VDD TO 4V) 40 100 PROPAGATION DELAY (ns) RISE AND FALL TIMES (ns) VDD = XHB-XHS = 12V, CGATE = 1000pF 30 RISE 20 FALL 10 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 80 xHI to xHO 60 40 xLI to xLO 20 -60 160 -40 0 20 40 60 80 100 120 140 160 450 500 JUNCTION TEMPERATURE (oC) FIGURE 11. RISE AND FALL TIMES (10-90%) FIGURE 12. PROPAGATION DELAY 80 100 TJ = 25oC REFRESH TIME (s) UPPER DISABLE TURN-OFF PROPAGATION DELAY (ns) -20 LOWER DISABLE TURN-OFF LOWER ENABLE TURN-ON 10 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 60 40 20 0 0 160 FIGURE 13. DISABLE PIN PROPAGATION DELAY 50 100 150 200 250 300 CRFSH (pF) 350 FIGURE 14. REFRESH TIME 8 400 HIP4086 Typical Performance Curves (Continued) 11 6 10.5 UNDERVOLTAGE SHUTDOWN/ ENABLE VOLTAGE 4 2 RDEL = 10k 10 ENABLE (50K, UVLO TO GND) 9.5 9 8.5 TRIP (50K, UVLO TO GND) 8 7.5 TRIP/ENABLE (0K, UVLO TO VDD) 7 ENABLE (UVLO OPEN) TRIP (UVLO OPEN) 6.5 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 6 -60 160 FIGURE 15. DEAD TIME -40 -20 0 20 40 60 80 100 120 140 160 JUNCTION TEMPERATURE (oC) FIGURE 16. UNDERVOLTAGE THRESHOLD 25 LEAKAGE CURRENT (A) DEAD TIME (s) RDEL = 100k VxHS = 80V 20 15 10 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 FIGURE 17. IxHS LEAKAGE CURRENT 9 140 160 HIP4086 Dual-In-Line Plastic Packages (PDIP) E24.3 (JEDEC MS-001-AF ISSUE D) N 24 LEAD NARROW BODY DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- A2 -C- SEATING PLANE e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.210 - 5.33 4 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8 eA C 0.008 0.014 0.204 0.355 - D 1.230 1.280 31.24 D1 0.005 - 0.13 A L D1 MIN A E D MAX A1 -ABASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. - 5 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 32.51 24 24 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 10 HIP4086 Small Outline Plastic Packages (SOIC) M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 -C- e 0.25(0.010) M 0.1043 2.35 2.65 - 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e C 0.10(0.004) C A M NOTES 0.0926 A1 B MAX 0.0040 h x 45o A MIN A L D MILLIMETERS MAX A1 SEATING PLANE -A- MIN B S 0.05 BSC - 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: 1.27 BSC H 24 0o 24 7 8o Rev. 0 12/93 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Harris Semiconductor products are sold by description only. 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