LM48557 LM48557 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Controland Reset Literature Number: SNAS486C March 9, 2010 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset General Description Key Specifications The LM48557 is a single supply, mono, ceramic speaker driver with an integrated charge-pump, designed for portable devices, such as cell phones and portable media players, where board space is at a premium. The LM48557 charge pump allows the device to deliver 5.8VRMS from a single 4.2V supply. The LM48557 features high power supply rejection ratio (PSRR), 80dB at 217Hz, allowing the device to operate in noisy environments without additional power supply conditioning. Flexible power supply requirements allow operation from 2.7V to 4.5V. The LM48557 features an active low reset input that reverts the device to its default state. Additionally, the LM48557 features a 36-step I2C volume control and mute function. The low power Shutdown mode reduces supply current consumption to 0.01A. The LM48557's superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. The LM48557 is available in an ultra-small 16-bump micro SMD package (1.965mmx1.965mm). Output Voltage at VDD = 4.2V RL = 1F +22, THD+N 1% 5.8VRMS (typ) Features Integrated Charge Pump Bridge-tied Load Output Differential Input High PSRR I2C Volume and Mode Control Reset Input Advanced Click-and-Pop Suppression Low Supply Current Minimum external components Micro-power shutdown Available in space-saving 16-bump micro SMD package Applications Mobile phones PDAs Notebook Electronic Devices MP3 Players Boomer(R) is a registered trademark of National Semiconductor Corporation. (c) 2010 National Semiconductor Corporation 300981 www.national.com LM48557 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset LM48557 LM48557 Typical Application 30098103 FIGURE 1. Typical Audio Amplifier Application Circuit www.national.com 2 LM48557 Connection Diagrams TL Package 1.965mm x 1.965mm x 0.6mm 16-Bump micro SMD Marking 30098110 Top View XY - Date Code TT - Lot Traceability G - Boomer Family M2 - LM48557TL 30098112 Top View Order Number LM48557TL See NS Package Number TLA1611A Ordering Information Order Number Package Package DWG # Transport Media MSL Level Green Status LM48557TL 16-Bump micro SMD LM48557TLX 16-Bump micro SMD TLA1611A 250 units on tape and reel 1 RoHS & no Sb/Br TLA1611A 3000 units on tape and reel 1 RoHS & no Sb/Br 3 www.national.com LM48557 UR Package 1.965mm x 1.965mm x 0.35mm 16-Bump micro SMD Marking 30098101 Top View XY - Date Code TT - Lot Traceability G - Boomer Family N5 - LM48557UR 30098112 Top View Order Number LM48557UR See NS Package Number URA1611A Ordering Information Order Number Package Package DWG # Transport Media MSL Level Green Status LM48557UR 16-Bump micro SMD URA1611A 250 units on tape and reel 1 RoHS & no Sb/Br LM48557URX 16-Bump micro SMD URA1611A 3000 units on tape and reel 1 RoHS & no Sb/Br www.national.com 4 LM48557 Bump Descriptions Bump Name A1 SVDD Signal Power Supply Description A2 SGND Signal Ground A3 VCM A4 IN- Common Mode Sense Input Amplifier Inverting input B1 OUT- Amplifier Inverting output B2 OUT+ Amplifier Non-Inverting Output B3 RESET Active Low Reset Input. Connect to VDD for normal operation. Toggle between VDD and GND to reset the device. B4 IN+ C1 CPVSS Charge Pump Output C2 SCL I2C Serial Clock Input SDA I2C Serial Data Input C3 C4 I2CV DD D1 C1N D2 PGND Amplifier Non-Inverting Input I2C Supply Voltage Charge Pump Flying Capacitor Negative Terminal Power Ground D3 C1P Charge Pump Flying Capacitor Positive Terminal D4 PVDD Power Supply 5 www.national.com LM48557 Thermal Resistance Absolute Maximum Ratings (Note 1, Note JA (typ) - (TLA1611A) 63C/W Soldering Information See AN-1112 "Micro SMD Wafer Level Chip Scale Package." 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (Note 1) Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Rating-Human Body Model (Note 4) ESD Rating-Machine Model (Note 5) Junction Temperature Operating Ratings 5.25V -65C to +150C -0.3V to VDD +0.3V Internally Limited Temperature Range TMIN TA TMAX Supply Voltage PVDD and SVDD 2kV -40C TA +85C 2.7V VDD 4.5V 1.7V I2CVDD 4.5V I2CVDD 150V 150C Electrical Characteristics VDD = 4.2V (Note 1, Note 2) The following specifications apply for AV = 6dB, RL = 1F + 22, C1 = 2.2F, C2 = 2.2F, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. LM48557 Symbol Parameter Conditions Min Typ Max (Note 7) (Note 6) (Note 7) Units VDD Supply Voltage Range 2.7 4.5 V I2CVDD I2C Supply Voltage Range 1.7 4.5 V IDD Quiescent Power Supply Current VIN = 0V, RL = 5 8 mA ISD Shutdown Current Shutdown Enabled 0.01 1 A Differential Output Offset Voltage VIN = 0V, AV = 0dB 3 12 mV VIN = 0V, AV = 48dB 40 160 mV VIH Logic High Input Threshold RESET, VDD = 2.7V to 4.5V VIL Logic Low Input Threshold RESET, VDD = 2.7V to 4.5V |VOS| AV Gain 1.4 V 0.4 V Minimum Gain Setting Volume Control = 000001 -25.5 -25 -24.5 dB Maximum Gain Setting Volume Control = 111111 47 48 49 dB AV(MUTE) Mute Attenuation RIN Input Resistance 1 VIN Common Mode Input Voltage Range -1 Volume Control = 000000 -90 dB 3 M 1 VP-P RL = 1F + 22, THD+N = 1% 5.5 5.8 VRMS 15.6 16.4 VP-P 4.0 VRMS f = 1kHz 5.6 VRMS f = 5kHz 2.9 VRMS VO = 4VRMS, f = 1kHz, AV = 48dB 0.05 % f = 1kHz VO Output Voltage f = 5kHz RL = 2.2F + 10, THD+N = 1% THD+N Total Harmonic Distortion + Noise www.national.com 6 Symbol Parameter Min Typ Max (Note 7) (Note 6) (Note 7) Conditions Units VDD = 4.2V + 200mVP-P (sine), Inputs AC GND, CIN = 0.1F, AV = 0dB PSRR Power Supply Rejection Ratio (Figure 2) fRIPPLE = 217Hz 80 dB fRIPPLE = 1kHz 80 dB 40 dB 40 dB 36 dB 37 dB VDD = 4.2V + 200mVP-P (sine), Inputs AC GND, CIN = 0.1F, AV = 48dB f = 1kHz 15 f = 5kHZ CMRR VCM = 200mVP-P (sine), Common Mode Rejection Ratio CIN = 0.1F, AV = 48dB (Figure 3) fRIPPLE = 500Hz 16 fRIPPLE = 1kHz fSW Charge Pump Switching Frequency SNR Signal To Noise Ratio OS Output Noise TWU Wake Up Time 230 300 370 kHz VOUT = 5VRMS, f = 1kHz AV = 48dB 74 AV = 0dB, A-Weighted Filter 20 AV = 48dB, A-weighted Filter 1 mV From shutdown 5 ms I2C Interface Characteristics 1.7V I2CVDD 4.5V (Notes 1, 2) dB 30 V The following specifications apply for RPU = 1k to I2CVDD, unless otherwise specified. Limits apply for TA = 25C. LM48557 Symbol VIH Parameter Logic Input High Threshold Conditions VIL Logic Input Low Threshold SDA, SCL Logic Output Low Threshold SDA, ISDA = 3.6mA Logic Output High Current SDA, SCL, Typ Max (Note 6) (Note 7) Units 0.7 x I2CVDD SDA, SCL VOL IOH Min (Note 7) V 0.3 x I2CV DD I2CV 0.35 = 4.5V SCL Frequency DD V V 2 A 400 kHz 6 SDA Setup Time 100 5 SDA Stable Time 1 Start Condition Time 100 ns 7 Stop Condition Time 100 ns 0 7 ns 250 900 ns www.national.com LM48557 LM48557 LM48557 Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. The Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Operating Ratings except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Typical values represent most likely parametric norms at TA = +25C, and at the Operation Rating at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis. 30098106 FIGURE 2. PSRR Test Circuit 30098104 FIGURE 3. CMRR Test Circuit www.national.com 8 LM48557 Typical Performance Characteristics THD+N vs Frequency VDD = 3.6V, ZL = 1F + 22 AV = 48dB, VO = 2.5V THD+N vs Frequency VDD = 4.2V, ZL = 1F + 22 AV = 48dB 30098132 30098133 THD+N vs Output Voltage ZL = 1F + 22, AV = 0dB Output Voltage vs Frequency VDD = 4.2V, ZL = 1F + 22 THD+N = 1% 30098126 30098127 Power Consumption vs Output Voltage VDD = 3.6V, ZL = 1F + 22 Power Consumption vs Output Voltage VDD = 4.2V, ZL = 1F + 22 30098128 30098129 9 www.national.com LM48557 CMRR vs Frequency VDD = 4.2V, VRIPPLE = 200mVP-P, AV = 48dB PSRR vs Frequency VDD = 4.2V, VRIPPLE = 200mVP-P 30098135 30098170 Output Voltage vs Supply Voltage ZL = 1F + 22, THD+N = 1% Supply Current vs Supply Voltage No Load 30098130 30098131 Charge Pump Output Voltage vs Load Current VDD = 4.2V 30098171 www.national.com 10 R/W = 1. In other words, the LM48557 will not issue an ACK when R/W = 1. Each address bit is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the LM48557. If the LM48557 receives the correct address, the device pulls the SDA line low, generating an acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. The LM48557 has two registers, Mode Control and Volume Control. The register address and register data are combined into a single byte, the most significant bit (MSB) indicates which register is being addressed. To address the Mode Control register, set the MSB of the data byte to 0, followed by seven bits of register data. To address the Volume Control register, set the MSB of the data byte to 1, followed by seven bits of register data. After the 8-bit register data word is sent, the LM48557 sends another ACK bit. The LM48557 supports single and multi-byte write operations, any number of data bytes can be transmitted to the device between START and STOP conditions. Following the acknowledgement of the last register data word, the master issues a STOP bit, allowing SDA to go high while SCL is high. I2C COMPATIBLE INTERFACE The LM48557 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48557 and the master can communicate at clock rates up to 400kHz. Figure 4 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48557 is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 5). Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 6). The LM48557 device address is 11011110. I2C BUS FORMAT The I2C bus format is shown in Figure 6. The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. Set R/W = 0; the LM48557 is a WRITE-ONLY device and will not respond to 30098111 FIGURE 4. I2C Timing Diagram 300981g8 FIGURE 5. Start and Stop Diagram 300981e2 FIGURE 6. Example Write Sequence 11 www.national.com LM48557 Application Information LM48557 TABLE 1. Device Address B7 B6 B5 B4 B3 B2 B1 B0 R/W 1 1 0 1 1 1 1 0 Device Address TABLE 2. Control Registers Register Name B7 B6 B5 B4 B3 B2 B1 B0 Mode Control 0 0 0 0 0 0 MUTE SHDN Volume Control 1 0 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 TABLE 3. Mode Control Registers BIT NAME B0 SHDN B1 MUTE B2 B3 VALUE DESCRIPTION 0 Shutdown mode 1 Normal operation DEFAULT SETTING 0 0 Normal operation 1 Device mute, AV = -90dB. RESERVED* X Unused, Set to 0 0 RESERVED* X Unused, Set to 0 0 0 0 B4 TESTMODE 0 Set B4 to 0. B4 = 1 enables TESTMODE. See TESTMODE section. B5 RESERVED* X Unused, Set to 0 0 B6 RESERVED* X Unused, Set to 0 0 B7 REGISTER ADDRESS 0 Set to 0 to access Mode Control register 0 *RESERVED bits are Don't Cares and are ignored by the device. The state of the RESERVED bits does not affect device operation. TABLE 4. Volume Control Registers VALUE DESCRIPTION DEFAULT SETTING BIT NAME B0:B5 VOL0:VOL5 B6 RESERVED* X Unused, Set to 0 0 B7 REGISTER ADDRESS 1 Set to 1 to access Volume Control register 1 See Volume Controls amplifier gain/attenuation Control Table *RESERVED bits are Don't Cares and are ignored by the device. The state of the RESERVED bits does not affect device operation. www.national.com 12 0 30098109 FIGURE 7. Single-Byte Write Example 30098105 FIGURE 8. Multi-Byte Write Example positive supply voltage (PVDD). The LM48557 takes advantage of the increased head room created by the charge pump and the bridge-tied load (BTL) architecture, delivering significantly more voltage than a single-ended, single-supply amplifier to the speaker. GENERAL AMPLIFIER FUNCTION The LM48557 is a fully differential ceramic speaker driver that utilizes National's inverting charge pump technology to deliver over 5.8VRMS to a 1F ceramic speaker while operating from a single 4.2V supply. The low noise, inverting charge pump generates a negative supply voltage (CPVSS) from the 13 www.national.com LM48557 address, and the LM48557 responds with an ACK (Figure 8). The master device then transmits the first data byte. Following the LM48557's ACK, the master device does not issue a STOP condition, transmitting a second data byte instead. The LM48557 responds with an ACK bit. The master device can continue to issue data bytes, and the LM48557 will respond with an ACK, until a STOP condition is issued. Once a STOP condition is issued, the LM48557 ignores the I2C bus until the master issues the LM48557's device address. SINGLE AND MULTI-BYTE WRITE OPERATION The LM48557 supports both single-byte and multi-byte write operations. A single-byte write operation begins with the master device transmitting a START condition followed by the device address (Figure 7). After receiving the correct device address, the LM48557 generates an ACK bit. The master device transmits the register data byte, after which the LM48557 generates and ACK bit. Following the ACK, the master issues a STOP condition, completing the singly-byte data transfer. A multi-byte write operation is similar to a single-byte operation, the master device issues a START condition and device LM48557 TABLE 5. Volume Control Table VOLUME STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB) 1 (MUTE) 0 0 0 0 0 0 -90 2 0 0 0 0 0 1 -25 3 0 0 0 0 1 0 -22 4 0 0 0 0 1 1 -19 5 0 0 0 1 0 0 -16 6 0 0 0 1 0 1 -13 7 0 0 0 1 1 0 -10 8 0 0 0 1 1 1 -8 9 0 0 1 0 0 0 -6 10 0 0 1 0 0 1 -4 11 0 0 1 0 1 0 -2 12 0 0 1 0 1 1 0 13 0 0 1 1 0 0 2 14 0 0 1 1 0 1 4 15 0 0 1 1 1 0 6 16 0 0 1 1 1 1 8 17 0 1 0 0 0 0 10 18 0 1 0 0 0 1 12 19 0 1 0 0 1 0 14 20 0 1 0 0 1 1 16 21 0 1 0 1 0 0 18 22 0 1 0 1 0 1 20 23 0 1 0 1 1 0 22 24 0 1 0 1 1 1 24 25 0 1 1 0 0 0 26 26 0 1 1 0 0 1 28 27 0 1 1 0 1 0 30 28 0 1 1 0 1 1 32 29 0 1 1 1 0 0 34 30 0 1 1 1 0 1 36 31 0 1 1 1 1 0 38 32 0 1 1 1 1 1 40 Do Not Use Volume Steps 33-60 See Table 6 61 1 1 1 1 0 0 42 62 1 1 1 1 0 1 44 63 1 1 1 1 1 0 46 64 1 1 1 1 1 1 48 www.national.com 14 VOLUME STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB) 33 1 0 0 0 0 0 -90 34 1 0 0 0 0 1 -25 35 1 0 0 0 1 0 -22 36 1 0 0 0 1 1 -19 37 1 0 0 1 0 0 -16 38 1 0 0 1 0 1 -13 39 1 0 0 1 1 0 -10 40 1 0 0 1 1 1 -8 41 1 0 1 0 0 0 -6 42 1 0 1 0 0 1 -4 43 1 0 1 0 1 0 0 44 1 0 1 0 1 1 4 45 1 0 1 1 0 0 8 46 1 0 1 1 0 1 12 47 1 0 1 1 1 0 14 48 1 0 1 1 1 1 16 49 1 1 0 0 0 0 18 50 1 1 0 0 0 1 20 51 1 1 0 0 1 0 22 52 1 1 0 0 1 1 24 53 1 1 0 1 0 0 26 54 1 1 0 1 0 1 28 55 1 1 0 1 1 0 30 56 1 1 0 1 1 1 32 57 1 1 1 0 0 0 34 58 1 1 1 0 0 1 36 59 1 1 1 0 1 0 38 60 1 1 1 0 1 1 40 15 www.national.com LM48557 TABLE 6. Unused Volume Steps LM48557 VOLUME CONTROL The LM48557 has a 64 step volume control, but only 36 steps are recommended for use. Use steps 1 through 32 and steps 61 through 64 to set the gain of the device. Accessing steps 33 through 60 results in the repeated gain conditions shown in Table 6. Steps 33 through 60 are not tested and should not be used. results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2F, the RDS(ON) of the charge pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used in systems where low maximum output power requirements. SHUTDOWN FUNCTION The LM48557 features a low-power shutdown mode that disables the device lowers the quiescent current to 0.01A. Set bit B0 (SHDN) of the Mode Control register to 0 to disable the amplifier and charge pump. Set SHDN to 1 for normal operation. Shutdown mode does not clear the I2C register. When re-enabled, the device returns to its previous volume setting. To clear the I2C register, either remove power from the device, or toggle RESET (see RESET section). Charge Pump Hold Capacitor (C2) The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2 reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance. A lower value capacitor can be used in systems where low maximum output power requirements. Input Capacitor Selection Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM48557. The input capacitors create a high-pass filter with the input resistors RIN. The -3dB point of the high pass filter is found using Equation (1) below. RESET The LM48557 features an active low reset input. Driving RESET low clears the I2C register. Volume control is set to 000000 (-90dB) and SHDN is set to 0, disabling the device. While RESET is low, the LM48557 ignores any I2C data. After the device is reset, and RESET is driven high, the LM48557 remains in shutdown mode with the volume set to -90dB. Reenable the device by writing to the I2C register. f = 1 / 2RINCIN (Hz) MUTE The LM48557 features a mute mode. Set bit B1 (MUTE) of the Mode Control register to 1 to mute the device. In mute mode, the gain is set to -90dB, equivalent to the volume step 1. Set MUTE = 0 to unmute the device. Once unmuted, the device returns to its previous volume step. Where the value of R IN is given in the Electrical Characteristics Table. High pass filtering the audio signal helps protect the speakers. When the LM48557 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR. TEST MODE If enabled, TESTMODE does not affect device performance under normal operating conditions. Operating above the recommended supply voltage range with TESTMODE enabled can result in damage to the device. COMMON MODE SENSE The LM48557 features a common mode sense pin (VCM, pin A3) that includes additional common mode cancelling circuitry that improves the CMRR. When the volume control is set at a high gain step such as 48dB, any mismatch in the input capacitors would degrade CMRR performance significantly. With the VCM pin connected to the ground of the input source, it takes the input capacitor mismatches out of the equation and therefore improves the CMRR. Another advantage with this feature is that only one input capacitor is needed in the single-ended configuration as opposed to two well matched capacitors. See next section for details of different configurations of the LM48857. PROPER SELECTION OF EXTERNAL COMPONENTS Power Supply Bypassing/Filtering Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1F ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. Charge Pump Capacitor Selection Use low ESR ceramic capacitors (less than 100m) for optimum performance. Charge Pump Flying Capacitor (C1) The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that is too low www.national.com (1) 16 Ground-Referenced Audio Source The LM48557 input stage is compatible with ground-referenced input sources, such as CODECs with an integrated headphone amplifier. Connect either input, IN+ or IN- to the 30098107 FIGURE 9. Single-Ended Input Configuration with a Ground-Referenced Source CODEC outputs in parallel through two equal value resistors to either IN+ or IN-, and connect the unused input and VCM to the CODEC ground. Select the value of the resistors based on the desired frequency response created by the combination of the input resistor and the input coupling capacitor. NON-GROUND REFERENCED AUDIO SOURCE Stereo-to-Mono Conversion The LM48557 can convert a single-ended stereo signal to a mono BTL signal (Figure 10). Connect the left and right 30098108 FIGURE 10. Single-Ended Stereo-to-Mono BTL Conversion 17 www.national.com LM48557 CODEC output, and connect the unused input and VCM to the CODEC output ground (Figure 9). An input coupling capacitor in series with the source and device input is recommended to block the CODEC output offset voltage, minimizing click and pop and zipper noise during volume transitions. SINGLE-ENDED INPUT CONFIGURATION LM48557 improves audio performance, minimizes crosstalk between channels and prevents switching noise from interfering with the audio signal. Use of power and ground planes is recommended. Place all digital components and route digital signal traces as far as possible from analog components and traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines must cross either over or under each other, ensure that they cross in a perpendicular fashion. PCB Layout Guidelines Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due to trace resistance between the LM48557 and the load results in decreased output power and efficiency. Trace resistance between the power supply and ground has the same effect as a poorly regulated supply, increased ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize losses due to trace resistance, as well as route heat away from the device. Proper grounding LM48557TL Demoboard Bill of Materials Designator Quantity Description U1 1 LM48557TL Differential, Mono, Ceramic Speaker Driver with I2C Volume Control, and Reset C1, C2, C5, C6, C7 5 CAP CERAMIC 2.2F 10V X5R 10% 0603 C3, C4 2 CAP .1F 16V CERAMIC X7R 10% 1206 C8 1 CAP TANT LOESR 10F 16V 10% SMD J2 1 CONN SOCKET PCB VERT 16POS .1" JU1, JU2, JU3, JU4, VCM, VDD, GND, I2CVDD, IN+, IN-, OUT+, OUT- 12 CONN HEADER VERT .100 2POS 30Au JU5 1 CONN HEADER VERT .100 3POS 30Au R1, R2 2 RES 5.1K OHM 1/10W 5% 0603 SMD R3 1 RES 20K OHM 1/10W 5% 0603 SMD 4 Jumper Shunt w/handle, 30uin gold plated, 0.100" pitch JU1_SH, JU2_SH, JU3_SH, JU5_SH www.national.com 18 LM48557 PC Board Layout 30098124 30098125 Top Layer Silk Screen 30098122 30098123 Layer 2 Layer 3 19 www.national.com LM48557 30098120 30098121 Bottom Layer www.national.com Bottom Silkscreen 20 LM48557 Demo Board Schematic 30098119 FIGURE 11. LM48557 Demo Board Schematic 21 www.national.com LM48557 Revision History Rev Date 1.0 07/08/09 Initial released. 1.01 07/15/09 Deleted the "Tru-GND..." trademark on the cover page. 1.02 08/05/09 Text edits. 1.03 08/06/09 Fixed a typo error. 1.04 01/11/10 Added the LM48557UR package drawing, top markings, and the marketing outline. www.national.com Description 22 LM48557 Physical Dimensions inches (millimeters) unless otherwise noted 16-Bump micro SMD Order Number LM48557TL NS Package Number TLA1611A X1 = 1.965 0.03 X2 = 1.965 0.03 X3 = 0.6 0.075 23 www.national.com LM48557 Package Preview 16-Bump micro SMD NS Package Number URA16XXX X1 = 1.965 0.03 X2 = 1.965 0.03 X3 = 0.350 0.045 www.national.com 24 LM48557 Notes 25 www.national.com LM48557 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH(R) Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise(R) Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagicTM www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise(R) Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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