FEDD5118165F-02
Issue Date: Mar. 23, 2010
MSM5118165F
1,048,576-Word 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
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DESCRIPTION
The MSM5118165F is a 1,048,576-word 16-bit dynamic RAM fabricated in LAPIS Semiconductor’s
silicon-gate CMOS technology. The MSM5118165F achieves high integration, high-speed operation,
and low-power consumption because LAPIS Semiconductor manufactures the device in a
quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5118165F is available in a
42-pin plastic SOJ or 50/44-pin plastic TSOP.
FEATURES
· 1,048,576-word 16-bit configuration
· Single 5V power supply, 10% tolerance
· Input : TTL compatible, low input capacitance
· Output : TTL compatible, 3-state
· Refresh : 1024 cycles/16ms
· Fast page mode with EDO, read modify write capability
· CAS before RAS refresh, hidden refresh, RAS-only refresh capability
· Packages
42-pin 400mil plastic SOJ (SOJ42-P-400-1.27) (Product : MSM5118165F-xxJS)
50/44-pin 400mil plastic TSOP (TSOPII50/44-P-400-0.80-K) (Product : MSM5118165F-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.) Power Dissipation
Family tRAC t
AA t
CAC t
OEA
Cycle Time
(Min.) Operating
(Max.)
Standby
(Max.)
50ns 25ns 13ns 13ns 84ns 743mW
60ns 30ns 15ns 15ns 104ns 688mW
MSM5118165F
70ns 35ns 20ns 20ns 124ns 633mW
5.5mW
FEDD5118165F-02
MSM5118165F
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PIN CONFIGURATION (TOP VIEW)
Pin Name Function
A0–A9 Address Input
RAS Row Address Strobe
LCAS Lower Byte Column Address Strobe
UCAS Upper Byte Column Address Strobe
DQ1–DQ16 Data Input/Data Output
OE Output Enable
WE Write Enable
VCC Power Supply (5V)
VSS Ground (0V)
NC No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must
be provided to every VSS pin.
42-Pin Plastic
SOJ
50/44-Pin Plastic TSOP
(K Type)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DQ1
DQ2
DQ3
DQ4
VCC
VC
VCC
VSS
VS
VSS
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
A
9
A
8
A
7
A
6
A
0
A
1
A
2
A
3
DQ5
DQ6
DQ7
DQ8
NC
NC
WE
R
A
S
NC
NC
NC
A
5
A
4
L
CAS
U
CAS
O
E
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
DQ1
DQ2
DQ3
DQ4
VCC
VC
A
3
VSS
VS
VSS
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
A
9
A
8
A
7
A
6
NC
A
0
A
1
A
2
DQ5
DQ6
DQ7
DQ8
NC
NC
NC
WE
A
NC
NC
A
5
A
4
L
CAS
U
CA
S
O
E
22
23
24
25
29
28
27
26
VCC
NC
FEDD5118165F-02
MSM5118165F
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FUNCTION TABLE
Input Pin DQ Pin
RAS LCAS UCAS WE OE DQ1-DQ8 DQ9-DQ16
Function Mode
H * * * * High-Z High-Z Standby
L H H * * High-Z High-Z Refresh
L L H H L DOUT High-Z Lower Byte Read
L H L H L High-Z DOUT Upper Byte Read
L L L H L DOUT D
OUT Word Read
L L H L H DIN Don’t Care Lower Byte Write
L H L L H Don’t Care DIN Upper Byte Write
L L L L H DIN D
IN Word Write
L L L H H High-Z High-Z
* : “H” or “L”
FEDD5118165F-02
MSM5118165F
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ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on Any Pin Relative to VSS V
IN, VOUT –0.5 to VCC+ 0.5 V
Voltage VCC Supply relative to VSS V
CC –0.5 to 7 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD* 1 W
Operating Temperature Topr 0 to 70 °C
Storage Temperature Tstg –55 to 150 °C
*: Ta = 25C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter Symbol Min. Typ. Max. Unit
VCC 4.5 5.0 5.5 V
Power Supply Voltage
VSS 0 0 0 V
Input High Voltage VIH 2.4 VCC + 0.5*1 V
Input Low Voltage VIL 0.5*2 0.8 V
Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which VCC is applied).
*2. The input voltage is VSS 2.0V when the pulse width is less than 20ns (the pulse width respect to the
point at which VSS is applied).
PIN CAPACITANCE
(Vcc = 5V 10%, Ta = 25°C, f = 1 MHz)
Parameter Symbol Min. Max. Unit
Input Capacitance (A0 - A9) CIN1 — 5 pF
Input Capacitance
(RAS, LCAS, UCAS, WE, OE) CIN2 — 7 pF
Output Capacitance (DQ1 - DQ16) CI/O — 7 pF
FEDD5118165F-02
MSM5118165F
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DC CHARACTERISTICS
(VCC = 5V 10%, Ta = 0 to 70°C)
MSM5118165
F-50
MSM5118165
F-60
MSM5118165
F-70
Parameter Symbol Condition
Min. Max. Min. Max. Min. Max.
Unit Note
Output High Voltage VOH IOH = 5.0mA 2.4 VCC 2.4 VCC 2.4 VCC V
Output Low Voltage VOL IOL = 4.2mA 0 0.4 0 0.4 0 0.4 V
Input Leakage
Current ILI
0V VI 6.5V;
All other pins not
under test = 0V
10 10 10 10 10 10 A
Output Leakage
Current ILO DQ disable
0V VO VCC 10 10 10 10 10 10 A
Average Power
Supply Current
(Operating)
ICC1
RAS, CAS cycling,
tRC = Min. 135 125 115 mA 1,2
RAS, CAS = VIH 2 2 2
Power Supply
Current
(Standby)
ICC2 RAS, CAS
VCC 0.2V 1 1 1
mA 1
Average Power
Supply Current
(RAS-only Refresh)
ICC3
RAS cycling,
CAS = VIH,
tRC = Min.
135 125 115 mA 1,2
Power Supply
Current
(Standby)
ICC5
RAS = VIH,
CAS = VIL,
DQ = enable
5 5 5 mA 1
Average Power
Supply Current
(CAS before RAS
Refresh)
ICC6
RAS = cycling,
CAS before RAS 135 125 115 mA 1,2
Average Power
Supply Current
(Fast Page Mode)
ICC7
RAS = VIL,
CAS cycling,
tHPC = Min.
120 110 100 mA 1,3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
FEDD5118165F-02
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AC CHARACTERISTICS (1/2)
(VCC = 5V 10%, Ta = 0 to 70°C) Note1,2,3
MSM5118165
F-50
MSM5118165
F-60
MSM5118165
F-70
Parameter Symbol
Min. Max. Min. Max. Min. Max.
Unit Note
Random Read or Write Cycle Time tRC 84 104 124 ns
Read Modify Write Cycle Time tRWC 110 135 160 ns
Fast Page Mode Cycle Time tHPC 20 25 30 ns
Fast Page Mode Read Modify Write
Cycle Time tHPRWC 58 68 78 ns
Access Time from RAS t
RAC 50 60 70 ns 4, 5, 6
Access Time from CAS t
CAC 13 15 20 ns 4,5
Access Time from Column Address tAA 25 30 35 ns 4,6
Access Time from CAS Precharge tCPA 30 35 40 ns 4,13
Access Time from OE t
OEA 13 15 20 ns 4
Output Low Impedance Time from
CAS tCLZ 0 0 0 ns 4
Data Output Hold After CAS Low tDOH 5 5 5 ns
CAS to Data Output Buffer Turn-
off Delay Time tCEZ 0 13 0 15 0 20 ns 7,8
RAS to Data Output Buffer Turn-
off Delay Time tREZ 0 13 0 15 0 20 ns 7,8
OE to Data Output Buffer Turn-off
Delay Time tOEZ 0 13 0 15 0 20 ns 7
WE to Data Output Buffer Turn-
off Delay Time tWEZ 0 13 0 15 0 20 ns 7
Transition Time tT 1 50 1 50 1 50 ns 3
Refresh Period tREF 16 16 16 ms
RAS Precharge Time tRP 30 40 50 ns
RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns
RAS Pulse Width
(Fast Page Mode with EDO) tRASP 50 100,000 60 100,000 70 100,000 ns
RAS Hold Time tRSH 7 10 13 ns
RAS Hold Time referenced to OE t
ROH 7 10 13 ns
CAS Precharge Time
(Fast Page Mode with EDO) tCP 7 10 10 ns 15
CAS Pulse Width tCAS 7 10,000 10 10,000 13 10,000 ns
CAS Hold Time tCSH 35 40 45 ns
CAS to RAS Precharge Time tCRP 5 5 5 ns 13
RAS Hold Time from CAS Precharge tRHCP 30 35 40 ns 13
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MSM5118165F
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AC CHARACTERISTICS (2/2)
(VCC = 5V 10%, Ta = 0 to 70°C) Note1,2,3
MSM5118165
F-50
MSM5118165
F-60
MSM5118165
F-70
Parameter Symbol
Min. Max. Min. Max. Min. Max.
Unit Note
OE Hold Time from CAS
(DQ Disable) tCHO 5 5 5 ns
RAS to CAS Delay Time tRCD 11 37 14 45 14 50 ns 5
RAS to Column Address Delay Time tRAD 9 25 12 30 12 35 ns 6
Row Address Set-up Time tASR 0 0 0 ns
Row Address Hold Time tRAH 7 10 10 ns
Column Address Set-up Time tASC 0 0 0 ns 12
Column Address Hold Time tCAH 7 10 13 ns 12
Column Address to RAS Lead Time tRAL 25 30 35 ns
Read Command Set-up Time tRCS 0 0 0 ns 12
Read Command Hold Time tRCH 0 0 0 ns 9,12
Read Command Hold Time
referenced to RAS tRRH 0 0 0 ns 9
Write Command Set-up Time tWCS 0 0 0 ns 10,12
Write Command Hold Time tWCH 7 10 13 ns 12
Write Command Pulse Width tWP 7 10 10 ns
WE Pulse Width (DQ Disable) tWPE 7 10 10 ns
OE Command Hold Time tOEH 7 10 13 ns
OE Precharge Time tOEP 7 10 10 ns
OE Command Hold Time tOCH 7 10 10 ns
Write Command to RAS Lead Time tRWL 7 10 13 ns
Write Command to CAS Lead Time tCWL 7 10 13 ns 14
Data-in Set-up Time tDS 0 0 0 ns 11,12
Data-in Hold Time tDH 7 10 13 ns 11,12
OE to Data-in Delay Time tOED 13 15 20 ns
CAS to WE Delay Time tCWD 30 34 44 ns 10
Column Address to WE Delay Time tAWD 42 49 59 ns 10
RAS to WE Delay Time tRWD 67 79 94 ns 10
CAS Precharge WE Delay Time tCPWD 47 54 64 ns 10
CAS Active Delay Time from RAS
Precharge tRPC 5 5 5 ns 12
RAS to CAS Set-up Time
(CAS before RAS) tCSR 5 5 5 ns 12
RAS to CAS Hold Time
(CAS before RAS) tCHR 10 10 10 ns 13
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MSM5118165F
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Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 2ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT)
are measured between VIH and VIL.
4. -50 is measured with a load circuit equivalent to 2 TTL load and 50pF, and -60/-70 is measured with a
load circuit equivalent to 2 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
t
RCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit,
then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
t
RAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit,
then the access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the
open circuit condition and are not referenced to output voltage levels.
8. tCEZ, and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and
the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD
(Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify
write cycle and data out will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to
the WE leading edge in an OE control write cycle, or a read modify write cycle.
12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.
14. tCWL should be satisfied by both UCAS and LCAS.
15. tCP is determined by the time both UCAS and LCAS are high.
FEDD5118165F-02
MSM5118165F
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TIMING CHART
Read Cycle
Write Cycle (Early Write)
tCEZ
tCLZ
tCAC
tOE
A
t
A
SC
tRRH
tRAH t
A
SR
tRAD
tRAL
tCRP
tCAH
tCRP tRCD
tRC
tRAS
tRP
tCSH
tRSH
tCAS
tRAC
t
AA
tRCS
tROH
tRCH
tREZ
tOEZ
Row Column
Valid Data-out
O
p
en
R
AS VIH
VIL
C
AS VIH
VIL
Address VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VOH
VOL
“H” or “L”
tDS tDH
tWCS tWCH
tCWL
t
A
SR tRAH t
A
SC
tCRP
tRP
tRC
tRAS
tRWL
tCSH
tCRP tRCD tRSH
tCAS
tCAH
tRAD
tRAL
tWP
Valid Data-in
Row Column
R
AS VIH
VIL
C
AS VIH
VIL
Address VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VIH
VIL
“H” or “L”
O
p
en
FEDD5118165F-02
MSM5118165F
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Read Modify Write Cycle
tDS
tDH
tOEZ
tCLZ
tOED
t
AA
tOEH
tRWD
tCWD
tCWL
tRWL
tCAH
t
A
SC
t
A
SR tRAH
tRAD
tCRP tRCD tRSH
tCAS
tCRP
tCAC
Valid
Data-out
Row
tCSH
Column
tRAC
tOE
A
tRCS
t
A
WD
t
WP
tRWC
tRAS
tRP
Valid
Data-in
R
AS VIH
VIL
C
AS VIH
VIL
A
ddress VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VI/OH
VI/OL
“H” or “L”
FEDD5118165F-02
MSM5118165F
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Fast Page Mode Read Cycle (part-1)
Fast Page Mode Read Cycle (part-2)
tHPC
tRASP
tCSH
tRCD
t
AA
tOEP
tCHO tCAC
tOEP
tCAC
tCP
A
t
AA
tOE
A
t
AA
tRAC
tRRH
tOCH
tCAH
t
A
SC
tRAH
tRAD
tRCS
t
A
SR t
A
SC tCAH
tCP
tCAS tCAS
tCP
tCRP
tCLZ
tCAH
Valid
Data-out
Valid *
Data-out
Valid *
Data-out
Valid Data-out
tOE
A
tOE
A
tOEZ
tCAC
t
A
SC
tRP
tRHCP
tCAS
tDOH
tOEZ tREZ
Row Column Column Column
R
AS VIH
VIL
C
AS VIH
VIL
Address VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VOH
VOL
“H” or “L”* : Same Data,
tHPC
tCAS
tHPC
tCEZ
Valid
Data-out
tCAC
Valid Data-out
tDOH
tCAC
Valid
Data-out
tCP
A
t
AA
tRCH
tRCS
tOE
A
tRAC
t
AA
tRCS
tCRP
t
A
SR tCAH
t
A
SC
tRAH
tRAD
t
A
SC
tCP
t
A
SC
tCAH
tCP
tCAS
tRHCP
tCSH
tRCD
tCLZ
tCAH
t
AA
tWEZ
tCAC
tCAS
tRP
R
AS VIH
VIL
C
AS VIH
VIL
Address VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VOH
VOL
tRASP
tWPE
Row Column Column Column
“H” or “L”
tCRP
FEDD5118165F-02
MSM5118165F
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Fast Page Mode Write Cycle (Early Write)
Fast Page Mode Read Modify Write Cycle
tDH tDS
tDH
tDS
tDH
tDS
Valid
Data-in
t
WCH
t
WCS
tWCS
t
WCH
t
WCH
t
WCS
t
A
SC tCAH
t
A
SC tCAH
tRAD
t
A
SR t
A
SC
tRAH
tRCD
tCRP
tCAS tCAS
tRSH tCP
tCAS
tRP
tHPC
Valid
Data-in
Valid
Data-in
tCSH
tCAH
tCP
tHPC
tRASP
Row Column Column Column
“H” or “L”
R
AS VIH
VIL
C
AS VIH
VIL
A
ddress VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VIH
VIL
tDH
tOE
A
t
AA
tOED
tDH
tOEZ
tOEH
tCAC
tOED
tOEZ
tOEH
t
A
WD t
A
WD
t
WP
tDS
t
AA
tDS
Column
tCWD
tRCS
tCAH
tHPRWC
tCP
A
tCWL
tCAH
t
A
SC
tCP tRWL
tRWD
tCWD
tRCD
tCRP
tRASP
tOE
A
tRCS
t
WP
tCPWD
Row Column
tRAC
tCAC
Valid
Data
-
in
Valid
Data
-
out
tCLZ
Valid
Data
-
in
Valid
Dat
a
-
out
tCLZ
tRAH
t
A
SR
tRAD
t
A
SC
R
AS VIH
VIL
C
AS VIH
VIL
A
ddress VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VI/OH
VI/OL
“H” or “L”
FEDD5118165F-02
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RAS-only Refresh Cycle
CAS before RAS Refresh Cycle
t
A
SR tRAH
tCRP tRPC
tRP
tRAS
tRC
tCEZ
R
AS VIH
VIL
C
AS VIH
VIL
VIH
VIL
A
ddress
VOH
VOL
DQ
“H” or “L”
Note:
W
E
,
O
E= “H” or “L”
Row
O
p
en
tRPC
tRP
tRC
tRAS
tCHR
tCEZ
tCSR
tRP
tCP
tRPC
R
AS VIH
VIL
C
AS VIH
VIL
VOH
VOL
DQ O
p
en
FEDD5118165F-02
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Hidden Refresh Read Cycle
Hidden Refresh Write Cycle
tREZ
tRAC
tCLZ
tOEZ
tROH
tOE
A
tCAC tRRH
t
AA
tRAL
tRCS
tCAH
tRAH
t
A
SR t
A
SC
Column
tRAD
tRP
tRAS
tRC
tRP
tCHR
tRAS
tRSH
tRCD
tCRP
tRC
R
AS VIH
VIL
C
AS VIH
VIL
Address VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VOH
VOL O
p
en
Row
Valid Data-out
“H” or “L”
tCEZ
tDH
tDS
tWCH
tWCS
tRWL
tRAL
tRAD
tCAH
tRAH
t
A
SR t
A
SC
tRCD
tCRP tRSH tRP
tCHR
tRP
tRAS
tRC tRC
tRAS
tWP
R
AS VIH
VIL
C
AS VIH
VIL
Address VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VIH
VIL
Row Column
Valid Data-in
“H” or “L”
FEDD5118165F-02
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REVISION HISTORY
Page
Document
No. Date Previous
Edition
Current
Edition
Description
FEDD5118165F-01 Aug.15, 2000 – –
1s
t
edition
(
revised PIN CAPASITANCE format
)
– – Changed Company-name and LOGO
1 1 Corrected errata
FEDD5118165F-02 Mar.23, 2010
3 3 Deleted BLOCK DIAGRAM
FEDD5118165F-02
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