The MAX5650/MAX5651/MAX5652 parallel-input, volt-
age-output, 16-bit, digital-to-analog converters (DACs)
provide monotonic 16-bit output voltage over the full
extended operating temperature range. The MAX5650/
MAX5651 include an internal precision low drift
(10ppm/°C) bandgap voltage reference, while the
MAX5652 requires an external reference. The MAX5650
operates from a +5V single supply and has a +4.096V
internal reference. The MAX5651 operates from either a
+3V or +5V single supply and has a +2.048V internal
reference. The MAX5652 operates from either a +3V or
+5V single supply and accepts an input reference voltage
between +2V and AVDD. TheMAX5650/MAX5651/
MAX5652 parallel inputs are double buffered and con-
figurable as a single 16-bit wide input or a 2-byte input.
The MAX5650/MAX5651/MAX5652 unbuffered DAC
voltage output ranges from 0 to VREF.
The MAX5650/MAX5651/MAX5652 feature an active-low
hardware clear input (CLR) that clears the registers and
the output to zero-scale (0000 hex) or midscale (8000
hex), depending on the state of the MID/ZERO input.
These devices include matched scaling resistors for use
with a precision external op amp (such as the MAX400)
to generate a bipolar output-voltage swing.
The MAX5650/MAX5651/MAX5652 are available in a 32-
pin, 5mm x 5mm TQFN package and are guaranteed
over the extended temperature range (-40°C to +85°C).
For 14-bit, pin-compatible versions of the MAX5650/
MAX5651/MAX5652, refer to the MAX5653/MAX5654/
MAX5655 datasheet.
For 12-bit, pin-compatible versions of the MAX5650/
MAX5651/MAX5652, refer to the MAX5656/MAX5657/
MAX5658 datasheet.
Applications
Automatic Test Equipment Servo Loops
Process Control Waveform Generators
Digital Calibration Motor Control
Actuator Control
Features
♦16-Bit Resolution
♦Parallel 16-Bit or 2-Byte Double Buffered Interface
♦Guaranteed Monotonic
♦Maximum INL: ±4 LSB
♦Fast 2µs Settling Time
♦Clear Input (CLR) Sets Output to Zero-Scale or
Midscale
♦Integrated Precision Resistors for Bipolar
Operation
♦Integrated Precision Bandgap Reference:
+4.096V (MAX5650)
+2.048V (MAX5651)
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
________________________________________________________________ Maxim Integrated Products 1
MAX5650
MAX5651
MAX5652
R
R
GND
OUT
INB
MTAP
INA
D15
D8
D7
D0
CLR
LDAC
CSLSB
WR
CSMSB
8-BIT MSB
INPUT
REGISTER
16-BIT DAC
REGISTER
8-BIT LSB
INPUT
REGISTER 16-BIT DAC
DGND AGND
REF
DV
DD
BANDGAP
REFERENCE
(MAX5650/
MAX5651
ONLY)
AV
DD
MID/ZERO
POWER-ON
RESET
Functional Diagram
General Description
19-3936; Rev 0; 2/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
Ordering Information
Note: All devices specified over the -40°C to +85°C
temperature range.
*EP = Exposed paddle. Connect to AGND or leave unconnected.
**Future product—contact factory for availability.
PART PIN-PACKAGE
PACKAGE
CODE
MAX5650ETJ
32 TQFN-EP* (5mm x 5mm)
T3255-4
MAX5651ETJ**
32 TQFN-EP* (5mm x 5mm)
T3255-4
MAX5652ETJ**
32 TQFN-EP* (5mm x 5mm)
T3255-4
Selector Guide
PART SUPPLY
VOLTAGE (V)
R EF ER EN C E
( V)
INL
(LSB, max)
MAX5650ETJ
+4.75 to +5.25 Inter nal , + 4.096
± 4
MAX5651ETJ
+2.7 to +5.25 Inter nal , + 2.048
—
MAX5652ETJ
+2.7 to +5.25
E xter nal —
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to DVDD……………………………………………...........±6V
AVDD to AGND, GND…………………………...…… -0.3V to +6V
DVDD to DGND…..…………………………………… -0.3V to +6V
DGND to GND……………………………………… -0.3V to +0.3V
DGND, GND to AGND…………………………….. -0.3V to +0.3V
D0–D15, CSLSB, CSMSB, WR, LDAC, CLR, MID/ZERO,
to DGND…………………………………-0.3V to (DVDD + 0.3V)
REF to AGND……………………………….-0.3V to (AVDD + 0.3V)
OUT, MTAP, INA to AGND, GND...........................-0.3V to AVDD
INB to AGND ..……………………………………………-6V to +6V
INB to MTAP………………………………………………-6V to +6V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA= +70°C)
32-Pin TQFN (derate 20.8mW/°C above +70°C)….2758.6mW
Operating Temperature Range …………………..-40°C to +85°C
Storage Temperature Range…………………….-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS—MAX5650
(AVDD = DVDD = +4.75V to +5.25V, AGND = DGND = GND = 0V, VREF = internal, RL= ∞, CL= 10pF, CREF = 1µF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution N 16 Bits
Differential Nonlinearity DNL Guaranteed monotonic ±0.5 ±1 LSB
Integral Nonlinearity INL ±4 LSB
Zero-Code Offset Error ZSE ±80 µV
Zero-Code Temperature
Coefficient ZSTC (Note 2) ±0.05 ppmFS/
°C
Gain Error (Note 3) ±10 LSB
Gain-Error Temperature
Coefficient (Note 2) ±0.1 ppm/°C
DAC Output Resistance ROUT (Note 4) 6.2 kΩ
Bipolar Resistor Ratio RINB / RINA 1Ω/Ω
Bipolar Resistor Ratio Error ±0.05 %
Bipolar Resistor Ratio
Temperature Coefficient (Note 2) ±0.5 ppm/°C
Bipolar Resistor Value RINB and RINA (Note 4) 12.4 kΩ
VOLTAGE REFERENCE (RREF = 10kΩ, CREF(MIN) = 1µF)
Voltage Reference VREF TA = +25°C 4.081 4.106 4.111 V
Reference Voltage Temperature
Coefficient TCVREF (Note 2) 10 ppm/°C
Reference Load Regulation VOUT /
IOUT 0 ≤ IOUT ≤ VREF / 10kΩ0.1 0.6 µV/µA
Short-Circuit Current 6mA
Reference Load IREF 400 µA
Reference Power-Up Time Settle to 0.5 LSB 4 ms
Power-Supply Rejection Ratio PSRR AVDD = DVDD = 4.75V to 5.25V (FS code) 0.5 mV/V
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—MAX5650 (continued)
(AVDD = DVDD = +4.75V to +5.25V, AGND = DGND = GND = 0V, VREF = internal, RL= ∞, CL= 10pF, CREF = 1µF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE—ANALOG SECTION
Output Settling Time 7F60H to 80A0H or 80A0H to 7F60H to 0.5 LS B2 µs
DAC Glitch Impulse Major carry transition 10 nV·s
Digital Feedthrough Code = 0000 hex; CSLSB = CSMSB =
DVDD, D0–D15 transition from 0 to DVDD 3 nV·s
DYNAMIC PERFORMANCE—VOLTAGE REFERENCE SECTION
Frequency = 0.1Hz to 10Hz 15 µVP-P
Noise Voltage (Note 6) Frequency = 10Hz to 1kHz 12 µVRMS
VREF Glitch Impulse For zero-scale to full-scale or full-scale to
zero-scale transition 10 nV·s
STATIC PERFORMANCE—DIGITAL INPUTS
Input High Voltage VIH (Note 8) 2.4 V
Input Low Voltage VIL (Note 8) 0.8 V
Input Current IIN ±1 µA
Input Capacitance CIN 5pF
POWER SUPPLY
Analog Supply Range AVDD 4.75 5.25 V
Digital Supply Range DVDD (Note 9) AVDD -
0.3
AVDD
+ 0.3 V
Positive Supply Current IAVDD +
IDVDD Al l d i g i tal i np uts at D V
D D
or 0V , AV
D D = D V
D D 2mA
TIMING CHARACTERISTICS (Figure 4)
CSMSB and CSLSB Pulse Width tCS 40 ns
WR Pulse Width tWR 40 ns
CSMSB or CSLSB to WR
Setup Time tCWS 0ns
CSMSB or CSLSB to WR
Hold Time tCWH 0ns
Data Valid to WR Setup Time tDWS 40 ns
Data Valid to WR Hold Time tDWH 0ns
LDAC Pulse Width tLDAC 40 ns
CLR Pulse Width tCLR 40 ns
Note 1: 100% production tested at TA= +25°C and TA= +85°C. Guaranteed by design at TA= -40°C.
Note 2: Temperature coefficient is determined by the box method in which the maximum change over the temperature range is
divided by ∆T.
Note 3: Gain error is measured at the full-scale code and is calculated with respect to the reference voltage (REF).
Note 4: Resistor tolerance is typically ±20%.
Note 5: Guaranteed by design, not production tested.
Note 6: Noise is measured at the reference output.
Note 7: Min/max range guaranteed by gain-error test. Operation outside min/max limits results in degraded performance.
Note 8: The devices draw higher supply current when the digital inputs are driven between (DVDD - 0.5V) and (DGND + 0.5V).
See Digital Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.
Note 9: For optimal performance AVDD = DVDD.
TOTAL SUPPLY CURRENT
vs. TEMPERATURE (MAX5650)
MAX5650 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
0.8
0.9
1.0
1.1
1.2
0.7
-40 85
CODE = FFFF
0.00001
0.001
0.0001
0.1
0.01
10
1
100
0231 456
DIGITAL SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE (MAX5650)
MAX5650 toc08
DIGITAL INPUT VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
ALL DIGITAL INPUTS
CONNECTED TOGETHER
AVDD = DVDD = 5.25V
400ns/div
FULL-SCALE
STEP RESPONSE (MAX5650)
D1
5V/div
0
MAX5650 toc09
VOUT
2V/div
0
CODE FFFF TO OOOO STEP
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
4 _______________________________________________________________________________________
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5650 toc01
TEMPERATURE (°C)
INL (LSB)
603510-15
-0.5
0
0.5
1.0
-1.0
-40 85
+INL
-INL
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE (MAX5650)
MAX5650 toc02
TEMPERATURE (°C)
OFFSET ERROR (µV)
603510-15
5
10
15
20
25
0
-40 85
GAIN ERROR
vs. TEMPERATURE (MAX5650)
MAX5650 toc03
TEMPERATURE (°C)
FS GAIN ERROR (LSB)
603510-15
-2
-1
0
1
2
-3
-40 85
REFERENCE VOLTAGE
vs. TEMPERATURE (MAX5650)
MAX5650 toc04
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
603510-15
4.096
4.097
4.098
4.099
4.100
4.095
-40 85
10µV/div
REFERENCE-VOLTAGE NOISE (MAX5650)
MAX5650 toc05
1s/div
f = 0.1Hz TO 10Hz
Typical Operating Characteristics
(AVDD = DVDD = +5V, AGND = DGND = GND = 0V, RL= ∞, CL= 10pF, CREF = 1µF for the MAX5650/MAX5651, TA= +25°C, unless
otherwise noted.)
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
_______________________________________________________________________________________ 5
400ns/div
FULL-SCALE
STEP RESPONSE (MAX5650)
D1
5V/div
0V
0V
MAX5650 toc10
VOUT
2V/div
CODE 0000 TO FFFF STEP
1µs/div
MAJOR-CARRY GLITCH
D15
5V/div
0V
0V
MAX5650 toc11
VOUT
20mV/div
CODE 7FFF TO 8000 STEP
1µs/div
MAJOR-CARRY GLITCH
D15
5V/div
0V
0V
MAX5650 toc12
VOUT
20mV/div
CODE 8000 TO 7FFF STEP
VOUT
20mV/div
D1
5V/div
DIGITAL FEEDTHROUGH (MAX5650)
MAX5650 toc13
1µs/div
FS TRANSITION
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, AGND = DGND = GND = 0V, RL= ∞, CL= 10pF, CREF = 1µF for the MAX5650/MAX5651, TA= +25°C, unless
otherwise noted.)
400ns/div
SMALL-SIGNAL
SETTLING TIME
0V
MAX5650 toc14
VOUT
10mV/div
CODE 0000 TO 00A2 STEP
400ns/div
SMALL-SIGNAL
SETTLING TIME
0V
MAX5650 toc15
VOUT
10mV/div
CODE 00A2 TO 0000 STEP
REFERENCE BANDWIDTH (MAX5652)
MAX5650 toc16
FREQUENCY (kHz)
VOUT/VREF (dB)
1000
-25
-30
-35
-40
-45
5
0
-5
-10
-15
-20
-50
10,00010 100
VREF = 3.5V + 0.5VP-P
CODE = FFFFh
REFERENCE FEEDTHROUGH (MAX5652)
MAX5650 toc17
FREQUENCY (kHz)
VOUT/VREF (dB)
10 100 1000
-60
-80
-100
0
-20
-40
-120
10,0000.01 0.1 1
VREF = 3.5V + 0.5VP-P
CODE = 0000h
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
6 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 D0 Data Input Bit 0 (LSB)
2 D1 Data Input Bit 1
3 D2 Data Input Bit 2
4 D3 Data Input Bit 3
5 D4 Data Input Bit 4
6 D5 Data Input Bit 5
7 D6 Data Input Bit 6
8 D7 Data Input Bit 7
9 D8 Data Input Bit 8
10 D9 Data Input Bit 9
11 D10 Data Input Bit 10
12 D11 Data Input Bit 11
13 D12 Data Input Bit 12
14 D13 Data Input Bit 13
15 D14 Data Input Bit 14
16 D15 Data Input Bit 15 (MSB)
17 DGND Digital Ground
18 DVDD Digital Supply. Bypass DVDD to DGND with a 0.1µF capacitor as close to the device as possible.
19 CSLSB Lower 8-Bit Active-Low Chip Select. When CSLSB is driven low the data inputs D0–D7 are loaded to
the input and DAC registers depending on the state of WR and LDAC (see Table 1).
20 CSMSB Upper 8-Bit Active-Low Chip Select. When CSMSB is driven low the data inputs D8–D15 are loaded
to the input and DAC registers depending on the state of WR and LDAC (see Table 1).
21 WR
Active-Low Write Input. While chip select (CSLSB and/or CSMSB) is low, the data on D0–D7 and/or
D8–D15 is presented to the input register when WR is low. A rising edge on WR then latches the data
to the input register (see Table 1). Hold WR low to make the input register transparent.
22 LDAC
Asynchronous Active-Low Load DAC Input. When LDAC is low, the data in the input register is
presented to the DAC register. A rising edge on LDAC then latches the data to the DAC register (see
Table 1). Hold WR and LDAC low to perform a write-through operation.
23 CLR
Asynchronous Active-Low Clear DAC Input. Pull CLR low to clear the input and DAC registers and
set the DAC output to midscale (8000 hex), if MID/ZERO is high, or zero scale (0000 hex), if
MID/ZERO is low.
24 MID/ZERO Midscale/Zero-Scale Clear Output Value Select. Pull MID/ZERO low for zero-scale clear output (0000
hex) or high for midscale clear output (8000 hex).
25 MTAP Internal Scaling Resistor Midpoint Tap. Connect to the inverting input of an external op amp.
26 INB Internal Resistor Input B. Free end of internal resistor (RINB). Connect to the output of an external
output buffer for bipolar operation.
27 AVDD Analog Supply. Bypass AVDD to AGND with a 0.1µF capacitor as close to the device as possible.
28 AGND Analog Ground
29 INA Internal Resistor Input A. Free end of internal resistor (RINA). Connect to REF for bipolar operation.
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
_______________________________________________________________________________________ 7
Pin Description (continued)
Typical Application Circuits
PIN NAME FUNCTION
Internal Reference Voltage Output (MAX5650/MAX5651). Connect a 1µF < CREF < 47µF between
REF and AGND as close to the device as possible. The internal reference voltage of the MAX5650 is
+4.096V and +2.048V for the MAX5651.
30 REF
External Reference Voltage Input (MAX5652). Connect to an external voltage reference source
between +2V and AVDD.
31 OUT DAC Output
32 GND DAC Ground
— EP Exposed paddle. Connect to AGND or leave unconnected.
MAX5650
MAX5651
MAX5652
8-BIT MSB
INPUT
REGISTER
16-BIT DAC
REGISTER
8-BIT LSB
INPUT
REGISTER
16-BIT DAC
R
R
D15
D8
D7
D0
DGND AGND
GND
OUT
0 TO VREF
INB
MTAP
INA
REFDVDD
8-BIT BUS
CONTROL
LINES
µC
BANDGAP
REFERENCE
(MAX5650/
MAX5651
ONLY)
CLR
LDAC
CSLSB
WR
CSMSB
AVDD
MID/ZERO
POWER-ON
RESET
Figure 1. Typical Application Circuit for µC Byte-Wide Interface
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
8 _______________________________________________________________________________________
MAX5650
MAX5651
MAX5652
8-BIT MSB
INPUT
REGISTER
16-BIT DAC
REGISTER
8-BIT LSB
INPUT
REGISTER
16-BIT DAC
R
R
D15
D8
D7
D0
DGND AGND
GND
0 TO VREF
0 TO VREF
INB
+12V
OUT
MTAP
INA
REF
DVDD
16-BIT BUS
CONTROL
LINES
ASIC
BANDGAP
REFERENCE
(MAX5650/
MAX5651
ONLY)
ACTUATOR
DRIVE
CIRCUIT
CLR
LDAC
CSLSB
WR
CSMSB
AVDD
MID/ZERO
POWER-ON
RESET
Figure 2. Typical Application Circuit for Unipolar Configuration
Typical Application Circuits (continued)
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
_______________________________________________________________________________________ 9
MAX5650
MAX5651
MAX5652
8-BIT MSB
INPUT
REGISTER
16-BIT DAC
REGISTER
8-BIT LSB
INPUT
REGISTER
16-BIT DAC
R
R
D15
D8
D7
D0
DGND AGND
GND
+/- VREF
0 TO VREF
INB
+5V
-5V
OUT
MTAP
INAREF
DVDD
BANDGAP
REFERENCE
(MAX5650/
MAX5651 ONLY)
CLR
LDAC
CSLSB
WR
CSMSB
AVDD
MID/ZERO
POWER-ON
RESET
8-BIT BUS
CONTROL
LINES
FPGA
Figure 3. Typical Application Circuit for Bipolar Configuration
Typical Application Circuits (continued)
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
10 ______________________________________________________________________________________
The MAX5650/MAX5651/MAX5652 parallel-input, volt-
age-output DACs offer full 16-bit performance with less
than ±4 LSB integral nonlinearity and less than ±1 LSB
differential nonlinearity, ensuring monotonic perfor-
mance over the full operating temperature range. The
DAC is composed of an inverted R2R ladder with the
unbuffered output available directly at OUT, allowing
16-bit performance from the reference voltage to the
DAC ground (GND). The parallel inputs are double-
buffered and configurable as a single 16-bit wide input
or a 2-byte input. The MAX5650/MAX5651 include inter-
nal precision low-drift (10ppm/°C) bandgap voltage ref-
erences of +4.096V and +2.048V, respectively. The
MAX5652 accepts an external reference voltage
between +2V and AVDD. The MAX5650 operates with a
supply voltage range of +4.75V to +5.25V, while the
MAX5651/MAX5652 operate with a supply voltage
range of +2.7V to +5.25V.
Voltage Reference
The MAX5650/MAX5651 provide a 10ppm/°C (typ)
internal precision bandgap voltage reference with a
load regulation specification of less than 0.6µV/µA
(maximum) over the entire operating temperature
range. The reference voltage for the MAX5650 is
+4.096V, while the reference voltage for the MAX5651
is +2.048V. Connect a capacitor ranging between 1µF
and 47µF from REF to ground as close to the device as
possible. Use a low-ESR ceramic capacitor such as the
GRM series from Murata.
The MAX5652 accepts an external reference with a
voltage range extending from +2V to AVDD. The output
voltage of the DAC is determined as follows:
where N is the numeric value of the DAC’s binary input
code (0 to 65535) and VREF is the reference voltage.
At a full-scale transition, the instantaneous charge
demand from the external reference is about 550pC.
For a reference with a 1µF load capacitor, the charge
demand causes an instantaneous reference voltage
drop of 550µV. A 10µF load capacitor causes a voltage
drop of 55µV. This glitch recovers in a time inversely
proportional to the bandwidth of the voltage reference,
which should be sufficiently fast to recover before the
next DAC transition to avoid accumulation of the glitch
energy and a shift in the average reference voltage. For
a +4.096V reference with 1µF bypass capacitor, it
takes three time constants to recover to 0.5 LSB accu-
racy. Therefore, a 96kHz bandwidth reference recovers
in 5µs while a 960kHz bandwidth reference recovers in
0.5µs.
For further voltage-reference selection assistance, visit
www.maxim-ic.com/appnotes.cfm/appnote_number/754.
CSMSB
WR
CSLSB
LDAC
D0–D15 VALID
DATA
VALID
DATA
tCWS
tWR
tWR
tCS
tCS
tCWS
tCWH
tCWH
tLDAC
tDWS tDWS
tDWH tDWH
Figure 4. Timing Diagram
Detailed Description
VVxN
OUT REF
= / 65536
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
______________________________________________________________________________________ 11
Digital Interface
The MAX5650/MAX5651/MAX5652 accept a single 16-
bit wide input or an 8 plus 8-bit wide input. Data latches
or transfers directly to the DAC depending on the state
of the control inputs CLR, CSLSB, CSMSB, LDAC,
MID/ZERO, and WR. All digital inputs are compatible
with both TTL and CMOS logic.
The double buffered input consists of an input register
and a DAC register (see the Functional Diagram). Data
is loaded into the input register using CSLSB, CSMSB,
and WR. The input register is transparent when WR and
CSLSB and/or CSMSB are low. The rising edge of WR,
while CSLSB is low, latches the lower byte (D0–D7) into
the input register. The rising edge of WR, while CSMSB is
low, latches the upper byte (D8–D15) into the input regis-
ter. The sequence of loading the MSB and LSB does not
matter. See Figure 1 for byte-wide interface circuit.
The DAC register is transparent when LDAC is low. The
rising edge of LDAC latches data into the DAC register.
The DAC’s analog output reflects the data held in the
DAC register. Both the input register and DAC register
are transparent when CSLSB, CSMSB, WR, and LDAC
are driven low. In this case, any change at D0–D15 appears
at the output instantly. See Table 1 for the truth table.
Table 1. Truth Table
CLR CSLSB CSMSB WR LDAC FUNCTION
1 0 1 0 1 Loads least significant byte into the input register. DAC output remains unchanged.
1 0 1 1 Latches least significant byte into the input register. DAC output remains unchanged.
1 1 0 0 1 Loads most significant byte into the input register. DAC output remains unchanged.
11 0 1
Latches most significant byte into the input register. DAC output remains
unchanged.
1X X10
Transfers data from the input register into the DAC register and updates the DAC
output.
1X X1 Latches data from the input register into the DAC register. DAC output remains
unchanged.
11 000
Most significant input and DAC registers are transparent. DAC output updates
immediately with the most significant input data and least significant input register
data.
1 X X 1 1 No operation.
10 000
Both most significant and least significant input registers and DAC register are
transparent. DAC output updates immediately with the most significant and least
significant input data.
1 0 0 0 1 Loads all 16 bits into the input register. DAC output remains unchanged.
10 100
Least significant input and DAC registers are transparent. DAC output updates
immediately with the least significant input data and most significant register data.
11 1X0
Transfers data held in the input register to the DAC register and updates the DAC
output.
1 1 1 X 1 No operation.
0X XXX
Sets the input and DAC registers and DAC output to midscale (if MID/ZERO = 1) or
zero-scale (if MID/ZERO = 0).
0 = Low state.
1 = High state.
X = Don’t care.
= Rising edge.
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
12 ______________________________________________________________________________________
The MAX5650/MAX5651/MAX5652 provide an asyn-
chronous clear input (CLR). Asserting CLR resets the
input and DAC registers and DAC output to midscale if
the MID/ZERO input is high and to zero scale when
MID/ZERO is low.
Power-On Reset (POR)
The MAX5650/MAX5651/MAX5652 provide an internal
POR circuit. On power-up, the input and DAC registers
and DAC output are set to 0000 hex if MID/ZERO is low
or 8000 hex if MID/ZERO is high. Wait 10µs after
power-up before pulling CSMSB or CSLSB low.
Internal Scaling Resistors
The MAX5650/MAX5651/MAX5652 include two internal
scaling resistors of 12.4kΩ(typ) each that are matched
to 0.05% or better. Use these resistors with a precision
external op amp to generate a bipolar output swing
(see the Bipolar Operation section). The free ends of
these resistors are accessible at INA and INB while the
midpoint is accessible at MTAP. Connect INB to the
output of the op amp and INA to REF for bipolar opera-
tion. Negative voltages are only allowed at INB (see the
Absolute Maximum Ratings section).
Applications Information
Unipolar Buffered/Unbuffered Operation
Unbuffered operation reduces power consumption as
well as the offset error contributed by the external out-
put buffer (see Figure 1). The R2R DAC output is avail-
able directly at OUT, allowing 16-bit performance from
+VREF to GND without degradation at zero scale.
The typical application circuit (Figure 2) shows the
MAX5650/MAX5651/MAX5652 configured for a
buffered unipolar voltage-output operation. Use the
integrated precision matched resisters for op-amp
input impedance matching. Table 2 shows digital
codes and corresponding output voltages for unipolar
buffered or unbuffered operation.
Bipolar Operation
For bipolar voltage-output operation, use an external op
amp (such as the MAX400) in conjunction with the
internal scaling resistors (see Figure 3). Connect the
free end of the internal resistor (INB) to the output of the
external op amp and the free end of the other resistor
(INA) to REF. Connect the midpoint of the resistors to
the inverting input of the op amp. Connect the output of
the DAC to the noninverting input of the external op
amp. The resulting transfer function is as follows:
where D is the decimal value of the DACs binary input
code. Table 3 shows digital codes and corresponding
output voltages for bipolar operation.
Power-Supply and Layout Considerations
Careful PC board layout is important for optimal system
performance. Wire-wrapped boards, sockets, and
breadboards are not recommended. Keep analog and
digital signals separate to reduce noise injection and
digital feedthrough. Connect AGND and DGND to the
highest quality ground available. Star-connect all
ground return paths back to AGND or use a multilayer
board with a low-inductance ground plane. Connect
analog and digital ground planes together at a low-
impedance power-supply source. For the MAX5652,
keep the trace between the reference source to the ref-
erence input short and low impedance. Bypass each
supply with a 0.1µF capacitor as close as possible to
the IC for optimal 16-bit performance.
Chip Information
PROCESS: BiCMOS
Table 2. Unipolar Code Table
Table 3. Bipolar Code Table
VVD
OUT REF
=− [( / , ) ]2 65 536 1
DAC LATCH CONTENTS
MSB LSB ANALOG OUTPUT, VOUT
1111 1111 1111 1111 VREF x (65,535 / 65,536)
1000 0000 0000 0000 VREF x (32,768 / 65,536)
= 0.5VREF
0000 0000 0000 0001 VREF x (1 / 65,536)
0000 0000 0000 0000 0V
DAC LATCH CONTENTS
MSB LSB ANALOG OUTPUT, VOUT
1111 1111 1111 1111 +VREF x (32,767 / 32,768)
1000 0000 0000 0001 +VREF x (1 / 32,768)
1000 0000 0000 0000 0V
0111 1111 1111 1111 -VREF (1 / 32,768)
0000 0000 0000 0000 -VREF x (32,768 / 32,768)
= -VREF
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
______________________________________________________________________________________ 13
Pin Configuration
MAX5650
MAX5651
MAX5652
TQFN
5mm x 5mm
+
TOP VIEW
29
30
28
27
12
11
13
D1
D3
D4
D5
D6
14
D0
CLR
WR
CSMSB
MID/ZERO
CSLSB
DVDD
12
AGND
4567
2324 22 20 19 18
INA
REF
D13
D12
D11
D10
D2 LDAC
3
21
31 10
OUT D9
32 9
GND D8
AVDD
26 15 D14
INB
25 16 D15
D7 DGND
8
17
MTAP
MAX5650/MAX5651/MAX5652
16-Bit, Parallel-Input, Voltage-Output DACs
with Internal Reference
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Inc.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Inc.
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45°
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
L
L
DETAIL B
L
L1
e
AAAAA
MARKING
I
12
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
L
e/2
COMMON DIMENSIONS
MAX.
EXPOSED PAD VARIATIONS
D2
NOM.MIN. MIN.
E2
NOM. MAX.
NE
ND
PKG.
CODES
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR
T2855-3 AND T2855-6.
NOTES:
SYMBOL
PKG.
N
L1
e
E
D
b
A3
A
A1
k
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
JEDEC
0.70 0.800.75
4.90
4.90
0.25
0.25
0
--
4
WHHB
4
16
0.350.30 5.10
5.105.00
0.80 BSC.
5.00
0.05
0.20 REF.
0.02
MIN. MAX.NOM.
16L 5x5
L0.30 0.500.40
------
WHHC
20
5
5
5.00
5.00
0.30
0.55
0.65 BSC.
0.45
0.25
4.90
4.90
0.25
0.65
--
5.10
5.10
0.35
20L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-1
28
7
7
5.00
5.00
0.25
0.55
0.50 BSC.
0.45
0.25
4.90
4.90
0.20
0.65
--
5.10
5.10
0.30
28L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-2
32
8
8
5.00
5.00
0.40
0.50 BSC.
0.30
0.25
4.90
4.90
0.50
--
5.10
5.10
32L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
0.20 0.25 0.30
DOWN
BONDS
ALLOWED
YES3.103.00 3.203.103.00 3.20T2055-3 3.103.00 3.203.103.00 3.20
T2055-4
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-7 2.60 2.70 2.80 2.60 2.70 2.80
3.20
3.00 3.10T3255-3 3 3.203.00 3.10
3.203.00 3.10T3255-4 3 3.203.00 3.10
NO
NO
NO
NO
YES
YES
YES
YES
3.203.00T1655-3 3.10 3.00 3.10 3.20 NO
NO3.203.103.003.10T1655N-1 3.00 3.20
3.353.15T2055-5 3.25 3.15 3.25 3.35 YES
3.35
3.15
T2855N-1 3.25 3.15 3.25 3.35 NO
3.353.15T2855-8 3.25 3.15 3.25 3.35 YES
3.203.10T3255N-1 3.00 NO
3.203.103.00
L
0.40
0.40
**
**
**
**
**
**
**
**
**
**
**
**
**
** SEE COMMON DIMENSIONS TABLE
±0.15
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
I
22
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
3.30T4055-1 3.20 3.40 3.20 3.30 3.40 ** YES
0.050 0.02
0.600.40 0.50
10
-----
0.30 40
10
0.40 0.50
5.10
4.90 5.00
0.25 0.35 0.45
0.40 BSC.
0.15
4.90 0.250.20
5.00 5.10
0.20 REF.
0.70
MIN.
0.75 0.80
NOM.
40L 5x5
MAX.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
T1655-2 ** YES3.203.103.003.103.00 3.20
T3255-5 YES3.003.103.00 3.20 3.203.10 **
exceptions
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)