1997 Microchip Technology Inc. DS30390E-page 1
PIC16C7X
8-Bit CMOS Microcontrollers with A/D Converter
Devices included in this data sheet:
PIC16C7X Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14 words of Program Memory,
up to 368 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• PIC16C72 • PIC16C74A
• PIC16C73 • PIC16C76
• PIC16C73A • PIC16C77
• PIC16C74
• Wide operating voltage range: 2.5V to 6.0V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
•
< 2 mA @ 5V, 4 MHz
•
15
µ
A typical @ 3V, 32 kHz
•
< 1
µ
A typical standby current
PIC16C7X Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module(s)
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM max. resolution is 10-bit
• 8-bit multichannel analog-to-digital converter
• Synchronous Serial Port (SSP) with
SPI
and I
2
C
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls
• Brown-out detection circuitry for
Brown-out Reset (BOR)
PIC16C7X Features 72 73 73A 74 74A 76 77
Program Memory (EPROM) x 14 2K 4K 4K 4K 4K 8K 8K
Data Memory (Bytes) x 8 128 192 192 192 192 368 368
I/O Pins 22 22 22 33 33 22 33
Parallel Slave Port — — — Yes Yes — Yes
Capture/Compare/PWM Modules 1 222222
Timer Modules 3 333333
A/D Channels 5 558858
Serial Communication SPI/I
2
C SPI/I
2
C,
USART SPI/I
2
C,
USART SPI/I
2
C,
USART SPI/I
2
C,
USART SPI/I
2
C,
USART SPI/I
2
C,
USART
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes — Yes Yes Yes
Interrupt Sources 8 11 11 12 12 11 12
PIC16C7X
DS30390E-page 2
1997 Microchip Technology Inc.
Pin Diagrams
PIC16C72
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, Windowed Side Brazed Ceramic
PIC16C72
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SSOP
PIC16C73
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIC16C73A
SDIP, SOIC, Windowed Side Brazed Ceramic
PIC16C76
PDIP, Windowed CERDIP
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16C74
PIC16C74A
PIC16C77
1997 Microchip Technology Inc. DS30390E-page 3
PIC16C7X
Pin Diagrams (Cont.’d)
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
22
21
20
19
18
17
16
15
14
13
12
PIC16C74
MQFP
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1 6
5
4
3
2
1
44
43
42
41
40
28
27
26
25
24
23
22
21
20
19
18
PIC16C74
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC 44
43
42
41
40
39
38
37
36
35
34
22
21
20
19
18
17
16
15
14
13
12
MQFP
PLCC
PIC16C74A PIC16C74A
TQFP
PIC16C77
PIC16C77
RC1/T1OSI/CCP2
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC
PIC16C7X
DS30390E-page 4
1997 Microchip Technology Inc.
Table of Contents
1.0 General Description....................................................................................................................................................................... 5
2.0 PIC16C7X Device Varieties........................................................................................................................................................... 7
3.0 Architectural Overview................................................................................................................................................................... 9
4.0 Memory Organization................................................................................................................................................................... 19
5.0 I/O Ports....................................................................................................................................................................................... 43
6.0 Overview of Timer Modules......................................................................................................................................................... 57
7.0 Timer0 Module............................................................................................................................................................................. 59
8.0 Timer1 Module............................................................................................................................................................................. 65
9.0 Timer2 Module............................................................................................................................................................................. 69
10.0 Capture/Compare/PWM Module(s).............................................................................................................................................. 71
11.0 Synchronous Serial Port (SSP) Module....................................................................................................................................... 77
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ...................................................................................... 99
13.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117
14.0 Special Features of the CPU ..................................................................................................................................................... 129
15.0 Instruction Set Summary............................................................................................................................................................ 147
16.0 Development Support................................................................................................................................................................ 163
17.0 Electrical Characteristics for PIC16C72..................................................................................................................................... 167
18.0 Electrical Characteristics for PIC16C73/74................................................................................................................................ 183
19.0 Electrical Characteristics for PIC16C73A/74A........................................................................................................................... 201
20.0 Electrical Characteristics for PIC16C76/77................................................................................................................................ 219
21.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 241
22.0 Packaging Information............................................................................................................................................................... 251
Appendix A: ................................................................................................................................................................................... 263
Appendix B: Compatibility............................................................................................................................................................. 263
Appendix C: What’s New............................................................................................................................................................... 264
Appendix D: What’s Changed....................................................................................................................................................... 264
Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 265
Pin Compatibility ................................................................................................................................................................................ 271
Index .................................................................................................................................................................................................. 273
List of Examples................................................................................................................................................................................. 279
List of Figures..................................................................................................................................................................................... 280
List of Tables...................................................................................................................................................................................... 283
Reader Response.............................................................................................................................................................................. 286
PIC16C7X Product Identification System........................................................................................................................................... 287
F or register and module descriptions in this data sheet, de vice legends sho w which devices apply to those sections. As
an example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and
PIC16C74A devices.
Applicable Devices
72 73 73A 74 74A 76 77
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
1997 Microchip Technology Inc. DS30390E-page 5
PIC16C7X
1.0 GENERAL DESCRIPTION
The PIC16C7X is a family of
low-cost, high-perfor-
mance, CMOS, fully-static, 8-bit microcontrollers with
integrated analog-to-digital (A/D) converters, in the
PIC16CXX mid-range family.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller f am-
ily has enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches which require two
cycles. A total of 35 instructions (reduced instruction
set) are av ailable . Additionally, a large register set gives
some of the architectural innov ations used to achieve a
very high performance.
PIC16CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The
PIC16C72
has 128 bytes of RAM and 22 I/O pins.
In addition several peripheral features are available
including: three timer/counters, one Capture/Compare/
PWM module and one serial port. The Synchronous
Serial Por t can be configured as either a 3-wire Serial
Peripheral Interface (SPI) or the two-wire Inter-Inte-
grated Circuit (I
2
C) bus. Also a 5-channel high-speed
8-bit A/D is provided. The 8-bit resolution is ideally
suited for applications requiring low-cost analog inter-
face, e.g. thermostat control, pressure sensing, etc.
The
PIC16C73/73A
devices have 192 bytes of RAM,
while the
PIC16C76
has 368 by es of RAM. Each de vice
has 22 I/O pins. In addition, several peripheral features
are available including: three timer/counters, two Cap-
ture/Compare/PWM modules and two serial ports. The
Synchronous Serial Por t can be configured as either a
3-wire Serial Peripheral Interface (SPI) or the two-wire
Inter-Integrated Circuit (I
2
C) bus. The Universal Syn-
chronous Asynchronous Receiver Transmitter
(USART) is also known as the Serial Communications
Interface or SCI. Also a 5-channel high-speed 8-bit A/
D is provided.The 8-bit resolution is ideally suited for
applications requiring low-cost analog interface, e.g.
thermostat control, pressure sensing, etc.
The
PIC16C74/74A
devices have 192 bytes of RAM,
while the
PIC16C77
has 368 bytes of RAM. Each
device has 33 I/O pins. In addition several peripheral
features are available including: three timer/counters,
two Capture/Compare/PWM modules and two serial
por ts. The Synchronous Serial Por t can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integr ated Circuit (I
2
C) bus . The Uni-
versal Synchronous Asynchronous Receiver Transmit-
ter (USART) is also known as the Serial
Communications Interface or SCI. An 8-bit Parallel
Slave Port is provided. Also an 8-channel high-speed
8-bit A/D is provided. The 8-bit resolution is ideally
suited for applications requiring low-cost analog inter-
face, e.g. thermostat control, pressure sensing, etc.
The PIC16C7X family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are f our oscillator options, of which the single pin
RC oscillator provides a lo w-cost solution, the LP oscil-
lator minimizes power consumption, XT is a standard
crystal, and the HS is for High Speed crystals. The
SLEEP (power-down) feature provides a power saving
mode. The user can wake up the chip from SLEEP
through several external and internal interrupts and
resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against softw are lock-
up .
A UV erasable CERDIP packaged version is ideal for
code development while the cost-effective One-Time-
Programmable (OTP) version is suitable for production
in any volume.
The PIC16C7X f amily fits perfectly in applications r ang-
ing from security and remote sensors to appliance con-
trol and automotive. The EPROM technology makes
customization of application programs (transmitter
codes, motor speeds, receiver frequencies, etc.)
extremely fast and convenient. The small footprint
packages make this microcontroller series perfect for
all applications with space limitations. Low cost, low
power, high performance, ease of use and I/O fle xibility
make the PIC16C7X v ery versatile e v en in areas where
no microcontroller use has been considered before
(e.g. timer functions, serial communication, capture
and compare, PWM functions and coprocessor appli-
cations).
1.1 Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller fam-
ily will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendix A for
a detailed list of enhancements. Code written for the
PIC16C5X can be easily ported to the PIC16CXX fam-
ily of devices (Appendix B).
1.2 Development Support
PIC16C7X devices are supported by the complete line
of Microchip Development tools.
Please refer to Section 16.0 for more details about
Microchip’s development tools.
PIC16C7X
DS30390E-page 6
1997 Microchip Technology Inc.
TABLE 1-1: PIC16C7XX FAMILY OF DEVCES
PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72
(1)
Clock
Maximum Frequency
of Operation (MHz) 20 20 20 20 20 20
Memory
EPROM Program Memory
(x14 words) 512 1K 1K 2K 2K —
ROM Program Memory
(14K words) —————2K
Data Memory (bytes) 36 36 68 128 128 128
Peripherals
Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/
PWM Module(s) ————1 1
Serial Port(s)
(SPI/I
2
C, USART) — — — — SPI/I
2
C SPI/I
2
C
Parallel Slave Port — — — — — —
A/D Converter (8-bit) Channels 4 4 4 4 5 5
Features
Interrupt Sources 4 4 4 4 8 8
I/O Pins 13 13 13 13 22 22
Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes Yes Yes Yes
Packages 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
28-pin SDIP,
SOIC, SSOP 28-pin SDIP,
SOIC, SSOP
PIC16C73A PIC16C74A PIC16C76 PIC16C77
Clock
Maximum Frequency of Oper-
ation (MHz) 20 20 20 20
Memory
EPROM Program Memory
(x14 words) 4K 4K 8K 8K
Data Memory (bytes) 192 192 368 368
Peripherals
Timer Module(s) TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/PWM Mod-
ule(s) 2222
Serial Port(s) (SPI/I
2
C, US-
ART) SPI/I
2
C, USART SPI/I
2
C, USART SPI/I
2
C, USART SPI/I
2
C, USART
Parallel Slave Port — Yes — Yes
A/D Converter (8-bit) Channels 5858
Features
Interrupt Sources 11 12 11 12
I/O Pins 22 33 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit Serial Programming Yes Yes Yes Yes
Brown-out Reset Yes Yes Yes Yes
Packages 28-pin SDIP,
SOIC 40-pin DIP;
44-pin PLCC,
MQFP, TQFP
28-pin SDIP,
SOIC 40-pin DIP;
44-pin PLCC,
MQFP, TQFP
All PIC16/17 F amily devices have Power-on Reset, selectable Watchdog Timer, selectab le code protect and high I/O current capabil-
ity. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
1997 Microchip Technology Inc. DS30390E-page 7
PIC16C7X
2.0 PIC16C7X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are av ailab le. Depending on application and production
requirements, the proper de vice option can be selected
using the inf ormation in the PIC16C7X Product Identifi-
cation System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
For the PIC16C7X family, there are two device “types”
as indicated in the device number:
1.
C
, as in PIC16
C
74. These devices have
EPROM type memory and operate over the
standard voltage range.
2.
LC
, as in PIC16
LC
74. These devices have
EPROM type memory and operate over an
extended voltage range.
2.1 UV Erasable Devices
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART
Plus and PRO MATE
II
programmers both support programming of the
PIC16C7X.
2.2 One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
2.3 Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
f or users who choose not to prog r am a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4 Serialized Quick-Turnaround
Production (SQTP
SM
) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with diff erent serial numbers. The serial num-
bers may be random, pseudo-random, or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
PIC16C7X
DS30390E-page 8
1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 9
PIC16C7X
3.0 ARCHITECTURAL OVERVIEW
The high perfor mance of the PIC16CXX family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which,
program and data are accessed from separate memo-
ries using separate buses. This improves bandwidth
ov er traditional v on Neumann architecture in which pro-
gram and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit wide data word. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions (Example 3-1). Consequently, all instructions (35)
e x ecute in a single cycle (200 ns @ 20 MHz) e xcept for
program branches.
The table below lists program memory (EPROM) and
data memory (RAM) for each PIC16C7X device.
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (sym-
metrical) instr uction set that makes it possible to carry
out any operation on an y register using an y addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
Device Program
Memory Data Memory
PIC16C72 2K x 14 128 x 8
PIC16C73 4K x 14 192 x 8
PIC16C73A 4K x 14 192 x 8
PIC16C74 4K x 14 192 x 8
PIC16C74A 4K x 14 192 x 8
PIC16C76 8K x 14 368 x 8
PIC16C77 8K x 14 386 x 8
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
aff ect the v alues of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register . The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
PIC16C7X
DS30390E-page 10 1997 Microchip Technology Inc.
FIGURE 3-1: PIC16C72 BLOCK DIAGRAM
EPROM
Program
Memory
2K x 14
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
128 x 8
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
Timer0
A/D Synchronous
Serial Port
PORTA
PORTB
PORTC
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
CCP1
Timer1 Timer2
RA4/T0CKI
RA5/SS/AN4
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
8
3
1997 Microchip Technology Inc. DS30390E-page 11
PIC16C7X
FIGURE 3-2: PIC16C73/73A/76 BLOCK DIAGRAM
EPROM
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit) RAM
File
Registers
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
USART
PORTA
PORTB
PORTC
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
8
Brown-out
Reset(2)
Note 1: Higher order bits are from the STATUS register.
2: Brown-out Reset is not available on the PIC16C73.
CCP1 CCP2 Synchronous
A/DTimer0 Timer1 Timer2
Serial Port
RA4/T0CKI
RA5/SS/AN4
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
8
3
Device Program Memory Data Memory (RAM)
PIC16C73
PIC16C73A
PIC16C76
4K x 14
4K x 14
8K x 14
192 x 8
192 x 8
368 x 8
PIC16C7X
DS30390E-page 12 1997 Microchip Technology Inc.
FIGURE 3-3: PIC16C74/74A/77 BLOCK DIAGRAM
EPROM
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit) RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI
RA5/SS/AN4
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD7/PSP7:RD0/PSP0
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
8
Brown-out
Reset(2)
Note 1: Higher order bits are from the STATUS register.
2: Brown-out Reset is not available on the PIC16C74.
USART
CCP1 CCP2 Synchronous
A/DTimer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
Parallel Slave Port
8
3
Device Program Memory Data Memory (RAM)
PIC16C74
PIC16C74A
PIC16C77
4K x 14
4K x 14
8K x 14
192 x 8
192 x 8
368 x 8
1997 Microchip Technology Inc. DS30390E-page 13
PIC16C7X
TABLE 3-1: PIC16C72 PINOUT DESCRIPTION
Pin Name DIP
Pin# SSOP
Pin# SOIC
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 9 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2 4 4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 5 5 I/O TTL RA3 can also be analog input3 or analog ref erence voltage
RA4/T0CKI 6 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/AN4 7 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 22 I/O TTL
RB2 23 23 23 I/O TTL
RB3 24 24 24 I/O TTL
RB4 25 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 28 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI 12 12 12 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 17 17 I/O ST
RC7 18 18 18 I/O ST
VSS 8, 19 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PIC16C7X
DS30390E-page 14 1997 Microchip Technology Inc.
TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION
Pin Name DIP
Pin# SOIC
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2 4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1997 Microchip Technology Inc. DS30390E-page 15
PIC16C7X
TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION
Pin Name DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input.
OSC2/CLK OUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0
RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1
RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference
voltage
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. POR TB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt on change pin.
RB5 38 42 15 I/O TTL Interrupt on change pin.
RB6 39 43 16 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PIC16C7X
DS30390E-page 16 1997 Microchip Technology Inc.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or
Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USAR T Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USAR T Asynchronous Receiv e or
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0 19 21 38 I/O ST/TTL(3)
RD1/PSP1 20 22 39 I/O ST/TTL(3)
RD2/PSP2 21 23 40 I/O ST/TTL(3)
RD3/PSP3 22 24 41 I/O ST/TTL(3)
RD4/PSP4 27 30 2 I/O ST/TTL(3)
RD5/PSP5 28 31 3 I/O ST/TTL(3)
RD6/PSP6 29 32 4 I/O ST/TTL(3)
RD7/PSP7 30 33 5 I/O ST/TTL(3)
PORTE is a bi-directional I/O port.
RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can also be read control f or the parallel sla ve port,
or analog input5.
RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel sla ve port,
or analog input6.
RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave
port, or analog input7.
VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,28,
40 12,13,
33,34 — These pins are not internally connected. These pins should
be left unconnected.
TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.’d)
Pin Name DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1997 Microchip Technology Inc. DS30390E-page 17
PIC16C7X
3.1 Clocking Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instr uc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-4.
3.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instr uction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the e xecution cycle , the f etched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-4: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
PIC16C7X
DS30390E-page 18 1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 19
PIC16C7X
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16C7X family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The amount of program memory available to
each device is listed below:
For those devices with less than 8K program memory,
accessing a location abov e the physically implemented
address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PIC16C72 PROGRAM
MEMORY MAP AND STACK
Applicable Devices
72 73 73A 74 74A 76 77
Device Program
Memory Address Range
PIC16C72 2K x 14 0000h-07FFh
PIC16C73 4K x 14 0000h-0FFFh
PIC16C73A 4K x 14 0000h-0FFFh
PIC16C74 4K x 14 0000h-0FFFh
PIC16C74A 4K x 14 0000h-0FFFh
PIC16C76 8K x 14 0000h-1FFFh
PIC16C77 8K x 14 0000h-1FFFh
PC<12:0>
13
0000h
0004h
0005h
07FFh
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt V ector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
0800h
User Memory
Space
FIGURE 4-2: PIC16C73/73A/74/74A
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt V ector
On-chip Program
On-chip Program
Memory (Page 1)
Memory (Page 0)
CALL, RETURN
RETFIE, RETLW
User Memory
Space
PIC16C7X
DS30390E-page 20 1997 Microchip Technology Inc.
FIGURE 4-3: PIC16C76/77 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt V ector
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Page 0
Page 1
Page 2
Page 3
07FFh
0800h
0FFFh
1000h
17FFh
1800h
User Memory
Space
On-Chip
On-Chip
On-Chip
On-Chip
4.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1:RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 4.5).
Applicable Devices
72 73 73A 74 74A 76 77
1997 Microchip Technology Inc. DS30390E-page 21
PIC16C7X
FIGURE 4-4: PIC16C72 REGISTER FILE
MAP
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
ADCON1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
BFh
C0h
Unimplemented data memory locations, read as
'0'.
Note 1: Not a physical register.
File
Address
FIGURE 4-5: PIC16C73/73A/74/74A
REGISTER FILE MAP
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address File
Address
Unimplemented data memory locations, read as
'0'.
Note 1: Not a physical register.
2: These registers are not physically imple-
mented on the PIC16C73/73A, read as '0'.
PIC16C7X
DS30390E-page 22 1997 Microchip Technology Inc.
FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'.
Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require
relocation of data memory usage in the user application code if upgrading to the PIC16C76/77.
File
Address
Indirect addr.(*) Indirect addr.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
120h 1A0h
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(*)
PORTD
PORTE TRISD
TRISE
TMR0 OPTION
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
TXSTA
SPBRG
ADCON1
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
accesses
70h - 7Fh
EFh
F0h
accesses
70h-7Fh
16Fh
170h
accesses
70h-7Fh
General
Purpose
Register
General
Purpose
Register
TRISB
PORTB
96 Bytes 80 Bytes 80 Bytes 80 Bytes
16 Bytes 16 Bytes
(1)
(1)
(1)
(1)
1997 Microchip Technology Inc. DS30390E-page 23
PIC16C7X
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral f ea-
tures are described in the section of that peripheral f ea-
ture.
TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(3)
Bank 0
00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h(1) STATUS IRP(4) RP1(4) RP0 TO PD ZDCC0001 1xxx 000q quuu
04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h — Unimplemented — —
09h — Unimplemented — —
0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h — Unimplemented — —
19h — Unimplemented — —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
PIC16C7X
DS30390E-page 24 1997 Microchip Technology Inc.
Bank 1
80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h(1) STATUS IRP(4) RP1(4) RP0 TO PD ZDCC0001 1xxx 000q quuu
84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h — Unimplemented — —
89h — Unimplemented — —
8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000
8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Dh — Unimplemented — —
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
1997 Microchip Technology Inc. DS30390E-page 25
PIC16C7X
TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 0
00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h(4) STATUS IRP(7) RP1(7) RP0 TO PD ZDCC0001 1xxx 000q quuu
04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.
PIC16C7X
DS30390E-page 26 1997 Microchip Technology Inc.
Bank 1
80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h(4) STATUS IRP(7) RP1(7) RP0 TO PD ZDCC0001 1xxx 000q quuu
84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR(6) ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.
1997 Microchip Technology Inc. DS30390E-page 27
PIC16C7X
TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 0
00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.
PIC16C7X
DS30390E-page 28 1997 Microchip Technology Inc.
Bank 1
80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.
1997 Microchip Technology Inc. DS30390E-page 29
PIC16C7X
Bank 2
100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
103h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
104h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch-
10Fh — Unimplemented — —
Bank 3
180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
183h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
184h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch-
18Fh — Unimplemented — —
TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.
PIC16C7X
DS30390E-page 30 1997 Microchip Technology Inc.
4.2.2.1 STATUS REGISTER
The STATUS register , shown in Figure 4-7, contains the
arithmetic status of the ALU, the RESET status and the
bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Fur ther more, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Applicable Devices
72 73 73A 74 74A 76 77
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This lea ves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
aff ect the Z, C or DC bits from the STATUS register . For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
Note 1: For those devices that do not use bits IRP
and RP1 (STATUS<7:6>), maintain these
bits clear to ensure upward compatibility
with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1997 Microchip Technology Inc. DS30390E-page 31
PIC16C7X
4.2.2.2 OPTION REGISTER
The OPTION register is a readable and writable regis-
ter which contains various control bits to configure the
TMR0/WDT prescaler, the External INT Interrupt,
TMR0, and the weak pull-ups on PORTB.
Applicable Devices
72 73 73A 74 74A 76 77
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the W atchdog Timer .
FIGURE 4-8: OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C7X
DS30390E-page 32 1997 Microchip Technology Inc.
4.2.2.3 INTCON REGISTER
The INTCON Register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and Exter nal
RB0/INT pin interrupts.
Applicable Devices
72 73 73A 74 74A 76 77
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
FIGURE 4-9: INTCON REGISTER
(ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: GIE:(1) Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: For the PIC16C73 and PIC16C74, if an interrupt occurs while the GIE bit is being cleared, the GIE bit
may be unintentionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine.
Refer to Section 14.5 for a detailed description.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
1997 Microchip Technology Inc. DS30390E-page 33
PIC16C7X
4.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
Applicable Devices
72 73 73A 74 74A 76 77 Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
FIGURE 4-10: PIE1 REGISTER PIC16C72 (ADDRESS 8Ch)
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6: ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-4: Unimplemented: Read as '0'
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIC16C7X
DS30390E-page 34 1997 Microchip Technology Inc.
FIGURE 4-11: PIE1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6: ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5: RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4: TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved
on these devices, always maintain this bit clear.
1997 Microchip Technology Inc. DS30390E-page 35
PIC16C7X
4.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
Peripheral interrupts.
Applicable Devices
72 73 73A 74 74A 76 77
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear pr ior to enabling an
interrupt.
FIGURE 4-12: PIR1 REGISTER PIC16C72 (ADDRESS 0Ch)
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6: ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4: Unimplemented: Read as '0'
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
PIC16C7X
DS30390E-page 36 1997 Microchip Technology Inc.
FIGURE 4-13: PIR1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 0Ch)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6: ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5: RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is empty
bit 4: TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved
on these devices, always maintain this bit clear.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
1997 Microchip Technology Inc. DS30390E-page 37
PIC16C7X
4.2.2.6 PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 4-14: PIE2 REGISTER (ADDRESS 8Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIC16C7X
DS30390E-page 38 1997 Microchip Technology Inc.
4.2.2.7 PIR2 REGISTER
This register contains the CCP2 interrupt flag bit.
Applicable Devices
72 73 73A 74 74A 76 77
.Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear pr ior to enabling an
interrupt.
FIGURE 4-15: PIR2 REGISTER (ADDRESS 0Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
1997 Microchip Technology Inc. DS30390E-page 39
PIC16C7X
4.2.2.8 PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry con-
tain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
Applicable Devices
72 73 73A 74 74A 76 77
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
clear, indicating a bro wn-out has occurred.
The BOR status bit is a don't care and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
FIGURE 4-16: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
— — — — — — POR BOR(1) R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR(1): Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: Brown-out Reset is not implemented on the PIC16C73/74.
PIC16C7X
DS30390E-page 40 1997 Microchip Technology Inc.
4.3 PCL and PCLATH
The program counter (PC) is 13-bits wide . The lo w byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the
PC will be cleared. Figure 4-17 shows the two situa-
tions for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to
PCL (PCLATH<4:0> → PCH). The lower example in
the figure shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-17: LOADING OF PC IN
DIFFERENT SITUATIONS
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an off-
set to the program counter (ADDWF PCL). When doing
a table read using a computed GOTO method, care
should be e xercised if the tab le location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note
“Implementing a Table Read"
(AN556).
4.3.2 STACK
The PIC16CXX f amily has an 8 lev el deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable . The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack oper ates as a circular buff er . This means that
after the stack has been PUSHed eight times , the ninth
push overwrites the value that w as stored from the first
push. The tenth push overwrites the second push (and
so on).
Applicable Devices
72 73 73A 74 74A 76 77
PC 12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU
GOTO, CALL
Opcode <10:0>
8
PC 12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
4.4 Program Memory Paging
PIC16C7X de vices are capab le of addressing a contin-
uous 8K word b lock of prog ram memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction the upper 2 bits
of the address are provided by PCLATH<4:3>. When
doing a CALL or GOTO instruction, the user must ensure
that the page select bits are programmed so that the
desired program memory page is addressed. If a return
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is pushed onto the stack. Therefore,
manipulation of the PCLATH<4:3> bits are not required
for the return instructions (which POPs the address
from the stack).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
Note 2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an inter-
rupt address.
Applicable Devices
72 73 73A 74 74A 76 77
Note: PIC16C7X devices with 4K or less of pro-
gram memory ignore paging bit
PCLATH<4>. The use of PCLATH<4> as a
general purpose read/write bit is not rec-
ommended since this may affect upward
compatibility with future products.
1997 Microchip Technology Inc. DS30390E-page 41
PIC16C7X
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored b y the interrupt ser-
vice routine (if interrupts are used).
EXAMPLE 4-1: CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BSF PCLATH,3 ;Select page 1 (800h-FFFh)
BCF PCLATH,4 ;Only on >4K devices
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
:
ORG 0x900
SUB1_P1: ;called subroutine
: ;page 1 (800h-FFFh)
:
RETURN ;return to Call subroutine
;in page 0 (000h-7FFh)
4.5 Indirect Addressing, INDF and FSR
Registers
The INDF register is not a ph ysical register . Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
ma y be affected). An effectiv e 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-18.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF register
incf FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
CONTINUE
: ;yes continue
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 4-18: DIRECT/INDIRECT ADDRESSING
For register file map detail see Figure 4-4, and Figure 4-5.
Data
Memory
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
not used
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
PIC16C7X
DS30390E-page 42 1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 43
PIC16C7X
5.0 I/O PORTS
Some pins for these I/O por ts are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1 PORTA and TRISA Registers
PORTA is a 6-bit latch.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL input
levels and full CMOS output drivers. All pins have data
direction bits (TRIS registers) which can configure
these pins as output or input.
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will wr ite to the por t latch. All
write operations are read-modify-write operations.
Theref ore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 5-1: INITIALIZING PORTA
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; PIC16C76/77 only
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as '0'.
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
FIGURE 5-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 5-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Data
bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
VSS
I/O pin(1)
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
QD
Q
CK
QD
Q
CK
EN
QD
EN
PIC16C7X
DS30390E-page 44 1997 Microchip Technology Inc.
TABLE 5-1: PORTA FUNCTIONS
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input
RA1/AN1 bit1 TTL Input/output or analog input
RA2/AN2 bit2 TTL Input/output or analog input
RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
1997 Microchip Technology Inc. DS30390E-page 45
PIC16C7X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
EXAMPLE 5-2: INITIALIZING PORTB
BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the POR TB pins has a w eak internal pull-up . A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION<7>). The
weak pull-up is automatically turned off when the por t
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 5-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
Applicable Devices
72 73 73A 74 74A 76 77
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION<7>).
Schmitt Trigger
Buffer
TRIS Latch
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user , in the interrupt service routine, can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook,
"Implementing Wake-Up on Key
Stroke"
(AN552).
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Note: For the PIC16C73/74, if a change on the
I/O pin should occur when the read opera-
tion is being executed (start of the Q2
cycle), then interrupt flag bit RBIF may not
get set.
PIC16C7X
DS30390E-page 46 1997 Microchip Technology Inc.
FIGURE 5-4: BLOCK DIAGRAM OF
RB7:RB4 PINS (PIC16C73/74)
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION<7>).
FIGURE 5-5: BLOCK DIAGRAM OF
RB7:RB4 PINS (PIC16C72/
73A/74A/76/77)
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode Q3
Q1
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION<7>).
TABLE 5-3: PORTB FUNCTIONS
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
1997 Microchip Technology Inc. DS30390E-page 47
PIC16C7X
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C7X
DS30390E-page 48 1997 Microchip Technology Inc.
5.3 PORTC and TRISC Registers
PORTC is an 8-bit bi-directional por t. Each pin is indi-
vidually configurable as an input or output through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instr uctions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 5-3: INITIALIZING PORTC
BCF STATUS, RP0 ; Select Bank 0
BCF STATUS, RP1 ; PIC16C76/77 only
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 5-6: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORT/PERIPHERAL Select(2)
Data bus
WR
PORT
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
PORT
Peripheral
OE(3)
Peripheral input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: P ort/P eripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
TABLE 5-5: PORTC FUNCTIONS
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI/CCP2(1) bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output
RC6/TX/CK(2) bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART
Synchronous Clock
RC7/RX/DT(2) bit7 ST Input/output port pin or USART Asynchronous Receive, or USART
Synchronous Data
Legend: ST = Schmitt Trigger input
Note 1: The CCP2 multiplexed function is not enabled on the PIC16C72.
2: The TX/CK and RX/DT multiplexed functions are not enabled on the PIC16C72.
1997 Microchip Technology Inc. DS30390E-page 49
PIC16C7X
TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged.
PIC16C7X
DS30390E-page 50 1997 Microchip Technology Inc.
5.4 PORTD and TRISD Registers
PORTD is an 8-bit por t with Schmitt Tr igger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 5-7: PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
TABLE 5-7: PORTD FUNCTIONS
TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1
RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5
RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
1997 Microchip Technology Inc. DS30390E-page 51
PIC16C7X
5.5 PORTE and TRISE Register
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O PORTE becomes control inputs for the micropro-
cessor por t when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs) and that register ADCON1 is configured f or dig-
ital I/O. In this mode the input buffers are TTL.
Figure 5-9 shows the TRISE register, which also con-
trols the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. The
operation of these pins is selected b y control bits in the
ADCON1 register. When selected as an analog input,
these pins will read as '0's.
TRISE controls the direction of the RE pins, e v en when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Applicable Devices
72 73 73A 74 74A 76 77 FIGURE 5-8: PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
Note: On a Power-on Reset these pins are con-
figured as analog inputs.
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
QD
CK
QD
CK
EN
QD
EN
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 5-9: TRISE REGISTER (ADDRESS 89h)
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — bit2 bit1 bit0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7 : IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6: OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4: PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3: Unimplemented: Read as '0'
PORTE Data Direction Bits
bit 2: Bit2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1: Bit1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
PIC16C7X
DS30390E-page 52 1997 Microchip Technology Inc.
TABLE 5-9: PORTE FUNCTIONS
TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in parallel slave port mode or
analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in parallel slav e port mode or
analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
1997 Microchip Technology Inc. DS30390E-page 53
PIC16C7X
5.6 I/O Programming Considerations
5.6.1 BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU , ex ecute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a por t with both inputs and
outputs defined. For example, a BSF operation on bit5
of POR TB will cause all eight bits of POR TB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of POR TB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, ov erwriting the previous content. As long as the pin
sta ys in the input mode, no prob lem occurs. Howe ver, if
bit0 is switched to an output, the content of the data
latch may now be unknown.
Reading the por t register, reads the values of the por t
pins. Writing to the port register wr ites the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this v alue , and
this value is then written to the port latch.
Example 5-4 shows the effect of two sequential read-
modify-write instructions on an I/O port.
Applicable Devices
72 73 73A 74 74A 76 77
EXAMPLE 5-4: READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
;Initial PORT settings: PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
; PORT latch PORT pins
; ---------- ---------
BCF PORTB, 7 ; 01pp pppp 11pp pppp
BCF PORTB, 6 ; 10pp pppp 11pp pppp
BSF STATUS, RP0 ;
BCF TRISB, 7 ; 10pp pppp 11pp pppp
BCF TRISB, 6 ; 10pp pppp 10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the le v el on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
5.6.2 SUCCESSIVE OPER ATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas f or reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-
10). Therefore, care must be exercised if a write fol-
lowed by a read operation is carried out on the same I/
O port. The sequence of instructions should be such to
allow the pin voltage to stabilize (load dependent)
before the next instruction which causes that file to be
read into the CPU is e xecuted. Otherwise, the previous
state of that pin may be read into the CPU rather than
the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
FIGURE 5-10: SUCCESSIVE I/O OPERATION
PC PC + 1 PC + 2 PC + 3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
fetched
RB7:RB0
MOVWF PORTB
write to
PORTB NOP
Port pin
sampled here
NOP
MOVF PORTB,W
Instruction
executed MOVWF PORTB
write to
PORTB
NOP
MOVF PORTB,W
PC
TPD
Note:
This example sho ws a write to POR TB
followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
where TCY = instruction cycle
TPD = propagation delay
Therefore , at higher clock frequencies,
a write follow ed by a read may be prob-
lematic.
PIC16C7X
DS30390E-page 54 1997 Microchip Technology Inc.
5.7 Parallel Slave Port
PORTD operates as an 8-bit wide Parallel Slave Por t,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable b y the e xternal world through RD
control input pin RE0/RD /AN5 and WR control input pin
RE1/WR/AN6.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input, RE1/
WR/AN6 to be the WR input and RE2/CS /AN7 to be the
CS (chip select) input. For this functionality, the corre-
sponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set) and
the A/D port configuration bits PCFG2:PCFG0
(ADCON1<2:0>) must be set, which will configure pins
RE2:RE0 as digital I/O.
There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored,
since the microprocessor is controlling the direction of
data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full status flag bit IBF (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal
the write is complete (Figure 5-12). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The input Buffer Overflow status flag bit
IBO V (TRISE<5>) is set if a second write to the P arallel
Slav e Port is attempted when the previous b yte has not
been read out of the buffer.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full sta-
tus flag bit OBF (TRISE<6>) is cleared immediately
(Figure 5-13) indicating that the PORTD latch is w aiting
to be read by the external bus. When either the CS or
RD pin becomes high (le vel triggered), the interrupt flag
bit PSPIF is set on the Q4 clock cycle, following the
next Q2 cycle, indicating that the read is complete.
OBF remains low until data is written to PORTD by the
user firmware.
When not in P arallel Slav e P ort mode, the IBF and OBF
bits are held clear. However, if flag bit IBOV was previ-
ously set, it must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared b y the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 5-11: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL
SLAVE PORT)
Data bus
WR
PORT
RD
RDx
QD
CK
EN
QD
EN
PORT
pin
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
1997 Microchip Technology Inc. DS30390E-page 55
PIC16C7X
FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
08h PORTD Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
PIC16C7X
DS30390E-page 56 1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 57
PIC16C7X
6.0 OVERVIEW OF TIMER
MODULES
The PIC16C72, PIC16C73/73A, PIC16C74/74A,
PIC16C76/77 each have three timer modules.
Each module can generate an interrupt to indicate that
an event has occurred (i.e. timer overflow). Each of
these modules is e xplained in full detail in the following
sections. The timer modules are:
• Timer0 Module (Section 7.0)
• Timer1 Module (Section 8.0)
• Timer2 Module (Section 9.0)
6.1 Timer0 Overview
The Timer0 module is a simple 8-bit overflow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock. When the clock
source is an exter nal clock, the Timer0 module can be
selected to increment on either the rising or falling
edge.
The Timer0 module also has a programmable pres-
caler option. This prescaler can be assigned to either
the Timer0 module or the Watchdog Timer. Bit PSA
(OPTION<3>) assigns the prescaler , and bits PS2:PS0
(OPTION<2:0>) determine the prescaler value. Timer0
can increment at the following rates: 1:1 (when pres-
caler assigned to Watchdog timer), 1:2, 1:4, 1:8, 1:16,
1:32, 1:64, 1:128, and 1:256 (Timer0 only).
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s fre-
quency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.
6.2 Timer1 Overview
Timer1 is a 16-bit timer/counter. The clock source can
be either the internal system clock (Fosc/4), an e xternal
clock, or an external crystal. Timer1 can operate as
either a timer or a counter. When operating as a
counter (exter nal clock source), the counter can either
operate synchronized to the device or asynchronously
to the de vice. Asynchronous oper ation allows Timer1 to
operate during sleep, which is useful for applications
that require a real-time clock as well as the power sav-
ings of SLEEP mode.
Timer1 also has a prescaler option which allows
Timer1 to increment at the f ollowing rates: 1:1, 1:2, 1:4,
and 1:8. Timer1 can be used in conjunction with the
Capture/Compare/PWM module. When used with a
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
CCP module, Timer1 is the time-base for 16-bit Cap-
ture or the 16-bit Compare and must be synchronized
to the device.
6.3 Timer2 Overview
Timer2 is an 8-bit timer with a programmable prescaler
and postscaler, as well as an 8-bit period register
(PR2). Timer2 can be used with the CCP1 module (in
PWM mode) as well as the Baud Rate Generator for
the Synchronous Serial Port (SSP). The prescaler
option allows Timer2 to increment at the following
rates: 1:1, 1:4, 1:16.
The postscaler allows the TMR2 register to match the
period register (PR2) a programmable n umber of times
before generating an interrupt. The postscaler can be
programmed from 1:1 to 1:16 (inclusive).
6.4 CCP Overview
The CCP module(s) can operate in one of these three
modes: 16-bit capture, 16-bit compare, or up to 10-bit
Pulse Width Modulation (PWM).
Capture mode captures the 16-bit value of TMR1 into
the CCPRxH:CCPRxL register pair. The capture event
can be programmed for either the falling edge, rising
edge, fourth rising edge, or the sixteenth rising edge of
the CCPx pin.
Compare mode compares the TMR1H:TMR1L register
pair to the CCPRxH:CCPRxL register pair. When a
match occurs an interrupt can be generated, and the
output pin CCPx can be forced to given state (High or
Low), TMR1 can be reset (CCP1), or TMR1 reset and
start A/D conv ersion (CCP2). This depends on the con-
trol bits CCPxM3:CCPxM0.
PWM mode compares the TMR2 register to a 10-bit
duty cycle register (CCPRxH:CCPRxL<5:4>) as well as
to an 8-bit period register (PR2). When the TMR2 reg-
ister = Duty Cycle register, the CCPx pin will be forced
low. When TMR2 = PR2, TMR2 is cleared to 00h, an
interrupt can be generated, and the CCPx pin (if an out-
put) will be forced high.
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X
DS30390E-page 58 1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 59
PIC16C7X
7.0 TIMER0 MODULE
The Timer0 module timer/counter has the f ollowing f ea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode, Timer0 will increment
either on e very rising or f alling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
Applicable Devices
72 73 73A 74 74A 76 77
Source Edge Select bit T0SE (OPTION<4>). Clearing
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 7.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software b y control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable . When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
7.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software b y the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP. See
Figure 7-4 for Timer0 interrupt timing.
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
clocks TMR0
PSout
(2 cycle delay)
PSout
Data bus
8
PSA
PS2, PS1, PS0 Set interrupt
flag bit T0IF
on overflow
3
PC-1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
Instruction
Fetch
TMR0
PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0
MO VWF TMR0 MO VF TMR0,W MO VF TMR0,W MOVF TMR0,W MO VF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PIC16C7X
DS30390E-page 60 1997 Microchip Technology Inc.
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
FIGURE 7-4: TIMER0 INTERRUPT TIMING
PC+
6
PC-1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
Instruction
Fetch
TMR0
PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
T0 NT0+1
MO VWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MO VF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1
T0+1 NT0
Instruction
Execute
Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
11
OSC1
CLKOUT(3)
Timer0
T0IF bit
(INTCON<2>)
FEh
GIE bit
(INTCON<7>)
INSTRUCTION
PC
Instruction
fetched
PC PC +1 PC +1 0004h 0005h
Instruction
executed
Inst (PC)
Inst (PC-1)
Inst (PC+1)
Inst (PC)
Inst (0004h) Inst (0005h)
Inst (0004h)Dummy cycle Dummy cycle
FFh 00h 01h 02h
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
FLOW
1997 Microchip Technology Inc. DS30390E-page 61
PIC16C7X
7.2 Using Timer0 with an External Clock
When an e xternal clock input is used f or Timer0, it must
meet certain requirements. The requirements ensure
the e xternal clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1 EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the exter nal clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 7-5).
Therefore, it is necessary for T0CKI to be high for at
least 2Tosc (and a small RC delay of 20 ns) and low for
at least 2Tosc (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
Applicable Devices
72 73 73A 74 74A 76 77
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres-
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4Tosc (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
7.2.2 TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
e xternal clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 7-5 shows the dela y
from the external clock edge to the timer incrementing.
FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0 T0 T0 + 1 T0 + 2
Small pulse
misses sampling
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
(3) (1)
PIC16C7X
DS30390E-page 62 1997 Microchip Technology Inc.
7.3 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
availab le which is m utually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
Applicable Devices
72 73 73A 74 74A 76 77
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e .g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The pres-
caler is not readable or writable.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (=Fosc/4)
SYNC
2
Cycles TMR0 reg
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
1997 Microchip Technology Inc. DS30390E-page 63
PIC16C7X
7.3.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
execution.
EXAMPLE 7-1: CHANGING PRESCALER (TIMER0→WDT)
To change prescaler from the WDT to the Timer0 mod-
ule use the sequence shown in Example 7-2.
EXAMPLE 7-2: CHANGING PRESCALER (WDT→TIMER0)
CLRWDT ;Clear WDT and prescaler
BSF STATUS, RP0 ;Bank 1
MOVLW b'xxxx0xxx' ;Select TMR0, new prescale value and
MOVWF OPTION_REG ;clock source
BCF STATUS, RP0 ;Bank 0
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0
Note: To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 7-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
1) BSF STATUS, RP0 ;Bank 1
Lines 2 and 3 do NOT have to
be included if the final desired
prescale value is other than 1:1.
If 1:1 is final desired value, then
a temporary prescale value is
set in lines 2 and 3 and the final
prescale value will be set in lines
10 and 11.
2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of
3) MOVWF OPTION_REG ;other than 1:1
4) BCF STATUS, RP0 ;Bank 0
5) CLRF TMR0 ;Clear TMR0 and prescaler
6) BSF STATUS, RP1 ;Bank 1
7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value
8) MOVWF OPTION_REG ;
9) CLRWDT ;Clears WDT and prescaler
10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT
11) MOVWF OPTION_REG ;
12) BCF STATUS, RP0 ;Bank 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
01h,101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
PIC16C7X
DS30390E-page 64 1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 65
PIC16C7X
8.0 TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls ov er to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
• As a timer
• As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Applicable Devices
72 73 73A 74 74A 76 77
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on ever y rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “reset input”. This reset can
be generated by either of the two CCP modules
(Section 10.0). Figure 8-1 shows the Timer1 control
register.
For the PIC16C72/73A/74A/76/77, when the Timer1
oscillator is enabled (T1OSCEN is set), the RC1/
T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC<1:0> value is ignored.
For the PIC16C73/74, when the Timer1 oscillator is
enabled (T1OSCEN is set), RC1/T1OSI/CCP2 pin
becomes an input, however the RC0/T1OSO/T1CKI
pin will have to be configured as an input b y setting the
TRISC<0> bit.
FIGURE 8-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
PIC16C7X
DS30390E-page 66 1997 Microchip Technology Inc.
8.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
8.2 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set or pin RC0/T1OSO/T1CKI when bit
T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
8.2.1 EXTERNAL CLOCK INPUT TIMING FOR
SYNCHRONIZED COUNTER MODE
When an e xternal clock input is used f or Timer1 in syn-
chronized counter mode, it must meet cer tain require-
ments. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also , there
is a dela y in the actual incrementing of TMR1 after syn-
chronization.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessar y for T1CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the appropri-
ate electrical specifications, parameters 45, 46, and 47.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple-
counter type prescaler so that the prescaler output is
symmetrical. In order for the exter nal clock to meet the
sampling requirement, the ripple-counter must be
taken into account. Therefore, it is necessary for T1CKI
to hav e a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and lo w time is that the y do
not violate the minimum pulse width requirements of
10 ns). Refer to the appropriate electrical specifica-
tions, parameters 40, 42, 45, 46, and 47.
FIGURE 8-2: TIMER1 BLOCK DIAGRAM
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 SLEEP input
T1OSCEN
Enable
Oscillator(1) FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(2)
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
2: The CCP2 module is not implemented in the PIC16C72.
3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode.
Set flag bit
TMR1IF on
Overflow TMR1
(3)
1997 Microchip Technology Inc. DS30390E-page 67
PIC16C7X
8.3 Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 8.3.2).
In asynchronous counter mode, Timer1 can not be
used as a time-base for capture or compare operations.
8.3.1 EXTERNAL CLOCK INPUT TIMING WITH
UNSYNCHRONIZED CLOCK
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
cer tain minimum high time and low time requirements.
Refer to the appropriate Electrical Specifications Sec-
tion, timing parameters 45, 46, and 47.
8.3.2 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is r unning,
from an exter nal asynchronous clock, will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems since
the timer may overflow between the reads.
F or writes, it is recommended that the user simply stop
the timer and write the desired values. A wr ite conten-
tion ma y occur by writing to the timer registers while the
register is incrementing. This may produce an unpre-
dictable value in the timer register.
Reading the 16-bit value requires some care.
Example 8-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
Applicable Devices
72 73 73A 74 74A 76 77
EXAMPLE 8-1: READING A 16-BIT FREE-
RUNNING TIMER
; All interrupts are disabled
MOVF TMR1H, W ;Read high byte
MOVWF TMPH ;
MOVF TMR1L, W ;Read low byte
MOVWF TMPL ;
MOVF TMR1H, W ;Read high byte
SUBWF TMPH, W ;Sub 1st read
; with 2nd read
BTFSC STATUS,Z ;Is result = 0
GOTO CONTINUE ;Good 16-bit read
;
; TMR1L may have rolled over between the read
; of the high and low bytes. Reading the high
; and low bytes now will read a good value.
;
MOVF TMR1H, W ;Read high byte
MOVWF TMPH ;
MOVF TMR1L, W ;Read low byte
MOVWF TMPL ;
; Re-enable the Interrupt (if required)
CONTINUE ;Continue with your code
8.4 Timer1 Oscillator
A crystal oscillator circuit is built in betw een pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 8-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 8-1: CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
Applicable Devices
72 73 73A 74 74A 76 77
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
PIC16C7X
DS30390E-page 68 1997 Microchip Technology Inc.
8.5 Resetting Timer1 using a CCP Trigger
Output
The CCP2 module is not implemented on the
PIC16C72 device.
If the CCP1 or CCP2 module is configured in compare
mode to generate a “special event trigger"
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the e v ent that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
Applicable Devices
72 73 73A 74 74A 76 77
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
8.6 Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset e xcept by the CCP1 and CCP2
special event triggers.
T1CON register is reset to 00h on a Po wer-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
8.7 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
1997 Microchip Technology Inc. DS30390E-page 69
PIC16C7X
9.0 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
PWM mode of the CCP module(s). The TMR2 register
is readable and writable, and is cleared on any device
reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register . The PR2 register is ini-
tialized to FFh upon reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 9-2 shows the Timer2 control register.
Applicable Devices
72 73 73A 74 74A 76 77
9.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
9.2 Output of TMR2
The output of TMR2 (bef ore the postscaler) is f ed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 9-1: TIMER2 BLOCK DIAGRAM
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
Comparator
TMR2
Sets flag
TMR2 reg
output (1)
Reset
Postscaler
Prescaler
PR2 reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
to
PIC16C7X
DS30390E-page 70 1997 Microchip Technology Inc.
FIGURE 9-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2: TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
1997 Microchip Technology Inc. DS30390E-page 71
PIC16C7X
10.0 CAPTURE/COMPARE/PWM
MODULE(s)
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Both the CCP1 and
CCP2 modules are identical in operation, with the
exception of the operation of the special event trigger.
Table 10-1 and Table 10-2 show the resources and
interactions of the CCP module(s). In the follo wing sec-
tions, the operation of a CCP module is described with
respect to CCP1. CCP2 operates the same as CCP1,
except where noted.
Applicable Devices
72 73 73A 74 74A 76 77 CCP1
72 73 73A 74 74A 76 77 CCP2
CCP1 module:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
CCP2 module:
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
For use of the CCP modules, refer to the Embedded
Control Handbook,
"Using the CCP Modules"
(AN594).
TABLE 10-1: CCP MODE - TIMER
RESOURCE
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
TABLE 10-2: INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time-base.
Capture Compare The compare should be configured for the special event trigger, which clears TMR1.
Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1.
PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM Capture None
PWM Compare None
PIC16C7X
DS30390E-page 72 1997 Microchip Technology Inc.
FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)/CCP2CON REGISTER (ADDRESS 1Dh)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit
W =Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate softw are interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special e v ent (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
and starts an A/D conversion (if A/D module is enabled))
11xx = PWM mode
10.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an ev ent occurs
on pin RC2/CCP1. An event is defined as:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software . If another capture occurs bef ore
the value in register CCPR1 is read, the old captured
value will be lost.
10.1.1 CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Applicable Devices
72 73 73A 74 74A 76 77
Note: If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
FIGURE 10-2: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
10.1.2 TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
10.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
1997 Microchip Technology Inc. DS30390E-page 73
PIC16C7X
10.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 10-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 10-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
10.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven High
• Driven Low
• Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 10-3: COMPARE MODE
OPERATION BLOCK
DIAGRAM
Applicable Devices
72 73 73A 74 74A 76 77
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conversion (CCP1 only for PIC16C72,
CCP2 only for PIC16C73/73A/74/74A/76/77).
10.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
10.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
10.2.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not aff ected. Only a CCP interrupt is generated (if
enabled).
10.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
eff ectively be a 16-bit progr ammab le period register for
Timer1.
The special trigger output of CCP2 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
F or the PIC16C72 only, the special ev ent trigger output
of CCP1 resets the TMR1 register pair, and starts an
A/D conversion (if the A/D module is enabled).
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
PIC16C7X
DS30390E-page 74 1997 Microchip Technology Inc.
10.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiple xed with the POR TC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 10-4 shows a simplified block diagram of the
CCP module in PWM mode.
F or a step by step procedure on ho w to set up the CCP
module for PWM operation, see Section 10.3.3.
FIGURE 10-4: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 10-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 10-5: PWM OUTPUT
Applicable Devices
72 73 73A 74 74A 76 77
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty cycle registers CCP1CON<5:4>
Clear Timer ,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
10.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the f ollowing three e v ents
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
10.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
Note: The Timer2 postscaler (see Section 9.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
Note: If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
log( FPWM
log(2)
FOSC )bits
=
1997 Microchip Technology Inc. DS30390E-page 75
PIC16C7X
EXAMPLE 10-2: PWM PERIOD AND DUTY
CYCLE CALCULATION
Desired PWM frequency is 78.125 kHz,
Fosc = 20 MHz
TMR2 prescale = 1
1/78.125 kHz= [(PR2) + 1] • 4 • 1/20 MHz • 1
12.8 µs = [(PR2) + 1] • 4 • 50 ns • 1
PR2 = 63
Find the maximum resolution of the duty cycle that can
be used with a 78.125 kHz frequency and 20 MHz
oscillator:
1/78.125 kHz= 2PWM RESOLUTION • 1/20 MHz • 1
12.8 µs= 2
PWM RESOLUTION • 50 ns • 1
256 = 2PWM RESOLUTION
log(256) = (PWM Resolution) • log(2)
8.0 = PWM Resolution
At most, an 8-bit resolution duty cycle can be obtained
from a 78.125 kHz frequency and a 20 MHz oscillator,
i.e., 0 ≤ CCPR1L:CCP1CON<5:4> ≤ 255. Any value
greater than 255 will result in a 100% duty cycle.
In order to achieve higher resolution, the PWM fre-
quency must be decreased. In order to achieve higher
PWM frequency, the resolution must be decreased.
Table 10-3 lists example PWM frequencies and resolu-
tions f or Fosc = 20 MHz. The TMR2 prescaler and PR2
values are also shown.
10.3.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 regis-
ter.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enab le Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM oper ation.
TABLE 10-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 10-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1111
PR2 V alue 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh(2) PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh(2) PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh(2) CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu
1Ch(2) CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu
1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.
PIC16C7X
DS30390E-page 76 1997 Microchip Technology Inc.
TABLE 10-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh(2) PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh(2) PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 module’ s register 0000 0000 0000 0000
92h PR2 Timer2 module’ s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh(2) CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu
1Ch(2) CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu
1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.
1997 Microchip Technology Inc. DS30390E-page 77
PIC16C7X
11.0 SYNCHRONOUS SERIAL
PORT (SSP) MODULE
11.1 SSP Module Overview
The Synchronous Serial Por t (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SSP module in I2C mode works the same in all
PIC16C7X de vices that hav e an SSP module . Howe v er
the SSP Module in SPI mode has differences between
the PIC16C76/77 and the other PIC16C7X devices.
The register definitions and operational description of
SPI mode has been split into two sections because of
the differences between the PIC16C76/77 and the
other PIC16C7X devices. The default reset values of
both the SPI modules is the same regardless of the
device:
11.2 SPI Mode for PIC16C72/73/73A/74/74A..........78
11.3 SPI Mode for PIC16C76/77..............................83
11.4 I2C™ Overview................................................89
11.5 SSP I2C Operation...........................................93
Refer to Application Note AN578,
“Use of the SSP
Module in the I
2
C Multi-Master Environment.”
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X
DS30390E-page 78 1997 Microchip Technology Inc.
11.2 SPI Mode for PIC16C72/73/73A/74/74A
This section contains register definitions and opera-
tional characteristics of the SPI module for the
PIC16C72, PIC16C73, PIC16C73A, PIC16C74,
PIC16C74A.
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
— — D/A P S R/W UA BF R = Readable bit
W =Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5: D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2: R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit infor mation following the last address match. This bit is valid from the address
match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1: UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0: BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Applicable Devices
72 73 73A 74 74A 76 77
1997 Microchip Technology Inc. DS30390E-page 79
PIC16C7X
FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit
W =Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6: SSPOV: Receive Overflow Detect bit
In SPI mode
1 = A new b yte is received while the SSPBUF register is still holding the pre vious data. In case of ov erflow ,
the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the SSP-
BUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set
since each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is receiv ed while the SSPBUF register is still holding the pre vious byte. SSPO V is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5: SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4: CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge.
0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge.
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = Fosc/4
0001 = SPI master mode, clock = Fosc/16
0010 = SPI master mode, clock = Fosc/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled Master Mode (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X
DS30390E-page 80 1997 Microchip Technology Inc.
11.2.1 OPERATION OF SSP MODULE IN SPI
MODE
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally a four th pin may be used when in a slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by prog ramming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Output/Input data on the Rising/
Falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a Buff er register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
hav e been receiv ed, that b yte is mo v ed to the SSPBUF
register. Then the Buffer Full bit, BF (SSPSTAT<0>)
and flag bit SSPIF are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>) will be
set. User software must clear bit WCOL so that it can
be determined if the following write(s) to the SSPBUF
completed successfully. When the application software
is e xpecting to receive v alid data, the SSPB UF register
should be read before the next byte of data to transfer
is written to the SSPBUF register . The Buff er Full bit BF
(SSPSTAT<0>) indicates when the SSPBUF register
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the SSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPB UF register m ust be read and/or writ-
ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col-
lision does not occur. Example 11-1 shows the loading
of the SSPBUF (SSPSR) register f or data transmission.
The shaded instruction is only required if the received
data is meaningful.
Applicable Devices
72 73 73A 74 74A 76 77
EXAMPLE 11-1: LOADING THE SSPBUF
(SSPSR) REGISTER
The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR register is
not directly readable or writable, and can only be
accessed from addressing the SSPBUF register. Addi-
tionally, the SSP status register (SSPSTAT) indicates
the various status conditions.
FIGURE 11-3: SSP BLOCK DIAGRAM
(SPI MODE)
BSF STATUS, RP0 ;Specify Bank 1
LOOP BTFSS SSPSTAT, BF ;Has data been
;received
;(transmit
;complete)?
GOTO LOOP ;No
BCF STATUS, RP0 ;Specify Bank 0
MOVF SSPBUF, W ;W reg = contents
;of SSPBUF
MOVWF RXDATA ;Save in user RAM
MOVF TXDATA, W ;W reg = contents
; of TXDATA
MOVWF SSPBUF ;New data to xmit
Read Write
Internal
data bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0 shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
Applicable Devices
72 73 73A 74 74A 76 77
1997 Microchip Technology Inc. DS30390E-page 81
PIC16C7X
To enable the serial port, SSP enable bit SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear enable bit SSPEN, re-initialize SSPCON
register, and then set enable bit SSPEN. This config-
ures the SDI, SDO, SCK, and SS pins as serial port
pins. For the pins to behave as the serial port function,
they m ust have their data direction bits (in the TRIS reg-
ister) appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
•SS
must have TRISA<5> set (if implemented)
Any serial port function that is not desired may be o v er-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
Figure 11-4 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed cloc k edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) is to broadcast data by
the software protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive , the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate . As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched interrupt flag bit SSPIF (PIR1<3>) is
set.
The clock polarity is selected by appropriately progr am-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 11-5 and Figure 11-6 where the MSB is trans-
mitted first. In master mode, the SPI clock rate (bit r ate)
is user programmable to be one of the following:
• Fosc/4 (or TCY)
• Fosc/16 (or 4 • TCY)
• Fosc/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum bit cloc k frequency (at 20 MHz)
of 5 MHz. When in slave mode the external clock must
meet the minimum high and low times.
In sleep mode, the slave can transmit and receive data
and wake the device from sleep.
FIGURE 11-4: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF register)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF register)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X
DS30390E-page 82 1997 Microchip Technology Inc.
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set the for synchro-
nous slave mode to be enabled. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. If the SS pin is taken low without resetting
SPI mode, the transmission will continue from the
point at which it was taken high. External pull-up/
pull-down resistors ma y be desirab le, depending on the
application.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiv er the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL
FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL
TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'.
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SSPIF
bit7
bit7 bit0
bit6 bit5 bit4 bit3 bit2 bit1 bit0
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SSPIF
bit7
bit7 bit0
bit6 bit5 bit4 bit3 bit2 bit1 bit0
SS
Applicable Devices
72 73 73A 74 74A 76 77
1997 Microchip Technology Inc. DS30390E-page 83
PIC16C7X
11.3 SPI Mode for PIC16C76/77
This section contains register definitions and opera-
tional characteristics of the SPI module on the
PIC16C76 and PIC16C77 only.
FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C76/77)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF R = Readable bit
W =Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
bit 6: CKE: SPI Clock Edge Select (Figure 11-11, Figure 11-12, and Figure 11-13)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5: D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Star t bit is
detected last, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3: S: Star t bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
detected last, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2: R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1: UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0: BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X
DS30390E-page 84 1997 Microchip Technology Inc.
FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C76/77)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit
W =Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6: SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new b yte is received while the SSPBUF register is still holding the pre vious data. In case of ov erflow ,
the data in SSPSR is lost. Overflow can only occur in sla v e mode . The user must read the SSPB UF, e v en
if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each
new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is receiv ed while the SSPBUF register is still holding the pre vious byte. SSPO V is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5: SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4: CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled master mode (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
Applicable Devices
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PIC16C7X
11.3.1 SPI MODE FOR PIC16C76/77
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
Additionally a four th pin may be used when in a slave
mode of operation:
• Slave Select (SS) RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by prog ramming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8-bits of data
hav e been receiv ed, that b yte is mo v ed to the SSPBUF
register. Then the buffer full detect bit BF
(SSPSTAT<0>) and interrupt flag bit SSPIF (PIR1<3>)
are set. This double buffering of the received data
(SSPBUF) allows the ne xt byte to start reception before
reading the data that was just receiv ed. An y write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit WCOL
(SSPCON<7>) will be set. User softw are must clear the
WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed success-
fully. When the application software is expecting to
receive valid data, the SSPBUF should be read before
the next byte of data to transfer is written to the
SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates
when SSPBUF has been loaded with the receiv ed data
(transmission is complete). When the SSPB UF is read,
bit BF is cleared. This data may be irrelevant if the SPI
is only a transmitter. Generally the SSP Interrupt is
used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or writ-
ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col-
lision does not occur. Example 11-2 shows the loading
of the SSPBUF (SSPSR) for data transmission. The
shaded instruction is only required if the received data
is meaningful.
EXAMPLE 11-2: LOADING THE SSPBUF
(SSPSR) REGISTER
(PIC16C76/77)
BCF STATUS, RP1 ;Specify Bank 1
BSF STATUS, RP0 ;
LOOP BTFSS SSPSTAT, BF ;Has data been
;received
;(transmit
;complete)?
GOTO LOOP ;No
BCF STATUS, RP0 ;Specify Bank 0
MOVF SSPBUF, W ;W reg = contents
; of SSPBUF
MOVF TXDATA, W ;W reg = contents
; of TXDATA
MOVWF SSPBUF ;New data to xmit
The block diagram of the SSP module, when in SPI
mode (Figure 11-9), shows that the SSPSR is not
directly readable or writable , and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
FIGURE 11-9: SSP BLOCK DIAGRAM
(SPI MODE)(PIC16C76/77)
MOVWF RXDATA ;Save in user RAM
Read Write
Internal
data bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0 shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
Applicable Devices
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DS30390E-page 86 1997 Microchip Technology Inc.
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO , SCK, and SS pins as serial port pins . F or the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
•SS
must have TRISA<5> set
Any serial port function that is not desired may be o v er-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
Figure 11-10 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed cloc k edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application firmware. This leads to three scenarios for
data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) is to broadcast data by
the firmware protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive , the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate . As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR1<3>)
is set.
The clock polarity is selected by appropriately progr am-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 11-11, Figure 11-12, and Figure 11-13 where
the MSB is transmitted first. In master mode, the SPI
clock rate (bit rate) is user programmable to be one of
the following:
•F
OSC/4 (or TCY)
•F
OSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum bit cloc k frequency (at 20 MHz)
of 5 MHz. When in slave mode the external clock must
meet the minimum high and low times.
In sleep mode, the slave can transmit and receive data
and wake the device from sleep.
FIGURE 11-10: SPI MASTER/SLAVE CONNECTION (PIC16C76/77)
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock
Applicable Devices
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PIC16C7X
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set for the synchro-
nous slave mode to be enabled. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. If the SS pin is taken low without resetting
SPI mode, the transmission will continue from the
point at which it was taken high. External pull-up/
pull-down resistors ma y be desirab le, depending on the
application.
.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiv er the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
Note: When the SPI is in Slav e Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
Note: If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
FIGURE 11-11: SPI MODE TIMING, MASTER MODE (PIC16C76/77)
FIGURE 11-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) (PIC16C76/77)
SCK (CKP = 0,
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SDI (SMP = 1)
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO
bit7
bit7 bit0
bit0
CKE = 0)
CKE = 1)
CKE = 0)
CKE = 1)
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS (optional)
Applicable Devices
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PIC16C7X
DS30390E-page 88 1997 Microchip Technology Inc.
FIGURE 11-13: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) (PIC16C76/77)
TABLE 11-2: REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C76/77)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh.
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS
(not optional)
Applicable Devices
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PIC16C7X
11.4 I2C™ Overview
This section provides an overview of the Inter-Inte-
grated Circuit (I2C) bus, with Section 11.5 discussing
the operation of the SSP module in I2C mode.
The I2C b us is a two-wire serial interface developed by
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. The enhanced specification (fast mode) is also
supported. This device will communicate with both
standard and f ast mode devices if attached to the same
bus. The clock will determine the data rate.
The I2C interf ace emplo ys a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hard-
ware , except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXX software. Table 11-3 defines some of the
I2C bus terminology. For additional information on the
I2C interface specification, refer to the Philips docu-
ment “
The
I
2
C bus and ho w to use it.”
#939839340011,
which can be obtained from the Philips Corporation.
In the I2C interface protocol each device has an
address. When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
f er. That is they can be thought of as operating in either
of these two relations:
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
le vel when no de vice is pulling the line do wn. The n um-
ber of devices that may be attached to the I2C bus is
limited only by the maximum bus loading specification
of 400 pF.
11.4.1 INITIATING AND TERMINATING DATA
TRANSFER
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SD A) are pulled high
through the exter nal pull-up resistors. The START and
STOP conditions determine the star t and stop of data
transmission. The START condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high tr ansition of
the SD A when the SCL is high. Figure 11-14 shows the
START and STOP conditions. The master generates
these conditions f or starting and terminating data trans-
fer. Due to the definition of the START and STOP con-
ditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
FIGURE 11-14: START AND STOP
CONDITIONS
SDA
SCL SP
Start
Condition Change
of Data
Allowed
Change
of Data
Allowed
Stop
Condition
TABLE 11-3: I2C BUS TERMINOLOGY
Term Description
Transmitter The device that sends the data to the bus.
Receiver The device that receives the data from the bus.
Master The device which initiates the transfer, generates the clock and terminates the transfer.
Slave The device addressed by a master.
Multi-master More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization Procedure where the clock signals of two or more devices are synchronized.
Applicable Devices
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DS30390E-page 90 1997 Microchip Technology Inc.
11.4.2 ADDRESSING I2C DEVICES
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 11-15). The
more complex is the 10-bit address with a R/W bit
(Figure 11-16). For 10-bit address format, two bytes
must be transmitted with the first fiv e bits specifying this
to be a 10-bit address.
FIGURE 11-15: 7-BIT ADDRESS FORMAT
FIGURE 11-16: I2C 10-BIT ADDRESS FORMAT
11.4.3 TRANSFER ACKNOWLEDGE
All data must be transmitted per b yte, with no limit to the
number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowl-
edge bit (ACK) (Figure 11-17). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 11-14).
SR/W ACK
Sent by
Slave
slave address
S
R/W Read/Write pulse
MSb LSb
Start Condition
ACK Acknowledge
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
sent by slave
= 0 for write
S
R/W
ACK
- Start Condition
- Read/Write Pulse
- Acknowledge
FIGURE 11-17: SLAVE-RECEIVER
ACKNOWLEDGE
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the sla ve to mo ve the
received data or fetch the data it needs to transfer
before allowing the clock to star t. This wait state tech-
nique can also be implemented at the bit level,
Figure 11-18. The slav e will inherently stretch the clock,
when it is a transmitter , b ut will not when it is a receiv er .
The slave will have to clear the SSPCON<4> bit to
enable clock stretching when it is a receiver.
S
Data
Output by
Transmitter
Data
Output by
Receiver
SCL from
Master
Start
Condition Clock Pulse for
Acknowledgment
not acknowledge
acknowledge
1289
FIGURE 11-18: DATA TRANSFER WAIT STATE
12 789 123 • 89 P
SDA
SCL S
Start
Condition Address R/W ACK Wait
State Data ACK
MSB acknowledgment
signal from receiver acknowledgment
signal from receiver
byte complete
interrupt with receiver
clock line held low while
interrupts are serviced
Stop
Condition
Applicable Devices
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PIC16C7X
Figure 11-19 and Figure 11-20 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-21.
FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE
FIGURE 11-20: MASTER-RECEIVER SEQUENCE
FIGURE 11-21: COMBINED FORMAT
For 7-bit address:
SSlave Address
First 7 bits
S R/W A1Slave Address
Second byte A2
Data A Data P
A master transmitter addresses a slave receiver
with a 10-bit address.
A/A
Slave AddressR/W A Data A Data A/A P
'0' (write) data transferred
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(write)
For 10-bit address:
For 7-bit address:
SSlave Address
First 7 bits
S R/W A1Slave Address
Second byte A2
A master transmitter addresses a slave receiver
with a 10-bit address.
Slave AddressR/W A Data A Data A P
'1' (read) data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(write)
For 10-bit address:
Slave Address
First 7 bits
Sr R/W A3 AData A PData
(read)
Combined format:
S
Combined format - A master addresses a slave with a 10-bit address, then transmits
Slave AddressR/W A Data A/A Sr P
(read) Sr = repeated
Transfer direction of data and acknowledgment bits depends on R/W bits.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Slave Address
First 7 bits
Sr R/W A
(write)
data to this slave and reads data from this slave.
Slave Address
Second byte Data Sr Slave Address
First 7 bits R/W A Data A A PA A Data A/A Data
(read)
Slave Address R/W A Data A/A
Start Condition (write) Direction of transfer
may change at this point
(read or write)
(n bytes + acknowledge)
Applicable Devices
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DS30390E-page 92 1997 Microchip Technology Inc.
11.4.4 MULTI-MASTER
The I2C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transf er data at the same time, arbi-
tration and synchronization occur.
11.4.4.1 ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 11-22), and turns off its data output stage. A
master which lost arbitration can generate cloc k pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
FIGURE 11-22: MULTI-MASTER
ARBITRATION
(TWO MASTERS)
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning mas-
ter-transmitter may be addressing it.
Arbitration is not allowed between:
• A repeated START condition
• A STOP condition and a data bit
• A repeated START condition and a STOP condi-
tion
Care needs to be taken to ensure that these conditions
do not occur.
transmitter 1 loses arbitration
DATA 1 SDA
DATA 1
DATA 2
SDA
SCL
11.2.4.2 Clock Synchronization
Clock synchronization occurs after the devices have
started arbitration. This is performed using a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high tr an-
sition of this clock may not change the state of the SCL
line, if another device clock is still within its low period.
The SCL line is held low by the device with the longest
low period. Devices with shorter low periods enter a
high wait-state, until the SCL line comes high. When
the SCL line comes high, all devices star t counting off
their high periods. The first device to complete its high
period will pull the SCL line low. The SCL line high time
is determined by the device with the shortest high
period, Figure 11-23.
FIGURE 11-23: CLOCK SYNCHRONIZATION
CLK
1
CLK
2
SCL
wait
state start counting
HIGH period
counter
reset
Applicable Devices
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PIC16C7X
11.5 SSP I2C Operation
The SSP module in I2C mode fully implements all slav e
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifica-
tions as well as 7-bit and 10-bit addressing. Two pins
are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISC<4:3> bits. The SSP module functions are
enabled by setting SSP Enable bit SSPEN (SSP-
CON<5>).
FIGURE 11-24: SSP BLOCK DIAGRAM
(I2C MODE)
The SSP module has five registers for I2C operation.
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
Read Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBUF reg
Internal
data bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
shift
clock
MSb
SDI/ LSb
SDA
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I
2
C Slave mode (7-bit address)
•I
2
C Slave mode (10-bit address)
•I
2
C Slave mode (7-bit address), with start and
stop bit interrupts enabled
•I
2
C Slave mode (10-bit address), with start and
stop bit interrupts enabled
•I
2
C Firmware controlled Master Mode, slave is
idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer. The SSPSTAT register is read only.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
bef ore reading the last byte of receiv ed data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address . In 10-bit
mode, the user first needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low b yte of the address needs to be
loaded (A7:A0).
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X
DS30390E-page 94 1997 Microchip Technology Inc.
11.5.1 SLAVE MODE
In slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The ov erflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 11-4 shows what happens when a data transfer
byte is receiv ed, given the status of bits BF and SSPO V.
The shaded cells show the condition where user soft-
ware did not properly clear the overflow condition. Flag
bit BF is cleared by reading the SSPB UF register while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification as well as the requirement of the SSP
module is shown in timing parameter #100 and param-
eter #101.
11.5.1.1 ADDRESSING
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the f alling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received b y the sla ve (Figure 11-16). The fiv e Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7- 9 for
slave-transmitter:
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the first (high)
byte of Address , if match releases SCL line , this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 11-4: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
SSPSR → SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 No No Yes
Applicable Devices
72 73 73A 74 74A 76 77
1997 Microchip Technology Inc. DS30390E-page 95
PIC16C7X
11.5.1.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT reg-
ister is cleared. The receiv ed address is loaded into the
SSPBUF register.
When the address byte overflow condition exists, then
no ackno wledge (ACK) pulse is given. An ov erflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte . Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
FIGURE 11-25: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 123456789123456789123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Address
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X
DS30390E-page 96 1997 Microchip Technology Inc.
11.5.1.3 TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slav e devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
f alling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 11-26).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the mas-
ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave then monitors for
another occurrence of the START bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register , which also loads the SSPSR reg-
ister. Then pin RC3/SCK/SCL should be enabled by
setting bit CKP.
FIGURE 11-26: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACKTransmitting DataR/W = 1Receiving Address
123456789 123456789 P
cleared in software
SSPBUF is written in software From SSP interrupt
service routine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written-to
before the CKP bit can be set)
Applicable Devices
72 73 73A 74 74A 76 77
1997 Microchip Technology Inc. DS30390E-page 97
PIC16C7X
11.5.2 MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a reset or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I 2C bus may be taken when the P
bit is set, or the bus is idle and both the S and P bits are
clear.
In master mode the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
'1' data bit must have the TRISC<4> bit set (input) and
a '0' data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
slave mode idle (SSPM3:SSPM0 = 1011) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
11.5.3 MULTI-MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
le vel is output. If a high le vel is e xpected and a lo w lev el
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enab led, the slav e contin ues to
receive . If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed an A CK pulse will be generated.
If arbitration was lost during the data transf er stage , the
device will need to re-transfer the data at a later time.
TABLE 11-5: REGISTERS ASSOCIATED WITH I2C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP(2) CKE(2) D/A P S R/W UA BF 0000 0000 0000 0000
87h TRISC PORTC Data Direction register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16C73/73A/76, always maintain these bits clear.
2: The SMP and CKE bits are implemented on the PIC16C76/77 only. All other PIC16C7X devices have these two bits unim-
plemented, read as '0'.
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X
DS30390E-page 98 1997 Microchip Technology Inc.
FIGURE 11-27: OPERATION OF THE I2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE
IDLE_MODE (7-bit):
if (Addr_match) { Set interrupt;
if (R/W = 1) { Send ACK = 0;
set XMIT_MODE;
}
else if (R/W = 0) set RCV_MODE;
}
RCV_MODE:
if ((SSPBUF=Full) OR (SSPOV = 1))
{ Set SSPOV;
Do not acknowledge;
}
else { transfer SSPSR → SSPBUF;
send ACK = 0;
}
Receive 8-bits in SSPSR;
Set interrupt;
XMIT_MODE:
While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low;
Send byte;
Set interrupt;
if ( ACK Received = 1) { End of transmission;
Go back to IDLE_MODE;
}
else if ( ACK Received = 0) Go back to XMIT_MODE;
IDLE_MODE (10-Bit):
If (High_byte_addr_match AND (R/W = 0))
{ PRIOR_ADDR_MATCH = FALSE;
Set interrupt;
if ((SSPBUF = Full) OR ((SSPOV = 1))
{ Set SSPOV;
Do not acknowledge;
}
else { Set UA = 1;
Send ACK = 0;
While (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Receive Low_addr_byte;
Set interrupt;
Set UA = 1;
If (Low_byte_addr_match)
{ PRIOR_ADDR_MATCH = TRUE;
Send ACK = 0;
while (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Set RCV_MODE;
}
}
}
else if (High_byte_addr_match AND (R/W = 1)
{ if (PRIOR_ADDR_MATCH)
{ send ACK = 0;
set XMIT_MODE;
}
else PRIOR_ADDR_MATCH = FALSE;
}
Applicable Devices
72 73 73A 74 74A 76 77
1997 Microchip Technology Inc. DS30390E-page 99
PIC16C7X
12.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interf ace or SCI). The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral de vices such as CRT ter-
minals and personal computers, or it can be configured
Applicable Devices
72 73 73A 74 74A 76 77
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, Serial EEPROMs etc.
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to
be set in order to configure pins RC6/TX/CK and RC7/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter .
FIGURE 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D R = Readable bit
W =Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6: TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5: TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4: SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3: Unimplemented: Read as '0'
bit 2: BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
Note: F or the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may expe-
rience a high rate of receive errors . It is recommended that BRGH = 0. If you desire a higher
baud rate than BRGH = 0 can support, refer to the device errata for additional information,
or use the PIC16C76/77.
0 = Low speed
Synchronous mode
Unused in this mode
bit 1: TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0: TX9D: 9th bit of transmit data. Can be parity bit.
PIC16C7X
DS30390E-page 100 1997 Microchip Technology Inc.
FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x
SPEN RX9 SREN CREN — FERR OERR RX9D R = Readable bit
W =Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6: RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5: SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4: CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3: Unimplemented: Read as '0'
bit 2: FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1: OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0: RX9D: 9th bit of received data (Can be parity bit)
1997 Microchip Technology Inc. DS30390E-page 101
PIC16C7X
12.1 USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode bit BRGH is ignored.
Table 12-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Given the desired baud r ate and F osc, the nearest inte-
ger value for the SPBRG register can be calculated
using the for mula in Table 12-1. From this, the error in
baud rate can be determined.
Example 12-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
Applicable Devices
72 73 73A 74 74A 76 77
EXAMPLE 12-1: CALCULATING BAUD
RATE ERROR
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new v alue to the SPBRG register, causes the
BRG timer to be reset (or cleared), this ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
Note: For the PIC16C73/73A/74/74A, the asyn-
chronous high speed mode (BRGH = 1)
may experience a high rate of receive
errors. It is recommended that BRGH = 0.
If you desire a higher baud rate than
BRGH = 0 can suppor t, refer to the device
errata for additional inf ormation, or use the
PIC16C76/77.
Desired Baud rate = Fosc / (64 (X + 1))
9600 = 16000000 /(64 (X + 1))
X=25.042 = 25
Calculated Baud Rate=16000000 / (64 (25 + 1))
= 9615
Error = (Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
= (9615 - 9600) / 9600
= 0.16%
TABLE 12-1: BAUD RATE FORMULA
TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1)) Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
PIC16C7X
DS30390E-page 102 1997 Microchip Technology Inc.
TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE
TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
7.15909 MHz SPBRG
value
(decimal)
KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
0.3 NA - - NA - - NA - - NA - -
1.2 NA - - NA - - NA - - NA - -
2.4 NA - - NA - - NA - - NA - -
9.6 NA - - NA - - 9.766 +1.73 255 9.622 +0.23 185
19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92
76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22
96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18
300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5
500 500 0 9 500 0 7 500 0 4 NA - -
HIGH 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0
LOW 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255
BAUD
RATE
(K)
FOSC = 5.0688 MHz 4 MHz
SPBRG
value
(decimal)
3.579545 MHz
SPBRG
value
(decimal)
1 MHz
SPBRG
value
(decimal)
32.768 kHz
SPBRG
value
(decimal)
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
0.3 NA - - NA - - NA - - NA - - 0.303 +1.14 26
1.2 NA - - NA - - NA - - 1.202 +0.16 207 1.170 -2.48 6
2.4 NA - - NA - - NA - - 2.404 +0.16 103 NA - -
9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 NA - -
19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 NA - -
76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 NA - -
96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 NA - - NA - -
300 316.8 +5.60 3 NA - - 298.3 -0.57 2 NA - - NA - -
500 NA - - NA - - NA - - NA - - NA - -
HIGH 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0
LOW 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
7.15909 MHz SPBRG
value
(decimal)KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
0.3 NA - - NA - - NA - - NA - -
1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92
2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46
9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11
19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5
76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 NA - -
96 104.2 +8.51 2 NA - - NA - - NA - -
300 312.5 +4.17 0 NA - - NA - - NA - -
500 NA - - NA - - NA - - NA - -
HIGH 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0
LOW 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255
BAUD
RATE
(K)
FOSC = 5.0688 MHz 4 MHz
SPBRG
value
(decimal)
3.579545 MHz
SPBRG
value
(decimal)
1 MHz
SPBRG
value
(decimal)
32.768 kHz
SPBRG
value
(decimal)KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1
1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 NA - -
2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 NA - -
9.6 9.9 +3.13 7 NA - - 9.322 -2.90 5 NA - - NA - -
19.2 19.8 +3.13 3 NA - - 18.64 -2.90 2 NA - - NA - -
76.8 79.2 +3.13 0 NA - - NA - - NA - - NA - -
96 NA - - NA - - NA - - NA - - NA - -
300 NA - - NA - - NA - - NA - - NA - -
500 NA - - NA - - NA - - NA - - NA - -
HIGH 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0
LOW 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255
1997 Microchip Technology Inc. DS30390E-page 103
PIC16C7X
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
7.16 MHz SPBRG
value
(decimal)KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46
19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22
38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11
57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7
115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3
250 250 0 4 250 0 3 NA - - NA - -
625 625 0 1 NA - - 625 0 0 NA - -
1250 1250 0 0 NA - - NA - - NA - -
BAUD
RATE
(K)
FOSC = 5.068 MHz SPBRG
value
(decimal)
4 MHz SPBRG
value
(decimal)
3.579 MHz SPBRG
value
(decimal)
1 MHz SPBRG
value
(decimal)
32.768 kHz SPBRG
value
(decimal)KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
9.6 9.6 0 32 NA - - 9.727 +1.32 22 8.928 -6.99 6 NA - -
19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 NA - -
38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 NA - -
57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 NA - -
115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 NA - - NA - -
250 NA - - NA - - 223.721 -10.51 0 NA - - NA - -
625 NA - - NA - - NA - - NA - - NA - -
1250 NA - - NA - - NA - - NA - - NA - -
Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may experience a high
rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0
can support, refer to the device errata for additional information, or use the PIC16C76/77.
PIC16C7X
DS30390E-page 104 1997 Microchip Technology Inc.
12.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth fall-
ing edges of a x16 clock (Figure 12-3). If bit BRGH is
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first f alling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
FIGURE 12-3: RX PIN SAMPLING SCHEME. BRGH = 0 (PIC16C73/73A/74/74A)
FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A)
FIGURE 12-5: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A)
RX
baud CLK
x16 CLK
Start bit Bit0
Samples
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Baud CLK for all but start bit
(RC7/RX/DT pin)
RX pin
baud clk
x4 clk
Q2, Q4 clk
Start Bit bit0 bit1
First falling edge after RX pin goes low
Second rising edge
Samples Samples Samples
1234123412
RX pin
baud clk
x4 clk
Q2, Q4 clk
Start Bit bit0
First falling edge after RX pin goes low
Second rising edge
Samples
1234
Baud clk for all but start bit
1997 Microchip Technology Inc. DS30390E-page 105
PIC16C7X
FIGURE 12-6: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 (PIC16C76/77)
RX
baud CLK
x16 CLK
Start bit Bit0
Samples
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Baud CLK for all but start bit
(RC7/RX/DT pin)
PIC16C7X
DS30390E-page 106 1997 Microchip Technology Inc.
12.2 USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-to-
zero (NRZ) format (one start bit, eight or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USAR T’s transmitter and receiver are
functionally independent but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware , but can be implemented in softw are (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
12.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 12-7. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
Applicable Devices
72 73 73A 74 74A 76 77
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware . It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register. Sta-
tus bit TRMT is a read only bit which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 12-7). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first star ted, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate tr ans-
fer to TSR resulting in an empty TXREG. A back-to-
back transfer is thus possible (Figure 12-9). Clearing
enable bit TXEN during a transmission will cause the
transmission to be abor ted and will reset the transmit-
ter. As a result the RC6/TX/CK pin will revert to hi-
impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transf er of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit maybe loaded in the TSR regis-
ter.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
Note 2: Flag bit TXIF is set when enab le bit TXEN
is set.
FIGURE 12-7: USART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG register
TSR register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
• • •
1997 Microchip Technology Inc. DS30390E-page 107
PIC16C7X
Steps to follow when setting up an Asynchronous
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1)
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 12-8: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 12-9: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
WORD 1 Stop Bit
WORD 1
Transmit Shift Reg
Start Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT bit
(Transmit shift
reg. empty flag)
Transmit Shift Reg.
Write to TXREG
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 1 Word 2
WORD 1 WORD 2
Start Bit Stop Bit Start Bit
Transmit Shift Reg.
WORD 1 WORD 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
PIC16C7X
DS30390E-page 108 1997 Microchip Technology Inc.
12.2.2 USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 12-10.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receiv e serial shifter oper-
ates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receiv e (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transf erred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hardw are. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register, i.e. it is a two deep FIFO. It is
possible for two bytes of data to be receiv ed and trans-
f erred to the RCREG FIFO and a third byte begin shift-
ing to the RSR register. On the detection of the STOP
bit of the third byte, if the RCREG register is still full
then overrun error bit OERR (RCSTA<1>) will be set.
The word in the RSR will be lost. The RCREG register
can be read twice to retrieve the two b ytes in the FIFO.
Overrun bit OERR has to be cleared in software. This
is done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, so it
is essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG, will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
FIGURE 12-10: USART RECEIVE BLOCK DIAGRAM
FIGURE 12-11: ASYNCHRONOUS RECEPTION
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR register
MSb LSb
RX9D RCREG register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷ 64
÷ 16
or Stop Start
(8) 710
RX9
• • •
Start
bit bit7/8
bit1bit0 bit7/8 bit0Stop
bit
Start
bit Start
bit
bit7/8 Stop
bit
RX (pin)
reg
Rcv buffer reg
Rcv shift
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
WORD 1
RCREG WORD 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
1997 Microchip Technology Inc. DS30390E-page 109
PIC16C7X
Steps to follow when setting up an Asynchronous
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1).
2. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
PIC16C7X
DS30390E-page 110 1997 Microchip Technology Inc.
12.3 USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RC6/TX/CK and RC7/RX/DT I/O pins to
CK (clock) and DT (data) lines respectiv ely. The Master
mode indicates that the processor transmits the master
clock on the CK line. The Master mode is entered by
setting bit CSRC (TXSTA<7>).
12.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 12-7. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit, TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware . It will reset only when new data is loaded into the
TXREG register . While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the ne xt av ailable
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 12-12). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 12-13). This is advantageous when slow
baud rates are selected, since the BRG is k ept in reset
when bits TXEN, CREN, and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally when transmission is first
star ted, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back trans-
fers are possible.
Applicable Devices
72 73 73A 74 74A 76 77
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will rev ert to hi-imped-
ance. If either bit CREN or bit SREN is set, during a
transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
reset although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single w ord), then after the single word is
received, bit SREN will be cleared and the serial port
will re vert back to tr ansmitting since bit TXEN is still set.
The DT line will immediately switch from hi-impedance
receive mode to transmit and start driving. To avoid
this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register . This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR w as empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
1997 Microchip Technology Inc. DS30390E-page 111
PIC16C7X
TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHR ONOUS MASTER TRANSMISSION
FIGURE 12-12: SYNCHRONOUS TRANSMISSION
FIGURE 12-13: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USAR T Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
Bit 0 Bit 1 Bit 7
WORD 1
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 2 Bit 0 Bit 1 Bit 7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
(Interrupt flag)
TRMT
TXEN bit '1' '1'
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
WORD 2
TRMT bit
Write word1 Write word2
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit0 bit1 bit2 bit6 bit7
TXEN bit
PIC16C7X
DS30390E-page 112 1997 Microchip Technology Inc.
12.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the tr ansfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
reset by the hardware. In this case it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e. it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
1997 Microchip Technology Inc. DS30390E-page 113
PIC16C7X
FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(interrupt)
Read
RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.
Q3Q4Q1Q2Q3Q4Q1 Q2Q3Q4Q2 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2 Q3Q4
'0'
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
'0'
Q1Q2Q3Q4
PIC16C7X
DS30390E-page 114 1997 Microchip Technology Inc.
12.4 USART Synchronous Slave Mode
Synchronous slave mode diff ers from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
12.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register .
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1. Enable the synchronous sla v e serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
Applicable Devices
72 73 73A 74 74A 76 77
12.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in slave mode.
If receive is enabled, by setting bit CREN, prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the prog r am will br anch to the interrupt v ector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, then set enable bit
RCIE.
3. If 9-bit reception is desired, then set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
1997 Microchip Technology Inc. DS30390E-page 115
PIC16C7X
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USAR T Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
PIC16C7X
DS30390E-page 116 1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 117
PIC16C7X
FIGURE 13-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON R =Readable bit
W =Writable bit
U =Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an internal RC oscillator)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2: GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conv ersion not in progress (This bit is automatically cleared by hardware when the A/D conv ersion
is complete)
bit 1: Unimplemented: Read as '0'
bit 0: ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Note 1: A/D channels 5, 6, and 7 are implemented on the PIC16C74/74A/77 only.
13.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has five
inputs for the PIC16C72/73/73A/76, and eight for the
PIC16C74/74A/77.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Applica-
tion Note AN546 for use of A/D Conver ter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approxima-
tion. The analog reference voltage is software select-
able to either the de vice’s positive supply v oltage (VDD)
or the voltage level on the RA3/AN3/VREF pin.
Applicable Devices
72 73 73A 74 74A 76 77
The A/D conv erter has a unique feature of being ab le to
operate while the de vice is in SLEEP mode. To operate
in sleep , the A/D conv ersion clock must be derived from
the A/D’s internal RC oscillator.
The A/D module has three registers. These registers
are: • A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Figure 13-1, controls
the operation of the A/D module. The ADCON1 regis-
ter, shown in Figure 13-2, configures the functions of
the por t pins. The por t pins can be configured as ana-
log inputs (RA3 can also be a voltage reference) or as
digital I/O.
PIC16C7X
DS30390E-page 118 1997 Microchip Technology Inc.
FIGURE 13-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit
W =Writable bit
U =Unimplemented
bit, read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
Note 1: RE0, RE1, and RE2 are implemented on the PIC16C74/74A/77 only.
A = Analog input
D = Digital I/O
PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF
000 AAAAA AAAVDD
001 AAAAVREF AAARA3
010 AAAAA DDDV
DD
011 AAAAVREF DDDRA3
100 AADDA DDDV
DD
101 AADDVREF DDDRA3
11x DDDDD DDD—
1997 Microchip Technology Inc. DS30390E-page 119
PIC16C7X
The ADRES register contains the result of the A/D con-
version. When the A/D conversion is complete, the
result is loaded into the ADRES register , the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF is set. The block diagrams of the A/D module are
shown in Figure 13-3.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To deter mine acquisition time, see Section 13.1.
After this acquisition time has elapsed the A/D conver-
sion can be star ted. The following steps should be fol-
lowed for doing an A/D conversion:
1. Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result register (ADRES), clear bit
ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 13-3: A/D BLOCK DIAGRAM
(Input voltage)
VIN
VREF
(Reference
voltage)
VDD
PCFG2:PCFG0
CHS2:CHS0
000 or
010 or
100
001 or
011 or
101
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
RA5/AN4
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
111
110
101
100
011
010
001
000
A/D
Converter
Note 1: Not available on PIC16C72/73/73A/76.
PIC16C7X
DS30390E-page 120 1997 Microchip Technology Inc.
13.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 13-4. The source
impedance (RS) and the internal sampling s witch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (R SS) imped-
ance varies ov er the device voltage (VDD), Figure 13-4.
The source impedance affects the offset voltage at the
analog input (due to pin leakage current). The maxi-
mum recommended impedance f or analog sources
is 10 kΩ. After the analog input channel is selected
(changed) this acquisition must be done bef ore the con-
version can be started.
To calculate the minimum acquisition time,
Equation 13-1 may be used. This equation calculates
the acquisition time to within 1/2 LSb error is used (512
steps for the A/D). The 1/2 LSb error is the maximum
error allowed for the A/D to meet its specified accuracy.
EQUATION 13-1: A/D MINIMUM CHARGING
TIME
VHOLD = (VREF - (VREF/512)) • (1 - e(-TCAP/CHOLD(RIC + RSS + RS)))
Given: VHOLD = (VREF/512), for 1/2 LSb resolution
The above equation reduces to:
TCAP = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)
Example 13-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
CHOLD = 51.2 pF
Rs = 10 kΩ
1/2 LSb error
Applicable Devices
72 73 73A 74 74A 76 77
VDD = 5V → Rss = 7 kΩ
Temp (application system max.) = 50°C
VHOLD = 0 @ t = 0
EXAMPLE 13-1: CALCULATING THE
MINIMUM REQUIRED
ACQUISITION TIME
TACQ = Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
TACQ =5 µs + TCAP + [(Temp - 25°C)(0.05 µs/°C)]
TCAP =-CHOLD (RIC + RSS + RS) ln(1/511)
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
-51.2 pF (18 kΩ) ln(0.0020)
-0.921 µs (-6.2364)
5.747 µs
TACQ =5 µs + 5.747 µs + [(50°C - 25°C)(0.05 µs/°C)]
10.747 µs + 1.25 µs
11.997 µs
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specifi-
cation.
Note 4: After a conversion has completed, a
2.0TAD dela y must complete bef ore acqui-
sition can begin again. During this time
the holding capacitor is not connected to
the selected A/D input channel.
FIGURE 13-4: ANALOG INPUT MODEL
CPIN
VA
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I leakage
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
5 6 7 8 9 10 11
( kΩ )
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
1997 Microchip Technology Inc. DS30390E-page 121
PIC16C7X
13.2 Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•2T
OSC
•8TOSC
• 32TOSC
• Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 13-1 shows the resultant TAD times der ived from
the device operating frequencies and the A/D clock
source selected.
Applicable Devices
72 73 73A 74 74A 76 77
13.3 Configuring Analog Port Pins
The ADCON1, TRISA, and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Applicable Devices
72 73 73A 74 74A 76 77
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
Note 2: Analog lev els on an y pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specification.
TABLE 13-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Device Frequency
Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz
2TOSC 00 100 ns(2) 400 ns(2) 1.6 µs6 µs
8TOSC 01 400 ns(2) 1.6 µs 6.4 µs24 µs(3)
32TOSC 10 1.6 µs 6.4 µs25.6 µs(3) 96 µs(3)
RC(5) 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
sleep operation only.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
PIC16C7X
DS30390E-page 122 1997 Microchip Technology Inc.
13.4 A/D Conversions
Example 13-2 shows how to perform an A/D conver-
sion. The RA pins are configured as analog inputs. The
analog reference (VREF) is the device VDD. The A/D
interrupt is enabled, and the A/D conversion clock is
FRC. The conversion is performed on the RA0 pin
(channel 0).
Applicable Devices
72 73 73A 74 74A 76 77
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the par tially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last v alue written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started on
the selected channel.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
EXAMPLE 13-2: A/D CONVERSION
BSF STATUS, RP0 ; Select Bank 1
BCF STATUS, RP1 ; PIC16C76/77 only
CLRF ADCON1 ; Configure A/D inputs
BSF PIE1, ADIE ; Enable A/D interrupts
BCF STATUS, RP0 ; Select Bank 0
MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected
MOVWF ADCON0 ;
BCF PIR1, ADIF ; Clear A/D interrupt flag bit
BSF INTCON, PEIE ; Enable peripheral interrupts
BSF INTCON, GIE ; Enable all interrupts
;
; Ensure that the required sampling time for the selected input channel has elapsed.
; Then the conversion may be started.
;
BSF ADCON0, GO ; Start A/D Conversion
: ; The ADIF bit will be set and the GO/DONE bit
: ; is cleared upon completion of the A/D Conversion.
1997 Microchip Technology Inc. DS30390E-page 123
PIC16C7X
13.4.1 FASTER CONVERSION - LOWER
RESOLUTION TRADE-OFF
Not all applications require a result with 8-bits of reso-
lution, but ma y instead require a f aster conv ersion time.
The A/D module allows users to make the trade-off of
conversion speed to resolution. Regardless of the res-
olution required, the acquisition time is the same. To
speed up the conversion, the clock source of the A/D
module may be switched so that the TAD time violates
the minimum specified time (see the applicable electri-
cal specification). Once the TAD time violates the mini-
mum specified time, all the following A/D result bits are
not valid (see A/D Conversion Timing in the Electrical
Specifications section.) The cloc k sources may only be
switched between the three oscillator versions (cannot
be switched from/to RC). The equation to determine
the time before the oscillator can be switched is as fol-
lows:
Conversion time = 2TAD + N • TAD + (8 - N)(2TOSC)
Where: N = number of bits of resolution required.
Since the TAD is based from the device oscillator, the
user must use some method (a timer, software loop,
etc.) to determine when the A/D oscillator may be
changed. Example 13-3 shows a comparison of time
required for a conversion with 4-bits of resolution, ver-
sus the 8-bit resolution conversion. The example is for
devices operating at 20 MHz and 16 MHz (The A/D
clock is programmed for 32TOSC), and assumes that
immediately after 6TAD, the A/D clock is programmed
for 2TOSC.
The 2TOSC violates the minimum T AD time since the last
4-bits will not be converted to correct values.
EXAMPLE 13-3: 4-BIT vs. 8-BIT CONVERSION TIMES
Freq. (MHz)(1) Resolution
4-bit 8-bit
TAD 20 1.6 µs 1.6 µs
16 2.0 µs 2.0 µs
TOSC 20 50 ns 50 ns
16 62.5 ns 62.5 ns
2TAD + N • TAD + (8 - N)(2TOSC) 20 10 µs 16 µs
16 12.5 µs 20 µs
Note 1: PIC16C7X devices have a minimum TAD time of 1.6 µs.
PIC16C7X
DS30390E-page 124 1997 Microchip Technology Inc.
13.5 A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another cloc k option (not
RC), a SLEEP instruction will cause the present conv er-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
13.6 A/D Accuracy/Error
The absolute accuracy specified for the A/D converter
includes the sum of all contributions for quantization
error , integral error , diff erential error , full scale error , off-
set error, and monotonicity. It is defined as the maxi-
mum de viation from an actual transition v ersus an ideal
transition for any code. The absolute error of the A/D
converter is specified at < ±1 LSb for V DD = VREF (ov er
the device’s specified operating range). However, the
accuracy of the A/D converter will degrade as VDD
diverges from VREF.
For a given range of analog inputs, the output digital
code will be the same. This is due to the quantization of
the analog input to a digital code. Quantization error is
typically ± 1/2 LSb and is inherent in the analog to dig-
ital conversion process. The only way to reduce quan-
tization error is to increase the resolution of the A/D
converter.
Offset error measures the first actual transition of a
code versus the first ideal transition of a code. Offset
error shifts the entire transfer function. Offset error can
be calibrated out of a system or introduced into a sys-
tem through the interaction of the total leakage current
and source impedance at the analog input.
Applicable Devices
72 73 73A 74 74A 76 77
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perfor m an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruc-
tion that sets the GO/DONE bit.
Applicable Devices
72 73 73A 74 74A 76 77
Gain error measures the maximum de viation of the last
actual transition and the last ideal transition adjusted
f or offset error. This error appears as a change in slope
of the transfer function. The difference in gain error to
full scale error is that full scale does not take offset error
into account. Gain error can be calibrated out in soft-
ware.
Linearity error refers to the uniformity of the code
changes. Linearity errors cannot be calibrated out of
the system. Integral non-linearity error measures the
actual code transition versus the ideal code transition
adjusted by the gain error for each code.
Diff erential non-linearity measures the maximum actual
code width versus the ideal code width. This measure
is unadjusted.
The maximum pin leakage current is ± 1 µA.
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high fre-
quencies, TAD should be derived from the device oscil-
lator. TAD must not violate the minimum and should be
≤ 8 µs for preferred operation. This is because TAD,
when derived from TOSC, is kept away from on-chip
phase clock tr ansitions . This reduces , to a large extent,
the effects of digital switching noise. This is not possi-
ble with the RC deriv ed clock. The loss of accur acy due
to digital switching noise can be significant if many I/O
pins are active.
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
13.7 Effects of a RESET
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The value that is in the ADRES register is not modified
for a Power-on Reset. The ADRES register will contain
unknown data after a Power-on Reset.
Applicable Devices
72 73 73A 74 74A 76 77
1997 Microchip Technology Inc. DS30390E-page 125
PIC16C7X
13.8 Use of the CCP Trigger
An A/D conversion can be started by the “special ev ent
trigger” of the CCP2 module (CCP1 on the PIC16C72
only). This requires that the CCP2M3:CCP2M0 bits
(CCP2CON<3:0>) be programmed as 1011 and that
the A/D module is enabled (ADON bit is set). When the
trigger occurs, the GO/DONE bit will be set, starting the
A/D conversion, and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
acquisition period with minimal software overhead
(moving the ADRES to the desired location). The
appropriate analog input channel must be selected and
the minimum acquisition done bef ore the “special e vent
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
13.9 Connection Considerations
If the input voltage e xceeds the rail v alues (VSS or VDD)
by greater than 0.2V, then the accuracy of the conver-
sion is out of specification.
An e xternal RC filter is sometimes added f or anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor , zener diode, etc.) should
have very little leakage current at the pin.
13.10 Transfer Function
The ideal transfer function of the A/D converter is as
f ollows: the first tr ansition occurs when the analog input
voltage (VAIN) is Analog VREF/256 (Figure 13-5).
Applicable Devices
72 73 73A 74 74A 76 77
Note: In the PIC16C72, the "special event trig-
ger" is implemented in the CCP1 module.
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 13-5: A/D TRANSFER FUNCTION
13.11 References
A very good reference for understanding A/D convert-
ers is the "Analog-Digital Conversion Handbook" third
edition, published by Prentice Hall (ISBN
0-13-03-2848-0).
Digital code output
FFh
FEh
04h
03h
02h
01h
00h
0.5 LSb
1 LSb
2 LSb
3 LSb
4 LSb
255 LSb
256 LSb
(full scale)
Analog input voltage
PIC16C7X
DS30390E-page 126 1997 Microchip Technology Inc.
FIGURE 13-6: FLOWCHART OF A/D OPERATION
TABLE 13-2: REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C72
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Acquire
ADON = 0
ADON = 0?
GO = 0?
A/D Clock
GO = 0
ADIF = 0
Abort Conversion
SLEEP
Power-down A/D Wait 2 TAD
Wake-up
Yes
No
Yes
No
No
Yes
Finish Conversion
GO = 0
ADIF = 1
Device in
No
Yes
Finish Conversion
GO = 0
ADIF = 1
Wait 2 TAD
Stay in Sleep
Selected Channel
= RC? SLEEP
No
Yes
Instruction?
Start of A/D
Conversion Delayed
1 Instruction Cycle
From Sleep?
Power-down A/D
Yes
No
Wait 2 TAD
Finish Conversion
GO = 0
ADIF = 1
SLEEP?
1997 Microchip Technology Inc. DS30390E-page 127
PIC16C7X
TABLE 13-3: SUMMARY OF A/D REGISTERS, PIC16C73/73A/74/74A/76/77
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73/73A/76, always maintain these bits clear.
PIC16C7X
DS30390E-page 128 1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 129
PIC16C7X
14.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC16CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, pro vide pow er saving oper ating modes and off er
code protection. These are:
• Oscillator selection
• Reset
- Power-on Reset (POR)
- P ower-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• W atchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
The PIC16CXX has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
Applicable Devices
72 73 73A 74 74A 76 77
the chip in reset until the crystal oscillator is stable . The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-do wn mode . The user can w ak e-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Sev eral oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
14.1 Configuration Bits
The configuration bits can be progr ammed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 14-1: CONFIGURATION WORD FOR PIC16C73/74
— — — — — — — — CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
Address 2007h
bit13 bit0
bit 13-5: Unimplemented: Read as '1'
bit 4: CP1:CP0: Code protection bits
11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 3: PWRTE: Power-up Timer Enable bit
1 = Power-up Timer enabled
0 = Power-up Timer disabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
PIC16C7X
DS30390E-page 130 1997 Microchip Technology Inc.
FIGURE 14-2: CONFIGURATION WORD FOR PIC16C72/73A/74A/76/77
CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
Address 2007h
bit13 bit0
bit 13-8 CP1:CP0: Code Protection bits (2)
5-4: 11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 7: Unimplemented: Read as '1'
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
1997 Microchip Technology Inc. DS30390E-page 131
PIC16C7X
14.2 Oscillator Configurations
14.2.1 OSCILLATOR TYPES
The PIC16CXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
• LP Low Power Crystal
• XT Crystal/Resonator
• HS High Speed Crystal/Resonator
• RC Resistor/Capacitor
14.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes a cr ystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 14-3). The
PIC16CXX Oscillator design requires the use of a par-
allel cut cr ystal. Use of a series cut cr ystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 14-4).
FIGURE 14-3: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 14-4: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Applicable Devices
72 73 73A 74 74A 76 77
C1
C2
XTAL
OSC2
Note1
OSC1
RFSLEEP
To internal
logic
PIC16CXX
RS
See Table 14-1 and Table 14-2 for recommended values
of C1 and C2.
Note 1: A series resistor may be required for AT strip
cut crystals.
OSC1
OSC2
Open
Clock from
ext. system PIC16CXX
TABLE 14-1: CERAMIC RESONATORS
TABLE 14-2: CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murata Erie CSA8.00MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
All resonators used did not have built-in capacitors.
Osc Type Crystal
Freq Cap. Range
C1 Cap. Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
These values are for design guidance only. See
notes at bottom of page.
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 14-1).
2: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
4: Rs may be required in HS mode as well as
XT mode to avoid overdriving crystals with
low drive level specification.
PIC16C7X
DS30390E-page 132 1997 Microchip Technology Inc.
14.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepack-
aged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types
of crystal oscillator circuits can be used; one with series
resonance, or one with parallel resonance.
Figure 14-5 shows implementation of a parallel reso-
nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inv erter performs the 180-degree phase shift that a par-
allel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ potenti-
ometer biases the 74AS04 in the linear region. This
could be used for external oscillator designs.
FIGURE 14-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Figure 14-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental fre-
quency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator cir-
cuit. The 330 kΩ resistors provide the negative feed-
back to bias the inverters in their linear region.
FIGURE 14-6: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
20 pF
+5V
20 pF
10k 4.7k
10k
74AS04
XTAL
10k
74AS04
CLKIN
To Other
Devices
PIC16CXX
330 kΩ
74AS04 74AS04 PIC16CXX
CLKIN
To Other
Devices
XTAL
330 kΩ
74AS04
0.1 µF
14.2.4 RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (Rext) and capacitor (Cext) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to nor mal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
Cext values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 14-7 shows how the R/C combina-
tion is connected to the PIC16CXX. For Rext values
below 2.2 kΩ, the oscillator operation may become
unstable, or stop completely. For very high Rext values
(e.g. 1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or pack-
age lead frame capacitance.
See characterization data for desired de vice f or RC fre-
quency variation from part to part due to normal pro-
cess variation. The v ariation is larger for larger R (since
leakage current variation will aff ect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
See characterization data for desired device for varia-
tion of oscillator frequency due to VDD for given Rext/
Ce xt values as well as frequency variation due to oper-
ating temperature for given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (see Figure 3-4 for
waveform).
FIGURE 14-7: RC OSCILLATOR MODE
OSC2/CLKOUT
Cext
VDD
Rext
VSS
PIC16CXX
OSC1
Fosc/4
Internal
clock
1997 Microchip Technology Inc. DS30390E-page 133
PIC16C7X
14.3 Reset
The PIC16CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR) (PIC16C72/73A/74A/76/
77)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The T O and PD bits are set or cleared diff er-
ently in different reset situations as indicated in
Table 14-5 and Table 14-6. These bits are used in soft-
ware to determine the nature of the reset. See
Table 14-8 for a full description of reset states of all reg-
isters.
Applicable Devices
72 73 73A 74 74A 76 77
A simplified bloc k diag ram of the on-chip reset circuit is
shown in Figure 14-8.
The PIC16C72/73A/74A/76/77 have a MCLR noise fil-
ter in the MCLR reset path. The filter will detect and
ignore small pulses.
It should be noted that a WDT Reset
does not drive
MCLR pin low.
FIGURE 14-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Reset
Enable OST
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: Brown-out Reset is implemented on the PIC16C72/73A/74A/76/77.
3: See Table 14-3 and Table 14-4 for time-out situations.
Brown-out
Reset BODEN
(1)
(2)
(3)
PIC16C7X
DS30390E-page 134 1997 Microchip Technology Inc.
14.4 Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST), and Brown-out Reset
(BOR)
14.4.1 POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate e xternal RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met. Brown-out Reset may be used to meet the startup
conditions.
For additional information, refer to Application Note
AN607, "
P ower-up Trouble Shooting
."
14.4.2 PO WER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is activ e. The
PWR T’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
Applicable Devices
72 73 73A 74 74A 76 77
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
14.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWR T dela y is o v er. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
14.4.4 BROWN-OUT RESET (BOR)
A configuration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for
greater than parameter #35, the bro wn-out situation will
reset the chip. A reset may not occur if VDD falls below
4.0V for less than parameter #35. The chip will remain
in Brown-out Reset until VDD rises above BVDD. The
Power-up Timer will now be invoked and will keep the
chip in RESET an additional 72 ms. If VDD drops below
BVDD while the Power-up Timer is running, the chip will
go back into a Brown-out Reset and the Power-up
Timer will be initialized. Once VDD rises above BVDD,
the Power-up Timer will execute a 72 ms time delay.
The Power-up Timer should always be enabled when
Brown-out Reset is enabled. Figure 14-9 shows typi-
cal brown-out situations.
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 14-9: BROWN-OUT SITUATIONS
72 ms
BVDD Max.
BVDD Min.
VDD
Internal
Reset
BVDD Max.
BVDD Min.
VDD
Internal
Reset 72 ms
<72 ms
72 ms
BVDD Max.
BVDD Min.
VDD
Internal
Reset
1997 Microchip Technology Inc. DS30390E-page 135
PIC16C7X
14.4.5 TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWR T time-out is invok ed after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 14-10,
Figure 14-11, and Figure 14-12 depict time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 14-11). This is useful for testing purposes or to
synchronize more than one PIC16CXX device operat-
ing in parallel.
Table 14-7 shows the reset conditions f or some special
function registers, while Table 14-8 shows the reset
conditions for all the registers.
14.4.6 POWER CONTROL/STATUS REGISTER
(PCON)
The Power Control/Status Register, PCON has up to
two bits, depending upon the device. Bit0 is not imple-
mented on the PIC16C73 or PIC16C74.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and check ed on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "Don’t Care" bit and is not necessarily predictable
if the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Applicable Devices
72 73 73A 74 74A 76 77
TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS, PIC16C73/74
TABLE 14-4: TIME-OUT IN VARIOUS SITUATIONS, PIC16C72/73A/74A/76/77
TABLE 14-5: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C73/74
Oscillator Configuration Power-up Wake-up from SLEEP
PWRTE = 1 PWRTE = 0
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 1024 TOSC
RC 72 ms — —
Oscillator Configuration Power-up Brown-out Wake-up from SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
RC 72 ms — 72 ms —
POR TO PD
011Power-on Reset
00xIllegal, T O is set on POR
0x0Illegal, PD is set on POR
101WDT Reset
100WDT W ake-up
1uuMCLR Reset during normal operation
110MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown
PIC16C7X
DS30390E-page 136 1997 Microchip Technology Inc.
TABLE 14-6: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C72/73A/74A/76/77
TABLE 14-7: RESET CONDITION FOR SPECIAL REGISTERS
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, T O is set on POR
0xx0Illegal, PD is set on POR
10xxBrown-out Reset
1101WDT Reset
1100WDT W ake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Condition Program
Counter STATUS
Register PCON
Register
PIC16C73/74
PCON
Register
PIC16C72/73A/74A/76/77
Power-on Reset 000h 0001 1xxx ---- --0- ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --u- ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --u- ---- --uu
WDT Reset 000h 0000 1uuu ---- --u- ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --u- ---- --uu
Brown-out Reset 000h 0001 1uuu N/A ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --u- ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded
with the interrupt vector (0004h).
TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT
or
Interrupt
W 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
INDF 72 73 73A 74 74A 76 77 N/A N/A N/A
TMR0 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 72 73 73A 74 74A 76 77 0000h 0000h PC + 1(2)
STATUS 72 73 73A 74 74A 76 77 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 72 73 73A 74 74A 76 77 --0x 0000 --0u 0000 --uu uuuu
PORTB 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 72 73 73A 74 74A 76 77 ---- -xxx ---- -uuu ---- -uuu
PCLATH 72 73 73A 74 74A 76 77 ---0 0000 ---0 0000 ---u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-7 for reset value for specific condition.
1997 Microchip Technology Inc. DS30390E-page 137
PIC16C7X
INTCON 72 73 73A 74 74A 76 77 0000 000x 0000 000u uuuu uuuu(1)
PIR1
72 73 73A 74 74A 76 77 -0-- 0000 -0-- 0000 -u-- uuuu(1)
72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu(1)
72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu(1)
PIR2 72 73 73A 74 74A 76 77 ---- ---0 ---- ---0 ---- ---u(1)
TMR1L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 72 73 73A 74 74A 76 77 --00 0000 --uu uuuu --uu uuuu
TMR2 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu
T2CON 72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu
SSPBUF 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu
CCPR1L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 72 73 73A 74 74A 76 77 --00 0000 --00 0000 --uu uuuu
RCSTA 72 73 73A 74 74A 76 77 0000 -00x 0000 -00x uuuu -uuu
TXREG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu
RCREG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu
CCPR2L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu
ADRES 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 72 73 73A 74 74A 76 77 0000 00-0 0000 00-0 uuuu uu-u
OPTION 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu
TRISA 72 73 73A 74 74A 76 77 --11 1111 --11 1111 --uu uuuu
TRISB 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu
TRISC 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu
TRISD 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu
TRISE 72 73 73A 74 74A 76 77 0000 -111 0000 -111 uuuu -uuu
PIE1 72 73 73A 74 74A 76 77 -0-- 0000 -0-- 0000 -u-- uuuu
72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu
72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu
PIE2 72 73 73A 74 74A 76 77 ---- ---0 ---- ---0 ---- ---u
PCON 72 73 73A 74 74A 76 77 ---- --0- ---- --u- ---- --u-
72 73 73A 74 74A 76 77 ---- --0u ---- --uu ---- --uu
PR2 72 73 73A 74 74A 76 77 1111 1111 1111 1111 1111 1111
TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register Applicable Devices Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT
or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-7 for reset value for specific condition.
PIC16C7X
DS30390E-page 138 1997 Microchip Technology Inc.
SSPADD 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 72 73 73A 74 74A 76 77 --00 0000 --00 0000 --uu uuuu
TXSTA 72 73 73A 74 74A 76 77 0000 -010 0000 -010 uuuu -uuu
SPBRG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu
ADCON1 72 73 73A 74 74A 76 77 ---- -000 ---- -000 ---- -uuu
TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register Applicable Devices Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT
or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-7 for reset value for specific condition.
1997 Microchip Technology Inc. DS30390E-page 139
PIC16C7X
FIGURE 14-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 14-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 14-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PIC16C7X
DS30390E-page 140 1997 Microchip Technology Inc.
FIGURE 14-13: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
Note 1: External Po wer-on Reset circuit is required
only if VDD po wer-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC16CXX
FIGURE 14-14: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
FIGURE 14-15: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal brown-out detection on the
PIC16C72/73A/74A/76/77 should be dis-
abled when using this circuit.
3: Resistors should be adjusted for the char-
acteristics of the transistor.
VDD 33k
10k
40k
VDD
MCLR
PIC16CXX
Note 1: This brown-out circuit is less expensiv e ,
albeit less accurate. Transistor Q1 turns
off when VDD is below a certain level
such that:
2: Internal brown-out detection on the
PIC16C72/73A/74A/76/77 should be
disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
VDD • R1
R1 + R2 = 0.7V
VDD
R2 40k
VDD
MCLR
PIC16CXX
R1
Q1
1997 Microchip Technology Inc. DS30390E-page 141
PIC16C7X
14.5 Interrupts
The PIC16C7X f amily has up to 12 sources of interrupt.
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’ s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be deter mined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-
17). The latency is the same for one or two cycle
Applicable Devices
72 73 73A 74 74A 76 77
Note: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
instructions. Individual interrupt flag bits are set regard-
less of the status of their corresponding mask bit or the
GIE bit.
Note: F or the PIC16C73/74, if an interrupt occurs
while the Global Interrupt Enable (GIE) bit
is being cleared, the GIE bit may uninten-
tionally be re-enabled by the user’s Inter-
rupt Service Routine (the RETFIE
instruction). The events that would cause
this to occur are:
1. An instruction clears the GIE bit while
an interrupt is acknowledged.
2. The program branches to the Interrupt
vector and executes the Interrupt Ser-
vice Routine.
3. The Interrupt Service Routine com-
pletes with the execution of the RET-
FIE instruction. This causes the GIE
bit to be set (enables interrupts), and
the program returns to the instruction
after the one which was meant to dis-
able interrupts.
Perform the following to ensure that inter-
rupts are globally disabled:
LOOP BCF INTCON, GIE ; Disable global
; interrupt bit
BTFSC INTCON, GIE ; Global interrupt
; disabled?
GOTO LOOP ; NO, try again
: ; Yes, continue
; with program
; flow
PIC16C7X
DS30390E-page 142 1997 Microchip Technology Inc.
FIGURE 14-16: INTERRUPT LOGIC
FIGURE 14-17: INT PIN INTERRUPT TIMING
PSPIF
PSPIE ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
CCP2IE
CCP2IF
The following table shows which devices have which interrupts.
Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16C72 Yes Yes Yes - Yes - - Yes Yes Yes Yes -
PIC16C73 Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes
PIC16C73A Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes
PIC16C74 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PIC16C74A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PIC16C76 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PIC16C77 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Interrupt Latency
PC PC+1 PC+1 0004h 0005h
Inst (0004h) Inst (0005h)
Dummy Cycle
Inst (PC) Inst (PC+1)
Inst (PC-1) Inst (0004h)
Dummy Cycle
Inst (PC)
—
1
4
51
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
2
3
1997 Microchip Technology Inc. DS30390E-page 143
PIC16C7X
14.5.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wak e-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 14.8 for details on SLEEP mode.
14.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 7.0)
14.5.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note: For the PIC16C73/74, if a change on the
I/O pin should occur when the read opera-
tion is being executed (start of the Q2
cycle), then the RBIF interrupt flag may not
get set.
14.6 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to sa ve k ey reg-
isters during an interrupt i.e., W register and STATUS
register. This will have to be implemented in software.
Example 14-1 stores and restores the STATUS, W, and
PCLATH registers. The register, W_TEMP, must be
defined in each bank and must be defined at the same
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1).
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
d) Executes the ISR code.
e) Restores the STATUS register (and bank select
bit).
f) Restores the W and PCLATH registers.
Applicable Devices
72 73 73A 74 74A 76 77
EXAMPLE 14-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
BCF STATUS, IRP ;Return to Bank 0
MOVF FSR, W ;Copy FSR to W
MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP
:
:(ISR)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
PIC16C7X
DS30390E-page 144 1997 Microchip Technology Inc.
14.7 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instr uction. Dur-
ing normal operation, a WDT time-out generates a
de vice RESET (W atchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 14.1).
14.7.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V DD and process variations from par t to part (see
DC specs). If longer time-out periods are desired, a
Applicable Devices
72 73 73A 74 74A 76 77
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler , if assigned to the WDT, and pre vent
it from timing out and generating a device RESET con-
dition.
The T O bit in the STATUS register will be cleared upon
a W atchdog Timer time-out.
14.7.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 14-18: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 14-19: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 14-1, and Figure 14-2 for operation of these bits.
From TMR0 Clock Source
(Figure 7-6)
To TMR0 (Figure 7-6)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8 - to - 1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
8
1997 Microchip Technology Inc. DS30390E-page 145
PIC16C7X
14.8 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O por ts maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no exter nal cir-
cuitr y is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or lo w e xternally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
14.8.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change , or some
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
The f ollowing peripheral interrupts can wak e the de vice
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. SSP (Start/Stop) bit detect interrupt.
3. SSP transmit or receive in sla ve mode (SPI/I2C).
4. CCP capture mode interrupt.
5. Parallel Slave Port read or write.
6. A/D conversion (when A/D clock source is RC).
7. Special event trigger (Timer1 in asynchronous
mode using an external clock).
8. USART TX or RX (synchronous slave mode).
Applicable Devices
72 73 73A 74 74A 76 77
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being e xecuted, the ne xt
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
14.8.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the follo wing will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device will imme-
diately wak e up from sleep . The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set bef ore the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instr uc-
tion should be executed before a SLEEP instruction.
PIC16C7X
DS30390E-page 146 1997 Microchip Technology Inc.
FIGURE 14-20: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
14.9 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
14.10 ID Locations
F our memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
14.11 In-Circuit Serial Programming
PIC16CXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines f or clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
Applicable Devices
72 73 73A 74 74A 76 77
Note: Microchip does not recommend code pro-
tecting windowed devices.
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the de vice into prog r amming/verify
mode, the progr am counter (PC) is at location 00h. A 6-
bit command is then supplied to the de vice . Depending
on the command, 14-bits of program data are then sup-
plied to or from the device, depending if the command
was a load or a read. For complete details of serial pro-
gramming, please refer to the PIC16C6X/7X Program-
ming Specifications (Literature #DS30228).
FIGURE 14-21: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16CXX
VDD
VSS
MCLR/VPP
RB6
RB7
+5V
0V
VPP
CLK
Data I/O
VDD
1997 Microchip Technology Inc. DS30390E-page 147
PIC16C7X
15.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summar y in Table 15-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 15-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register . If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label Label name
TOS Top of Stack
PC Program Counter
PCLATH Program Counter High Latch
GIE Global Interrupt Enable bit
WDT W atchdog Timer/Counter
TO Time-out bit
PD Power-down bit
dest Destination either the W register or the specified
register file location
[ ] Options
( ) Contents
→Assigned to
< > Register bit field
∈In the set of
i
talics
User defined term (font is courier)
The instruction set is highly orthogonal and is grouped
into three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle e xecuted as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
e xecution time is 1 µs . If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
Table 15-2 lists the instructions recognized by the
MPASM assembler.
Figure 15-1 shows the general f ormats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16C7X
DS30390E-page 148 1997 Microchip Technology Inc.
TABLE 15-2: PIC16CXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear W atchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that v alue present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is ex ecuted on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1997 Microchip Technology Inc. DS30390E-page 149
PIC16C7X
15.1 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [
label
] ADDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) + k → (W)
Status Affected: C, DC, Z
Encoding: 11 111x kkkk kkkk
Description: The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
data Write to
W
Example: ADDLW 0x15
Before Instruction
W = 0x10
After Instruction
W = 0x25
ADDWF Add W and f
Syntax: [
label
] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (destination)
Status Affected: C, DC, Z
Encoding: 00 0111 dfff ffff
Description: Add the contents of the W register with
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is 1 the result is
stored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example ADDWF FSR, 0
Before Instruction
W = 0x17
FSR = 0xC2
After Instruction
W = 0xD9
FSR = 0xC2
ANDLW AND Literal with W
Syntax: [
label
] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Encoding: 11 1001 kkkk kkkk
Description: The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
literal "k" Process
data Write to
W
Example ANDLW 0x5F
Before Instruction
W = 0xA3
After Instruction
W = 0x03
ANDWF AND W with f
Syntax: [
label
] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (destination)
Status Affected: Z
Encoding: 00 0101 dfff ffff
Description: AND the W register with register 'f'. If 'd'
is 0 the result is stored in the W regis-
ter. If 'd' is 1 the result is stored back in
register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example ANDWF FSR, 1
Before Instruction
W = 0x17
FSR = 0xC2
After Instruction
W = 0x17
FSR = 0x02
PIC16C7X
DS30390E-page 150 1997 Microchip Technology Inc.
BCF Bit Clear f
Syntax: [
label
] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Encoding: 01 00bb bfff ffff
Description: Bit 'b' in register 'f' is cleared.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write
register 'f'
Example BCF FLAG_REG, 7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
BSF Bit Set f
Syntax: [
label
] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Encoding: 01 01bb bfff ffff
Description: Bit 'b' in register 'f' is set.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write
register 'f'
Example BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
BTFSC Bit Test, Skip if Clear
Syntax: [
label
] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 01 10bb bfff ffff
Description: If bit 'b' in register 'f' is '1' then the next
instruction is executed.
If bit 'b', in register 'f', is '0' then the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
data No-
Operation
If Skip: (2nd Cycle)
Q1 Q2 Q3 Q4
No-
Operation No-
Operation No-
Operation No-
Operation
Example HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = address TRUE
if FLAG<1>=1,
PC = address FALSE
1997 Microchip Technology Inc. DS30390E-page 151
PIC16C7X
BTFSS Bit Test f, Skip if Set
Syntax: [
label
] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding: 01 11bb bfff ffff
Description: If bit 'b' in register 'f' is '0' then the next
instruction is executed.
If bit 'b' is '1', then the next instruction is
discarded and a NOP is executed
instead, making this a 2TCY instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
data No-
Operation
If Skip: (2nd Cycle)
Q1 Q2 Q3 Q4
No-
Operation No-
Operation No-
Operation No-
Operation
Example HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1,
PC = address TRUE
CALL Call Subroutine
Syntax: [
label
] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: (PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Encoding: 10 0kkk kkkk kkkk
Description: Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH. CALL
is a two cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity: Q1 Q2 Q3 Q4
1st Cycle Decode Read
literal 'k',
Push PC
to Stack
Process
data Write to
PC
2nd Cycle No-
Operation No-
Operation No-
Operation No-
Operation
Example HERE CALL THERE
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
PIC16C7X
DS30390E-page 152 1997 Microchip Technology Inc.
CLRF Clear f
Syntax: [
label
] CLRF f
Operands: 0 ≤ f ≤ 127
Operation: 00h → (f)
1 → Z
Status Affected: Z
Encoding: 00 0001 1fff ffff
Description: The contents of register 'f' are cleared
and the Z bit is set.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write
register 'f'
Example CLRF FLAG_REG
Before Instruction
FLAG_REG = 0x5A
After Instruction
FLAG_REG = 0x00
Z=1
CLRW Clear W
Syntax: [
label
] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Encoding: 00 0001 0xxx xxxx
Description: W register is cleared. Zero bit (Z) is
set.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode No-
Operation Process
data Write to
W
Example CLRW
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z=1
CLRWDT Clear Watchdog Timer
Syntax: [
label
] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler ,
1 → TO
1 → PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0100
Description: CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD are
set.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode No-
Operation Process
data Clear
WDT
Counter
Example CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT prescaler= 0
TO =1
PD =1
1997 Microchip Technology Inc. DS30390E-page 153
PIC16C7X
COMF Complement f
Syntax: [
label
] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affected: Z
Encoding: 00 1001 dfff ffff
Description: The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example COMF REG1,0
Before Instruction
REG1 = 0x13
After Instruction
REG1 = 0x13
W = 0xEC
DECF Decrement f
Syntax: [
label
] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination)
Status Affected: Z
Encoding: 00 0011 dfff ffff
Description: Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example DECF CNT, 1
Before Instruction
CNT = 0x01
Z=0
After Instruction
CNT = 0x00
Z=1
DECFSZ Decrement f, Skip if 0
Syntax: [
label
] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination);
skip if result = 0
Status Affected: None
Encoding: 00 1011 dfff ffff
Description: The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
If the result is 1, the next instruction, is
executed. If the result is 0, then a NOP is
executed instead making it a 2TCY instruc-
tion.
Words: 1
Cycles: 1(2)
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
data Write to
destination
If Skip: (2nd Cycle)
Q1 Q2 Q3 Q4
No-
Operation No-
Operation No-
Operation No-
Operation
Example HERE DECFSZ CNT, 1
GOTO LOOP
CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
CNT = CNT - 1
if CNT = 0,
PC = address CONTINUE
if CNT ≠0,
PC = address HERE+1
PIC16C7X
DS30390E-page 154 1997 Microchip Technology Inc.
GOTO Unconditional Branch
Syntax: [
label
] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Encoding: 10 1kkk kkkk kkkk
Description: GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity: Q1 Q2 Q3 Q4
1st Cycle Decode Read
literal 'k' Process
data Write to
PC
2nd Cycle No-
Operation No-
Operation No-
Operation No-
Operation
Example GOTO THERE
After Instruction
PC = Address THERE
INCF Increment f
Syntax: [
label
] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination)
Status Affected: Z
Encoding: 00 1010 dfff ffff
Description: The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example INCF CNT, 1
Before Instruction
CNT = 0xFF
Z=0
After Instruction
CNT = 0x00
Z=1
1997 Microchip Technology Inc. DS30390E-page 155
PIC16C7X
INCFSZ Increment f, Skip if 0
Syntax: [
label
] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination),
skip if result = 0
Status Affected: None
Encoding: 00 1111 dfff ffff
Description: The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 1, the next instruction is
executed. If the result is 0, a NOP is
executed instead making it a 2TCY
instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
data Write to
destination
If Skip: (2nd Cycle)
Q1 Q2 Q3 Q4
No-
Operation No-
Operation No-
Operation No-
Operation
Example HERE INCFSZ CNT, 1
GOTO LOOP
CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
CNT = CNT + 1
if CNT= 0,
PC = address CONTINUE
if CNT≠0,
PC = address HERE +1
IORLW Inclusive OR Literal with W
Syntax: [
label
] IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W)
Status Affected: Z
Encoding: 11 1000 kkkk kkkk
Description: The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
data Write to
W
Example IORLW 0x35
Before Instruction
W = 0x9A
After Instruction
W = 0xBF
Z=1
PIC16C7X
DS30390E-page 156 1997 Microchip Technology Inc.
IORWF Inclusive OR W with f
Syntax: [
label
] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (destination)
Status Affected: Z
Encoding: 00 0100 dfff ffff
Description: Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example IORWF RESULT, 0
Before Instruction
RESULT = 0x13
W = 0x91
After Instruction
RESULT = 0x13
W = 0x93
Z=1
MOVF Move f
Syntax: [
label
] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affected: Z
Encoding: 00 1000 dfff ffff
Description: The contents of register f is moved to a
destination dependant upon the status
of d. If d = 0, destination is W register. If
d = 1, the destination is file register f
itself. d = 1 is useful to test a file regis-
ter since status flag Z is affected.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example MOVF FSR, 0
After Instruction
W = value in FSR register
Z= 1
MOVLW Move Literal to W
Syntax: [
label
] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Encoding: 11 00xx kkkk kkkk
Description: The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
data Write to
W
Example MOVLW 0x5A
After Instruction
W = 0x5A
MOVWF Move W to f
Syntax: [
label
] MOVWF f
Operands: 0 ≤ f ≤ 127
Operation: (W) → (f)
Status Affected: None
Encoding: 00 0000 1fff ffff
Description: Move data from W register to register
'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write
register 'f'
Example MOVWF OPTION_REG
Before Instruction
OPTION = 0xFF
W = 0x4F
After Instruction
OPTION = 0x4F
W = 0x4F
1997 Microchip Technology Inc. DS30390E-page 157
PIC16C7X
NOP No Operation
Syntax: [
label
] NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 00 0000 0xx0 0000
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode No-
Operation No-
Operation No-
Operation
Example NOP
OPTION Load Option Register
Syntax: [
label
] OPTION
Operands: None
Operation: (W) → OPTION
Status Affected: None
Encoding: 00 0000 0110 0010
Description: The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Words: 1
Cycles: 1
Example To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
RETFIE Return from Interrupt
Syntax: [
label
] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Status Affected: None
Encoding: 00 0000 0000 1001
Description: Return from Interrupt. Stack is POPed
and Top of Stack (T OS) is loaded in the
PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Words: 1
Cycles: 2
Q Cycle Activity: Q1 Q2 Q3 Q4
1st Cycle Decode No-
Operation Set the
GIE bit Pop from
the Stack
2nd Cycle No-
Operation No-
Operation No-
Operation No-
Operation
Example RETFIE
After Interrupt
PC = TOS
GIE = 1
PIC16C7X
DS30390E-page 158 1997 Microchip Technology Inc.
RETLW Return with Literal in W
Syntax: [
label
] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affected: None
Encoding: 11 01xx kkkk kkkk
Description: The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Words: 1
Cycles: 2
Q Cycle Activity: Q1 Q2 Q3 Q4
1st Cycle Decode Read
literal 'k' No-
Operation Write to W ,
Pop from
the Stack
2nd Cycle No-
Operation No-
Operation No-
Operation No-
Operation
Example
TABLE
CALL TABLE ;W contains table
;offset value
• ;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [
label
] RETURN
Operands: None
Operation: TOS → PC
Status Affected: None
Encoding: 00 0000 0000 1000
Description: Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter . This
is a two cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity: Q1 Q2 Q3 Q4
1st Cycle Decode No-
Operation No-
Operation Pop from
the Stack
2nd Cycle No-
Operation No-
Operation No-
Operation No-
Operation
Example RETURN
After Interrupt
PC = TOS
1997 Microchip Technology Inc. DS30390E-page 159
PIC16C7X
RLF Rotate Left f through Carry
Syntax: [
label
] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Encoding: 00 1101 dfff ffff
Description: The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example RLF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W= 1100 1100
C=1
Register fC
RRF Rotate Right f through Carry
Syntax: [
label
] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Encoding: 00 1100 dfff ffff
Description: The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example RRF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W= 0111 0011
C=0
Register fC
PIC16C7X
DS30390E-page 160 1997 Microchip Technology Inc.
SLEEP
Syntax: [
label
] SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler ,
1 → TO,
0 → PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0011
Description: The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped. See
Section 14.8 for more details.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode No-
Operation No-
Operation Go to
Sleep
Example: SLEEP
SUBLW Subtract W from Literal
Syntax: [
label
] SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Encoding: 11 110x kkkk kkkk
Description: The W register is subtracted (2’s comple-
ment method) from the eight bit literal 'k'.
The result is placed in the W register.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
data Write to W
Example 1: SUBLW 0x02
Before Instruction
W= 1
C=?
Z=?
After Instruction
W= 1
C = 1; result is positive
Z=0
Example 2: Before Instruction
W= 2
C=?
Z=?
After Instruction
W= 0
C = 1; result is zero
Z=1
Example 3: Before Instruction
W= 3
C=?
Z=?
After Instruction
W = 0xFF
C = 0; result is negative
Z=0
1997 Microchip Technology Inc. DS30390E-page 161
PIC16C7X
SUBWF Subtract W from f
Syntax: [
label
] SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (destination)
Status Affected: C, DC, Z
Encoding: 00 0010 dfff ffff
Description: Subtract (2’s complement method) W reg-
ister from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
data Write to
destination
Example 1: SUBWF REG1,1
Before Instruction
REG1 = 3
W=2
C=?
Z=?
After Instruction
REG1 = 1
W=2
C = 1; result is positive
Z=0
Example 2: Before Instruction
REG1 = 2
W=2
C=?
Z=?
After Instruction
REG1 = 0
W=2
C = 1; result is zero
Z=1
Example 3: Before Instruction
REG1 = 1
W=2
C=?
Z=?
After Instruction
REG1 = 0xFF
W=2
C = 0; result is negative
Z=0
SWAPF Swap Nibbles in f
Syntax: [
label
] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Encoding: 00 1110 dfff ffff
Description: The upper and lower nibb les of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
data Write to
destination
Example SWAPF REG, 0
Before Instruction
REG1 = 0xA5
After Instruction
REG1 = 0xA5
W = 0x5A
TRIS Load TRIS Register
Syntax: [
label
] TRIS f
Operands: 5 ≤ f ≤ 7
Operation: (W) → TRIS register f;
Status Affected: None
Encoding: 00 0000 0110 0fff
Description: The instruction is supported for code
compatibility with the PIC16C5X prod-
ucts. Since TRIS registers are read-
able and writable, the user can directly
address them.
Words: 1
Cycles: 1
Example To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
PIC16C7X
DS30390E-page 162 1997 Microchip Technology Inc.
XORLW Exclusive OR Literal with W
Syntax: [
label
] XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Encoding: 11 1010 kkkk kkkk
Description: The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
data Write to
W
Example: XORLW 0xAF
Before Instruction
W = 0xB5
After Instruction
W = 0x1A
XORWF Exclusive OR W with f
Syntax: [
label
] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (destination)
Status Affected: Z
Encoding: 00 0110 dfff ffff
Description: Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read
register
'f'
Process
data Write to
destination
Example XORWF REG 1
Before Instruction
REG = 0xAF
W = 0xB5
After Instruction
REG = 0x1A
W = 0xB5
1997 Microchip Technology Inc. DS30390E-page 163
PIC16C7X
16.0 DEVELOPMENT SUPPORT
16.1 Development Tools
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB-SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy logic development system (
fuzzy
TECH−MP)
16.2 PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip micro-
controllers.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is av ailable for
European Union (EU) countries.
16.3 ICEPIC: Low-cost PIC16CXXX
In-Circuit Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXXX families of 8-bit
OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
16.4 PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
gram PIC16C5X, PIC16CXXX, PIC17CXX and
PIC14000 devices. It can also set configuration and
code-protect bits in this mode.
16.5 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
PICSTART Plus supports all PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 ma y be supported with an
adapter socket.
PIC16C7X
DS30390E-page 164 1997 Microchip Technology Inc.
16.6 PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-16B programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is availab le for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
16.7 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
sock et(s). Some of the f eatures include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C b us and separ ate headers f or connec-
tion to an LCD module and a keypad.
16.8 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiple x ed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
16.9 MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
16.10 Assembler (MPASM)
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and sev eral source and listing f ormats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator
System.
1997 Microchip Technology Inc. DS30390E-page 165
PIC16C7X
MPASM has the following features to assist in dev elop-
ing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (def ault), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the de velopment of y our assemble source code
shorter and more maintainable.
16.11 Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be perf ormed in; single step , e xecute until break, or
in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out-
side of the laboratory environment making it an excel-
lent multi-project software development tool.
16.12 C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC16/17 family of micro-
controllers. The compiler provides powerful integration
capabilities and ease of use not found with other
compilers.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display (PICMASTER emulator
software versions 1.13 and later).
16.13 Fuzzy Logic Development System
(
fuzzy
TECH-MP)
fuzzy
TECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version,
fuzzy
TECH-MP, edition for imple-
menting more complex systems.
Both versions include Microchip’s
fuzzy
LAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
16.14 MP-DriveWay – Application Code
Generator
MP-DriveWay is an easy-to-use Windows-based Appli-
cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Micro-
chip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integr ation of y our o wn
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
16.15 SEEVAL Evaluation and
Programming System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessar y to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
16.16 TrueGauge Intelligent Battery
Management
The TrueGauge development tool supports system
development with the MTA11200B TrueGauge Intelli-
gent Battery Management IC. System design verifica-
tion can be accomplished before hardware prototypes
are built. User interface is graphically-oriented and
measured data can be saved in a file for exporting to
Microsoft Excel.
16.17 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS ev al-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
PIC16C7X
DS30390E-page 166 1997 Microchip Technology Inc.
TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X 24CXX
25CXX
93CXX
HCS200
HCS300
HCS301
Emulator Products
PICMASTER/
PICMASTER-CE
In-Circuit Emulator ✔✔✔✔✔✔✔✔✔
Available
3Q97
ICEPIC Low-Cost
In-Circuit Emulator ✔ ✔✔✔✔✔
Software Tools
MPLAB
Integrated
Development
Environment ✔✔✔ ✔ ✔✔✔✔✔✔
MPLAB C
Compiler ✔✔✔ ✔ ✔✔✔✔✔✔
fuzzy
TECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool ✔✔✔✔✔✔✔✔✔
MP-DriveWay
Applications
Code Generator ✔✔✔✔✔ ✔
Total Endurance
Software Model ✔
Programmers
PICSTART
Lite Ultra Low-Cost
Dev. Kit ✔✔✔✔
PICSTART
Plus Low-Cost
Universal Dev. Kit ✔✔✔ ✔ ✔✔✔✔✔✔
PRO MATE II
Universal
Programmer ✔✔✔ ✔ ✔✔✔✔✔✔✔✔
KEELOQ
Programmer ✔
Demo Boards
SEEVAL
Designers Kit ✔
PICDEM-1 ✔✔ ✔ ✔
PICDEM-2 ✔✔
PICDEM-3 ✔
KEELOQ
Evaluation Kit ✔
1997 Microchip Technology Inc. DS30390E-page 167
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
17.0 ELECTRICAL CHARACTERISTICS FOR PIC16C72
Absolute Maximum Ratings †
Ambient temperature under bias..................................................................................................................-55 to +125˚C
Storage temperature............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ................................................................................................. 0 to +14V
Voltage on RA4 with respect to Vss................................................................................................................... 0 to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin............................................................................................................................300 mA
Maximum current into VDD pin...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (combined)..................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined).............................................................................200 mA
Maximum current sunk by PORTC ........................................................................................................................200 mA
Maximum current sourced by PORTC...................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes belo w V SS at the MCLR pin, inducing currents g reater than 80 mA, may cause latch-up . Thus,
a series resistor of 50-100Ω should be used when applying a “low” lev el to the MCLR pin rather than pulling
this pin directly to VSS.
TABLE 17-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
de vice . This is a stress rating only and functional operation of the device at those or any other conditions abo ve those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
OSC PIC16C72-04 PIC16C72-10 PIC16C72-20 PIC16LC72-04 JW Devices
RC
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3.0V
IPD: 5.0 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
XT
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3.0V
IPD: 5.0 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
HS
VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
Not recommended for use
in HS mode
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V IDD: 20 mA max. at 5.5V
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.
LP
VDD: 4.0V to 6.0V
IDD: 52.5 µA typ. at
32 kHz, 4.0V
IPD: 0.9 µA typ. at 4.0V
Freq: 200 kHz max.
Not recommended for use
in LP mode Not recommended for use
in LP mode
VDD: 2.5V to 6.0V
IDD: 48 µA max. at
32 kHz, 3.0V
IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max.
VDD: 2.5V to 6.0V
IDD: 48 µA max. at
32 kHz, 3.0V
IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
PIC16C7X
DS30390E-page 168 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
17.1 DC Characteristics: PIC16C72-04 (Commercial, Industrial, Extended)
PIC16C72-10 (Commercial, Industrial, Extended)
PIC16C72-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001
D001A Supply Voltage VDD 4.0
4.5 -
-6.0
5.5 V
VXT, RC and LP osc configuration
HS osc configuration
D002* RAM Data Retention
Voltage (Note 1) VDR - 1.5 - V
D003 VDD start voltage to
ensure internal Power-
on Reset Signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
Signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled
3.7 4.0 4.4 V Extended Only
D010
D013
Supply Current
(Note 2,5) IDD -
-
2.7
10
5.0
20
mA
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D015 Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
D020
D021
D021A
D021B
Power-down Current
(Note 3,5) IPD -
-
-
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT disab led, -40°C to +125°C
D023 Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating v oltage and frequency. Other f actors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1997 Microchip Technology Inc. DS30390E-page 169
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
17.2 DC Characteristics: PIC16LC72-04 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001 Supply V oltage V DD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz)
D002* RAM Data Retention Volt-
age (Note 1) VDR - 1.5 - V
D003 VDD start voltage to
ensure internal Power-on
Reset signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled
D010
D010A
Supply Current
(Note 2,5) IDD -
-
2.0
22.5
3.8
48
mA
µA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D015* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
D020
D021
D021A
Power-down Current
(Note 3,5) IPD -
-
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating v oltage and frequency. Other f actors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
PIC16C7X
DS30390E-page 170 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
17.3 DC Characteristics: PIC16C72-04 (Commercial, Industrial, Extended)
PIC16C72-10 (Commercial, Industrial, Extended)
PIC16C72-20 (Commercial, Industrial, Extended)
PIC16LC72-04 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 17.1
and Section 17.2.
Param
No. Characteristic Sym Min Typ
†Max Units Conditions
Input Low Voltage
I/O ports VIL
D030 with TTL buff er V SS - 0.15VDD V For entire VDD range
D030A VSS - 0.8V V 4.5 ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS - 0.2VDD V
D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V
D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1
Input High Voltage
I/O ports VIH -
D040 with TTL buff er 2.0 - V DD V 4.5 ≤ VDD ≤ 5.5V
D040A 0.25VDD
+ 0.8V -VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range
D042 MCLR 0.8VDD -VDD V
D042A OSC1 (XT, HS and LP) 0.7VDD -VDD V Note1
D043 OSC1 (in RC mode) 0.9VDD -VDD V
D070 PORTB weak pull-up current IPURB 50 250 †400 µAVDD = 5V, VPIN = VSS
Input Leakage Current (Notes 2, 3)
D060 I/O ports IIL --±1µA Vss ≤ VPIN ≤ VDD, Pin at hi-
impedance
D061 MCLR, RA4/T0CKI - - ±5µA Vss ≤ VPIN ≤ VDD
D063 OSC1 - - ±5µA Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
Output Low Voltage
D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as current sourced by the pin.
1997 Microchip Technology Inc. DS30390E-page 171
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
Output High Voltage
D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D150* Open-Drain High Voltage VOD - - 14 V RA4 pin
Capacitive Loading Specs on Out-
put Pins
D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes
when e xternal clock is used to
drive OSC1.
D101
D102 All I/O pins and OSC2 (in RC mode)
SCL, SDA in I2C mode CIO
CB-
--
-50
400 pF
pF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 17.1
and Section 17.2.
Param
No. Characteristic Sym Min Typ
†Max Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as current sourced by the pin.
PIC16C7X
DS30390E-page 172 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
17.4 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
FIGURE 17-1: LOAD CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
SF Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464Ω
CL= 50 pF for all pins except OSC2
15 pF for OSC2 output
Load condition 1 Load condition 2
1997 Microchip Technology Inc. DS30390E-page 173
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
17.5 Timing Diagrams and Specifications
FIGURE 17-2: EXTERNAL CLOCK TIMING
TABLE 17-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
Fosc External CLKIN Frequency
(Note 1) DC — 4 MHz XT and RC osc mode
DC — 4 MHz HS osc mode (-04)
DC — 10 MHz HS osc mode (-10)
DC — 20 MHz HS osc mode (-20)
DC — 200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC osc mode
0.1 — 4 MHz XT osc mode
4
5—
—20
200 MHz
kHz HS osc mode
LP osc mode
1 Tosc External CLKIN Period
(Note 1) 250 — — ns XT and RC osc mode
250 — — ns HS osc mode (-04)
100 — — ns HS osc mode (-10)
50 — — ns HS osc mode (-20)
5— —µs LP osc mode
Oscillator Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (-04)
100
50 —
—250
250 ns
ns HS osc mode (-10)
HS osc mode (-20)
5— —µs LP osc mode
2T
CY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC
3 TosL,
TosH External Clock in (OSC1) High or
Low Time 100 — — ns XT oscillator
2.5 — — µs LP oscillator
15 — — ns HS oscillator
4 TosR,
TosF External Clock in (OSC1) Rise or
Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device e x ecuting code .
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
PIC16C7X
DS30390E-page 174 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-3: CLKOUT AND I/O TIMING
TABLE 17-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1
11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1
12* TckR CLKOUT rise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT ↑ TOSC + 200 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1
17* TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid — 50 150 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16C72 100 — — ns
PIC16LC72 200 — — ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns
20* TioR Port output rise time PIC16C72 — 10 40 ns
PIC16LC72 — — 80 ns
21* TioF Port output fall time PIC16C72 — 10 40 ns
PIC16LC72 — — 80 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 17-1 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
old value new value
1997 Microchip Technology Inc. DS30390E-page 175
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 17-5: BROWN-OUT RESET TIMING
TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — µsVDD = 5V, -40˚C to +125˚C
31* Twdt Watchdog Timer Time-out P eriod
(No Prescaler) 71833msVDD = 5V, -40˚C to +125˚C
32 Tost Oscillation Start-up Timer Period — 1024TOSC ——TOSC = OSC1 period
33* Tpwrt P ow er-up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C
34 TIOZ I/O Hi-impedance from MCLR Low
or W atchdog Timer Reset — — 2.1 µs
35 TBOR Brown-out Reset pulse width 100 — — µsVDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 17-1 for load conditions.
VDD BVDD
35
PIC16C7X
DS30390E-page 176 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C7X 15 — — ns
PIC16LC7X 25 — — ns
Asynchronous PIC16C7X 30 — — ns
PIC16LC7X 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C7X 15 — — ns
PIC16LC7X 25 — — ns
Asynchronous PIC16C7X 30 — — ns
PIC16LC7X 50 — — ns
47* Tt1P T1CKI input period Synchronous PIC16C7X Greater of:
30 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
PIC16LC7X Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16C7X 60 — — ns
PIC16LC7X 100 — — ns
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 17-1 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 or
TMR1
1997 Microchip Technology Inc. DS30390E-page 177
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 input low time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C72 10 — — ns
PIC16LC72 20 — — ns
51* TccH CCP1 input high time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C72 10 — — ns
PIC16LC72 20 — — ns
52* TccP CCP1 input period 3TCY + 40
N— — ns N = prescale
value (1,4 or 16)
53* TccR CCP1 output rise time PIC16C72 — 10 25 ns
PIC16LC72 — 25 45 ns
54* TccF CCP1 output fall time PIC16C72 — 10 25 ns
PIC16LC72 — 25 45 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 17-1 for load conditions.
RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC2/CCP1
(Compare or PWM Mode)
PIC16C7X
DS30390E-page 178 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-8: SPI MODE TIMING
TABLE 17-7: SPI MODE REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
70 TssL2scH,
TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns
71 TscH SCK input high time (slave mode) TCY + 20 — — ns
72 TscL SCK input low time (slave mode) TCY + 20 — — ns
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK
edge 50 — — ns
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK
edge 50 — — ns
75 TdoR SDO data output rise time — 10 25 ns
76 TdoF SDO data output fall time — 10 25 ns
77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78 TscR SCK output rise time (master mode) — 10 25 ns
79 TscF SCK output fall time (master mode) — 10 25 ns
80 TscH2doV,
TscL2doV SDO data output valid after SCK
edge — — 50 ns
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 17-1 for load conditions
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
1997 Microchip Technology Inc. DS30390E-page 179
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-9: I2C BUS START/STOP BITS TIMING
TABLE 17-8: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ Max Units Conditions
90 TSU:STA START condition 100 kHz mode 4700 — — ns Only relev ant for repeated START
condition
Setup time 400 kHz mode 600 — —
91 THD:STA START condition 100 kHz mode 4000 — — ns After this period the first clock
pulse is generated
Hold time 400 kHz mode 600 — —
92 TSU:STO STOP condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO STOP condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note: Refer to Figure 17-1 for load conditions
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
PIC16C7X
DS30390E-page 180 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-10: I2C BUS DATA TIMING
TABLE 17-9: I2C BUS DATA REQUIREMENTS
Parameter
No. Sym Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4.0 — µs De vice m ust operate at a mini-
mum of 1.5 MHz
400 kHz mode 0.6 — µs De vice m ust oper ate at a mini-
mum of 10 MHz
SSP Module 1.5TCY —
101 TLOW Clock low time 100 kHz mode 4.7 — µs Device must oper ate at a mini-
mum of 1.5 MHz
400 kHz mode 1.3 — µs De vice m ust oper ate at a mini-
mum of 10 MHz
SSP Module 1.5TCY —
102 TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
103 TFSDA and SCL fall time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
90 TSU:STA START condition
setup time 100 kHz mode 4.7 — µs Only relevant for repeated
START condition
400 kHz mode 0.6 — µs
91 THD:STA START condition hold
time 100 kHz mode 4.0 — µs After this period the first clock
pulse is generated
400 kHz mode 0.6 — µs
106 THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
92 TSU:STO STOP condition setup
time 100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109 TAA Output valid from
clock 100 kHz mode — 3500 ns Note 1
400 kHz mode — — ns
110 TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
before a ne w transmission can
start
400 kHz mode 1.3 — µs
Cb Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz)S I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LO W period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
Note: Refer to Figure 17-1 for load conditions
90
91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
1997 Microchip Technology Inc. DS30390E-page 181
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
TABLE 17-10: A/D CONVERTER CHARACTERISTICS:
PIC16C72-04 (Commercial, Industrial, Extended)
PIC16C72-10 (Commercial, Industrial, Extended)
PIC16C72-20 (Commercial, Industrial, Extended)
PIC16LC72-04 (Commercial, Industrial)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 8-bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02 EABS Total Absolute error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 — Monotonicity — guaranteed — — VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage 3.0V — VDD + 0.3 V
A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V
A30 ZAIN Recommended impedance of
analog voltage source — — 10.0 kΩ
A40 IAD A/D conversion current (VDD) PIC16C72 — 180 — µA Average current consump-
tion when A/D is on.
(Note 1)
PIC16LC72 — 90 — µA
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 13.1.
During A/D Conversion
cycle
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
PIC16C7X
DS30390E-page 182 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 17-11: A/D CONVERSION TIMING
TABLE 17-11: A/D CONVERSION REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
130 TAD A/D clock period PIC16C72 1.6 — — µsTOSC based, VREF ≥ 3.0V
PIC16LC72 2.0 — — µsTOSC based, VREF full range
PIC16C72 2.0 4.0 6.0 µs A/D RC Mode
PIC16LC72 3.0 6.0 9.0 µs A/D RC Mode
131 TCNV Conversion time (not including S/H
time) (Note 1) — 9.5 — TAD
132 TACQ Acquisition time Note 2
5*
20
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135 TSWC Switching from convert → sample time 1.5 § — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2) (1)
7 6543210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
134
1997 Microchip Technology Inc. DS30390E-page 183
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
18.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73/74
Absolute Maximum Ratings †
Ambient temperature under bias..................................................................................................................-55 to +125˚C
Storage temperature............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ................................................................................................. 0 to +14V
Voltage on RA4 with respect to Vss................................................................................................................... 0 to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin............................................................................................................................300 mA
Maximum current into VDD pin...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ...............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)...................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes belo w V SS at the MCLR pin, inducing currents g reater than 80 mA, may cause latch-up . Thus,
a series resistor of 50-100Ω should be used when applying a “low” lev el to the MCLR pin rather than pulling
this pin directly to VSS.
Note 3: PORTD and PORTE are not implemented on the PIC16C73.
TABLE 18-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
de vice . This is a stress rating only and functional operation of the device at those or any other conditions abo ve those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
OSC PIC16C73-04
PIC16C74-04 PIC16C73-10
PIC16C74-10 PIC16C73-20
PIC16C74-20 PIC16LC73-04
PIC16LC74-04 JW Devices
RC
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 3.0V to 6.0V
IDD: 3.8 mA max. at 3.0V
IPD: 13.5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
XT
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 3.0V to 6.0V
IDD: 3.8 mA max. at 3.0V
IPD: 13.5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
HS
VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
Not recommended for
use in HS mode
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V IDD: 15 mA max. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.
LP
VDD: 4.0V to 6.0V
IDD: 52.5 µA typ. at
32 kHz, 4.0V
IPD: 0.9 µA typ. at 4.0V
Freq: 200 kHz max.
Not recommended for
use in LP mode Not recommended for
use in LP mode
VDD: 3.0V to 6.0V
IDD: 48 µA max. at
32 kHz, 3.0V
IPD: 13.5 µA max. at 3.0V
Freq: 200 kHz max.
VDD: 3.0V to 6.0V
IDD: 48 µA max. at
32 kHz, 3.0V
IPD: 13.5 µA max. at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
PIC16C7X
DS30390E-page 184 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
18.1 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial)
PIC16C73/74-10 (Commercial, Industrial)
PIC16C73/74-20 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001
D001A Supply Voltage V DD 4.0
4.5 -
-6.0
5.5 V
VXT, RC and LP osc configuration
HS osc configuration
D002* RAM Data Retention
Voltage (Note 1) VDR - 1.5 - V
D003 VDD start voltage to
ensure internal Power-on
Reset signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D010
D013
Supply Current (Note 2,5) IDD -
-
2.7
13.5
5
30
mA
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D020
D021
D021A
Power-down Current
(Note 3,5) IPD -
-
-
10.5
1.5
1.5
42
21
24
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These par ameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
1997 Microchip Technology Inc. DS30390E-page 185
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
18.2 DC Characteristics: PIC16LC73/74-04 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001 Supply Voltage VDD 3.0 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz)
D002* RAM Data Retention
Voltage (Note 1) VDR - 1.5 - V
D003 VDD start voltage to
ensure internal Po w er-on
Reset signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D010
D010A
Supply Current (Note 2,5) I DD -
-
2.0
22.5
3.8
48
mA
µA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
Power-down Current
(Note 3,5) IPD -
-
-
7.5
0.9
0.9
30
13.5
18
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
PIC16C7X
DS30390E-page 186 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
18.3 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial)
PIC16C73/74-10 (Commercial, Industrial)
PIC16C73/74-20 (Commercial, Industrial)
PIC16LC73/74-04 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 18.1 and
Section 18.2.
Param
No. Characteristic Sym Min Typ
†Max Units Conditions
Input Low Voltage
I/O ports VIL
D030 with TTL buff er V SS - 0.15VDD V For entire VDD range
D030A VSS - 0.8V V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS - 0.2VDD V
D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V
D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1
Input High Voltage
I/O ports VIH -
D040 with TTL buff er 2.0 - V DD V 4.5V ≤ VDD ≤ 5.5V
D040A 0.25VDD
+ 0.8V -VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range
D042 MCLR 0.8VDD -VDD V
D042A OSC1 (XT, HS and LP) 0.7VDD -VDD V Note1
D043 OSC1 (in RC mode) 0.9VDD -VDD V
D070 PORTB weak pull-up current IPURB 50 250 400 µAVDD = 5V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060 I/O ports IIL --±1µA Vss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061 MCLR, RA4/T0CKI - - ±5µA Vss ≤ VPIN ≤ VDD
D063 OSC1 - - ±5µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
Output Low Voltage
D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
Output High Voltage
D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D150* Open-Drain High Voltage VOD - - 14 V RA4 pin
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1997 Microchip Technology Inc. DS30390E-page 187
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
Capacitive Loading Specs on
Output Pins
D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102 All I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode CIO
CB-
--
-50
400 pF
pF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 18.1 and
Section 18.2.
Param
No. Characteristic Sym Min Typ
†Max Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC16C7X
DS30390E-page 188 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
18.4 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
FIGURE 18-1: LOAD CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
SF Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464Ω
CL= 50 pF f or all pins e xcept OSC2, b ut including POR TD and POR TE outputs as
ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16C73.
Load condition 1 Load condition 2
1997 Microchip Technology Inc. DS30390E-page 189
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
18.5 Timing Diagrams and Specifications
FIGURE 18-2: EXTERNAL CLOCK TIMING
TABLE 18-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
Fosc External CLKIN Frequency
(Note 1) DC — 4 MHz XT and RC osc mode
DC — 4 MHz HS osc mode (-04)
DC — 10 MHz HS osc mode (-10)
DC — 20 MHz HS osc mode (-20)
DC — 200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC osc mode
0.1 — 4 MHz XT osc mode
4
5—
—20
200 MHz
kHz HS osc mode
LP osc mode
1 Tosc External CLKIN Period
(Note 1) 250 — — ns XT and RC osc mode
250 — — ns HS osc mode (-04)
100 — — ns HS osc mode (-10)
50 — — ns HS osc mode (-20)
5— —µs LP osc mode
Oscillator Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (-04)
100
50 —
—250
250 ns
ns HS osc mode (-10)
HS osc mode (-20)
5— —µs LP osc mode
2T
CY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC
3 TosL,
TosH External Clock in (OSC1) High or
Low Time 50 — — ns XT oscillator
2.5 — — µs LP oscillator
15 — — ns HS oscillator
4 TosR,
TosF External Clock in (OSC1) Rise or
Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device e x ecuting code .
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
PIC16C7X
DS30390E-page 190 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-3: CLKOUT AND I/O TIMING
TABLE 18-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1
11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1
12* TckR CLKOUT rise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT ↑ 0.25TCY + 25 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1
17* TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid — 50 150 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16C73/74 100 — — ns
PIC16LC73/74 200 — — ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns
20* TioR Port output rise time PIC16C73/74 — 10 25 ns
PIC16LC73/74 — — 60 ns
21* TioF Port output fall time PIC16C73/74 — 10 25 ns
PIC16LC73/74 — — 60 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 18-1 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
old value new value
1997 Microchip Technology Inc. DS30390E-page 191
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
TABLE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse Width (low) 100 — — ns VDD = 5V, -40˚C to +85˚C
31* Twdt Watchdog Timer Time-out P eriod
(No Prescaler) 71833msVDD = 5V, -40˚C to +85˚C
32 Tost Oscillation Start-up Timer Period — 1024TOSC ——TOSC = OSC1 period
33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +85˚C
34 TIOZ I/O Hi-impedance from MCLR Low
or W atchdog Timer Reset — — 100 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 18-1 for load conditions.
PIC16C7X
DS30390E-page 192 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C7X 15 — — ns
PIC16LC7X 25 — — ns
Asynchronous PIC16C7X 30 — — ns
PIC16LC7X 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C7X 15 — — ns
PIC16LC7X 25 — — ns
Asynchronous PIC16C7X 30 — — ns
PIC16LC7X 50 — — ns
47* Tt1P T1CKI input period Synchronous PIC16C7X Greater of:
30 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
PIC16LC7X Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16C7X 60 — — ns
PIC16LC7X 100 — — ns
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 18-1 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 or
TMR1
1997 Microchip Technology Inc. DS30390E-page 193
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 18-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 and CCP2
input low time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C73/74 10 — — ns
PIC16LC73/74 20 — — ns
51* TccH CCP1 and CCP2
input high time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C73/74 10 — — ns
PIC16LC73/74 20 — — ns
52* TccP CCP1 and CCP2 input period 3TCY + 40
N— — ns N = prescale value
(1,4 or 16)
53* TccR CCP1 and CCP2 output fall time PIC16C73/74 — 10 25 ns
PIC16LC73/74 — 25 45 ns
54* TccF CCP1 and CCP2 output fall time PIC16C73/74 — 10 25 ns
PIC16LC73/74 — 25 45 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 18-1 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
PIC16C7X
DS30390E-page 194 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-7: PARALLEL SLAVE PORT TIMING (PIC16C74)
TABLE 18-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C74)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
62 TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20 — — ns
63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) PIC16C74 20 — — ns
PIC16LC74 35 — — ns
64 TrdL2dtV RD↓ and CS↓ to data–out valid — — 80 ns
65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 — 30 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 18-1 for load conditions
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
1997 Microchip Technology Inc. DS30390E-page 195
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-8: SPI MODE TIMING
TABLE 18-8: SPI MODE REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
70 TssL2scH,
TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns
71 TscH SCK input high time (slave mode) TCY + 20 — — ns
72 TscL SCK input low time (slave mode) TCY + 20 — — ns
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK
edge 50 — — ns
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK
edge 50 — — ns
75 TdoR SDO data output rise time — 10 25 ns
76 TdoF SDO data output fall time — 10 25 ns
77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78 TscR SCK output rise time (master mode) — 10 25 ns
79 TscF SCK output fall time (master mode) — 10 25 ns
80 TscH2doV,
TscL2doV SDO data output valid after SCK
edge — — 50 ns
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 18-1 for load conditions
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
PIC16C7X
DS30390E-page 196 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-9: I2C BUS START/STOP BITS TIMING
TABLE 18-9: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ Max Units Conditions
90 TSU:STA START condition 100 kHz mode 4700 — — ns Only relev ant for repeated START
condition
Setup time 400 kHz mode 600 — —
91 THD:STA START condition 100 kHz mode 4000 — — ns After this period the first clock
pulse is generated
Hold time 400 kHz mode 600 — —
92 TSU:STO STOP condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO STOP condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note: Refer to Figure 18-1 for load conditions
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
1997 Microchip Technology Inc. DS30390E-page 197
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-10: I2C BUS DATA TIMING
TABLE 18-10: I2C BUS DATA REQUIREMENTS
Parameter
No. Sym Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4.0 — µs De vice m ust operate at a mini-
mum of 1.5 MHz
400 kHz mode 0.6 — µs De vice m ust oper ate at a mini-
mum of 10 MHz
SSP Module 1.5TCY —
101 TLOW Clock low time 100 kHz mode 4.7 — µs Device must oper ate at a mini-
mum of 1.5 MHz
400 kHz mode 1.3 — µs De vice m ust oper ate at a mini-
mum of 10 MHz
SSP Module 1.5TCY —
102 TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
103 TFSDA and SCL fall time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
90 TSU:STA START condition
setup time 100 kHz mode 4.7 — µs Only relevant for repeated
START condition
400 kHz mode 0.6 — µs
91 THD:STA START condition hold
time 100 kHz mode 4.0 — µs After this period the first clock
pulse is generated
400 kHz mode 0.6 — µs
106 THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
92 TSU:STO STOP condition setup
time 100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109 TAA Output valid from
clock 100 kHz mode — 3500 ns Note 1
400 kHz mode — — ns
110 TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
before a ne w transmission can
start
400 kHz mode 1.3 — µs
Cb Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LO W period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
Note: Refer to Figure 18-1 for load conditions
90
91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC16C7X
DS30390E-page 198 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 18-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 18-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 18-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid PIC16C73/74 — — 80 ns
PIC16LC73/74 — — 100 ns
121 Tckrf Clock out rise time and fall time
(Master Mode) PIC16C73/74 — — 45 ns
PIC16LC73/74 — — 50 ns
122 Tdtrf Data out rise time and fall time PIC16C73/74 — — 45 ns
PIC16LC73/74 — — 50 ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
125 TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time) 15 — — ns
126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 18-1 for load conditions
121 121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Note: Refer to Figure 18-1 for load conditions
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
1997 Microchip Technology Inc. DS30390E-page 199
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
TABLE 18-13: A/D CONVERTER CHARACTERISTICS:
PIC16C73/74-04 (Commercial, Industrial)
PIC16C73/74-10 (Commercial, Industrial)
PIC16C73/74-20 (Commercial, Industrial)
PIC16LC73/74-04 (Commercial, Industrial)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 8-bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02 EABS Total Absolute error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 — Monotonicity — guaranteed — — VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage 3.0V — VDD + 0.3 V
A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V
A30 ZAIN Recommended impedance of
analog voltage source — — 10.0 kΩ
A40 IAD A/D conversion current
(VDD)PIC16C73/74 — 180 — µA Average current consump-
tion when A/D is on.
(Note 1)
PIC16LC73/74 — 90 — µA
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 13.1.
During A/D Conversion
cycle
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
PIC16C7X
DS30390E-page 200 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 18-13: A/D CONVERSION TIMING
TABLE 18-14: A/D CONVERSION REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
130 TAD A/D clock period PIC16C73/74 1.6 — — µsTOSC based, VREF ≥ 3.0V
PIC16LC73/74 2.0 — — µsTOSC based, VREF full range
PIC16C73/74 2.0 4.0 6.0 µs A/D RC Mode
PIC16LC73/74 3.0 6.0 9.0 µs A/D RC Mode
131 TCNV Conv ersion time (not including S/H time)
(Note 1) — 9.5 — TAD
132 TACQ Acquisition time Note 2
5*
20
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135 TSWC Switching from convert → sample time 1.5 § — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2) (1)
7 6543210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
134
1997 Microchip Technology Inc. DS30390E-page 201
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
19.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73A/74A
Absolute Maximum Ratings †
Ambient temperature under bias..................................................................................................................-55 to +125˚C
Storage temperature............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ................................................................................................. 0 to +14V
Voltage on RA4 with respect to Vss................................................................................................................... 0 to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin............................................................................................................................300 mA
Maximum current into VDD pin...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ...............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)...................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes belo w V SS at the MCLR pin, inducing currents g reater than 80 mA, may cause latch-up . Thus,
a series resistor of 50-100Ω should be used when applying a “low” lev el to the MCLR pin rather than pulling
this pin directly to VSS.
Note 3: PORTD and PORTE are not implemented on the PIC16C73A.
TABLE 19-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
de vice . This is a stress rating only and functional operation of the device at those or any other conditions abo ve those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
OSC PIC16C73A-04
PIC16C74A-04 PIC16C73A-10
PIC16C74A-10 PIC16C73A-20
PIC16C74A-20 PIC16LC73A-04
PIC16LC74A-04 JW Devices
RC
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3.0V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
XT
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3.0V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
HS
VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
Not recommended for
use in HS mode
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V IDD: 20 mA max. at 5.5V
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.
LP
VDD: 4.0V to 6.0V
IDD: 52.5 µA typ. at
32 kHz, 4.0V
IPD: 0.9 µA typ. at 4.0V
Freq: 200 kHz max.
Not recommended for
use in LP mode Not recommended for
use in LP mode
VDD: 2.5V to 6.0V
IDD: 48 µA max. at
32 kHz, 3.0V
IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max.
VDD: 2.5V to 6.0V
IDD: 48 µA max. at
32 kHz, 3.0V
IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
PIC16C7X
DS30390E-page 202 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
19.1 DC Characteristics: PIC16C73A/74A-04 (Commercial, Industrial, Extended)
PIC16C73A/74A-10 (Commercial, Industrial, Extended)
PIC16C73A/74A-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001
D001A Supply Voltage V DD 4.0
4.5 -
-6.0
5.5 V
VXT, RC and LP osc configuration
HS osc configuration
D002* RAM Data Retention
Voltage (Note 1) VDR - 1.5 - V
D003 VDD start voltage to
ensure internal Power-on
Reset signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled
3.7 4.0 4.4 V Extended Range Only
D010
D013
Supply Current (Note 2,5) IDD -
-
2.7
10
5
20
mA
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D015* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
D020
D021
D021A
D021B
Power-down Current
(Note 3,5) IPD -
-
-
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +125°C
D023* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These par ameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1997 Microchip Technology Inc. DS30390E-page 203
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
19.2 DC Characteristics: PIC16LC73A/74A-04 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001 Supply Voltage VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz)
D002* RAM Data Retention
Voltage (Note 1) VDR - 1.5 - V
D003 VDD start voltage to
ensure internal Po w er-on
Reset signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled
D010
D010A
Supply Current (Note 2,5) I DD -
-
2.0
22.5
3.8
48
mA
µA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D015* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
D020
D021
D021A
Power-down Current
(Note 3,5) IPD -
-
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
PIC16C7X
DS30390E-page 204 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
19.3 DC Characteristics: PIC16C73A/74A-04 (Commercial, Industrial, Extended)
PIC16C73A/74A-10 (Commercial, Industrial, Extended)
PIC16C73A/74A-20 (Commercial, Industrial, Extended)
PIC16LC73A/74A-04 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 19.1 and
Section 19.2.
Param
No. Characteristic Sym Min Typ
†Max Units Conditions
Input Low Voltage
I/O ports VIL
D030 with TTL buff er V SS - 0.15VDD V For entire VDD range
D030A VSS - 0.8V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS - 0.2VDD V
D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V
D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1
Input High Voltage
I/O ports VIH -
D040 with TTL buff er 2.0 - V DD V 4.5V ≤ VDD ≤ 5.5V
D040A 0.25VDD
+ 0.8V -VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range
D042 MCLR 0.8VDD -VDD V
D042A OSC1 (XT, HS and LP) 0.7VDD -VDD V Note1
D043 OSC1 (in RC mode) 0.9VDD -VDD V
D070 PORTB weak pull-up current IPURB 50 250 400 µAVDD = 5V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060 I/O ports IIL --±1µA Vss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061 MCLR, RA4/T0CKI - - ±5µA Vss ≤ VPIN ≤ VDD
D063 OSC1 - - ±5µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
Output Low Voltage
D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1997 Microchip Technology Inc. DS30390E-page 205
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
Output High Voltage
D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D150* Open-Drain High Voltage VOD - - 14 V RA4 pin
Capacitive Loading Specs on
Output Pins
D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102 All I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode CIO
CB-
--
-50
400 pF
pF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 19.1 and
Section 19.2.
Param
No. Characteristic Sym Min Typ
†Max Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC16C7X
DS30390E-page 206 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
19.4 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
FIGURE 19-1: LOAD CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
SF Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464Ω
CL= 50 pF f or all pins e xcept OSC2, b ut including POR TD and POR TE outputs as
ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16C73A.
Load condition 1 Load condition 2
1997 Microchip Technology Inc. DS30390E-page 207
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
19.5 Timing Diagrams and Specifications
FIGURE 19-2: EXTERNAL CLOCK TIMING
TABLE 19-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
Fosc External CLKIN Frequency
(Note 1) DC — 4 MHz XT and RC osc mode
DC — 4 MHz HS osc mode (-04)
DC — 10 MHz HS osc mode (-10)
DC — 20 MHz HS osc mode (-20)
DC — 200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC osc mode
0.1 — 4 MHz XT osc mode
4
5—
—20
200 MHz
kHz HS osc mode
LP osc mode
1 Tosc External CLKIN Period
(Note 1) 250 — — ns XT and RC osc mode
250 — — ns HS osc mode (-04)
100 — — ns HS osc mode (-10)
50 — — ns HS osc mode (-20)
5— —µs LP osc mode
Oscillator Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (-04)
100
50 —
—250
250 ns
ns HS osc mode (-10)
HS osc mode (-20)
5— —µs LP osc mode
2T
CY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC
3 TosL,
TosH External Clock in (OSC1) High or
Low Time 100 — — ns XT oscillator
2.5 — — µs LP oscillator
15 — — ns HS oscillator
4 TosR,
TosF External Clock in (OSC1) Rise or
Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device e x ecuting code .
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
PIC16C7X
DS30390E-page 208 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-3: CLKOUT AND I/O TIMING
TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1
11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1
12* TckR CLKOUT rise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT ↑ TOSC + 200 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1
17* TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid — 50 150 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16C73A/74A 100 — — ns
PIC16LC73A/74A 200 — — ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns
20* TioR Port output rise time PIC16C73A/74A — 10 40 ns
PIC16LC73A/74A — — 80 ns
21* TioF Port output fall time PIC16C73A/74A — 10 40 ns
PIC16LC73A/74A — — 80 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 19-1 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
old value new value
1997 Microchip Technology Inc. DS30390E-page 209
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 19-5: BROWN-OUT RESET TIMING
TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — µsVDD = 5V, -40˚C to +125˚C
31* Twdt Watchdog Timer Time-out P eriod
(No Prescaler) 71833msVDD = 5V, -40˚C to +125˚C
32 Tost Oscillation Start-up Timer Period — 1024TOSC ——TOSC = OSC1 period
33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C
34 TIOZ I/O Hi-impedance from MCLR Low
or W atchdog Timer Reset — — 2.1 µs
35 TBOR Brown-out Reset pulse width 100 — — µsVDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 19-1 for load conditions.
VDD BVDD
35
PIC16C7X
DS30390E-page 210 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C7X 15 — — ns
PIC16LC7X 25 — — ns
Asynchronous PIC16C7X 30 — — ns
PIC16LC7X 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C7X 15 — — ns
PIC16LC7X 25 — — ns
Asynchronous PIC16C7X 30 — — ns
PIC16LC7X 50 — — ns
47* Tt1P T1CKI input period Synchronous PIC16C7X Greater of:
30 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
PIC16LC7X Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16C7X 60 — — ns
PIC16LC7X 100 — — ns
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 19-1 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 or
TMR1
1997 Microchip Technology Inc. DS30390E-page 211
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 19-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 and CCP2
input low time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C73A/74A 10 — — ns
PIC16LC73A/74A 20 — — ns
51* TccH CCP1 and CCP2
input high time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C73A/74A 10 — — ns
PIC16LC73A/74A 20 — — ns
52* TccP CCP1 and CCP2 input period 3TCY + 40
N— — ns N = prescale
value (1,4 or 16)
53* TccR CCP1 and CCP2 output rise time PIC16C73A/74A —1025ns
PIC16LC73A/74A — 25 45 ns
54* TccF CCP1 and CCP2 output fall time PIC16C73A/74A —1025ns
PIC16LC73A/74A — 25 45 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated.
These parameters are for design guidance only and are not tested.
Note: Refer to Figure 19-1 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
PIC16C7X
DS30390E-page 212 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-8: PARALLEL SLAVE PORT TIMING (PIC16C74A)
TABLE 19-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C74A)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
62 TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20
25 —
——
—ns
ns Extended
Range Only
63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) PIC16C74A 20 — — ns
PIC16LC74A 35 — — ns
64 TrdL2dtV RD↓ and CS↓ to data–out valid —
——
—80
90 ns
ns Extended
Range Only
65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 — 30 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 19-1 for load conditions
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
1997 Microchip Technology Inc. DS30390E-page 213
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-9: SPI MODE TIMING
TABLE 19-8: SPI MODE REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
70 TssL2scH,
TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns
71 TscH SCK input high time (slave mode) TCY + 20 — — ns
72 TscL SCK input low time (slave mode) TCY + 20 — — ns
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK
edge 100 — — ns
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK
edge 100 — — ns
75 TdoR SDO data output rise time — 10 25 ns
76 TdoF SDO data output fall time — 10 25 ns
77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78 TscR SCK output rise time (master mode) — 10 25 ns
79 TscF SCK output fall time (master mode) — 10 25 ns
80 TscH2doV,
TscL2doV SDO data output valid after SCK
edge — — 50 ns
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 19-1 for load conditions
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
PIC16C7X
DS30390E-page 214 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-10: I2C BUS START/STOP BITS TIMING
TABLE 19-9: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ Max Units Conditions
90 TSU:STA START condition 100 kHz mode 4700 — — ns Only relev ant for repeated START
condition
Setup time 400 kHz mode 600 — —
91 THD:STA START condition 100 kHz mode 4000 — — ns After this period the first clock
pulse is generated
Hold time 400 kHz mode 600 — —
92 TSU:STO STOP condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO STOP condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note: Refer to Figure 19-1 for load conditions
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
1997 Microchip Technology Inc. DS30390E-page 215
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-11: I2C BUS DATA TIMING
TABLE 19-10: I2C BUS DATA REQUIREMENTS
Parameter
No. Sym Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4.0 — µs De vice m ust operate at a mini-
mum of 1.5 MHz
400 kHz mode 0.6 — µs De vice m ust oper ate at a mini-
mum of 10 MHz
SSP Module 1.5TCY —
101 TLOW Clock low time 100 kHz mode 4.7 — µs Device must oper ate at a mini-
mum of 1.5 MHz
400 kHz mode 1.3 — µs De vice m ust oper ate at a mini-
mum of 10 MHz
SSP Module 1.5TCY —
102 TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
103 TFSDA and SCL fall time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
90 TSU:STA START condition
setup time 100 kHz mode 4.7 — µs Only relevant for repeated
START condition
400 kHz mode 0.6 — µs
91 THD:STA START condition hold
time 100 kHz mode 4.0 — µs After this period the first clock
pulse is generated
400 kHz mode 0.6 — µs
106 THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
92 TSU:STO STOP condition setup
time 100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109 TAA Output valid from
clock 100 kHz mode — 3500 ns Note 1
400 kHz mode — — ns
110 TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
before a ne w transmission can
start
400 kHz mode 1.3 — µs
Cb Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LO W period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
Note: Refer to Figure 19-1 for load conditions
90
91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC16C7X
DS30390E-page 216 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 19-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 19-13: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 19-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid PIC16C73A/74A — — 80 ns
PIC16LC73A/74A — — 100 ns
121 Tckrf Clock out rise time and f all time
(Master Mode) PIC16C73A/74A — — 45 ns
PIC16LC73A/74A — — 50 ns
122 Tdtrf Data out rise time and fall time PIC16C73A/74A — — 45 ns
PIC16LC73A/74A — — 50 ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
125 TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time) 15 — — ns
126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 19-1 for load conditions
121 121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Note: Refer to Figure 19-1 for load conditions
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
1997 Microchip Technology Inc. DS30390E-page 217
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
TABLE 19-13: A/D CONVERTER CHARACTERISTICS:
PIC16C73A/74A-04 (Commercial, Industrial, Extended)
PIC16C73A/74A-10 (Commercial, Industrial, Extended)
PIC16C73A/74A-20 (Commercial, Industrial, Extended)
PIC16LC73A/74A-04 (Commercial, Industrial)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 8-bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02 EABS Total Absolute error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 — Monotonicity — guaranteed — — VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage 3.0V — VDD + 0.3 V
A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V
A30 ZAIN Recommended impedance of
analog voltage source — — 10.0 kΩ
A40 IAD A/D conversion current
(VDD)PIC16C73A/74A — 180 — µA Average current consump-
tion when A/D is on.
(Note 1)
PIC16LC73A/74A — 90 — µA
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 13.1.
During A/D Conversion
cycle
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
PIC16C7X
DS30390E-page 218 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 19-14: A/D CONVERSION TIMING
TABLE 19-14: A/D CONVERSION REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
130 TAD A/D clock period PIC16C73A/74A 1.6 — — µsTOSC based, VREF ≥ 3.0V
PIC16LC73A/74A 2.0 — — µsTOSC based, VREF full range
PIC16C73A/74A 2.0 4.0 6.0 µs A/D RC Mode
PIC16LC73A/74A 3.0 6.0 9.0 µs A/D RC Mode
131 TCNV Conversion time (not including S/H time)
(Note 1) — 9.5 — TAD
132 TACQ Acquisition time Note 2
5*
20
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135 TSWC Switching from convert → sample time 1.5 § — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2) (1)
7 6543210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
134
1997 Microchip Technology Inc. DS30390E-page 219
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
20.0 ELECTRICAL CHARACTERISTICS FOR PIC16C76/77
Absolute Maximum Ratings †
Ambient temperature under bias..................................................................................................................-55 to +125˚C
Storage temperature............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ................................................................................................. 0 to +14V
Voltage on RA4 with respect to Vss................................................................................................................... 0 to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin............................................................................................................................300 mA
Maximum current into VDD pin...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ...............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)...................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes belo w V SS at the MCLR pin, inducing currents g reater than 80 mA, may cause latch-up . Thus,
a series resistor of 50-100Ω should be used when applying a “low” lev el to the MCLR pin rather than pulling
this pin directly to VSS.
Note 3: PORTD and PORTE are not implemented on the PIC16C76.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
de vice . This is a stress rating only and functional operation of the device at those or any other conditions abo ve those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16C7X
DS30390E-page 220 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
TABLE 20-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
OSC PIC16C76-04
PIC16C77-04 PIC16C76-10
PIC16C77-10 PIC16C76-20
PIC16C77-20 PIC16LC76-04
PIC16LC77-04 JW Devices
RC
VDD: 4.0V to 6.0V
IDD: 5 mA max.
at 5.5V
IPD: 16 µA max.
at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ.
at 5.5V
IPD: 1.5 µA typ.
at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ.
at 5.5V
IPD: 1.5 µA typ.
at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max.
at 3.0V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max.
at 5.5V
IPD: 16 µA max.
at 4V
Freq: 4 MHz max.
XT
VDD: 4.0V to 6.0V
IDD: 5 mA max.
at 5.5V
IPD: 16 µA max.
at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ.
at 5.5V
IPD: 1.5 µA typ.
at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ.
at 5.5V
IPD: 1.5 µA typ.
at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max.
at 3.0V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max.
at 5.5V
IPD: 16 µA max.
at 4V
Freq: 4 MHz max.
HS
VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
Not recommended for
use in HS mode
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ.
at 5.5V IDD: 10 mA max.
at 5.5V IDD: 20 mA max.
at 5.5V IDD: 20 mA max.
at 5.5V
IPD: 1.5 µA typ.
at 4.5V IPD: 1.5 µA typ.
at 4.5V IPD: 1.5 µA typ.
at 4.5V IPD: 1.5 µA typ.
at 4.5V
Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.
LP
VDD: 4.0V to 6.0V
IDD: 52.5 µA typ.
at 32 kHz, 4.0V
IPD: 0.9 µA typ.
at 4.0V
Freq: 200 kHz max.
Not recommended for
use in LP mode Not recommended for
use in LP mode
VDD: 2.5V to 6.0V
IDD: 48 µA max.
at 32 kHz, 3.0V
IPD: 5.0 µA max.
at 3.0V
Freq: 200 kHz max.
VDD: 2.5V to 6.0V
IDD: 48 µA max.
at 32 kHz, 3.0V
IPD: 5.0 µA max.
at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
1997 Microchip Technology Inc. DS30390E-page 221
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
20.1 DC Characteristics: PIC16C76/77-04 (Commercial, Industrial, Extended)
PIC16C76/77-10 (Commercial, Industrial, Extended)
PIC16C76/77-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001
D001A Supply Voltage V DD 4.0
4.5 -
-6.0
5.5 V
VXT, RC and LP osc configuration
HS osc configuration
D002* RAM Data Retention
Voltage (Note 1) VDR - 1.5 - V
D003 VDD start voltage to
ensure internal Power-on
Reset signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled
3.7 4.0 4.4 V Extended Range Only
D010
D013
Supply Current (Note 2,5) IDD -
-
2.7
10
5
20
mA
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D015* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
D020
D021
D021A
D021B
Power-down Current
(Note 3,5) IPD -
-
-
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +125°C
D023* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These par ameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
PIC16C7X
DS30390E-page 222 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
20.2 DC Characteristics: PIC16LC76/77-04 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001 Supply Voltage VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz)
D002* RAM Data Retention
Voltage (Note 1) VDR - 1.5 - V
D003 VDD start voltage to
ensure internal Po w er-on
Reset signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled
D010
D010A
Supply Current (Note 2,5) I DD -
-
2.0
22.5
3.8
48
mA
µA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D015* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
D020
D021
D021A
Power-down Current
(Note 3,5) IPD -
-
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current
(Note 6) ∆IBOR - 350 425 µA BOR enabled VDD = 5.0V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1997 Microchip Technology Inc. DS30390E-page 223
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
20.3 DC Characteristics: PIC16C76/77-04 (Commercial, Industrial, Extended)
PIC16C76/77-10 (Commercial, Industrial, Extended)
PIC16C76/77-20 (Commercial, Industrial, Extended)
PIC16LC76/77-04 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 20.1 and
Section 20.2.
Param
No. Characteristic Sym Min Typ
†Max Units Conditions
Input Low Voltage
I/O ports VIL
D030 with TTL buff er V SS - 0.15VDD V For entire VDD range
D030A VSS - 0.8V V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS - 0.2VDD V
D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V
D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1
Input High Voltage
I/O ports VIH -
D040 with TTL buff er 2.0 - V DD V 4.5V ≤ VDD ≤ 5.5V
D040A 0.25VDD
+ 0.8V -VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range
D042 MCLR 0.8VDD -VDD V
D042A OSC1 (XT, HS and LP) 0.7VDD -VDD V Note1
D043 OSC1 (in RC mode) 0.9VDD -VDD V
D070 PORTB weak pull-up current IPURB 50 250 400 µAVDD = 5V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060 I/O ports IIL --±1µA Vss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061 MCLR, RA4/T0CKI - - ±5µA Vss ≤ VPIN ≤ VDD
D063 OSC1 - - ±5µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
Output Low Voltage
D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC16C7X
DS30390E-page 224 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
Output High Voltage
D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D150* Open-Drain High Voltage VOD - - 14 V RA4 pin
Capacitive Loading Specs on
Output Pins
D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102 All I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode CIO
CB-
--
-50
400 pF
pF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 20.1 and
Section 20.2.
Param
No. Characteristic Sym Min Typ
†Max Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1997 Microchip Technology Inc. DS30390E-page 225
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
20.4 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
FIGURE 20-1: LOAD CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
SF Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464Ω
CL= 50 pF f or all pins e xcept OSC2, b ut including POR TD and POR TE outputs as
ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16C76.
Load condition 1 Load condition 2
PIC16C7X
DS30390E-page 226 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
20.5 Timing Diagrams and Specifications
FIGURE 20-2: EXTERNAL CLOCK TIMING
TABLE 20-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
Fosc External CLKIN Frequency
(Note 1) DC — 4 MHz XT and RC osc mode
DC — 4 MHz HS osc mode (-04)
DC — 10 MHz HS osc mode (-10)
DC — 20 MHz HS osc mode (-20)
DC — 200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC osc mode
0.1 — 4 MHz XT osc mode
4
5—
—20
200 MHz
kHz HS osc mode
LP osc mode
1 Tosc External CLKIN Period
(Note 1) 250 — — ns XT and RC osc mode
250 — — ns HS osc mode (-04)
100 — — ns HS osc mode (-10)
50 — — ns HS osc mode (-20)
5— —µs LP osc mode
Oscillator Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (-04)
100
50
—
—
250
250
ns
ns
HS osc mode (-10)
HS osc mode (-20)
5— —µs LP osc mode
2T
CY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC
3 TosL,
TosH External Clock in (OSC1) High or
Low Time 100 — — ns XT oscillator
2.5 — — µs LP oscillator
15 — — ns HS oscillator
4 TosR,
TosF External Clock in (OSC1) Rise or
Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device e x ecuting code .
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
1997 Microchip Technology Inc. DS30390E-page 227
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-3: CLKOUT AND I/O TIMING
TABLE 20-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1
11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1
12* TckR CLKOUT rise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT ↑ TOSC + 200 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1
17* TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid — 50 150 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16C76/77 100 — — ns
PIC16LC76/77 200 — — ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns
20* TioR Port output rise time PIC16C76/77 — 10 40 ns
PIC16LC76/77 — — 80 ns
21* TioF Port output fall time PIC16C76/77 — 10 40 ns
PIC16LC76/77 — — 80 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 20-1 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
old value new value
PIC16C7X
DS30390E-page 228 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 20-5: BROWN-OUT RESET TIMING
TABLE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — µsVDD = 5V, -40˚C to +125˚C
31* Twdt Watchdog Timer Time-out P eriod
(No Prescaler) 71833msVDD = 5V, -40˚C to +125˚C
32 Tost Oscillation Start-up Timer Period — 1024TOSC ——TOSC = OSC1 period
33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C
34 TIOZ I/O Hi-impedance from MCLR Low
or W atchdog Timer Reset — — 2.1 µs
35 TBOR Brown-out Reset pulse width 100 — — µsVDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 20-1 for load conditions.
VDD BVDD
35
1997 Microchip Technology Inc. DS30390E-page 229
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C7X 15 — — ns
PIC16LC7X 25 — — ns
Asynchronous PIC16C7X 30 — — ns
PIC16LC7X 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C7X 15 — — ns
PIC16LC7X 25 — — ns
Asynchronous PIC16C7X 30 — — ns
PIC16LC7X 50 — — ns
47* Tt1P T1CKI input period Synchronous PIC16C7X Greater of:
30 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
PIC16LC7X Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16C7X 60 — — ns
PIC16LC7X 100 — — ns
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 20-1 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 or
TMR1
PIC16C7X
DS30390E-page 230 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 20-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 and CCP2
input low time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C76/77 10 — — ns
PIC16LC76/77 20 — — ns
51* TccH CCP1 and CCP2
input high time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C76/77 10 — — ns
PIC16LC76/77 20 — — ns
52* TccP CCP1 and CCP2 input period 3TCY + 40
N— — ns N = prescale
value (1,4 or 16)
53* TccR CCP1 and CCP2 output rise time PIC16C76/77 —1025ns
PIC16LC76/77 — 25 45 ns
54* TccF CCP1 and CCP2 output fall time PIC16C76/77 —1025ns
PIC16LC76/77 — 25 45 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated.
These parameters are for design guidance only and are not tested.
Note: Refer to Figure 20-1 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
1997 Microchip Technology Inc. DS30390E-page 231
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-8: PARALLEL SLAVE PORT TIMING (PIC16C77)
TABLE 20-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C77)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
62 TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20
25 —
——
—ns
ns Extended
Range Only
63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) PIC16C77 20 — — ns
PIC16LC77 35 — — ns
64 TrdL2dtV RD↓ and CS↓ to data–out valid —
——
—80
90 ns
ns Extended
Range Only
65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 — 30 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 20-1 for load conditions
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
PIC16C7X
DS30390E-page 232 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0)
FIGURE 20-10: SPI MASTER MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSB LSB
BIT6 - - - - - -1
MSB IN LSB IN
BIT6 - - - -1
Refer to Figure 20-1 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSB
79
73
MSB IN
BIT6 - - - - - -1
LSB IN
BIT6 - - - -1
LSB
Refer to Figure 20-1 for load conditions.
1997 Microchip Technology Inc. DS30390E-page 233
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-11: SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 20-12: SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSB LSB
BIT6 - - - - - -1
MSB IN BIT6 - - - -1 LSB IN
83
Refer to Figure 20-1 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSB BIT6 - - - - - -1 LSB
77
MSB IN BIT6 - - - -1 LSB IN
80
83
Refer to Figure 20-1 for load conditions.
PIC16C7X
DS30390E-page 234 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
TABLE 20-8: SPI MODE REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
70* TssL2scH,
TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns
71* TscH SCK input high time (slave mode) TCY + 20 — — ns
72* TscL SCK input low time (slave mode) TCY + 20 — — ns
73* TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK
edge 100 — — ns
74* TscH2diL,
TscL2diL Hold time of SDI data input to SCK
edge 100 — — ns
75* TdoR SDO data output rise time — 10 25 ns
76* TdoF SDO data output fall time — 10 25 ns
77* TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78* TscR SCK output rise time (master mode) — 10 25 ns
79* TscF SCK output fall time (master mode) — 10 25 ns
80* TscH2doV,
TscL2doV SDO data output valid after SCK
edge — — 50 ns
81* TdoV2scH,
TdoV2scL SDO data output setup to SCK
edge TCY ——ns
82* TssL2doV SDO data output valid after SS↓
edge — — 50 ns
83* TscH2ssH,
TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1997 Microchip Technology Inc. DS30390E-page 235
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-13: I2C BUS START/STOP BITS TIMING
TABLE 20-9: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ Max Units Conditions
90 TSU:STA START condition 100 kHz mode 4700 — — ns Only relev ant for repeated START
condition
Setup time 400 kHz mode 600 — —
91 THD:STA START condition 100 kHz mode 4000 — — ns After this period the first clock
pulse is generated
Hold time 400 kHz mode 600 — —
92 TSU:STO STOP condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO STOP condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note: Refer to Figure 20-1 for load conditions
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
PIC16C7X
DS30390E-page 236 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-14: I2C BUS DATA TIMING
TABLE 20-10: I2C BUS DATA REQUIREMENTS
Parameter
No. Sym Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4.0 — µs De vice m ust operate at a mini-
mum of 1.5 MHz
400 kHz mode 0.6 — µs De vice m ust oper ate at a mini-
mum of 10 MHz
SSP Module 1.5TCY —
101 TLOW Clock low time 100 kHz mode 4.7 — µs Device must oper ate at a mini-
mum of 1.5 MHz
400 kHz mode 1.3 — µs De vice m ust oper ate at a mini-
mum of 10 MHz
SSP Module 1.5TCY —
102 TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
103 TFSDA and SCL fall time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
90 TSU:STA START condition
setup time 100 kHz mode 4.7 — µs Only relevant for repeated
START condition
400 kHz mode 0.6 — µs
91 THD:STA START condition hold
time 100 kHz mode 4.0 — µs After this period the first clock
pulse is generated
400 kHz mode 0.6 — µs
106 THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
92 TSU:STO STOP condition setup
time 100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109 TAA Output valid from
clock 100 kHz mode — 3500 ns Note 1
400 kHz mode — — ns
110 TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
before a ne w transmission can
start
400 kHz mode 1.3 — µs
Cb Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LO W period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
Note: Refer to Figure 20-1 for load conditions
90
91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
1997 Microchip Technology Inc. DS30390E-page 237
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 20-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 20-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid PIC16C76/77 — — 80 ns
PIC16LC76/77 — — 100 ns
121 Tckrf Clock out rise time and f all time
(Master Mode) PIC16C76/77 — — 45 ns
PIC16LC76/77 — — 50 ns
122 Tdtrf Data out rise time and fall time PIC16C76/77 — — 45 ns
PIC16LC76/77 — — 50 ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
125 TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time) 15 — — ns
126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 20-1 for load conditions
121 121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Note: Refer to Figure 20-1 for load conditions
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
PIC16C7X
DS30390E-page 238 1997 Microchip Technology Inc.
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TABLE 20-13: A/D CONVERTER CHARACTERISTICS:
PIC16C76/77-04 (Commercial, Industrial, Extended)
PIC16C76/77-10 (Commercial, Industrial, Extended)
PIC16C76/77-20 (Commercial, Industrial, Extended)
PIC16LC76/77-04 (Commercial, Industrial)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 8-bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02 EABS Total Absolute error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 — Monotonicity — guaranteed — — VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage 3.0V — VDD + 0.3 V
A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V
A30 ZAIN Recommended impedance of
analog voltage source — — 10.0 kΩ
A40 IAD A/D conversion current
(VDD)PIC16C76/77 — 180 — µA Average current consump-
tion when A/D is on.
(Note 1)
PIC16LC76/77 — 90 — µA
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 13.1.
During A/D Conversion
cycle
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
1997 Microchip Technology Inc. DS30390E-page 239
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-17: A/D CONVERSION TIMING
TABLE 20-14: A/D CONVERSION REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
130 TAD A/D clock period PIC16C76/77 1.6 — — µsTOSC based, VREF ≥ 3.0V
PIC16LC76/77 2.0 — — µsTOSC based, VREF full range
PIC16C76/77 2.0 4.0 6.0 µs A/D RC Mode
PIC16LC76/77 3.0 6.0 9.0 µs A/D RC Mode
131 TCNV Conv ersion time (not including S/H time)
(Note 1) — 9.5 — TAD
132 TACQ Acquisition time Note 2
5*
20
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135 TSWC Switching from convert → sample time 1.5 § — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2) (1)
7 6543210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 Tcy
134
PIC16C7X
DS30390E-page 240 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
NOTES:
1997 Microchip Technology Inc. DS30390E-page 241
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
21.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (i.e., outside specified V
DD
range). This is for information only and devices are guaranteed to operate properly only within the specified
range.
FIGURE 21-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE)
FIGURE 21-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE)
Note: The data presented in this section is a statistical summary of data collected on units from diff erent lots o v er
a period of time and matr ix samples. 'Typical' represents the mean of the distr ibution at, 25°C, while 'max'
or 'min' represents (mean +3σ) and (mean -3σ) respectively where σ is standard deviation.
35
30
25
20
15
10
5
02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD(nA)
VDD(Volts)
IPD(µA)
VDD(Volts)
10.000
1.000
0.100
0.010
0.001
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
85°C
70°C
25°C
0°C
-40°C
PIC16C7X
DS30390E-page 242 1997 Microchip Technology Inc.
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FIGURE 21-3: TYPICAL IPD vs. VDD @ 25°C
(WDT ENABLED, RC MODE)
FIGURE 21-4: MAXIMUM IPD vs. VDD (WDT
ENABLED, RC MODE)
25
20
15
10
5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD(µA)
VDD(Volts)
35
30
25
20
15
10
5
02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD(µA)
VDD(Volts)
-40°C
0°C
70°C
85°C
FIGURE 21-5: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD
FIGURE 21-6: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD
FIGURE 21-7: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Fosc(MHz)
Cext = 22 pF, T = 25°C
R = 100k
R = 10k
R = 5k
Shaded area is beyond recommended range.
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Fosc(MHz)
Cext = 100 pF, T = 25°C
R = 100k
R = 10k
R = 5k
R = 3.3k
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
1000
900
800
700
600
500
400
300
200
100
0
Fosc(kHz)
Cext = 300 pF, T = 25°C
R = 3.3k
R = 5k
R = 10k
R = 100k
Data based on matrix samples. See first page of this section for details.
1997 Microchip Technology Inc. DS30390E-page 243
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 21-8: TYPICAL IPD vs. VDD BROWN-
OUT DETECT ENABLED (RC
MODE)
FIGURE 21-9: MAXIMUM IPD vs. VDD
BROWN-OUT DETECT
ENABLED
(85°C TO -40°C, RC MODE)
The shaded region represents the built-in hysteresis of the
brown-out reset circuitry.
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
1400
1200
1000
800
600
400
200
0
VDD(Volts)
IPD(µA)
Device in
Brown-out
Device NOT in
Brown-out Reset
Reset
The shaded region represents the built-in hysteresis of the
brown-out reset circuitry.
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
1400
1200
1000
800
600
400
200
0
VDD(Volts)
IPD(µA)
4.3
1600
Device NOT in
Brown-out Reset
Device in
Brown-out
Reset
FIGURE 21-10: TYPICAL IPD vs. TIMER1
ENABLED (32 kHz, RC0/RC1 =
33 pF/33 pF, RC MODE)
FIGURE 21-11: MAXIMUM IPD vs. TIMER1
ENABLED
(32 kHz, RC0/RC1 = 33 pF/33
pF, 85°C TO -40°C, RC MODE)
30
25
20
15
10
5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
IPD(µA)
30
25
20
15
10
5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
IPD(µA)
35
40
45
Data based on matrix samples. See first page of this section for details.
PIC16C7X
DS30390E-page 244 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 21-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25°C)
FIGURE 21-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C)
2000
1800
1600
1400
1200
800
1000
600
400
200
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency(MHz)
IDD(µA)
Shaded area is
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
beyond recommended range
2000
1800
1600
1400
1200
800
1000
600
400
200
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency(MHz)
IDD(µA)
Shaded area is
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
beyond recommended range
Data based on matrix samples. See first page of this section for details.
1997 Microchip Technology Inc. DS30390E-page 245
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 21-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25°C)
FIGURE 21-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C)
1600
1400
1200
1000
800
600
400
200
00 200 400 600 800 1000 1200 1400 1600 1800
Frequency(kHz)
IDD(µA)
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
Shaded area is
beyond recommended range
1600
1400
1200
1000
800
600
400
200
00 200 400 600 800 1000 1200 1400 1600 1800
Frequency(kHz)
IDD(µA)
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
Shaded area is
beyond recommended range
Data based on matrix samples. See first page of this section for details.
PIC16C7X
DS30390E-page 246 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 21-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25°C)
FIGURE 21-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C)
1200
1000
800
600
400
200
00 100 200 300 400 500 600 700
Frequency(kHz)
IDD(µA)
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
1200
1000
800
600
400
200
00 100 200 300 400 500 600 700
Frequency(kHz)
IDD(µA)
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
Data based on matrix samples. See first page of this section for details.
1997 Microchip Technology Inc. DS30390E-page 247
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 21-18: TYPICAL IDD vs.
CAPACITANCE @ 500 kHz
(RC MODE)
TABLE 21-1: RC OSCILLATOR
FREQUENCIES
Cext Rext Average
Fosc @ 5V, 25°C
22 pF 5k 4.12 MHz ± 1.4%
10k 2.35 MHz ± 1.4%
100k 268 kHz ± 1.1%
100 pF 3.3k 1.80 MHz ± 1.0%
5k 1.27 MHz ± 1.0%
10k 688 kHz ± 1.2%
100k 77.2 kHz ± 1.0%
300 pF 3.3k 707 kHz ± 1.4%
5k 501 kHz ± 1.2%
10k 269 kHz ± 1.6%
100k 28.3 kHz ± 1.1%
The percentage variation indicated here is part to
part variation due to normal process distribution. The
variation indicated is ±3 standard deviation from
average value for VDD = 5V.
Capacitance(pF)
600
IDD(µA)
500
400
300
200
100
0
20 pF 100 pF 300 pF
5.0V
4.0V
3.0V
FIGURE 21-19: TRANSCONDUCTANCE(gm)
OF HS OSCILLATOR vs. VDD
FIGURE 21-20: TRANSCONDUCTANCE(gm)
OF LP OSCILLATOR vs. VDD
FIGURE 21-21: TRANSCONDUCTANCE(gm)
OF XT OSCILLATOR vs. VDD
4.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
gm(mA/V)
VDD(Volts)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max -40°C
Typ 25°C
Min 85°C
Shaded area is
beyond recommended range
110
100
90
80
70
60
50
40
30
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
gm(µA/V)
VDD(Volts)
Max -40°C
Typ 25°C
Min 85°C
Shaded areas are
beyond recommended range
1000
900
800
700
600
500
400
300
200
100
02.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
gm(µA/V)
VDD(Volts)
Max -40°C
Typ 25°C
Min 85°C
Shaded areas are
beyond recommended range
Data based on matrix samples. See first page of this section for details.
PIC16C7X
DS30390E-page 248 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 21-22: TYPICAL XTAL STARTUP
TIME vs. VDD (LP MODE, 25°C)
FIGURE 21-23: TYPICAL XTAL STARTUP
TIME vs. VDD (HS MODE, 25°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
Startup Time(Seconds)
32 kHz, 33 pF/33 pF
200 kHz, 15 pF/15 pF
7
6
5
4
3
2
1
4.0 4.5 5.0 5.5 6.0
VDD(Volts)
Startup Time(ms)
20 MHz, 33 pF/33 pF
8 MHz, 33 pF/33 pF
8 MHz, 15 pF/15 pF
20 MHz, 15 pF/15 pF
FIGURE 21-24: TYPICAL XTAL STARTUP
TIME vs. VDD (XT MODE, 25°C)
TABLE 21-2: CAPACITOR SELECTION
FOR CRYSTAL
OSCILLATORS
Osc Type Crystal
Freq Cap. Range
C1 Cap. Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
Crystals
Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
70
60
50
40
30
20
10
03.0 3.52.5 4.0 5.0 5.5 6.04.5
VDD(Volts)
Startup Time(ms)
200 kHz, 68 pF/68 pF
200 kHz, 47 pF/47 pF
1 MHz, 15 pF/15 pF
4 MHz, 15 pF/15 pF
Data based on matrix samples. See first page of this section for details.
1997 Microchip Technology Inc. DS30390E-page 249
PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 21-25: TYPICAL IDD vs. FREQUENCY
(LP MODE, 25°C)
FIGURE 21-26: MAXIMUM IDD vs.
FREQUENCY
(LP MODE, 85°C TO -40°C)
120
100
80
60
40
20
00 50 100 150 200
Frequency(kHz)
IDD(µA)
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
120
100
80
60
40
20
00 50 100 150 200
Frequency(kHz)
IDD(µA)
140
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
FIGURE 21-27: TYPICAL IDD vs. FREQUENCY
(XT MODE, 25°C)
FIGURE 21-28: MAXIMUM IDD vs.
FREQUENCY
(XT MODE, -40°C TO 85°C)
1200
1000
800
600
400
200
0
0.0 0.4 Frequency(MHz)
IDD(µA)
1400
1600
1800
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
1200
1000
800
600
400
200
0
0.0 0.4 Frequency(MHz)
IDD(µA)
1400
1600
1800
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
Data based on matrix samples. See first page of this section for details.
PIC16C7X
DS30390E-page 250 1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 21-29: TYPICAL IDD vs. FREQUENCY
(HS MODE, 25°C)
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.012 4 6 8 10 12 14 16 18 20
Frequency(MHz)
IDD(mA)
6.0V
5.5V
5.0V
4.5V
4.0V
FIGURE 21-30: MAXIMUM IDD vs.
FREQUENCY
(HS MODE, -40°C TO 85°C)
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.012 4 6 8 10 12 14 16 18 20
Frequency(MHz)
IDD(mA)
6.0V
5.5V
5.0V
4.5V
4.0V
Data based on matrix samples. See first page of this section for details.
1997 Microchip Technology Inc. DS30390E-page 251
PIC16C7X
22.0 PACKAGING INFORMATION
22.1 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil)(JW)
Package Group: Ceramic Side Brazed Dual In-Line (CER)
Symbol Millimeters Inches
Min Max Notes Min Max Notes
α0°10°0°10°
A 3.937 5.030 0.155 0.198
A1 1.016 1.524 0.040 0.060
A2 2.921 3.506 0.115 0.138
A3 1.930 2.388 0.076 0.094
B 0.406 0.508 0.016 0.020
B1 1.219 1.321 Typical 0.048 0.052
C 0.228 0.305 Typical 0.009 0.012
D 35.204 35.916 1.386 1.414
D1 32.893 33.147 Reference 1.295 1.305
E 7.620 8.128 0.300 0.320
E1 7.366 7.620 0.290 0.300
e1 2.413 2.667 Typical 0.095 0.105
eA 7.366 7.874 Reference 0.290 0.310
eB 7.594 8.179 0.299 0.322
L 3.302 4.064 0.130 0.160
N2828 2828
S 1.143 1.397 0.045 0.055
S1 0.533 0.737 0.021 0.029
E1 E
S
Base
Plane
Seating
Plane
B1 B
S1
D
LA1 A2A3 A
e1
Pin #1
Indicator Area
D1
C
eA
eB
α
N
PIC16C7X
DS30390E-page 252 1997 Microchip Technology Inc.
22.2 40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) (JW)
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
α0°10°0°10°
A 4.318 5.715 0.170 0.225
A1 0.381 1.778 0.015 0.070
A2 3.810 4.699 0.150 0.185
A3 3.810 4.445 0.150 0.175
B 0.355 0.585 0.014 0.023
B1 1.270 1.651 Typical 0.050 0.065 Typical
C 0.203 0.381 Typical 0.008 0.015 Typical
D 51.435 52.705 2.025 2.075
D1 48.260 48.260 Reference 1.900 1.900 Reference
E 15.240 15.875 0.600 0.625
E1 12.954 15.240 0.510 0.600
e1 2.540 2.540 Reference 0.100 0.100 Reference
eA 14.986 16.002 Typical 0.590 0.630 Typical
eB 15.240 18.034 0.600 0.710
L 3.175 3.810 0.125 0.150
N4040 4040
S 1.016 2.286 0.040 0.090
S1 0.381 1.778 0.015 0.070
N
Pin No. 1
Indicator
Area
E1 E
SD
B1
BD1
Base
Plane
Seating
Plane
S1
A1 A3 AA2
L
e1
αC
eA
eB
1997 Microchip Technology Inc. DS30390E-page 253
PIC16C7X
22.3 28-Lead Plastic Dual In-line (300 mil) (SP)
Package Group: Plastic Dual In-Line (PLA)
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
α0°10°0°10°
A 3.632 4.572 0.143 0.180
A1 0.381 – 0.015 –
A2 3.175 3.556 0.125 0.140
B 0.406 0.559 0.016 0.022
B1 1.016 1.651 Typical 0.040 0.065 Typical
B2 0.762 1.016 4 places 0.030 0.040 4 places
B3 0.203 0.508 4 places 0.008 0.020 4 places
C 0.203 0.331 Typical 0.008 0.013 Typical
D 34.163 35.179 1.385 1.395
D1 33.020 33.020 Reference 1.300 1.300 Reference
E 7.874 8.382 0.310 0.330
E1 7.112 7.493 0.280 0.295
e1 2.540 2.540 Typical 0.100 0.100 Typical
eA 7.874 7.874 Reference 0.310 0.310 Reference
eB 8.128 9.652 0.320 0.380
L 3.175 3.683 0.125 0.145
N 28 - 28 -
S 0.584 1.220 0.023 0.048
N
Pin No. 1
Indicator
Area
E1 E
SD
D1
Base
Plane
Seating
Plane
A1 A2 A
L
e1
αC
eA
eB
Detail A
Detail A
B2 B1
B
B3
PIC16C7X
DS30390E-page 254 1997 Microchip Technology Inc.
22.4 40-Lead Plastic Dual In-line (600 mil) (P)
Package Group: Plastic Dual In-Line (PLA)
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
α0°10°0°10°
A – 5.080 – 0.200
A1 0.381 – 0.015 –
A2 3.175 4.064 0.125 0.160
B 0.355 0.559 0.014 0.022
B1 1.270 1.778 Typical 0.050 0.070 Typical
C 0.203 0.381 Typical 0.008 0.015 Typical
D 51.181 52.197 2.015 2.055
D1 48.260 48.260 Reference 1.900 1.900 Reference
E 15.240 15.875 0.600 0.625
E1 13.462 13.970 0.530 0.550
e1 2.489 2.591 Typical 0.098 0.102 Typical
eA 15.240 15.240 Reference 0.600 0.600 Reference
eB 15.240 17.272 0.600 0.680
L 2.921 3.683 0.115 0.145
N4040 4040
S 1.270 – 0.050 –
S1 0.508 – 0.020 –
N
Pin No. 1
Indicator
Area
E1 E
SD
B1
BD1
Base
Plane
Seating
Plane
S1
A1 A2 A
L
e1
αC
eA
eB
1997 Microchip Technology Inc. DS30390E-page 255
PIC16C7X
22.5 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO)
Package Group: Plastic SOIC (SO)
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
α0°8°0°8°
A 2.362 2.642 0.093 0.104
A1 0.101 0.300 0.004 0.012
B 0.355 0.483 0.014 0.019
C 0.241 0.318 0.009 0.013
D 17.703 18.085 0.697 0.712
E 7.416 7.595 0.292 0.299
e 1.270 1.270 Typical 0.050 0.050 Typical
H 10.007 10.643 0.394 0.419
h 0.381 0.762 0.015 0.030
L 0.406 1.143 0.016 0.045
N2828 2828
CP – 0.102 – 0.004
Be
N
Index
Area
Chamfer
h x 45°
α
EH
123
CP
h x 45°
C
L
Seating
Plane
Base
Plane
D
A1 A
PIC16C7X
DS30390E-page 256 1997 Microchip Technology Inc.
22.6 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS)
Package Group: Plastic SSOP
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
α0°8°0°8°
A 1.730 1.990 0.068 0.078
A1 0.050 0.210 0.002 0.008
B 0.250 0.380 0.010 0.015
C 0.130 0.220 0.005 0.009
D 10.070 10.330 0.396 0.407
E 5.200 5.380 0.205 0.212
e 0.650 0.650 Reference 0.026 0.026 Reference
H 7.650 7.900 0.301 0.311
L 0.550 0.950 0.022 0.037
N2828 2828
CP - 0.102 - 0.004
Index
area
N
H
123
E
eB
CP
D
A
A1
Base plane
Seating plane
L
C
α
1997 Microchip Technology Inc. DS30390E-page 257
PIC16C7X
22.7 44-Lead Plastic Leaded Chip Carrier (Square)(PLCC)
Package Group: Plastic Leaded Chip Carrier (PLCC)
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
A 4.191 4.572 0.165 0.180
A1 2.413 2.921 0.095 0.115
D 17.399 17.653 0.685 0.695
D1 16.510 16.663 0.650 0.656
D2 15.494 16.002 0.610 0.630
D3 12.700 12.700 Reference 0.500 0.500 Reference
E 17.399 17.653 0.685 0.695
E1 16.510 16.663 0.650 0.656
E2 15.494 16.002 0.610 0.630
E3 12.700 12.700 Reference 0.500 0.500 Reference
N4444 4444
CP – 0.102 – 0.004
LT 0.203 0.381 0.008 0.015
S
0.177
.007 BD-E
-A-
0.254
D1
D
3
3
3
-C-
-F-
-D-
4
9
8
-B-
-E- S
0.177
.007 AF-G
S
S
EE1
-H-
-G-
6
2
3
.010 Max 1.524
.060
10
2
11
0.508
.020
1.651
.065
R1.14/0.64
.045/.025 R1.14/0.64
.045/.025
1.651
.065
0.508
.020 -H-
11
0.254
.010 Max
6
Min
0.812/0.661
.032/.026 3
-C-
0.64
.025 Min 5
0.533/0.331
.021/.013
0.177
.007 MAF-G S ,D-E S
1.27
.050
2 Sides AS
0.177
.007 BA
S
D3/E3
D20.101
.004
0.812/0.661
.032/.026
S
0.38
.015 F-G
4
S
0.38
.015 F-G
E2
D
-H-
A1
Seating
Plane
2 Sides
N Pics
PIC16C7X
DS30390E-page 258 1997 Microchip Technology Inc.
22.8 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) (PQ)
Package Group: Plastic MQFP
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
α0°7°0°7°
A 2.000 2.350 0.078 0.093
A1 0.050 0.250 0.002 0.010
A2 1.950 2.100 0.768 0.083
b 0.300 0.450 Typical 0.011 0.018 Typical
C 0.150 0.180 0.006 0.007
D 12.950 13.450 0.510 0.530
D1 9.900 10.100 0.390 0.398
D3 8.000 8.000 Reference 0.315 0.315 Reference
E 12.950 13.450 0.510 0.530
E1 9.900 10.100 0.390 0.398
E3 8.000 8.000 Reference 0.315 0.315 Reference
e 0.800 0.800 0.031 0.032
L 0.730 1.030 0.028 0.041
N4444 4444
CP 0.102 – 0.004 –
Index
area
9b
TYP 4x
Base
Plane
A2
eB
A
A1
Seating
Plane
6
D
D1
D3
4
5 7
E3E1E
10 0.20 M A-B
0.05 mm/mm D
HSSD
0.20 M A-B
CSSD
75
4
0.20 M A-B
CSSD
0.20 M A-B
HSSD
0.05 mm/mm A-B
C
L
1.60 Ref.
0.13/0.30 R
0.13 R min.
0.20 min.
PARTING
LINE
α
1997 Microchip Technology Inc. DS30390E-page 259
PIC16C7X
22.9 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) (TQ)
Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per
side. D1 and E1 dimensions including mold mismatch.
2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m
(0.003”)max.
3: This outline conforms to JEDEC MS-026.
Package Group: Plastic TQFP
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
A 1.00 1.20 0.039 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
D 11.75 12.25 0.463 0.482
D1 9.90 10.10 0.390 0.398
E 11.75 12.25 0.463 0.482
E1 9.90 10.10 0.390 0.398
L 0.45 0.75 0.018 0.030
e 0.80 BSC 0.031 BSC
b 0.30 0.45 0.012 0.018
b1 0.30 0.40 0.012 0.016
c 0.09 0.20 0.004 0.008
c1 0.09 0.16 0.004 0.006
N4444 4444
Θ0°7°0°7°
D
E
D1
E1
Pin#1
2
e
1.0ø (0.039ø) Ref.
Option 1 (TOP side)
Pin#1
2
Option 2 (TOP side)
3.0ø (0.118ø) Ref.
Detail A
Detail B L
1.00 Ref.
A2 A1 Ab
b1
cc1
Base Metal
Detail A
Lead Finish
Detail B
11°/13°(4x)
0° Min
11°/13°(4x)
Θ
R1 0.08 Min
R 0.08/0.20
Gage Plane
0.250
L
L1
S
0.20
Min
1.00 Ref
Detail B
PIC16C7X
DS30390E-page 260 1997 Microchip Technology Inc.
22.10 Package Marking Information
Legend: MM...M
XX...X
AA
BB
C
D1
E
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
Note:
Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
*
S = Tempe, Arizona, U.S.A.
AABBCAE
XXXXXXXXXXXX
XXXXXXXXXXXX
28-Lead SSOP
9517SBP
20I/SS025
PIC16C72
Example
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX
AABBCDE
MMMMMMMMMMMMMMMM
Example
945/CAA
PIC16C73-10/SO
XXXXXXXXXXXXXXX
AABBCDE
28-Lead PDIP (Skinny DIP)
MMMMMMMMMMMM
AABBCDE
Example
PIC16C73-10/SP
Example28-Lead Side Brazed Skinny Windowed
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
PIC16C73/JW
9517CAT
1997 Microchip Technology Inc. DS30390E-page 261
PIC16C7X
Package Marking Information (Cont’d)
Legend: MM...M
XX...X
AA
BB
C
D1
E
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
Note:
Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
*
S = Tempe, Arizona, U.S.A.
XXXXXXXXXXXXXXXXXX
AABBCDE
40-Lead PDIP
MMMMMMMMMMMMMM
9512CAA
Example
PIC16C74-04/P
44-Lead PLCC
MMMMMMMM
AABBCDE
XXXXXXXXXX
XXXXXXXXXX
44-Lead MQFP
XXXXXXXXXX
AABBCDE
MMMMMMMM
XXXXXXXXXX
Example
PIC16C74
AABBCDE
-10/L
Example
-10/PQ
AABBCDE
PIC16C74
MMMMMMMMM
XXXXXXXXXXX
AABBCDE
40-Lead CERDIP Windowed
XXXXXXXXXXX
PIC16C74/JW
AABBCDE
Example
PIC16C7X
DS30390E-page 262 1997 Microchip Technology Inc.
Package Marking Information (Cont’d)
Legend: MM...M
XX...X
AA
BB
C
D1
E
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
Note:
Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
*
S = Tempe, Arizona, U.S.A.
44-Lead TQFP
XXXXXXXXXX
AABBCDE
MMMMMMMM
XXXXXXXXXX
Example
-10/TQ
AABBCDE
PIC16C74A
1997 Microchip Technology Inc. DS30390E-page 263
PIC16C7X
APPENDIX A:
The following are the list of modifications over the
PIC16C5X microcontroller family:
1. Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 bef ore) and
register file (128 bytes now versus 32 bytes
before).
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
3. Data memory paging is redefined slightly.
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compati-
bility with PIC16C5X.
5. OPTION and TRIS registers are made address-
able.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Reg-
isters are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These tim-
ers are inv oked selectiv ely to av oid unnecessary
delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change feature.
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full eight bit register.
15. “In-circuit serial programming” is made possib le.
The user can program PIC16CXX de vices using
only five pins: VDD, VSS, MCLR/VPP, RB6 (clock)
and RB7 (data in/out).
16. PCON status register is added with a Power-on
Reset status bit (POR).
17. Code protection scheme is enhanced such that
portions of the program memory can be pro-
tected, while the remainder is unprotected.
18. Brown-out protection circuitry has been added.
Controlled by configuration word bit BODEN.
Brown-out reset ensures the device is placed in
a reset condition if VDD dips below a fixed set-
point.
APPENDIX B: COMPATIBILITY
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1. Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Verify all wr ites to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
PIC16C7X
DS30390E-page 264 1997 Microchip Technology Inc.
APPENDIX C: WHAT’S NEW
Added the following devices:
• PIC16C76
• PIC16C77
Removed the PIC16C710, PIC16C71, PIC16C711
from this datasheet.
Added PIC16C76 and PIC16C77 devices. The
PIC16C76/77 devices have 368 bytes of data memory
distributed in 4 banks and 8K of program memory in 4
pages. These two devices have an enhanced SPI that
supports both clock phase and polarity. The USART
has been enhanced.
When upgrading to the PIC16C76/77 please note that
the upper 16 bytes of data memory in banks 1,2, and 3
are mapped into bank 0. This may require relocation of
data memory usage in the user application code.
Added Q-cycle definitions to the Instruction Set Sum-
mary section.
APPENDIX D: WHAT’S CHANGED
Minor changes, spelling and grammatical changes.
Added the following note to the USART section. This
note applies to all devices except the PIC16C76 and
PIC16C77.
For the PIC16C73/73A/74/74A the asynchronous high
speed mode (BRGH = 1) ma y experience a high rate of
receive errors . It is recommended that BRGH = 0. If you
desire a higher baud rate than BRGH = 0 can suppor t,
refer to the device errata for additional information or
use the PIC16C76/77.
Divided SPI section into SPI for the PIC16C76/77 and
SPI for all other devices.
1997 Microchip Technology Inc. DS30390E-page 265
PIC16C7X
APPENDIX E: PIC16/17 MICROCONTROLLERS
E.1 PIC12CXXX Family of Devices
E.2 PIC14C000 Family of Devices
PIC12C508 PIC12C509 PIC12C671 PIC12C672
Clock Maximum Frequency
of Operation (MHz) 4444
Memory EPROM Program Memory 512 x 12 1024 x 12 1024 x 14 2048 x 14
Data Memory (bytes) 25 41 128 128
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0
A/D Converter (8-bit) Channels — — 4 4
Features
Wake-up from SLEEP on
pin change Yes Yes Yes Yes
I/O Pins 5555
Input Pins 1111
Internal Pull-ups Yes Yes Yes Yes
Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5
In-Circuit Serial Programming Yes Yes Yes Yes
Number of Instructions 33 33 35 35
Packages 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC
All PIC12C5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC12C5XX devices use serial programming with data pin GP1 and clock pin GP0.
PIC14C000
Clock Maximum Frequency of Operation (MHz) 20
Memory
EPROM Program Memory (x14 words) 4K
Data Memory (bytes) 192
Timer Module(s) TMR0
ADTMR
Peripherals Serial Port(s)
(SPI/I2C, USART) I2C with SMBus
Support
Features
Slope A/D Converter Channels 8 External; 6 Internal
Interrupt Sources 11
I/O Pins 22
Voltage Range (Volts) 2.7-6.0
In-Circuit Serial Programming Yes
Additional On-chip Features Internal 4MHz Oscillator, Bandgap Reference,Temperature Sensor,
Calibration Factors, Low Voltage Detector, SLEEP, HIBERNATE,
Comparators with Programmable References (2)
Packages 28-pin DIP (.300 mil), SOIC, SSOP
PIC16C7X
DS30390E-page 266 1997 Microchip Technology Inc.
E.3 PIC16C15X Family of Devices
E.4 PIC16C5X Family of Devices
PIC16C154 PIC16CR154 PIC16C156 PIC16CR156 PIC16C158 PIC16CR158
Clock Maximum Frequency
of Operation (MHz) 20 20 20 20 20 20
Memory
EPROM Program Memory
(x12 words) 512 — 1K — 2K —
ROM Program Memory
(x12 words) — 512 — 1K — 2K
RAM Data Memory (bytes) 25 25 25 25 73 73
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0
Features
I/O Pins 12 12 12 12 12 12
Voltage Range (Volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5
Number of Instructions 33 33 33 33 33 33
Packages 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability.
PIC16C52 PIC16C54 PIC16C54A PIC16CR54A PIC16C55 PIC16C56
Clock Maximum Frequency
of Operation (MHz) 4202020 2020
Memory
EPROM Program Memory
(x12 words) 384 512 512 — 512 1K
ROM Program Memory
(x12 words) — — — 512 — —
RAM Data Memory (bytes) 25 25 25 25 24 25
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0
Features
I/O Pins 12 12 12 12 20 12
Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.25
Number of Instructions 33 33 33 33 33 33
Packages 18-pin DIP,
SOIC 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
28-pin DIP,
SOIC,
SSOP
18-pin DIP,
SOIC;
20-pin SSOP
PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A
Clock Maximum Frequency
of Operation (MHz) 20 20 20 20
Memory
EPROM Program Memory
(x12 words) 2K — 2K —
ROM Program Memory
(x12 words) —2K — 2K
RAM Data Memory (bytes) 72 72 73 73
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0
Features
I/O Pins 20 20 12 12
Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25
Number of Instructions 33 33 33 33
Packages 28-pin DIP,
SOIC,
SSOP
28-pin DIP, SOIC,
SSOP 18-pin DIP, SOIC;
20-pin SSOP 18-pin DIP, SOIC;
20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and
high I/O current capability.
1997 Microchip Technology Inc. DS30390E-page 267
PIC16C7X
E.5 PIC16C55X Family of Devices
E.6 PIC16C62X and PIC16C64X Family of Devices
PIC16C554 PIC16C556(1) PIC16C558
Clock Maximum Frequency of Operation (MHz) 20 20 20
Memory EPROM Program Memory (x14 words) 512 1K 2K
Data Memory (bytes) 80 80 128
Peripherals Timer Module(s) TMR0 TMR0 TMR0
Comparators(s) — — —
Internal Reference Voltage — — —
Features
Interrupt Sources 3 3 3
I/O Pins 13 13 13
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0
Brown-out Reset — — —
Packages 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
PIC16C620 PIC16C621 PIC16C622 PIC16C642 PIC16C662
Clock Maximum Frequency
of Operation (MHz) 20 20 20 20 20
Memory EPROM Program Memory
(x14 words) 512 1K 2K 4K 4K
Data Memory (bytes) 80 80 128 176 176
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0
Comparators(s) 22222
Internal Reference Voltage Yes Yes Yes Yes Yes
Features
Interrupt Sources 44445
I/O Pins 13 13 13 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 3.0-6.0 3.0-6.0
Brown-out Reset Yes Yes Yes Yes Yes
Packages 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
28-pin PDIP,
SOIC,
Windowed
CDIP
40-pin PDIP,
Windowed
CDIP;
44-pin PLCC,
MQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C62X and PIC16C64X Family devices use serial programming with clock pin RB6 and data pin RB7.
PIC16C7X
DS30390E-page 268 1997 Microchip Technology Inc.
E.7 PIC16C6X Family of Devices
PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63
Clock Maximum Frequency
of Operation (MHz) 20 20 20 20 20
Memory
EPROM Program Memory
(x14 words) 1K 2K — 4K —
ROM Program Memory
(x14 words) — — 2K — 4K
Data Memory (bytes) 36 128 128 192 192
Peripherals
Timer Module(s) TMR0 TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/
PWM Module(s) —1122
Serial Port(s)
(SPI/I2C, USART) — SPI/I2C SPI/I2C SPI/I2C,
USART SPI/I2C
USART
Parallel Slave Port — — — — —
Features
Interrupt Sources 3 7 7 10 10
I/O Pins 13 22 22 22 22
Voltage Range (Volts) 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit Serial Programming Yes Yes Yes Yes Yes
Brown-out Reset — Yes Yes Yes Yes
Packages 18-pin DIP, SO 28-pin SDIP,
SOIC, SSOP 28-pin SDIP,
SOIC, SSOP 28-pin SDIP,
SOIC 28-pin SDIP,
SOIC
PIC16C64A PIC16CR64 PIC16C65A PIC16CR65 PIC16C66 PIC16C67
Clock Maximum Frequency
of Operation (MHz) 20 20 20 20 20 20
Memory
EPROM Program Memory
(x14 words) 2K — 4K — 8K 8K
ROM Program Memory (x14
words) —2K— 4K——
Data Memory (bytes) 128 128 192 192 368 368
Peripherals
Timer Module(s) TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/PWM Mod-
ule(s) 1 1 2 222
Serial Port(s) (SPI/I2C, USART) SPI/I2C SPI/I2C SPI/I2C,
USART SPI/I2C,
USART SPI/I2C,
USART SPI/I2C,
USART
Parallel Slave Port Yes Yes Yes Yes — Yes
Features
Interrupt Sources 8 8 11 11 10 11
I/O Pins 33 33 33 33 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes Yes Yes Yes Yes Yes
Packages 40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin
PLCC,
MQFP,
TQFP
28-pin SDIP,
SOIC 40-pin DIP;
44-pin
PLCC,
MQFP,
TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7.
1997 Microchip Technology Inc. DS30390E-page 269
PIC16C7X
E.8 PIC16C8X Family of Devices
E.9 PIC16C9XX Family Of Devices
PIC16F83 PIC16CR83 PIC16F84 PIC16CR84
Clock Maximum Frequency
of Operation (MHz) 10 10 10 10
Flash Program Memory 512 — 1K —
Memory EEPROM Program Memory — — — —
ROM Program Memory — 512 — 1K
Data Memory (bytes) 36 36 68 68
Data EEPROM (bytes) 64 64 64 64
Peripher-
als Timer Module(s) TMR0 TMR0 TMR0 TMR0
Features
Interrupt Sources 4 4 4 4
I/O Pins 13 13 13 13
Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0
Packages 18-pin DIP,
SOIC 18-pin DIP,
SOIC 18-pin DIP,
SOIC 18-pin DIP,
SOIC
All PIC16/17 Family de vices ha ve Power-on Reset, selectable Watchdog Timer, selectab le code protect and high I/O current capabi l-
ity. All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7.
PIC16C923 PIC16C924
Clock Maximum Frequency of Operation (MHz) 8 8
Memory EPROM Program Memory 4K 4K
Data Memory (bytes) 176 176
Peripherals
Timer Module(s) TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/PWM Module(s) 1 1
Serial Port(s)
(SPI/I2C, USART) SPI/I2C SPI/I2C
Parallel Slave Port — —
A/D Converter (8-bit) Channels — 5
LCD Module 4 Com,
32 Seg 4 Com,
32 Seg
Features
Interrupt Sources 8 9
I/O Pins 25 25
Input Pins 27 27
Voltage Range (Volts) 3.0-6.0 3.0-6.0
In-Circuit Serial Programming Yes Yes
Brown-out Reset — —
Packages 64-pin SDIP(1),
TQFP;
68-pin PLCC,
Die
64-pin SDIP(1),
TQFP;
68-pin PLCC,
Die
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa-
bility. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7.
PIC16C7X
DS30390E-page 270 1997 Microchip Technology Inc.
E.10 PIC17CXXX Family of Devices
PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44
Clock Maximum Frequency
of Operation (MHz) 33 33 33 33 33
Memory
EPROM Program Memory
(words) 2K — 4K — 8K
ROM Program Memory
(words) — 2K — 4K —
RAM Data Memory (bytes) 232 232 454 454 454
Peripherals
Timer Module(s) TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
Captures/PWM Module(s) 22222
Serial Port(s) (USART) Yes Yes Yes Yes Yes
Features
Hardware Multiply Yes Yes Yes Yes Yes
External Interrupts Yes Yes Yes Yes Yes
Interrupt Sources 11 11 11 11 11
I/O Pins 33 33 33 33 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
Number of Instructions 58 58 58 58 58
Packages 40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
PIC17C752 PIC17C756
Clock Maximum Frequency
of Operation (MHz) 33 33
Memory
EPROM Program Memory
(words) 8K 16K
ROM Program Memory
(words) ——
RAM Data Memory (bytes) 454 902
Peripherals
Timer Module(s) TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
Captures/PWM Module(s) 4/3 4/3
Serial Port(s) (USART) 2 2
Features
Hardware Multiply Yes Yes
External Interrupts Yes Yes
Interrupt Sources 18 18
I/O Pins 50 50
Voltage Range (Volts) 3.0-6.0 3.0-6.0
Number of Instructions 58 58
Packages 64-pin DIP;
68-pin LCC,
68-pin TQFP
64-pin DIP;
68-pin LCC,
68-pin TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability.
1997 Microchip Technology Inc. DS30390E-page 271
PIC16C7X
PIN COMPATIBILITY
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE E-1: PIN COMPATIBLE DEVICES
Pin Compatible Devices Package
PIC12C508, PIC12C509, PIC12C671, PIC12C672 8-pin
PIC16C154, PIC16CR154, PIC16C156,
PIC16CR156, PIC16C158, PIC16CR158,
PIC16C52, PIC16C54, PIC16C54A,
PIC16CR54A,
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622
PIC16C641, PIC16C642, PIC16C661, PIC16C662
PIC16C710, PIC16C71, PIC16C711, PIC16C715
PIC16F83, PIC16CR83,
PIC16F84A, PIC16CR84
18-pin,
20-pin
PIC16C55, PIC16C57, PIC16CR57B 28-pin
PIC16CR62, PIC16C62A, PIC16C63, PIC16CR63,
PIC16C66, PIC16C72, PIC16C73A, PIC16C76 28-pin
PIC16CR64, PIC16C64A, PIC16C65A,
PIC16CR65, PIC16C67, PIC16C74A, PIC16C77 40-pin
PIC17CR42, PIC17C42A,
PIC17C43, PIC17CR43, PIC17C44 40-pin
PIC16C923, PIC16C924 64/68-pin
PIC17C756, PIC17C752 64/68-pin
PIC16C7X
DS30390E-page 272 1997 Microchip Technology Inc.
NOTES:
1997 Microchip Technology Inc. DS30390E-page 273
PIC16C7X
INDEX
A
A/D Accuracy/Error ......................................................... 124
ADCON0 Register ....................................................117
ADCON1 Register ....................................................118
ADIF bit ....................................................................119
Analog Input Model Block Diagram ..........................120
Analog-to-Digital Converter ......................................117
Block Diagram ..........................................................119
Configuring Analog Port Pins ...................................121
Configuring the Interrupt ..........................................119
Configuring the Module ............................................119
Connection Considerations ......................................125
Conversion Clock .....................................................121
Conversion Time ......................................................123
Conversions .............................................................122
Converter Characteristics ................181, 199, 217, 238
Delays ......................................................................120
Effects of a Reset .....................................................124
Equations .................................................................120
Faster Conversion - Lower Resolution Tradeoff ......123
Flowchart of A/D Operation ......................................126
GO/DONE bit ...........................................................119
Internal Sampling Switch (Rss) Impedance .............120
Operation During Sleep ...........................................124
Sampling Requirements ...........................................120
Sampling Time .........................................................120
Source Impedance ...................................................120
Time Delays .............................................................120
Transfer Function .....................................................125
Using the CCP Trigger .............................................125
Absolute Maximum Ratings .....................167, 183, 201, 219
ACK ........................................................................90, 94, 95
ADIE bit ..............................................................................33
ADIF bit ..............................................................................35
ADRES Register ....................................23, 25, 27, 117, 119
ALU ...................................................................................... 9
Application Notes
AN546 (Using the Analog-to-Digital Converter) .......117
AN552 (Implementing Wake-up on Key Strokes Using
PIC16CXXX) ..............................................................45
AN556 (Table Reading Using PIC16CXX ..................40
AN578 (Use of the SSP Module in the I2C Multi-Master
Environment) ..............................................................77
AN594 (Using the CCP Modules) ..............................71
AN607, Power-up Trouble Shooting ........................134
Architecture
Harvard ........................................................................ 9
Overview ......................................................................9
von Neumann ...............................................................9
Assembler
MPASM Assembler ..................................................164
B
Baud Rate Error ...............................................................101
Baud Rate Formula ..........................................................101
Baud Rates
Asynchronous Mode ................................................102
Synchronous Mode ..................................................102
BF ..........................................................................78, 83, 94
Block Diagrams
A/D ...........................................................................119
Analog Input Model ..................................................120
Capture ...................................................................... 72
Compare .....................................................................73
I2C Mode ....................................................................93
On-Chip Reset Circuit ...............................................133
PIC16C72 ...................................................................10
PIC16C73 ...................................................................11
PIC16C73A .................................................................11
PIC16C74 ...................................................................12
PIC16C74A .................................................................12
PIC16C76 ...................................................................11
PIC16C77 ...................................................................12
PORTC .......................................................................48
PORTD (In I/O Port Mode) .........................................50
PORTD and PORTE as a Parallel Slave Port ............54
PORTE (In I/O Port Mode) .........................................51
PWM ...........................................................................74
RA3:RA0 and RA5 Port Pins ......................................43
RA4/T0CKI Pin ...........................................................43
RB3:RB0 Port Pins .....................................................45
RB7:RB4 Port Pins .....................................................46
SPI Master/Slave Connection .....................................81
SSP in I2C Mode ........................................................93
SSP in SPI Mode ..................................................80, 85
Timer0 ........................................................................59
Timer0/WDT Prescaler ...............................................62
Timer1 ........................................................................66
Timer2 ........................................................................69
USART Receive .......................................................108
USART Transmit ......................................................106
Watchdog Timer .......................................................144
BOR bit .......................................................................39, 135
BRGH bit ..........................................................................101
Buffer Full Status bit, BF ...............................................78, 83
C
C bit ....................................................................................30
C Compiler ........................................................................165
Capture/Compare/PWM
Capture
Block Diagram ....................................................72
CCP1CON Register ...........................................72
CCP1IF ...............................................................72
CCPR1 ...............................................................72
CCPR1H:CCPR1L .............................................72
Mode ..................................................................72
Prescaler ............................................................73
CCP Timer Resources ................................................71
Compare
Block Diagram ....................................................73
Mode ..................................................................73
Software Interrupt Mode .....................................73
Special Event Trigger .........................................73
Special Trigger Output of CCP1 .........................73
Special Trigger Output of CCP2 .........................73
Interaction of Two CCP Modules ................................71
Section ........................................................................71
Special Event Trigger and A/D Conversions ..............73
Capture/Compare/PWM (CCP)
PWM Block Diagram ..................................................74
PWM Mode .................................................................74
PWM, Example Frequencies/Resolutions ..................75
Carry bit ................................................................................9
CCP1CON ..........................................................................29
CCP1IE bit ..........................................................................33
CCP1IF bit ....................................................................35, 36
CCP2CON ..........................................................................29
CCP2IE bit ..........................................................................37
PIC16C7X
DS30390E-page 274 1997 Microchip Technology Inc.
CCP2IF bit ..........................................................................38
CCPR1H Register ............................................25, 27, 29, 71
CCPR1L Register .........................................................29, 71
CCPR2H Register ............................................25, 27, 29, 71
CCPR2L Register .............................................25, 27, 29, 71
CCPxM0 bit ........................................................................72
CCPxM1 bit ........................................................................72
CCPxM2 bit ........................................................................72
CCPxM3 bit ........................................................................72
CCPxX bit ...........................................................................72
CCPxY bit ...........................................................................72
CKE ....................................................................................83
CKP ..............................................................................79, 84
Clock Polarity Select bit, CKP ......................................79, 84
Clock Polarity, SPI Mode ...................................................81
Clocking Scheme ...............................................................17
Code Examples
Call of a Subroutine in Page 1 from Page 0 ...............41
Changing Between Capture Prescalers .....................73
Changing Prescaler (Timer0 to WDT) ........................63
Changing Prescaler (WDT to Timer0) ........................63
I/O Programming ........................................................53
Indirect Addressing ....................................................41
Initializing PORTA ......................................................43
Initializing PORTB ......................................................45
Initializing PORTC ......................................................48
Loading the SSPBUF Register ............................80, 85
Code Protection .......................................................129, 146
Computed GOTO ...............................................................40
Configuration Bits .............................................................129
Configuration Word ..........................................................129
Connecting Two Microcontrollers .......................................81
CREN bit ..........................................................................100
CS pin ................................................................................54
D
D/A ............................................................................... 78, 83
Data/Address bit, D/A ...................................................78, 83
DC bit .................................................................................30
DC Characteristics
PIC16C72 ................................................................168
PIC16C73 ................................................................184
PIC16C73A .............................................................. 202
PIC16C74 ................................................................184
PIC16C74A .............................................................. 202
PIC16C76 ................................................................221
PIC16C77 ................................................................221
Development Support ..................................................5, 163
Development Tools ..........................................................163
Digit Carry bit .......................................................................9
Direct Addressing ...............................................................41
E
Electrical Characteristics
PIC16C72 ................................................................167
PIC16C73 ................................................................183
PIC16C73A .............................................................. 201
PIC16C74 ................................................................183
PIC16C74A .............................................................. 201
PIC16C76 ................................................................219
PIC16C77 ................................................................219
External Brown-out Protection Circuit ..............................140
External Power-on Reset Circuit ......................................140
F
Family of Devices
PIC12CXXX ............................................................. 265
PIC14C000 .............................................................. 265
PIC16C15X .............................................................. 266
PIC16C55X .............................................................. 267
PIC16C5X ................................................................ 266
PIC16C62X and PIC16C64X ................................... 267
PIC16C6X ................................................................ 268
PIC16C7XX ................................................................. 6
PIC16C8X ................................................................ 269
PIC16C9XX ............................................................. 269
PIC17CXX ............................................................... 270
FERR bit .......................................................................... 100
FSR Register ........................... 23, 24, 25, 26, 27, 28, 29, 41
Fuzzy Logic Dev. System (
fuzzy
TECH-MP) ......... 163, 165
G
General Description ............................................................. 5
GIE bit .............................................................................. 141
I
I/O Ports
PORTA ...................................................................... 43
PORTB ...................................................................... 45
PORTC ...................................................................... 48
PORTD ................................................................ 50, 54
PORTE ...................................................................... 51
Section ....................................................................... 43
I/O Programming Considerations ...................................... 53
I2CAddressing ................................................................. 94
Addressing I2C Devices ............................................. 90
Arbitration .................................................................. 92
Block Diagram ........................................................... 93
Clock Synchronization ............................................... 92
Combined Format ...................................................... 91
I2C Operation ............................................................. 93
I2C Overview ............................................................. 89
Initiating and Terminating Data Transfer ................... 89
Master Mode .............................................................. 97
Master-Receiver Sequence ....................................... 91
Master-Transmitter Sequence ................................... 91
Mode .......................................................................... 93
Mode Selection .......................................................... 93
Multi-master ............................................................... 92
Multi-Master Mode ..................................................... 97
Reception .................................................................. 95
Reception Timing Diagram ........................................ 95
SCL and SDA pins ..................................................... 94
Slave Mode ................................................................ 94
START ....................................................................... 89
STOP ................................................................... 89, 90
Transfer Acknowledge ............................................... 90
Transmission ............................................................. 96
IDLE_MODE ...................................................................... 98
In-Circuit Serial Programming .................................. 129, 146
INDF .................................................................................. 29
INDF Register ...................................... 24, 25, 26, 27, 28, 41
Indirect Addressing ............................................................ 41
Initialization Condition for all Register .............................. 136
Instruction Cycle ................................................................ 17
Instruction Flow/Pipelining ................................................. 17
Instruction Format ............................................................ 147
1997 Microchip Technology Inc. DS30390E-page 275
PIC16C7X
Instruction Set
ADDLW ....................................................................149
ADDWF ....................................................................149
ANDLW ....................................................................149
ANDWF ....................................................................149
BCF ..........................................................................150
BSF ..........................................................................150
BTFSC ..................................................................... 150
BTFSS .....................................................................151
CALL ........................................................................151
CLRF ........................................................................152
CLRW ......................................................................152
CLRWDT ..................................................................152
COMF ......................................................................153
DECF ....................................................................... 153
DECFSZ ...................................................................153
GOTO ......................................................................154
INCF .........................................................................154
INCFSZ ....................................................................155
IORLW ..................................................................... 155
IORWF .....................................................................156
MOVF .......................................................................156
MOVLW ...................................................................156
MOVWF ................................................................... 156
NOP ......................................................................... 157
OPTION ................................................................... 157
RETFIE .................................................................... 157
RETLW ....................................................................158
RETURN ..................................................................158
RLF .......................................................................... 159
RRF ..........................................................................159
SLEEP .....................................................................160
SUBLW .................................................................... 160
SUBWF ....................................................................161
SWAPF .................................................................... 161
TRIS .........................................................................161
XORLW ....................................................................162
XORWF ....................................................................162
Section .....................................................................147
Summary Table ........................................................148
INT Interrupt .....................................................................143
INTCON ............................................................................. 29
INTCON Register ...............................................................32
INTEDG bit .................................................................31, 143
Internal Sampling Switch (Rss) Impedance .....................120
Interrupts ..........................................................................129
PortB Change ..........................................................143
RB7:RB4 Port Change ...............................................45
Section .....................................................................141
TMR0 ....................................................................... 143
IRP bit ................................................................................30
L
Loading of PC ....................................................................40
M
MCLR .......................................................................133, 136
Memory
Data Memory ..............................................................20
Program Memory ........................................................19
Program Memory Maps
PIC16C72 ...........................................................19
PIC16C73 ...........................................................19
PIC16C73A ........................................................19
PIC16C74 ...........................................................19
PIC16C74A ........................................................19
PIC16C76 ...........................................................20
PIC16C77 ...........................................................20
Register File Maps
PIC16C72 ...........................................................21
PIC16C73 ...........................................................21
PIC16C73A ........................................................21
PIC16C74 ...........................................................21
PIC16C74A ........................................................21
PIC16C76 ...........................................................21
PIC16C77 ...........................................................21
MPASM Assembler ..........................................................163
MPLAB-C ..........................................................................165
MPSIM Software Simulator ......................................163, 165
O
OERR bit ..........................................................................100
OPCODE ..........................................................................147
OPTION ..............................................................................29
OPTION Register ...............................................................31
Orthogonal ............................................................................9
OSC selection ...................................................................129
Oscillator
HS .....................................................................131, 135
LP .....................................................................131, 135
RC ............................................................................131
XT .....................................................................131, 135
Oscillator Configurations ..................................................131
Output of TMR2 ..................................................................69
P
P ...................................................................................78, 83
Packaging
28-Lead Ceramic w/Window .....................................251
28-Lead PDIP ...........................................................253
28-Lead SOIC ...........................................................255
28-Lead SSOP .........................................................256
40-Lead CERDIP w/Window ....................................252
40-Lead PDIP ...........................................................254
44-Lead MQFP .........................................................258
44-Lead PLCC ..........................................................257
44-Lead TQFP ..........................................................259
Paging, Program Memory ...................................................40
Parallel Slave Port ........................................................50, 54
PCFG0 bit .........................................................................118
PCFG1 bit .........................................................................118
PCFG2 bit .........................................................................118
PCL Register ............................23, 24, 25, 26, 27, 28, 29, 40
PCLATH ...........................................................................136
PCLATH Register .....................23, 24, 25, 26, 27, 28, 29, 40
PCON Register .....................................................29, 39, 135
PD bit ..................................................................30, 133, 135
PICDEM-1 Low-Cost PIC16/17 Demo Board ...........163, 164
PICDEM-2 Low-Cost PIC16CXX Demo Board .........163, 164
PICDEM-3 Low-Cost PIC16C9XXX Demo Board ............164
PICMASTER In-Circuit Emulator ......................................163
PIC16C7X
DS30390E-page 276 1997 Microchip Technology Inc.
PICSTART Low-Cost Development System ....................163
PIE1 Register ...............................................................29, 33
PIE2 Register ...............................................................29, 37
Pin Compatible Devices ...................................................271
Pin Functions
MCLR/VPP ......................................................13, 14, 15
OSC1/CLKIN ..................................................13, 14, 15
OSC2/CLKOUT ..............................................13, 14, 15
RA0/AN0 ........................................................13, 14, 15
RA1/AN1 ........................................................13, 14, 15
RA2/AN2 ........................................................13, 14, 15
RA3/AN3/VREF ...............................................13, 14, 15
RA4/T0CKI .....................................................13, 14, 15
RA5/AN4/SS ..................................................13, 14, 15
RB0/INT .........................................................13, 14, 15
RB1 ................................................................13, 14, 15
RB2 ................................................................13, 14, 15
RB3 ................................................................13, 14, 15
RB4 ................................................................13, 14, 15
RB5 ................................................................13, 14, 15
RB6 ................................................................13, 14, 15
RB7 ................................................................13, 14, 15
RC0/T1OSO/T1CKI .......................................13, 14, 16
RC1/T1OSI ................................................................13
RC1/T1OSI/CCP2 ................................................14, 16
RC2/CCP1 .....................................................13, 14, 16
RC3/SCK/SCL ...............................................13, 14, 16
RC4/SDI/SDA ................................................13, 14, 16
RC5/SDO .......................................................13, 14, 16
RC6 ............................................................................13
RC6/TX/CK ............................................14, 16, 99–114
RC7 ............................................................................13
RC7/RX/DT ............................................14, 16, 99–114
RD0/PSP0 ..................................................................16
RD1/PSP1 ..................................................................16
RD2/PSP2 ..................................................................16
RD3/PSP3 ..................................................................16
RD4/PSP4 ..................................................................16
RD5/PSP5 ..................................................................16
RD6/PSP6 ..................................................................16
RD7/PSP7 ..................................................................16
RE0/RD/AN5 ..............................................................16
RE1/WR/AN6 ............................................................. 16
RE2/CS/AN7 .............................................................. 16
SCK ......................................................................80–82
SDI ....................................................................... 80–82
SDO .....................................................................80–82
SS ........................................................................80–82
VDD ................................................................13, 14, 16
VSS .................................................................13, 14, 16
Pinout Descriptions
PIC16C72 ..................................................................13
PIC16C73 ..................................................................14
PIC16C73A ................................................................ 14
PIC16C74 ..................................................................15
PIC16C74A ................................................................ 15
PIC16C76 ..................................................................14
PIC16C77 ..................................................................15
PIR1 Register .....................................................................35
PIR2 Register .....................................................................38
POP ....................................................................................40
POR ......................................................................... 134, 135
Oscillator Start-up Timer (OST) ....................... 129, 134
Power Control Register (PCON) .............................. 135
Power-on Reset (POR) ............................ 129, 134, 136
Power-up Timer (PWRT) ................................. 129, 134
Power-Up-Timer (PWRT) ........................................ 134
Time-out Sequence ................................................. 135
Time-out Sequence on Power-up ............................ 139
TO .................................................................... 133, 135
POR bit ...................................................................... 39, 135
Port RB Interrupt .............................................................. 143
PORTA ...................................................................... 29, 136
PORTA Register .............................................. 23, 25, 27, 43
PORTB ...................................................................... 29, 136
PORTB Register .............................................. 23, 25, 27, 45
PORTC ...................................................................... 29, 136
PORTC Register .............................................. 23, 25, 27, 48
PORTD ...................................................................... 29, 136
PORTD Register .................................................... 25, 27, 50
PORTE ...................................................................... 29, 136
PORTE Register .................................................... 25, 27, 51
Power-down Mode (SLEEP) ............................................ 145
PR2 .................................................................................... 29
PR2 Register ......................................................... 26, 28, 69
Prescaler, Switching Between Timer0 and WDT ............... 63
PRO MATE Universal Programmer ................................. 163
Program Branches ............................................................... 9
Program Memory
Paging ....................................................................... 40
Program Memory Maps
PIC16C72 .................................................................. 19
PIC16C73 .................................................................. 19
PIC16C73A ................................................................ 19
PIC16C74 .................................................................. 19
PIC16C74A ................................................................ 19
Program Verification ........................................................ 146
PS0 bit ............................................................................... 31
PS1 bit ............................................................................... 31
PS2 bit ............................................................................... 31
PSA bit ............................................................................... 31
PSPIE bit ........................................................................... 34
PSPIF bit ............................................................................ 36
PSPMODE bit ........................................................ 50, 51, 54
PUSH ................................................................................. 40
R
R/W .............................................................................. 78, 83
R/W bit ............................................................. 90, 94, 95, 96
RBIF bit ...................................................................... 45, 143
RBPU bit ............................................................................ 31
RC Oscillator ............................................................ 132, 135
RCIE bit ............................................................................. 34
RCIF bit .............................................................................. 36
RCREG .............................................................................. 29
RCSTA Register ........................................................ 29, 100
RCV_MODE ...................................................................... 98
RD pin ................................................................................ 54
Read/Write bit Information, R/W .................................. 78, 83
Read-Modify-Write ............................................................. 53
Receive Overflow Detect bit, SSPOV ................................ 79
Receive Overflow Indicator bit, SSPOV ............................. 84
Register File ....................................................................... 20
1997 Microchip Technology Inc. DS30390E-page 277
PIC16C7X
Registers
FSR Summary ...........................................................29
INDFSummary ...........................................................29
Initialization Conditions ............................................136
INTCON
Summary ...........................................................29
MapsPIC16C72 .......................................................... 21
PIC16C73 .......................................................... 21
PIC16C73A ........................................................21
PIC16C74 .......................................................... 21
PIC16C74A ........................................................21
PIC16C76 .......................................................... 22
PIC16C77 .......................................................... 22
OPTION
Summary ...........................................................29
PCL Summary ...........................................................29
PCLATH
Summary ...........................................................29
PORTB
Summary ...........................................................29
Reset Conditions ......................................................136
SSPBUF
Section ...............................................................80
SSPCON
Diagram ............................................................. 79
SSPSR
Section ...............................................................80
SSPSTAT ...................................................................83
Diagram ............................................................. 78
Section ...............................................................78
STATUS
Summary ...........................................................29
Summary ..............................................................25, 27
TMR0
Summary ...........................................................29
TRISB
Summary ...........................................................29
Reset ........................................................................129, 133
Reset Conditions for Special Registers ...........................136
RP0 bit .........................................................................20, 30
RP1 bit ...............................................................................30
RX9 bit .............................................................................100
RX9D bit ...........................................................................100
S
S ...................................................................................78, 83
SCK ....................................................................................80
SCL .................................................................................... 94
SDI ..................................................................................... 80
SDO ................................................................................... 80
Serial Communication Interface (SCI) Module, See USART
Services
One-Time-Programmable (OTP) ................................. 7
Quick-Turnaround-Production (QTP) ...........................7
Serialized Quick-Turnaround Production (SQTP) ........7
Slave Mode
SCL ............................................................................94
SDA ............................................................................94
SLEEP .....................................................................129, 133
SMP ................................................................................... 83
Software Simulator (MPSIM) ...........................................165
SPBRG ..............................................................................29
SPBRG Register ...........................................................26, 28
Special Event Trigger .......................................................125
Special Features of the CPU ............................................129
Special Function Registers
PIC16C72 ...................................................................23
PIC16C73 .............................................................25, 27
PIC16C73A ...........................................................25, 27
PIC16C74 .............................................................25, 27
PIC16C74A ...........................................................25, 27
PIC16C76 ...................................................................27
PIC16C77 ...................................................................27
Special Function Registers, Section ...................................23
SPEN bit ...........................................................................100
SPI Block Diagram ......................................................80, 85
Master Mode ...............................................................86
Master Mode Timing ...................................................87
Mode ...........................................................................80
Serial Clock ................................................................85
Serial Data In ..............................................................85
Serial Data Out ...........................................................85
Slave Mode Timing .....................................................88
Slave Mode Timing Diagram ......................................87
Slave Select ................................................................85
SPI clock .....................................................................86
SPI Mode ....................................................................85
SSPCON ....................................................................84
SSPSTAT ...................................................................83
SPI Clock Edge Select bit, CKE .........................................83
SPI Data Input Sample Phase Select bit, SMP ..................83
SPI Mode ............................................................................80
SREN bit ...........................................................................100
SS .......................................................................................80
SSP Module Overview ........................................................77
Section ........................................................................77
SSPBUF .....................................................................86
SSPCON ....................................................................84
SSPSR .......................................................................86
SSPSTAT ...................................................................83
SSP in I2C Mode - See I2C
SSPADD .............................................................................93
SSPADD Register ............................................24, 26, 28, 29
SSPBUF .......................................................................29, 93
SSPBUF Register .........................................................25, 27
SSPCON ......................................................................79, 84
SSPCON Register ........................................................25, 27
SSPEN .........................................................................79, 84
SSPIE bit ............................................................................33
SSPIF bit ......................................................................35, 36
SSPM3:SSPM0 ............................................................79, 84
SSPOV ...................................................................79, 84, 94
SSPSTAT .....................................................................78, 93
SSPSTAT Register .....................................24, 26, 28, 29, 83
Stack ...................................................................................40
Overflows ....................................................................40
Underflow ...................................................................40
Start bit, S .....................................................................78, 83
STATUS Register .........................................................29, 30
Stop bit, P .....................................................................78, 83
Synchronous Serial Port (SSP)
Block Diagram, SPI Mode ..........................................80
SPI Master/Slave Diagram .........................................81
SPI Mode ....................................................................80
Synchronous Serial Port Enable bit, SSPEN ................79, 84
PIC16C7X
DS30390E-page 278 1997 Microchip Technology Inc.
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 ............................................................79, 84
Synchronous Serial Port Module ........................................77
Synchronous Serial Port Status Register ...........................83
T
T0CS bit .............................................................................31
T1CKPS0 bit ......................................................................65
T1CKPS1 bit ......................................................................65
T1CON ............................................................................... 29
T1CON Register ...........................................................29, 65
T1OSCEN bit .....................................................................65
T1SYNC bit ........................................................................65
T2CKPS0 bit ......................................................................70
T2CKPS1 bit ......................................................................70
T2CON Register ...........................................................29, 70
TAD ................................................................................... 121
Timer Modules, Overview ..................................................57
Timer0
RTCC ....................................................................... 136
Timers
Timer0
Block Diagram ....................................................59
External Clock ....................................................61
External Clock Timing ........................................61
Increment Delay .................................................61
Interrupt ..............................................................59
Interrupt Timing ..................................................60
Overview ............................................................ 57
Prescaler ............................................................62
Prescaler Block Diagram ...................................62
Section ............................................................... 59
Switching Prescaler Assignment ........................63
Synchronization .................................................61
T0CKI .................................................................61
T0IF ..................................................................143
Timing ................................................................ 59
TMR0 Interrupt .................................................143
Timer1
Asynchronous Counter Mode ............................67
Block Diagram ....................................................66
Capacitor Selection ............................................67
External Clock Input ...........................................66
External Clock Input Timing ...............................67
Operation in Timer Mode ...................................66
Oscillator ............................................................ 67
Overview ............................................................ 57
Prescaler ......................................................66, 68
Resetting of Timer1 Registers ...........................68
Resetting Timer1 using a CCP Trigger Output ..68
Synchronized Counter Mode .............................66
T1CON ...............................................................65
TMR1H ...............................................................67
TMR1L ............................................................... 67
Timer2
Block Diagram ....................................................69
Module ............................................................... 69
Overview ............................................................ 57
Postscaler .......................................................... 69
Prescaler ............................................................69
T2CON ...............................................................70
Timing Diagrams
A/D Conversion ................................182, 200, 218, 239
Brown-out Reset ..............................134, 175, 209, 228
Capture/Compare/PWM ...................177, 193, 211, 230
CLKOUT and I/O ..............................174, 190, 208, 227
External Clock Timing ...................... 173, 189, 207, 226
I2C Bus Data .................................... 180, 197, 215, 236
I2C Bus Start/Stop bits ..................... 179, 196, 214, 235
I2C Clock Synchronization ......................................... 92
I2C Data Transfer Wait State ..................................... 90
I2C Multi-Master Arbitration ....................................... 92
I2C Reception (7-bit Address) .................................... 95
Parallel Slave Port ................................................... 194
Power-up Timer ............................... 175, 191, 209, 228
Reset ............................................... 175, 191, 209, 228
SPI Master Mode ....................................................... 87
SPI Mode ................................................. 178, 195, 213
SPI Mode, Master/Slave Mode, No SS Control ......... 82
SPI Mode, Slave Mode With SS Control ................... 82
SPI Slave Mode (CKE = 1) ........................................ 88
SPI Slave Mode Timing (CKE = 0) ............................ 87
Start-up Timer .................................. 175, 191, 209, 228
Time-out Sequence ................................................. 139
Timer0 ....................................... 59, 176, 192, 210, 229
Timer0 Interrupt Timing ............................................. 60
Timer0 with External Clock ........................................ 61
Timer1 ............................................. 176, 192, 210, 229
USART Asynchronous Master Transmission .......... 107
USART Asynchronous Reception ........................... 108
USART RX Pin Sampling ................................ 104, 105
USART Synchronous Receive ................ 198, 216, 237
USART Synchronous Reception ............................. 113
USART Synchronous Transmission 111, 198, 216, 237
Wake-up from Sleep via Interrupt ............................ 146
Watchdog Timer .............................. 175, 191, 209, 228
TMR0 ................................................................................. 29
TMR0 Register ............................................................. 25, 27
TMR1CS bit ....................................................................... 65
TMR1H .............................................................................. 29
TMR1H Register .................................................... 23, 25, 27
TMR1IE bit ......................................................................... 33
TMR1IF bit ................................................................... 35, 36
TMR1L ............................................................................... 29
TMR1L Register ..................................................... 23, 25, 27
TMR1ON bit ....................................................................... 65
TMR2 ................................................................................. 29
TMR2 Register ....................................................... 23, 25, 27
TMR2IE bit ......................................................................... 33
TMR2IF bit ................................................................... 35, 36
TMR2ON bit ....................................................................... 70
TO bit ................................................................................. 30
TOUTPS0 bit ..................................................................... 70
TOUTPS1 bit ..................................................................... 70
TOUTPS2 bit ..................................................................... 70
TOUTPS3 bit ..................................................................... 70
TRISA ................................................................................ 29
TRISA Register ................................................ 24, 26, 28, 43
TRISB ................................................................................ 29
TRISB Register ................................................ 24, 26, 28, 45
TRISC ................................................................................ 29
TRISC Register ................................................ 24, 26, 28, 48
TRISD ................................................................................ 29
TRISD Register ...................................................... 26, 28, 50
TRISE ................................................................................ 29
TRISE Register ...................................................... 26, 28, 51
Two’s Complement .............................................................. 9
TXIE bit .............................................................................. 34
TXIF bit .............................................................................. 36
TXREG .............................................................................. 29
TXSTA ............................................................................... 29
TXSTA Register ................................................................. 99
1997 Microchip Technology Inc. DS30390E-page 279
PIC16C7X
U
UA ................................................................................ 78, 83
Universal Synchronous Asynchronous Receiver Transmitter
(USART) ............................................................................99
Update Address bit, UA ...............................................78, 83
USART
Asynchronous Mode ................................................106
Asynchronous Receiver ...........................................108
Asynchronous Reception .........................................109
Asynchronous Transmission ....................................107
Asynchronous Transmitter .......................................106
Baud Rate Generator (BRG) ....................................101
Receive Block Diagram ............................................108
Sampling ..................................................................104
Synchronous Master Mode ......................................110
Synchronous Master Reception ...............................112
Synchronous Master Transmission ..........................110
Synchronous Slave Mode ........................................114
Synchronous Slave Reception .................................114
Synchronous Slave Transmit ...................................114
Transmit Block Diagram ...........................................106
UV Erasable Devices ...........................................................7
W
W Register
ALU ..............................................................................9
Wake-up from SLEEP ......................................................145
Watchdog Timer (WDT) ...........................129, 133, 136, 144
WCOL .......................................................................... 79, 84
WDT .................................................................................136
Block Diagram ..........................................................144
Period .......................................................................144
Programming Considerations ..................................144
Timeout ....................................................................136
Word ................................................................................129
WR pin ...............................................................................54
Write Collision Detect bit, WCOL .................................79, 84
X
XMIT_MODE ......................................................................98
Z
Z bit ....................................................................................30
Zero bit .................................................................................9
LIST OF EXAMPLES
Example 3-1: Instruction Pipeline Flow............................17
Example 4-1: Call of a Subroutine in Page 1
from Page 0..............................................41
Example 4-2: Indirect Addressing....................................41
Example 5-1: Initializing PORTA......................................43
Example 5-2: Initializing PORTB......................................45
Example 5-3: Initializing PORTC .....................................48
Example 5-4: Read-Modify-Write Instructions
on an I/O Port ............................................53
Example 7-1: Changing Prescaler (Timer0→WDT).........63
Example 7-2: Changing Prescaler (WDT→Timer0).........63
Example 8-1: Reading a 16-bit Free-Running Timer.......67
Example 10-1: Changing Between Capture
Prescalers.................................................73
Example 10-2: PWM Period and Duty Cycle
Calculation.................................................75
Example 11-1: Loading the SSPBUF (SSPSR)
Register ....................................................80
Example 11-2: Loading the SSPBUF (SSPSR)
Register (PIC16C76/77) ...........................85
Example 12-1: Calculating Baud Rate Error....................101
Equation 13-1: A/D Minimum Charging Time...................120
Example 13-1: Calculating the Minimum Required
Acquisition Time .....................................120
Example 13-2: A/D Conversion........................................122
Example 13-3: 4-bit vs. 8-bit Conversion Times..............123
Example 14-1: Saving STATUS, W, and PCLATH
Registers in RAM.....................................143
PIC16C7X
DS30390E-page 280 1997 Microchip Technology Inc.
LIST OF FIGURES
Figure 3-1: PIC16C72 Block Diagram .........................10
Figure 3-2: PIC16C73/73A/76 Block Diagram.............11
Figure 3-3: PIC16C74/74A/77 Block Diagram.............12
Figure 3-4: Clock/Instruction Cycle..............................17
Figure 4-1: PIC16C72 Program Memory Map
and Stack..................................................19
Figure 4-2: PIC16C73/73A/74/74A Program
Memory Map and Stack............................19
Figure 4-3: PIC16C76/77 Program Memory
Map and Stack..........................................20
Figure 4-4: PIC16C72 Register File Map ....................21
Figure 4-5: PIC16C73/73A/74/74A Register
File Map ....................................................21
Figure 4-6: PIC16C76/77 Register File Map ...............22
Figure 4-7: Status Register (Address 03h,
83h, 103h, 183h)......................................30
Figure 4-8: OPTION Register (Address 81h,
181h).........................................................31
Figure 4-9: INTCON Register
(Address 0Bh, 8Bh, 10bh, 18bh)...............32
Figure 4-10: PIE1 Register PIC16C72
(Address 8Ch)...........................................33
Figure 4-11: PIE1 Register PIC16C73/73A/
74/74A/76/77 (Address 8Ch).....................34
Figure 4-12: PIR1 Register PIC16C72
(Address 0Ch)...........................................35
Figure 4-13: PIR1 Register PIC16C73/73A/
74/74A/76/77 (Address 0Ch).....................36
Figure 4-14: PIE2 Register (Address 8Dh)....................37
Figure 4-15: PIR2 Register (Address 0Dh)....................38
Figure 4-16: PCON Register (Address 8Eh) .................39
Figure 4-17: Loading of PC In Different
Situations ..................................................40
Figure 4-18: Direct/Indirect Addressing.........................41
Figure 5-1: Block Diagram of RA3:RA0
and RA5 Pins............................................43
Figure 5-2: Block Diagram of RA4/T0CKI Pin .............43
Figure 5-3: Block Diagram of RB3:RB0 Pins...............45
Figure 5-4: Block Diagram of RB7:RB4 Pins
(PIC16C73/74)..........................................46
Figure 5-5: Block Diagram of
RB7:RB4 Pins (PIC16C72/73A/
74A/76/77).................................................46
Figure 5-6: PORTC Block Diagram
(Peripheral Output Override)....................48
Figure 5-7: PORTD Block Diagram
(in I/O Port Mode).....................................50
Figure 5-8: PORTE Block Diagram
(in I/O Port Mode).....................................51
Figure 5-9: TRISE Register (Address 89h)..................51
Figure 5-10: Successive I/O Operation .........................53
Figure 5-11: PORTD and PORTE Block Diagram
(Parallel Slave Port)..................................54
Figure 5-12: Parallel Slave Port Write Waveforms........55
Figure 5-13: Parallel Slave Port Read Waveforms........55
Figure 7-1: Timer0 Block Diagram...............................59
Figure 7-2: Timer0 Timing: Internal Clock/No
Prescale....................................................59
Figure 7-3: Timer0 Timing: Internal
Clock/Prescale 1:2....................................60
Figure 7-4: Timer0 Interrupt Timing.............................60
Figure 7-5: Timer0 Timing with External Clock............61
Figure 7-6: Block Diagram of the Timer0/WDT
Prescaler...................................................62
Figure 8-1: T1CON: Timer1 Control Register
(Address 10h).......................................... 65
Figure 8-2: Timer1 Block Diagram .............................. 66
Figure 9-1: Timer2 Block Diagram .............................. 69
Figure 9-2: T2CON: Timer2 Control Register
(Address 12h).......................................... 70
Figure 10-1: CCP1CON Register (Address 17h)/
CCP2CON Register (Address 1Dh).......... 72
Figure 10-2: Capture Mode Operation
Block Diagram .......................................... 72
Figure 10-3: Compare Mode Operation
Block Diagram .......................................... 73
Figure 10-4: Simplified PWM Block Diagram................ 74
Figure 10-5: PWM Output ............................................. 74
Figure 11-1: SSPSTAT: Sync Serial Port Status
Register (Address 94h)............................. 78
Figure 11-2: SSPCON: Sync Serial Port Control
Register (Address 14h)............................. 79
Figure 11-3: SSP Block Diagram (SPI Mode)............... 80
Figure 11-4: SPI Master/Slave Connection................... 81
Figure 11-5: SPI Mode Timing, Master Mode
or Slave Mode w/o SS Control.................. 82
Figure 11-6: SPI Mode Timing, Slave Mode with
SS Control ................................................ 82
Figure 11-7: SSPSTAT: Sync Serial Port Status
Register (Address 94h)(PIC16C76/77)..... 83
Figure 11-8: SSPCON: Sync Serial Port Control
Register (Address 14h)(PIC16C76/77)..... 84
Figure 11-9: SSP Block Diagram (SPI Mode)
(PIC16C76/77).......................................... 85
Figure 11-10: SPI Master/Slave Connection
PIC16C76/77)........................................... 86
Figure 11-11: SPI Mode Timing, Master Mode
(PIC16C76/77)......................................... 87
Figure 11-12: SPI Mode Timing (Slave Mode
With CKE = 0) (PIC16C76/77)................. 87
Figure 11-13: SPI Mode Timing (Slave Mode
With CKE = 1) (PIC16C76/77).................. 88
Figure 11-14: Start and Stop Conditions......................... 89
Figure 11-15: 7-bit Address Format................................ 90
Figure 11-16: I2C 10-bit Address Format........................ 90
Figure 11-17: Slave-receiver Acknowledge .................... 90
Figure 11-18: Data Transfer Wait State.......................... 90
Figure 11-19: Master-transmitter Sequence ................... 91
Figure 11-20: Master-receiver Sequence........................ 91
Figure 11-21: Combined Format..................................... 91
Figure 11-22: Multi-master Arbitration
(Two Masters)........................................... 92
Figure 11-23: Clock Synchronization.............................. 92
Figure 11-24: SSP Block Diagram
(I2C Mode)................................................ 93
Figure 11-25: I2C Waveforms for Reception
(7-bit Address).......................................... 95
Figure 11-26: I2C Waveforms for Transmission
(7-bit Address).......................................... 96
Figure 11-27: Operation of the I2C Module in
IDLE_MODE, RCV_MODE or
XMIT_MODE ............................................ 98
Figure 12-1: TXSTA: Transmit Status and
Control Register (Address 98h)................ 99
Figure 12-2: RCSTA: Receive Status and
Control Register (Address 18h).............. 100
Figure 12-3: RX Pin Sampling Scheme. BRGH = 0
(PIC16C73/73A/74/74A)......................... 104
Figure 12-4: RX Pin Sampling Scheme, BRGH = 1
(PIC16C73/73A/74/74A)......................... 104
1997 Microchip Technology Inc. DS30390E-page 281
PIC16C7X
Figure 12-5: RX Pin Sampling Scheme, BRGH = 1
(PIC16C73/73A/74/74A) .........................104
Figure 12-6: RX Pin Sampling Scheme,
BRGH = 0 OR BRGH = 1 (
PIC16C76/77) .........................................105
Figure 12-7: USART Transmit Block Diagram.............106
Figure 12-8: Asynchronous Master Transmission.......107
Figure 12-9: Asynchronous Master Transmission
(Back to Back).........................................107
Figure 12-10: USART Receive Block Diagram..............108
Figure 12-11: Asynchronous Reception........................108
Figure 12-12: Synchronous Transmission.....................111
Figure 12-13: Synchronous Transmission
(Through TXEN)......................................111
Figure 12-14: Synchronous Reception
(Master Mode, SREN)............................. 113
Figure 13-1: ADCON0 Register (Address 1Fh)...........117
Figure 13-2: ADCON1 Register (Address 9Fh)...........118
Figure 13-3: A/D Block Diagram..................................119
Figure 13-4: Analog Input Model.................................120
Figure 13-5: A/D Transfer Function.............................125
Figure 13-6: Flowchart of A/D Operation.....................126
Figure 14-1: Configuration Word for
PIC16C73/74...........................................129
Figure 14-2: Configuration Word for
PIC16C72/73A/74A/76/77.......................130
Figure 14-3: Crystal/Ceramic Resonator
Operation (HS, XT or LP
OSC Configuration).................................131
Figure 14-4: External Clock Input Operation
(HS, XT or LP OSC Configuration) .........131
Figure 14-5: External Parallel Resonant Crystal
Oscillator Circuit...................................... 132
Figure 14-6: External Series Resonant Crystal
Oscillator Circuit..................................... 132
Figure 14-7: RC Oscillator Mode.................................132
Figure 14-8: Simplified Block Diagram of On-chip
Reset Circuit............................................133
Figure 14-9: Brown-out Situations...............................134
Figure 14-10: Time-out Sequence on Power-up
(MCLR not Tied to VDD): Case 1.............139
Figure 14-11: Time-out Sequence on Power-up
(MCLR Not Tied To VDD): Case 2..........139
Figure 14-12: Time-out Sequence on Power-up
(MCLR Tied to VDD)................................139
Figure 14-13: External Power-on Reset Circuit
(for Slow VDD Power-up).........................140
Figure 14-14: External Brown-out Protection
Circuit 1...................................................140
Figure 14-15: External Brown-out Protection
Circuit 2...................................................140
Figure 14-16: Interrupt Logic......................................... 142
Figure 14-17: INT Pin Interrupt Timing..........................142
Figure 14-18: Watchdog Timer Block Diagram .............144
Figure 14-19: Summary of Watchdog
Timer Registers....................................... 144
Figure 14-20: Wake-up from Sleep Through
Interrupt...................................................146
Figure 14-21: Typical In-Circuit Serial
Programming Connection .......................146
Figure 15-1: General Format for Instructions ..............147
Figure 17-1: Load Conditions......................................172
Figure 17-2: External Clock Timing.............................173
Figure 17-3: CLKOUT and I/O Timing.........................174
Figure 17-4: Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing......................................................175
Figure 17-5: Brown-out Reset Timing..........................175
Figure 17-6: Timer0 and Timer1 External
Clock Timings.........................................176
Figure 17-7: Capture/Compare/PWM
Timings (CCP1).......................................177
Figure 17-8: SPI Mode Timing.....................................178
Figure 17-9: I2C Bus Start/Stop Bits Timing.................179
Figure 17-10: I2C Bus Data Timing................................180
Figure 17-11: A/D Conversion Timing............................182
Figure 18-1: Load Conditions.......................................188
Figure 18-2: External Clock Timing..............................189
Figure 18-3: CLKOUT and I/O Timing..........................190
Figure 18-4: Reset, Watchdog Timer,
Oscillator Start-up Timer and Power-up Tim-
er Timing..................................................191
Figure 18-5: Timer0 and Timer1 External
Clock Timings.........................................192
Figure 18-6: Capture/Compare/PWM Timings
(CCP1 and CCP2)...................................193
Figure 18-7: Parallel Slave Port Timing
(PIC16C74)..............................................194
Figure 18-8: SPI Mode Timing.....................................195
Figure 18-9: I2C Bus Start/Stop Bits Timing.................196
Figure 18-10: I2C Bus Data Timing................................197
Figure 18-11: USART Synchronous Transmission
(Master/Slave) Timing..............................198
Figure 18-12: USART Synchronous Receive
(Master/Slave) Timing..............................198
Figure 18-13: A/D Conversion Timing............................200
Figure 19-1: Load Conditions.......................................206
Figure 19-2: External Clock Timing..............................207
Figure 19-3: CLKOUT and I/O Timing..........................208
Figure 19-4: Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Timing ...........................209
Figure 19-5: Brown-out Reset Timing..........................209
Figure 19-6: Timer0 and Timer1 External
Clock Timings.........................................210
Figure 19-7: Capture/Compare/PWM Timings
(CCP1 and CCP2)...................................211
Figure 19-8: Parallel Slave Port Timing
(PIC16C74A) ...........................................212
Figure 19-9: SPI Mode Timing.....................................213
Figure 19-10: I2C Bus Start/Stop Bits Timing.................214
Figure 19-11: I2C Bus Data Timing................................215
Figure 19-12: USART Synchronous Transmission
(Master/Slave) Timing..............................216
Figure 19-13: USART Synchronous Receive
(Master/Slave) Timing..............................216
Figure 19-14: A/D Conversion Timing............................218
Figure 20-1: Load Conditions.......................................225
Figure 20-2: External Clock Timing..............................226
Figure 20-3: CLKOUT and I/O Timing..........................227
Figure 20-4: Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Timing ...........................228
Figure 20-5: Brown-out Reset Timing..........................228
Figure 20-6: Timer0 and Timer1 External
Clock Timings..........................................229
Figure 20-7: Capture/Compare/PWM Timings
(CCP1 and CCP2)...................................230
Figure 20-8: Parallel Slave Port Timing
(PIC16C77).............................................231
PIC16C7X
DS30390E-page 282 1997 Microchip Technology Inc.
Figure 20-9: SPI Master Mode Timing (CKE = 0)........232
Figure 20-10: SPI Master Mode Timing (CKE = 1)........232
Figure 20-11: SPI Slave Mode Timing (CKE = 0)..........233
Figure 20-12: SPI Slave Mode Timing (CKE = 1)..........233
Figure 20-13: I2C Bus Start/Stop Bits Timing................235
Figure 20-14: I2C Bus Data Timing ...............................236
Figure 20-15: USART Synchronous Transmission
(Master/Slave) Timing.............................237
Figure 20-16: USART Synchronous Receive
(Master/Slave) Timing.............................237
Figure 20-17: A/D Conversion Timing ...........................239
Figure 21-1: Typical IPD vs. VDD (WDT Disabled,
RC Mode)................................................241
Figure 21-2: Maximum IPD vs. VDD (WDT
Disabled, RC Mode)................................241
Figure 21-3: Typical IPD vs. VDD @ 25°C (WDT
Enabled, RC Mode).................................242
Figure 21-4: Maximum IPD vs. VDD (WDT
Enabled, RC Mode).................................242
Figure 21-5: Typical RC Oscillator
Frequency vs. VDD..................................242
Figure 21-6: Typical RC Oscillator
Frequency vs. VDD..................................242
Figure 21-7: Typical RC Oscillator
Frequency vs. VDD..................................242
Figure 21-8: Typical IPD vs. VDD Brown-out
Detect Enabled (RC Mode).....................243
Figure 21-9: Maximum IPD vs. VDD Brown-out
Detect Enabled
(85°C to -40°C, RC Mode) ......................243
Figure 21-10: Typical IPD vs. Timer1 Enabled
(32 kHz, RC0/RC1= 33 pF/33 pF,
RC Mode)................................................243
Figure 21-11: Maximum IPD vs. Timer1 Enabled
(32 kHz, RC0/RC1 = 33
pF/33 pF, 85°C to -40°C, RC Mode).......243
Figure 21-12: Typical IDD vs. Frequency
(RC Mode @ 22 pF, 25°C)......................244
Figure 21-13: Maximum IDD vs. Frequency
(RC Mode @ 22 pF, -40°C to 85°C)........244
Figure 21-14: Typical IDD vs. Frequency
(RC Mode @ 100 pF, 25°C)....................245
Figure 21-15: Maximum IDD vs. Frequency (
RC Mode @ 100 pF, -40°C to 85°C).......245
Figure 21-16: Typical IDD vs. Frequency
(RC Mode @ 300 pF, 25°C)....................246
Figure 21-17: Maximum IDD vs. Frequency
(RC Mode @ 300 pF, -40°C to 85°C)......246
Figure 21-18: Typical IDD vs. Capacitance @
500 kHz (RC Mode) ................................247
Figure 21-19: Transconductance(gm) of
HS Oscillator vs. VDD..............................247
Figure 21-20: Transconductance(gm) of LP
Oscillator vs. VDD....................................247
Figure 21-21: Transconductance(gm) of XT
Oscillator vs. VDD....................................247
Figure 21-22: Typical XTAL Startup Time vs. VDD
(LP Mode, 25°C) .....................................248
Figure 21-23: Typical XTAL Startup Time vs. VDD
(HS Mode, 25°C).....................................248
Figure 21-24: Typical XTAL Startup Time vs. VDD
(XT Mode, 25°C).....................................248
Figure 21-25: Typical Idd vs. Frequency
(LP Mode, 25°C) .....................................249
Figure 21-26: Maximum IDD vs. Frequency
(LP Mode, 85°C to -40°C).......................249
Figure 21-27: Typical IDD vs. Frequency
(XT Mode, 25°C)..................................... 249
Figure 21-28: Maximum IDD vs. Frequency
(XT Mode, -40°C to 85°C)....................... 249
Figure 21-29: Typical IDD vs. Frequency
(HS Mode, 25°C) .................................... 250
Figure 21-30: Maximum IDD vs. Frequency
(HS Mode, -40°C to 85°C)...................... 250
1997 Microchip Technology Inc. DS30390E-page 283
PIC16C7X
LIST OF TABLES
Table 1-1: PIC16C7XX Family of Devces.................... 6
Table 3-1: PIC16C72 Pinout Description ................... 13
Table 3-2: PIC16C73/73A/76 Pinout Description.......14
Table 3-3: PIC16C74/74A/77 Pinout Description.......15
Table 4-1: PIC16C72 Special Function Register
Summary...................................................23
Table 4-2: PIC16C73/73A/74/74A Special
Function Register Summary......................25
Table 4-3: PIC16C76/77 Special Function
Register Summary ....................................27
Table 5-1: PORTA Functions..................................... 44
Table 5-2: Summary of Registers Associated
with PORTA ..............................................44
Table 5-3: PORTB Functions..................................... 46
Table 5-4: Summary of Registers Associated
with PORTB ..............................................47
Table 5-5: PORTC Functions.....................................48
Table 5-6: Summary of Registers Associated
with PORTC..............................................49
Table 5-7: PORTD Functions.....................................50
Table 5-8: Summary of Registers Associated
with PORTD..............................................50
Table 5-9: PORTE Functions..................................... 52
Table 5-10: Summary of Registers Associated
with PORTE ..............................................52
Table 5-11: Registers Associated with
Parallel Slave Port.....................................55
Table 7-1: Registers Associated with Timer0.............63
Table 8-1: Capacitor Selection for the
Timer1 Oscillator....................................... 67
Table 8-2: Registers Associated with Timer1
as a Timer/Counter ...................................68
Table 9-1: Registers Associated with
Timer2 as a Timer/Counter.......................70
Table 10-1: CCP Mode - Timer Resource....................71
Table 10-2: Interaction of Two CCP Modules ..............71
Table 10-3: Example PWM Frequencies and
Resolutions at 20 MHz..............................75
Table 10-4: Registers Associated with Capture,
Compare, and Timer1...............................75
Table 10-5: Registers Associated with PWM
and Timer2................................................76
Table 11-1: Registers Associated with SPI
Operation ..................................................82
Table 11-2: Registers Associated with SPI
Operation (PIC16C76/77) .........................88
Table 11-3: I2C Bus Terminology.................................89
Table 11-4: Data Transfer Received Byte
Actions ......................................................94
Table 11-5: Registers Associated with I2C
Operation ..................................................97
Table 12-1: Baud Rate Formula.................................101
Table 12-2: Registers Associated with Baud
Rate Generator .......................................101
Table 12-3: Baud Rates for Synchronous Mode........102
Table 12-4: Baud Rates for Asynchronous Mode
(BRGH = 0).............................................102
Table 12-5: Baud Rates for Asynchronous Mode
(BRGH = 1).............................................103
Table 12-6: Registers Associated with
Asynchronous Transmission...................107
Table 12-7: Registers Associated with
Asynchronous Reception........................109
Table 12-8: Registers Associated with Synchronous Mas-
ter Transmission......................................111
Table 12-9: Registers Associated with Synchronous Mas-
ter Reception ...........................................112
Table 12-10: Registers Associated with
Synchronous Slave Transmission ...........115
Table 12-11: Registers Associated with
Synchronous Slave Reception.................115
Table 13-1: TAD vs. Device Operating
Frequencies.............................................121
Table 13-2: Registers/Bits Associated with A/D,
PIC16C72................................................126
Table 13-3: Summary of A/D Registers,
PIC16C73/73A/74/74A/76/77 ..................127
Table 14-1: Ceramic Resonators................................131
Table 14-2: Capacitor Selection for Crystal
Oscillator..................................................131
Table 14-3: Time-out in Various Situations,
PIC16C73/74...........................................135
Table 14-4: Time-out in Various Situations,
PIC16C72/73A/74A/76/77 .......................135
Table 14-5: Status Bits and Their Significance,
PIC16C73/74...........................................135
Table 14-6: Status Bits and Their Significance,
PIC16C72/73A/74A/76/77 .......................136
Table 14-7: Reset Condition for Special
Registers..................................................136
Table 14-8: Initialization Conditions for all
Registers..................................................136
Table 15-1: Opcode Field Descriptions.......................147
Table 15-2: PIC16CXX Instruction Set .......................148
Table 16-1: Development Tools from Microchip.........166
Table 17-1: Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) .............................167
Table 17-2: External Clock Timing
Requirements ..........................................173
Table 17-3: CLKOUT and I/O Timing
Requirements ..........................................174
Table 17-4: Reset, Watchdog Timer,
Oscillator Start-up Timer, Power-up
Timer, and brown-out Reset
Requirements ..........................................175
Table 17-5: Timer0 and Timer1 External
Clock Requirements ................................176
Table 17-6: Capture/Compare/PWM
Requirements (CCP1) .............................177
Table 17-7: SPI Mode Requirements..........................178
Table 17-8: I2C Bus Start/Stop Bits
Requirements ..........................................179
Table 17-9: I2C Bus Data Requirements ....................180
Table 17-10: A/D Converter Characteristics:
PIC16C72-04
(Commercial, Industrial, Extended)
PIC16C72-10
(Commercial, Industrial, Extended)
PIC16C72-20
(Commercial, Industrial, Extended)
PIC16LC72-04
(Commercial, Industrial)...........................181
Table 17-11: A/D Conversion Requirements................182
Table 18-1: Cross Reference of Device
Specs for Oscillator Configurations
and Frequencies of Operation
(Commercial Devices) .............................183
PIC16C7X
DS30390E-page 284 1997 Microchip Technology Inc.
Table 18-2: external Clock Timing
Requirements..........................................189
Table 18-3: CLKOUT and I/O Timing
Requirements..........................................190
Table 18-4: Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Requirements.........................................191
Table 18-5: Timer0 and Timer1 External Clock
Requirements..........................................192
Table 18-6: Capture/Compare/PWM
Requirements (CCP1 and CCP2)...........193
Table 18-7: Parallel Slave Port Requirements
(PIC16C74).............................................194
Table 18-8: SPI Mode Requirements.........................195
Table 18-9: I2C Bus Start/Stop Bits
Requirements..........................................196
Table 18-10: I2C Bus Data Requirements....................197
Table 18-11: USART Synchronous Transmission
Requirements..........................................198
Table 18-12: usart Synchronous Receive
Requirements..........................................198
Table 18-13: A/D Converter Characteristics:................199
PIC16C73/74-04
(Commercial, Industrial)
PIC16C73/74-10
(Commercial, Industrial)
PIC16C73/74-20
(Commercial, Industrial)
PIC16LC73/74-04
(Commercial, Industrial)..........................199
Table 18-14: A/D Conversion Requirements................200
Table 19-1: Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices).............................201
Table 19-2: External Clock Timing
Requirements..........................................207
Table 19-3: CLKOUT and I/O Timing
Requirements..........................................208
Table 19-4: Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer,
and brown-out reset Requirements.........209
Table 19-5: Timer0 and Timer1 External Clock
Requirements..........................................210
Table 19-6: Capture/Compare/PWM
Requirements (CCP1 and CCP2)...........211
Table 19-7: Parallel Slave Port Requirements
(PIC16C74A)...........................................212
Table 19-8: SPI Mode Requirements.........................213
Table 19-9: I2C Bus Start/Stop Bits Requirements ....214
Table 19-10: I2C Bus Data Requirements....................215
Table 19-11: USART Synchronous Transmission
Requirements..........................................216
Table 19-12: USART Synchronous Receive
Requirements..........................................216
Table 19-13: A/D Converter Characteristics:................217
PIC16C73A/74A-04
(Commercial, Industrial, Extended)
PIC16C73A/74A-10
(Commercial, Industrial, Extended)
PIC16C73A/74A-20
(Commercial, Industrial, Extended)
PIC16LC73A/74A-04
(Commercial, Industrial)..........................217
Table 19-14: A/D Conversion Requirements................218
Table 20-1: Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) ............................ 220
Table 20-2: External Clock Timing
Requirements ......................................... 226
Table 20-3: CLKOUT and I/O Timing
Requirements ......................................... 227
Table 20-4: Reset, Watchdog Timer,
Oscillator Start-up Timer, Power-up
Timer, and brown-out reset
Requirements ......................................... 228
Table 20-5: Timer0 and Timer1 External Clock
Requirements ......................................... 229
Table 20-6: Capture/Compare/PWM
Requirements (CCP1 and CCP2)........... 230
Table 20-7: Parallel Slave Port Requirements
(PIC16C77)............................................. 231
Table 20-8: SPI Mode requirements.......................... 234
Table 20-9: I2C Bus Start/Stop Bits Requirements.... 235
Table 20-10: I2C Bus Data Requirements ................... 236
Table 20-11: USART Synchronous Transmission
Requirements ......................................... 237
Table 20-12: USART Synchronous Receive
Requirements ......................................... 237
Table 20-13: A/D Converter Characteristics: ............... 238
PIC16C76/77-04
(Commercial, Industrial, Extended)
PIC16C76/77-10
(Commercial, Industrial, Extended)
PIC16C76/77-20
(Commercial, Industrial, Extended)
PIC16LC76/77-04
(Commercial, Industrial).......................... 238
Table 20-14: A/D Conversion Requirements ............... 239
Table 21-1: RC Oscillator Frequencies...................... 247
Table 21-2: Capacitor Selection for Crystal
Oscillators............................................... 248
Table E-1: Pin Compatible Devices.......................... 271
1996 Microchip Technology Inc. DS30390E-page 285
PIC16C6X
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DS30390E-page 287 1997 Microchip Technology Inc.
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4. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
PART NO. -XX X /XX XXX Pattern: QTP, SQTP, Code or Special Requirements
Package: JW = Windowed CERDIP
PQ = MQFP (Metric PQFP)
TQ = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny plastic dip
P = PDIP
L = PLCC
SS = SSOP
Temperature
Range: -=0°C to +70°C
I = -40°C to +85°C
E = -40°C to +125°C
Frequency
Range: 04 = 200 kHz (PIC16C7X-04)
04 = 4 MHz
10 = 10 MHz
20 = 20 MHz
Device PIC16C7X :VDD range 4.0V to 6.0V
PIC16C7XT :VDD range 4.0V to 6.0V (Tape/Reel)
PIC16LC7X :VDD range 2.5V to 6.0V
PIC16LC7XT :VDD range 2.5V to 6.0V (Tape/Reel)
Examples
a) PIC16C72 - 04/P 301
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits, QTP
pattern #301
b) PIC16LC76 - 041/SO
Industrial Temp., SOIC
package, 4 MHz,
extended VDD limits
c) PIC16C74A - 10E/P
Automotiv e Temp.,
PDIP package , 10 MHz,
normal VDD limits
Information cont ai ned in this public ation regarding device applications and the li ke is intended for suggestion only and m ay be superseded by updates. No repr ese nta tion or warranty is given and n o liability is as sumed
by Microchip Technology Incorpora ted with respect to the accuracy or use of such information, or infringe ment of patents or othe r intellec tual property rights arising from such use or otherwis e. Use of Microc hip’s produc ts
as critical c om ponents in life s upport systems is not authorize d exc ept with expres s written appro val by M i crochip. No licenses are co nveyed, implicit l y or otherwise, under any intellectual propert y ri ght s. The M i cr ochip
logo and name are registered tradema rks of Mi crochip Technology Inc. in the U.S.A. and other countri es. All rights res erved. All other trademarks men tioned herein are the property of their respec tive companies.
1999 Microchip Technology Inc.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.
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ASIA/PACIFIC (continued)
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11/15/99
WORLDWIDE SALES AND SERVICE
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
