ADG1408YRUZREEL - ANALOG DEVICES - Datasheet.Directory

PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in

LFPAK56 using NextPower-S3 technology

14 March 2019 Product data sheet

1. General description

240 Amp, logic level gate drive N-channel enhancement mode MOSFET in 175 °C LFPAK56

package using advanced TrenchMOS Superjunction technology. This product has been designed

and qualified for high performance power switching applications.

2. Features and benefits

•240 A capability

•Avalanche rated, 100% tested at IAS = 190 A

•NextPower-S3 technology delivers 'superfast switching with soft recovery'

•Low QRR, QG and QGD for high system efficiency and low EMI designs

•Schottky-Plus body-diode, gives soft switching without the associated high IDSS leakage

•Optimised for 4.5 V gate drive utilising NextPower-S3 Superjunction technology

•High reliability LFPAK (Power SO8) package, copper-clip, solder die attach and

qualified to 175 °C

•Exposed leads can be wave soldered, visual solder joint inspection and high quality solder

joints

•Low parasitic inductance and resistance

3. Applications

•Synchronous rectification

•DC-to-DC converters

•High performance & high efficiency server power supply

•Motor control

•Power OR-ing

4. Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 40 V

IDdrain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - - 240 A

Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 238 W

Tjjunction temperature -55 - 175 °C

Static characteristics

VGS = 4.5 V; ID = 25 A; Tj = 25 °C;

Fig. 10

- 1.38 1.85 mΩRDSon drain-source on-state

resistance

VGS = 10 V; ID = 25 A; Tj = 25 °C;

Fig. 10

- 1.12 1.4 mΩ

Dynamic characteristics

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

Symbol Parameter Conditions Min Typ Max Unit

QGD gate-drain charge - 13 26 nC

QG(tot) total gate charge

ID = 25 A; VDS = 20 V; VGS = 4.5 V;

Fig. 12; Fig. 13 - 45 65 nC

[1] 240A continuous current has been successfully demonstrated during application test. Practically, the current will be limited by PCB,

thermal design and operating temperature.

5. Pinning information

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1 S source

2 S source

3 S source

4 G gate

mb D mounting base; connected to

drain

1 2 3 4

LFPAK56; Power-

SO8 (SOT669)

mbb076

6. Ordering information

Table 3. Ordering information

PackageType number

Name Description Version

PSMN1R4-40YLD LFPAK56;

Power-SO8

Plastic single-ended surface-mounted package (LFPAK56;

Power-SO8); 4 leads

SOT669

7. Marking

Table 4. Marking codes

Type number Marking code

PSMN1R4-40YLD 1D440L

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V

VDSM peak drain-source

voltage

tp ≤ 20 ns; f ≤ 500 kHz; EDS(AL) ≤ 200 nJ;

pulsed

- 45 V

VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 40 V

VGS gate-source voltage -20 20 V

Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 238 W

VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - 240 AIDdrain current

VGS = 10 V; Tmb = 100 °C; Fig. 2 - 214 A

IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 1201 A

Tstg storage temperature -55 175 °C

Product data sheet 14 March 2019 2 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

Symbol Parameter Conditions Min Max Unit

Tjjunction temperature -55 175 °C

Tsld(M) peak soldering

temperature

- 260 °C

VESD electrostatic discharge

voltage

HBM 2 - kV

Source-drain diode

ISsource current Tmb = 25 °C - 198.6 A

ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 1201 A

Avalanche ruggedness

ID = 74 A; Vsup ≤ 40 V; RGS = 50 Ω;

VGS = 10 V; Tj(init) = 25 °C; unclamped;

tp = 0.23 ms

[2] - 446 mJEDS(AL)S non-repetitive drain-

source avalanche energy

ID = 25 A; Vsup ≤ 40 V; RGS = 50 Ω;

VGS = 10 V; Tj(init) = 25 °C; unclamped;

tp = 2.52 ms

[2] - 1641 mJ

IAS non-repetitive avalanche

current

Vsup ≤ 40 V; VGS = 10 V; Tj(init) = 25 °C;

RGS = 50 Ω

[2] - 190 A

[1] 240A continuous current has been successfully demonstrated during application test. Practically, the current will be limited by PCB,

thermal design and operating temperature.

[2] Protected by 100% test

Tmb (°C)

0 20015050 100

03aa16

120

Pder

(%)

Fig. 1. Normalized total power dissipation as a

function of mounting base temperature

aaa-013028

0 25 50 75 100 125 150 175 200

160

240

320

Tmb (°C)

(A)(A)

(1)(1)

(1) 240A Continuous current has been successfully

demonstrate during application tests. Practically the

current will be limited by PCB, thermal design and

operation temperature.

VGS ≥ 10 V

Fig. 2. Continuous drain current as a function of

mounting base temperature

Product data sheet 14 March 2019 3 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

aaa-013030

10-1 1 10 102

10-1

102

103

104

VDS (V)

(A)(A)

DCDC

100 ms100 ms

10 ms10 ms

1 ms1 ms

100 µs100 µs

tp = 10 µstp = 10 µs

Limit RDSon = VDS / ID

Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

9. Thermal characteristics

Table 6. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from

junction to mounting

base

Fig. 4 - 0.56 0.63 K/W

Fig. 5 - 50 - K/WRth(j-a) thermal resistance from

junction to ambient Fig. 6 - 125 - K/W

aaa-009500

10-6 10-5 10-4 10-3 10-2 10-1 1

10-3

10-2

10-1

tp (s)

Zth(j-mb)

(K/W)(K/W)

δ = T

single shotsingle shot

δ = 0.5δ = 0.5

0.20.2

0.10.1

0.050.05

0.020.02

Fig. 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

Product data sheet 14 March 2019 4 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

aaa-005750

Fig. 5. PCB layout for thermal resistance junction to

ambient 1” square pad; FR4 Board; 2oz copper

aaa-005751

Fig. 6. PCB layout for thermal resistance junction to

ambient minimum footprint;FR4 board; 2oz

copper

10. Characteristics

Table 7. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - VV(BR)DSS drain-source

breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V

VGS(th) gate-source threshold

voltage

ID = 1 mA; VDS=VGS; Tj = 25 °C 1.05 1.7 2.2 V

ΔVGS(th)/ΔT gate-source threshold

voltage variation with

temperature

25 °C ≤ Tj ≤ 150 °C - -4.8 - mV/K

VDS = 32 V; VGS = 0 V; Tj = 25 °C - - 1 µAIDSS drain leakage current

VDS = 32 V; VGS = 0 V; Tj = 125 °C - 12 - µA

VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nAIGSS gate leakage current

VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA

VGS = 10 V; ID = 25 A; Tj = 25 °C;

Fig. 10

- 1.12 1.4 mΩ

VGS = 10 V; ID = 25 A; Tj = 175 °C;

Fig. 10; Fig. 11

- - 2.65 mΩ

VGS = 4.5 V; ID = 25 A; Tj = 25 °C;

Fig. 10

- 1.38 1.85 mΩ

RDSon drain-source on-state

resistance

VGS = 4.5 V; ID = 25 A; Tj = 175 °C;

Fig. 10; Fig. 11

- - 3.4 mΩ

RGgate resistance f = 1 MHz - 1.1 3.43 Ω

Dynamic characteristics

ID = 25 A; VDS = 20 V; VGS = 10 V;

Fig. 12; Fig. 13

- 96 143 nC

ID = 25 A; VDS = 20 V; VGS = 4.5 V;

Fig. 12; Fig. 13

- 45 65 nC

QG(tot) total gate charge

ID = 0 A; VDS = 0 V; VGS = 10 V - 85 - nC

QGS gate-source charge - 15 25 nC

QGS(th) pre-threshold gate-

source charge

ID = 25 A; VDS = 20 V; VGS = 4.5 V;

Fig. 12; Fig. 13 - 9 - nC

Product data sheet 14 March 2019 5 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

Symbol Parameter Conditions Min Typ Max Unit

QGS(th-pl) post-threshold gate-

source charge

- 6 - nC

QGD gate-drain charge - 13 26 nC

VGS(pl) gate-source plateau

voltage

ID = 25 A; VDS = 20 V; Fig. 12; Fig. 13 - 2.7 - V

Ciss input capacitance - 6661 10413 pF

Coss output capacitance - 1543 2309 pF

Crss reverse transfer

capacitance

VDS = 20 V; VGS = 0 V; f = 1 MHz;

Tj = 25 °C; Fig. 14

- 299 658 pF

td(on) turn-on delay time - 39 - ns

trrise time - 49 - ns

td(off) turn-off delay time - 47 - ns

tffall time

VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V;

RG(ext) = 5 Ω

- 30 - ns

Qoss output charge VGS = 0 V; VDS = 20 V; f = 1 MHz;

Tj = 25 °C

- 50 - nC

Source-drain diode

VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.78 1.2 V

trr reverse recovery time - 47 - ns

Qrrecovered charge [1] - 61 - nC

tareverse recovery rise

time

- 25.4 - ns

tbreverse recovery fall

time

IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;

VDS = 20 V; Fig. 16

- 21.7 - ns

[1] includes capacitive recovery

aaa-013032

012345

100

150

200

250

300

VDS (V)

(A)(A)

2.6 V2.6 V

2.8 V2.8 V

VGS = 3 VVGS = 3 V

3.5 V3.5 V

4.5 V4.5 V

10 V10 V

Tj = 25 °C

Fig. 7. Output characteristics; drain current as a

function of drain-source voltage; typical values

aaa-013033

0 2 4 6 8 10 12 14 16

VGS (V)

RDSon

(mΩ)(mΩ)

Fig. 8. Drain-source on-state resistance as a function

of gate-source voltage; typical values

Product data sheet 14 March 2019 6 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

aaa-013035

0 0.5 1 1.5 2 2.5 3 3.5 4

100

150

200

250

300

VGS (V)

(A)(A)

Tj = 25°CTj = 25°C175°C175°C

Fig. 9. Transfer characteristics; drain current as a

function of gate-source voltage; typical values

aaa-013038

0 60 120 180 240 300

ID (A)

RDSon

(mΩ)(mΩ)

2.8 V2.8 V 3 V3 V

3.5 V3.5 V

4.5 V4.5 V

10 V10 V

Tj = 25 °C

Fig. 10. Drain-source on-state resistance as a function

of drain current; typical values

aaa-013039

-60 -30 0 30 60 90 120 150 180

0.4

0.8

1.2

1.6

Tj (°C)

10 V10 V

VGS = 4.5 VVGS = 4.5 V

Fig. 11. Normalized drain-source on-state resistance

factor as a function of junction temperature

003aaa508

VGS

VGS(th)

QGS1

QGS2

QGD

VDS

QG(tot)

QGS

VGS(pl)

Fig. 12. Gate charge waveform definitions

Product data sheet 14 March 2019 7 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

aaa-013040

0 20 40 60 80 100

QG (nC)

VGS

(V)(V)

20 V20 V

VDS = 8 VVDS = 8 V

32 V32 V

Fig. 13. Gate-source voltage as a function of gate

charge; typical values

aaa-013041

10-1 1 10 102

102

103

104

VDS (V)

(pF)(pF) Ciss

Ciss

Coss

Crss

Fig. 14. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

aaa-013042

0 0.2 0.4 0.6 0.8 1 1.2

102

103

VSD (V)

(A)(A)

Tj = 25°CTj = 25°C175°C175°C

Fig. 15. Source current as a function of source-drain

voltage; typical values

003aal160

t (s)

(A)

IRM

0.25 IRM

tatb

trr

Fig. 16. Reverse recovery timing definition

Product data sheet 14 March 2019 8 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

11. Package outline

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT669 MO-235

sot669_po

11-03-25

13-02-27

Unit(1)

max

nom

min

1.20

1.01

0.15

0.00

0.25

0.50

0.35

4.41

3.62

2.2

2.0

6.2

5.8

0.85

0.40

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669

A1A2

1.10

0.95

A3b b2b3

0.1

L2w y

8°

0°

b4c c2D(1) D1(1) E(1) E1(1)

3.3

3.1

1.27

H L

0.25

0.19

0.30

0.24

4.20 1.3

0.8

0.25

0.9

0.7

4.10

3.80

5.0

4.8

1.3

0.8

A C

1/2 e

w A

0 5 mm

scale

12 3 4

mounting

base

y C

(A3)

detail X

Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669)

Product data sheet 14 March 2019 9 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

12. Soldering

0.6

(3×)

0.7

(4×)

0.25

(2×)

0.25

(2×)

0.6

(4×)

4.2

4.7

0.25

(2×)

1.27

1.1

3.81

0.9

(3×)

SP opening =

Cu - 0.050

SR opening =

Cu + 0.075

2.15

2.55

3.45 3.5

3.3

solder lands

solder resist occupied area

solder paste

125 µm stencil

Dimensions in mm

SOT669

Footprint information for reflow soldering

sot669_fr

Fig. 18. Reflow soldering footprint for LFPAK56; Power-SO8 (SOT669)

Product data sheet 14 March 2019 10 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

SOT669Wave soldering footprint information for LFPAK56 package

sot669_fw

solder lands

Dimensions in mm

Issue date 15-04-13

15-04-16

4.826

0.6 (x4) 1.27

0.635

1.78

1.72

2.1

1.4

Fig. 19. Wave soldering footprint for LFPAK56; Power-SO8 (SOT669)

Product data sheet 14 March 2019 11 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

13. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

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Product data sheet 14 March 2019 12 / 13

Nexperia PSMN1R4-40YLD

N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Applications.................................................................. 1

4. Quick reference data.................................................... 1

5. Pinning information......................................................2

6. Ordering information....................................................2

7. Marking.......................................................................... 2

8. Limiting values............................................................. 2

9. Thermal characteristics............................................... 4

10. Characteristics............................................................ 5

11. Package outline.......................................................... 9

12. Soldering................................................................... 10

13. Legal information......................................................12

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 14 March 2019

Product data sheet 14 March 2019 13 / 13