NCP3230 Buck Converter - High Current, Synchronous The NCP3230 is a high current, high efficiency, voltage-feed- forward voltage-mode synchronous buck converter which operates from 4.5 V to 18 V input and generates output voltages down to 0.6 V at up to 30 A load. www.onsemi.com Features MARKING DIAGRAM Wide Input Voltage Range from 4.5 V to 18 V 0.6 V Internal Reference Voltage 500 kHz Switching Frequency External Programmable Soft-start Lossless Low-side FET Current Sensing Output Over-voltage Protection and Under-voltage Protection System Over-temperature Protection using a Thermistor or Sensor Hiccup Mode Operation for All Faults Pre-bias Start-up Adjustable Output Voltage Power Good Output Internal Over-temperature Protection This is a Pb-Free Device 1 1 40 NCP3230 A WL YY WW G PG OTS AGND ISET 4 SS VIN 5 FB VIN 6 COMP VIN 7 1 8 2 9 3 10 VIN 11 VIN 12 VIN 13 VIN 14 37 PGND VSWH 15 36 BST PGND 16 35 VSW PGND 17 PGND 18 PGND 19 32 VSWH PGND 20 31 VSWH 40 EN VIN EP42 39 VCC GND EP41 38 VB 34 VSWH 27 28 29 PGND PGND VSWH 30 26 PGND VSWH 25 PGND 23 PGND 24 22 33 VSWH PGND 21 VSWH EP43 PGND Cellular Base Stations ASIC, FPGA, DSP and CPU Core and I/O Supplies Telecom and Network Equipment Server and Storage System = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package PIN CONNECTIONS Typical Applications * * * * NCP3230 AWLYYWWG QFN40 6x6, 0.5P CASE 485CM PGND * * * * * * * * * * * * * (TOP VIEW) ORDERING INFORMATION Device Package Shipping NCP3230MNTXG QFN-40 (Pb-Free) 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2016 August, 2019 - Rev. 2 1 Publication Order Number: NCP3230/D NCP3230 VB LDO VCC VCC VB VB VB BST VIN OSC COMP VREF FB VDD Control Logic Ramp Generator PWM Logic + E/A - - and - SS UVLO OVP, UVP Power Good OCP, TSD Protection Soft Start VCC 2 mA EN VB VSWH VSW PVDD Enable Logic 1.2 V POR PGND PG VB + - VREF OTS ISET AGND Figure 1. NCP3230 Block Diagram www.onsemi.com 2 NCP3230 PIN DESCRIPTION Pin No. Symbol 1 SS A capacitor from this pin to GND allows the user to adjust the soft-start ramp time. Description 2 FB Output voltage feedback. 3 COMP 4 ISET 5 AGND 6 OTS 7 PG Power good indicator of the output voltage. Open-drain output. Connect PG to VDD with an external resistor. 8-14, EP42 VIN The VIN pin is connected to the internal power NMOS switch. The VIN pin has high di/dt edges and must be decoupled to ground close to the pin of the device. 15, 29-34, EP43 VSWH The VSWH pin is the connection of the drain and source of the internal NMOS switches. At switch off, the inductor will drive this pin below ground as the body diode and the NMOS conducts with a high dv/dt. 16-28, 37 PGND Ground reference and high-current return path for the bottom gate driver and low- side NMOS. 35 VSW IC connection to the switch node between the top MOSFET and bottom MOSFET. Return path of the high- side gate driver. 36 BST Top gate driver input supply, a bootstrap capacitor connection between the switch node and this pin. 38 VB The internal LDO output and input supply for the NCP3230. Connect a minimum of 4.7 mF ceramic capacitor from this pin to ground. 39 VCC Input Supply for IC. This pin must be connected to VIN. Decouple the VCC pin close to ground near the pin of the device. 40 EN Logic control for enabling the switcher. An internal pull-up enables the device automatically. The EN pin can also be driven high to turn on the device, or low to turn off the device. A comparator and precision reference allow the user to implement this pin as an adjustable UVLO circuit. EP41 GND Output of the error amplifier. A resistor from this pin to ground sets the over-current protection (OCP) threshold. Analog ground. Negative input of internal thermal comparator. Tie this pin to ground if not in use. Exposed Pad. Connect GND to a large copper plane at ground potential to improve thermal dissipation. VIN VIN BST VCC VOUT VSWH VSW VB PGND NCP3230 ISET AGND VPG EN FB OTS PG COMP SS 1 MW Figure 2. Typical Application Circuit www.onsemi.com 3 NCP3230 ABSOLUTE MAXIMUM RATINGS (measured vs. GND pads, unless otherwise noted) Rating Symbol Value Unit VIN, VCC 20.5 -0.3 V VSW to GND VSWH, VSW 25 -0.6 (DC) 30 (t < 50 ns) -4 (t < 100 ns) V BST to GND BST 30 (DC) -0.6 (DC) 32 (t < 50 ns) V BST to VSW VBST_VSW 6.5 (DC) -0.3 (DC) V 6.0 -0.3 V Power Supply to GND All other pins Operating Ambient Temperature Range (Note 1) TA -40 to +90 C Operating Junction Temperature Range (Note 1) TJ -40 to +150 C TJ(MAX) +150 C Tstg -55 to +150 C Maximum Junction Temperature Storage Temperature Range Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The maximum package power dissipation limit must not be exceeded. PD + T J(MAX) * T A R qJA THERMAL INFORMATION HS FET Junction-to-case-bottom thermal resistance (Note 2) RqJC-HS 1.3 C/W LS FET Junction-to-case-bottom thermal resistance (Note 2) RqJC-LS 0.6 C/W RqA 35 C/W Junction-to-ambient thermal resistance 2. RJC thermal resistance is obtained by simulating a cold plate test on the exposed power pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. www.onsemi.com 4 NCP3230 ELECTRICAL CHARACTERISTICS (-40C < TJ < +125C, VCC = 12 V, for min/max values unless otherwise noted, TJ = +25C for typical values) Parameter Symbol Test Conditions Min Typ Max Units POWER SUPPLY 18 V VB UVLO Threshold (Rising) 4.1 4.2 4.3 V VB UVLO Threshold (Falling) 3.4 3.66 3.8 V 4.9 5.15 5.45 V IB = 25 mA, VCC = 4.5 V 36 100 mV EN = H, COMP = H, no switching; PG open; no switching 4.9 6.6 mA NCP3230; EN = 0; VCC = 18 V; PG open 100 140 mA NCP3230; EN = 0; VCC = 4.5 V; PG open 58 75 mA V VIN/VCC Operation Voltage VB Output Voltage VIN/VCC VB VB Dropout Voltage VCC Quiescent Current Shutdown Supply Current 4.5 VCC = 6 V, 0 IB 40 mA FEEDBACK VOLTAGE FB Input Voltage Feedback Input Bias Current VFB TJ = 25C, 4.5 V VCC 18 V 0.597 0.6 0.603 -40C TJ 125C; 4.5 V VCC 18 V 0.594 0.6 0.606 IFB VFB = 0.6 V 75 nA ERROR AMPLIFIER 60 85 dB 24 MHz 60 2.5 V/m COMP Clamp Voltage, High 3.46 V COMP Clamp Voltage, Low 436 mV Open Loop DC Gain (Note 4) Open Loop Unity Gain Bandwidth F0dB,EA Open Loop Phase Margin Slew Rate COMP pin to GND = 10 pF Output Source Current VFB = 0 V 15 mA Output Sink Current VFB = 1 V 20 mA CURRENT LIMIT Low-side RDSON over ISET Current RDSON/ISET Low-side ISET Current Source Temperature Coefficient TC_LS_I-SET TJ = 25C See OCP section for more information Low-side OCP Switch-over Threshold (Note 4) Low-side Fixed OCP Threshold (Note 4) LS_OCPth Low-side Programmable OCP Range LS_OCPth LS OCP Blanking time (Note 4) LS_Tblnk 42 W/A +0.31 %/C 600 mV 300 mV < 600 mV 150 ns PWM Maximum duty cycle fsw = 500 kHz, VFB = 0 V 4.5 V < VCC < 18 V 94 % Minimum duty cycle VCOMP < PWM Ramp Offset Voltage 0 % Minimum GH on-time (Note 3) 60 ns PWM Ramp Amplitude (Note 3) VCC/8.3 VCC/6.3 VCC/5.3 V 3. Guaranteed by characterization 4. Guaranteed by design www.onsemi.com 5 NCP3230 ELECTRICAL CHARACTERISTICS (-40C < TJ < +125C, VCC = 12 V, for min/max values unless otherwise noted, TJ = +25C for typical values) Parameter Symbol Test Conditions Min Typ Max Units PWM PWM Ramp Offset (Note 3) 0.64 V OSCILLATOR Oscillator Frequency Range Hiccup Timer fsw fsw = 500 kHz 4.5 V < VCC < 18 V 450 500 550 kHz thiccup tss < 1 ms, fsw = 500 kHz 4 ms tss > 1 ms, fsw = 500 kHz 4 x tss ms ENABLE INPUT (EN) EN Input Operating Range Enable Threshold Voltage VEN rising Enable Hysteresis VEN falling Deep Disable Threshold 1.1 1.2 5.5 V 1.3 V 142 0.7 Enable Pull-up Current 0.8 mV 0.9 V 2.15 mA SOFTSTART INPUT (SS) SS Startup Delay tSSD 1.33 ms SS End Threshold SSEND 0.6 V SS Source Current ISS 2.15 2.5 2.8 mA 10 20 30 mA 662 675 686 mV VOLTAGE MONITOR PG = 0.15 V Power Good Sink Current Output Overvoltage Rising Threshold Overvoltage Fault Blanking Time 20 Output Under-Voltage Trip Threshold 500 Under-voltage Protection Blanking Time 525 ms 550 mV 20 ms POWER STAGE High-side On Resistance RDSONH VGS = 5 V, ID = 2 A 4.0 mW Low-side On Resistance RDSONL VGS = VB, ID = 2 A 0.85 mW IBOOT = 2 mA 28 mV VFBOOT THERMAL MONITOR (OTS) 0.59 OTS comparator reference voltage (Rising Threshold) OTS comparator reference voltage (Falling Hysteresis) (Note 3) 0.6 0.61 V 50 mV Thermal Shutdown Threshold 150 C Thermal Shutdown Hysteresis 25 C THERMAL SHUTDOWN 3. Guaranteed by characterization 4. Guaranteed by design Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 6 NCP3230 fSW, SWITCHING FREQUENCY (kHz) 0.602 0.601 0.600 0.599 0.598 0.597 0.596 -40 -25 -10 5 20 35 50 65 80 95 110 125 503 VCC = 12 V 502 501 500 VCC = 4.5 V 499 498 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) Figure 3. Reference Voltage vs. Temperature Figure 4. Switching Frequency vs. Temperature 1.23 1.22 1.21 1.20 1.19 -40 -25 -10 5 20 35 50 65 80 95 110 125 1.10 1.09 1.08 1.07 1.06 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 5. Rising Enable Threshold vs. Temperature Figure 6. Falling Enable Threshold vs. Temperature 7 100 90 IQ, QUIESCENT CURRENT (mA) ISD, SHUTDOWN CURRENT (mA) 504 TJ, JUNCTION TEMPERATURE (C) VEN, FALLING ENABLE THRESHOLD (V) VEN, RISING ENABLE THRESHOLD (V) VFB, FEEDBACK REFERENCE VOLTAGE (V) TYPICAL CHARACTERISTICS 80 70 60 50 40 30 20 VCC = 12 V 10 0 -40 -25 -10 5 20 35 50 65 80 6 5 4 3 2 1 VCC = 12 V, No Switching 0 -40 -25 -10 95 110 125 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 7. Shutdown Current vs. Temperature Figure 8. Quiescent Current vs. Temperature www.onsemi.com 7 NCP3230 TYPICAL CHARACTERISTICS 45 44 2.65 43 RDS(ON)/ISET (W/A) 2.60 2.55 2.50 2.45 2.40 5 20 35 50 65 80 40 39 38 35 -40 -25 -10 95 110 125 35 50 65 80 95 110 125 Figure 9. Soft-start Current vs. Temperature Figure 10. RDS(on)/ISET Current vs. Temperature 1.4 6.0 1.3 5.5 VIN/VCC = 4.5 V 5.0 VIN/VCC = 12 V 4.5 4.0 3.5 3.0 -40 -25 -10 5 20 50 35 65 80 95 1.2 VIN/VCC = 4.5 V 1.1 1.0 VIN/VCC = 12 V 0.9 0.8 0.7 0.6 -40 -25 -10 110 125 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 11. High-side RDS(on) vs. Temperature Figure 12. Low-side RDS(on) vs. Temperature 100 100 95 95 90 85 VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V VOUT = 5.0 V 80 VIN = 12 V TA = Room 75 0 20 TJ, JUNCTION TEMPERATURE (C) 6.5 70 5 TJ, JUNCTION TEMPERATURE (C) LOW-SIDE FET RDS(on) (mW) HIGH-SIDE FET RDS(on) (mW) 41 36 2.30 -40 -25 -10 EFFICIENCY (%) 42 37 2.35 EFFICIENCY (%) ISS, SOFT-START CURRENT (mA) 2.70 5 10 15 20 25 90 85 VIN = 5 V TA = Room 75 70 30 VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V 80 0 5 10 15 20 IOUT, LOAD CURRENT (A) IOUT, LOAD CURRENT (A) Figure 13. Efficiency vs. Iout (Vin = 12 V) Figure 14. Efficiency vs. Iout (Vin = 5 V) www.onsemi.com 8 25 30 NCP3230 TYPICAL CHARACTERISTICS 4.30 Rising Threshold 0.60 4.26 0.59 4.22 0.58 0.57 4.18 0.56 4.14 Falling Threshold 0.55 0.54 -40 -25 -10 5 20 35 50 65 80 4.10 -40 -25 -10 95 110 125 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 15. OTS Threshold vs. Temperature Figure 16. VB UVLO Rising Threshold vs. Junction Temperature OVP, OVERVOLTAGE THRESHOLD (mV) 3.80 3.76 3.72 3.68 3.64 3.60 -40 -25 -10 5 20 35 50 65 80 95 110 125 680 679 678 677 676 675 674 673 672 671 670 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 17. VB UVLO Falling Threshold vs. Junction Temperature Figure 18. Output OVP vs. Junction Temperature UVP, UNDERVOLTAGE THRESHOLD (mV) VB UVLO, FALLING THRESHOLD VOLTAGE (V) VB UVLO RISING THRESHOLD VOLTAGE (V) OTS, OVERTEMPERATURE THRESHOLD VOLTAGE (V) 0.61 560 558 556 554 552 550 548 546 544 542 540 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) Figure 19. Output UVP vs. Junction Temperature www.onsemi.com 9 NCP3230 TYPICAL CHARACTERISTICS CH1 (Blue): EN CH2 (Aqua): COMP CH3 (Purple): Vout CH4 (Green): SS CH1 (Blue): VSW CH2 (Aqua): COMP CH3 (Purple): Vout CH4 (Green): SS Figure 20. Typical Startup Waveforms (Vin = 12 V, Iout = 25 A, Vout = 1 V) Figure 21. Typical Short Circuit Waveforms (Vin = 12 V) www.onsemi.com 10 NCP3230 OPERATION DESCRIPTION Overview Adaptive Non-Overlap Gate Driver The NCP3230 is a 500 kHz, high efficiency, high current PWM synchronous buck converter. It operates with a single supply voltage from 4.5 to 18 V and can provide output current as high as 30 A. NCP3230 utilizes voltage mode with voltage feed-forward control to respond instantly to Vin changes and provide for easier compensation over the supply range of the converter. The device also includes pre-bias startup capability to allow monotonic startup in the event of a pre-biased output condition. Protection features include overcurrent protection (OCP), output over and under voltage protection (OVP, UVP), and power good. The enable function is highly programmable to allow for adjustable startup voltages at higher input voltages. There is also an adjustable soft-start, an over- temperature comparator, and internal thermal shutdown. In a synchronous buck converter, a certain dead time is required between the low side drive signal and high side drive signal to avoid shoot through. During the dead time, the body diode of the low side FET freewheels the current. NCP3230 implements adaptive dead time control to minimize the dead time, as well as preventing shoot through. Precision Enable (EN) The ENABLE block allows the output to be toggled on and off and is a precision analog input. When the EN voltage exceeds V_EN, the controller will initiate the soft-start sequence as long as the input voltage and sub-regulated voltage have exceeded their UVLO thresholds. V_EN_hyst helps to reject noise and allow the pin to be resistively coupled to the input voltage or sequenced with other rails. If the EN voltage is held below typically 0.8 V, the NCP3230 enters a deep disable state where the internal bias circuitry is off. As the voltage at EN continues to rise, the Enable comparator and reference are active and provide a more accurate EN threshold. The drivers are held off until the rising voltage at EN crosses V_EN. An internal 2 mA pullup automatically enables the device when the EN pin is left floating. Reference Voltage The NCP3230 incorporates an internal reference that allows output voltages as low as 0.6 V. The tolerance of the internal reference is guaranteed over the entire operating temperature range of the controller. The reference voltage is trimmed using a test configuration that accounts for error amplifier offset and bias currents. Oscillator Ramp The ramp waveform is a saw tooth formed at the PWM frequency with a peak-to-peak amplitude of VCC/6.3, offset from GND by typically 0.64 V. The PWM duty cycle is limited to a typical 94%, allowing the bootstrap capacitor to charge during each cycle. INPUT SUPPLY / VCC VDD 2 mA EN Error Amplifier The error amplifier's primary function is to regulate the converter's output voltage using a resistor divider connected from the converter's output to the FB pin of the controller, as shown in the Applications Schematic. A type III compensation network must be connected around the error amplifier to stabilize the converter. It has a bandwidth of greater than 24 MHz, with open loop gain of at least 60 dB. 1.2 V Figure 22. Enable Functional Block Diagram Pre-bias Startup In some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 V to just below the regulation voltage. This situation occurs for a number of reasons: the converter's output capacitors may have residual charge on them or the converter's output may be held up by a low current standby power supply. NCP3230 supports pre-bias start up by holding off switching until the feedback voltage and thus the output voltage rises above the set regulated voltage. If the pre-bias voltage is higher than the set regulated voltage, switching does not occur until the output voltage drops back to the regulation point. Programmable Soft-Start An external capacitor connected from the SS pin to ground sets up the soft start period, which can limit the start-up inrush current. The soft start period can be programmed based on the Equation 1. t SS + C SS I SS V ref Enable Logic (eq. 1) OCP is the only fault that is active during a soft-start. www.onsemi.com 11 NCP3230 Power Good (PG) Operation Power Good Pullup Voltage LSOCP Trip Level Inductor Current Start Reset/Start Reset/Start Backup Counter Start Hiccup Hiccup Counter 1 2 3 tHiccup = 4xtSS Skipped Pulses showing Skip Count Figure 23. LSOCP Function with Counters and Power Good Shown (exaggerated for informational purposes) www.onsemi.com 12 NCP3230 PROTECTION FEATURES Hiccup Mode RSET + The NCP3230 utilizes hiccup mode for all of its fault conditions. Upon entering hiccup mode after a fault detection, the NCP3230 turns off the high side and low side FET's and PG goes low. It waits for tHICCUP ms before reinitiating a soft-start. tHiccup is defined as four soft start timeouts (tss). The equation for tss is shown in Equation 1. OCP is the only active fault detection during the hiccup mode soft start. i LS RDSON i SET 3.5 (eq. 2) In this equation, iLS is the inductor peak current value, RDSON is the on resistance of low-side MOSFET, and iSET is a current source out of the ISET pin, which can compensate the temperature effects of on resistance of low-side MOSFET. NCP3230 can guarantee that RDSON/iSET is a constant value. By doing this, OCP accuracy won't be affected by the variation of MOSFET RDSON. In case RSET is not connected, the device switches the OCP threshold to a fixed 300 mV threshold. After one OCP event is detected, the NCP3230 keeps the high-side MOSFET off until the low-side MOSFET falls below the trip point again and the high-side MOSFET turns on in the next clock cycle. So the low-side over current protection shows pulse skipping behavior. An internal OCP counter will count up to 3 consecutive OCP events. After the third consecutive count, the device enters hiccup/latch mode. The scheme of LS OCP and hiccup mode protection is described in Figure 23. To prevent nuisance trips, there is a backup counter that will reset the OCP counter after 7 consecutive cycles without an LSOCP trigger. The backup counter is reset and then started again after each OCP trip until the third OCP count as stated above occurs. Over Temperature Comparator (OTS) The NCP3230 provides an over-temperature shutdown (OTS) comparator with 50 mV hysteresis and a 0.6 V reference in order to remotely sense an external temperature detector or thermistor. When the voltage at the OTS pin rises above 0.6 V, the drivers stop switching and both FET's remain off. When this voltage drops below typically 0.55 V, a new soft-start cycle is generated automatically. Tie the OTS pin to ground if this function is not required. Over Voltage Protection (OVP) When the voltage at the FB pin (VFB) is above the OVP threshold for greater than 20 ms (typical), an OVP fault is set. The high side FET (HSFET) will turn off and the low side FET (LSFET) will turn on. The open-drain PG pull down will turn on at that point as well, thus pulling PG low. Once VFB has fallen below the Undervoltage Protection Threshold (UVP), the device will enter hiccup mode. Thermal Shutdown (TSD) The NCP3230 protects itself from overheating with an internal thermal monitoring circuit. If the junction temperature exceeds the thermal shutdown threshold both the upper and lower MOSFETs will be shut OFF. Once the temperature drops below the falling hysteresis threshold, the voltage at the COMP pin will be pulled below the ramp valley voltage and a soft-start will be initiated. Under Voltage Protection (UVP) A UVP circuit monitors the VFB voltage to detect an under voltage event. If the VFB voltage is below this threshold for more than 20 ms, a UVP fault is set and the device will enter hiccup mode. Over Current Protection (OCP) The NCP3230 over current protection scheme senses the peak freewheeling current in the low-side FET (LSOCP) after a blanking time of 150 ns as shown in Figure 23. The low-side MOSFET drain to source voltage is compared against the voltage of an internal temperature compensated current source and a user-selected resistor RSET. The value of RSET for a given OCP level is defined by the follow equation: Power Good Monitor (PG) NCP3230 monitors the output voltage and signal when the output is out of regulation or during a non-regulated pre-bias condition, or fault condition. When the output voltage is within the OVP and UVP thresholds, the power good pin is a high impedance output. If the NCP3230 detects an OCP, OVP, UVP, OTS, TSD or is in soft start, it pulls PG pin low. The PG pin is an open drain 10-mA pull down output. www.onsemi.com 13 NCP3230 Layout Guidelines When laying out a power PCB for the NCP3230 there are several key points to consider. To improve the Low-side OCP accuracy, users should use single ground connection instead of separate analog ground and power ground. Make sure that the inner layers (at least 2nd layer, 3rd layer and 4th layer) are dedicated for ground plane. Do not use other copper planes to break or interrupt the shape of ground plane, which may add more parasitic components to affect the sensing accuracy. Thermal management consideration: the major heat flow path from package to the ambient is through the copper on the PCB, the area and thickness of copper plane affect the themeral performance; maximize the copper coverage on all the layers to increase the effective thermal conductivity of the board. This is importatnt especially when there is no heat sinks attached to the PCB on the other side of the package; add as many thermal vias as possible directly under the package ground pad to maximize the effective out-of-plane thermal conductivity of the board; all the thermal vias must be either plated (copper) shut or plugged and capped on both sides of the board. This prevents solder seeping in to the thermal vias causing solder voids. Solder voides are higher detrimental to the thermal and electrical performance of the package; to ensure reliability and performance, the solder coverage should be at least 85 percent. This means the total voids on the ground pad should be less than 15 percent with no single void larger than 1 mm. Several smaller voids are always better than a few big voids. Special Layout Guide: please pay attention to the special requirement of layout guide. To improve the High-side OCP accuracy, users should connect VCC and VIN directly and do not place any type of filter or resistor between these two pins. Base Component Placement High current path components should be placed to keep the current path as tight as possible. Placement of components on the bottom of the board such as input or output decoupling can add loop inductance. Ground Return for Power and Signals Solid, uninterrupted ground planes must be present and adjacent to the high current path. Copper Shapes on Component Layers Large copper planes on one or multiple layers with adequate vias will increase thermal transfer, reduce copper conduction losses, and minimize loop inductance. Greater than 20 A designs require 2-3 layer shapes or more, increasing the number of layers will only improve performance. This applies to input, output, and switch node shapes. Via Placement for Power and Ground Place enough vias to adequately connect outer layers to inner layers for thermal transfer and to minimize added inductance in layer transition. Multiple vias should be placed near important components like input ceramics and output ceramic capacitors. Key Signal Routes Do not route sensitive signals, such as FB, near or under noisy nets such as the switch node, VSW, to reduce noise coupling on the sensitive lines. Thermal Copper Shapes Duplicate and extend shapes from Component Layers to improve thermal performance. www.onsemi.com 14 NCP3230 PACKAGE DIMENSIONS QFN40 6x6, 0.5P CASE 485CM ISSUE O A B D PIN ONE LOCATION 2X EEE EEE EEE L1 DETAIL A E ALTERNATE CONSTRUCTIONS EE EE 0.15 C EXPOSED Cu 2X TOP VIEW 0.15 C (A3) DETAIL B 0.10 C DIM A A1 A3 b D D2 D3 E E2 E3 E4 e G K L L1 MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION A 43X SIDE VIEW A1 0.08 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. POSITIONAL TOLERANCE APPLIES TO ALL THREE EXPOSED PADS. L L C NOTE 4 SEATING PLANE 0.10 C A B D3 D2 NOTE 5 G DETAIL A 40X L MILLIMETERS MIN MAX 0.80 1.00 --- 0.05 0.20 REF 0.18 0.30 6.00 BSC 2.30 2.50 1.40 1.60 6.00 BSC 4.30 4.50 1.90 2.10 1.64 1.84 0.50 BSC 2.20 BSC 0.20 --- 0.30 0.50 --- 0.15 SOLDERING FOOTPRINT 6.30 E3 4.56 E2 1.66 E4 1 40 K G 1 G e 40X e/2 BOTTOM VIEW 40X 0.63 2.56 b 0.10 C A B 0.05 C 2.16 4.56 NOTE 3 6.30 2.16 PKG OUTLINE 0.50 PITCH 40X 0.30 DIMENSIONS: MILLIMETERS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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