PLUS16R6DN - Philips Semiconductors / NXP Semiconductors

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 853–1358 10777

FEATURES

•Ultra high-speed

–tPD = 7.5ns and fMAX = 74MHz for the

PLUS16R8-7 Series

–tPD = 10ns and fMAX = 60 MHz for the

PLUS16R8D Series

•100% functionally and pin-for-pin

compatible with industry standard 20-pin

PAL ICs

•Power-up reset function to enhance state

machine design and testability

•Design support provided via SNAP and

other CAD tools for Series 20 PAL devices

•Field-programmable on industry standard

programmers

•Security fuse

•Individual 3-State control of all outputs

DESCRIPTION

The Philips Semiconductors PLUS16XX

family consists of ultra high-speed 7.5ns and

10ns versions of Series 20 PAL devices.

The PLUS16XX family is 100% functional

and pin-compatible with the 16L8, 16R8,

16R6, and 16R4 Series devices.

The sum of products (AND-OR) architecture

is comprised of 64 programmable AND gates

and 8 fixed OR gates. Multiple bidirectional

pins provide variable input/output pin ratios.

Individual 3-State control of all outputs and

registers with feedback (R8, R6, R4) is also

provided. Proprietary designs can be

protected by programming the security fuse.

The PLUS16R8, R6, and R4 have D-type

flip-flops which are loaded on the

Low-to-High transition of the clock input.

In order to facilitate state machine design and

testing, a power-up reset function has been

incorporated into these devices to reset all

internal registers to Active-Low after a

specific period of time.

The Philips Semiconductors State-of-the-Art

oxide isolation Bipolar fabrication process is

employed to achieve high-performance

operation.

The PLUS16XX family of devices are field

programmable, enabling the user to quickly

generate custom patterns using standard

programming equipment. See the

programmer chart for qualified programmers.

The SNAP software package from Philips

Semiconductors supports easy design entry

for the PLUS16XX series as well as other

PLD devices from Philips Semiconductors.

The PLUS16XX series are also supported by

other standard CAD tools for PAL-type

devices.

Order codes are listed in the Ordering

Information table.

DEVICE NUMBER DEDICATED

INPUTS COMBINATORIAL

OUTPUTS REGISTERED

OUTPUTS

PLUS16L8 10 8 (6 I/O) 0

PLUS16R8 8 0 8

PLUS16R6 8 2 I/O 6

PLUS16R4 8 4 I/O 4

ORDERING INFORMATION

DESCRIPTION ORDER CODE DRAWING NUMBER

20-Pin Plastic Dual-In-Line

300mil-wide

PLUS16R8DN

PLUS16R6DN

PLUS16R4DN

PLUS16L8DN

PLUS16R8–7N

PLUS16R6–7N

PLUS16R4–7N

PLUS16L8–7N

0408B

20-Pin Plastic Leaded Chip Carrier (PLCC)

PLUS16R8DA

PLUS16R6DA

PLUS16R4DA

PLUS16L8DA

PLUS16R8–7A

PLUS16R6–7A

PLUS16R4–7A

PLUS16L8–7A

0400E

NOTE:

The PLUS16XX series of devices are also processed to military requirements for operation over

the military temperature range. For specifications and ordering information, consult the Philips

Semiconductors Military Data Book.

PAL is a registered trademark of Advanced Micro Devices, Inc.

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 37

PIN CONFIGURATIONS

123 1920

SYMBOL DESCRIPTION

I Dedicated Input

O Dedicated combinatorial Output

Q Registered output

B Bidirectional (input/output)

CLK Clock input

OE Output Enable

VCC Supply Voltage

GND Ground

SYMBOL DESCRIPTION

I Dedicated Input

O Dedicated combinatorial Output

Q Registered output

B Bidirectional (input/output)

CLK Clock input

OE Output Enable

VCC Supply Voltage

GND Ground

10 11

D Q

AND

ARRAY

D Q

PLUS16R8PLUS16L8

CLK

GND

VCC

10 11

AND

ARRAY

GND

VCC

PLUS16R8PLUS16L8

9 10 11 12 13

VCC O7

GND

I2I1I0

AND

ARRAY OUTPUTS

123 1920

9 10 12 13

VCC Q7

GND

I1I0

AND

ARRAY OUTPUTS

CLK

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 38

PIN CONFIGURATIONS

SYMBOL DESCRIPTION

I Dedicated Input

O Dedicated combinatorial Output

Q Registered output

B Bidirectional (input/output)

CLK Clock input

OE Output Enable

VCC Supply Voltage

GND Ground

PLUS16R4

123 1920

9 10 12 13

VCC B7

GND

I1I0

AND

ARRAY OUTPUTS

CLK

SYMBOL DESCRIPTION

I Dedicated Input

O Dedicated combinatorial Output

Q Registered output

B Bidirectional (input/output)

CLK Clock input

OE Output Enable

VCC Supply Voltage

GND Ground

10 11

D Q

AND

ARRAY

PLUS16R6

CLK

GND

VCC

PLUS16R6

123 1920

9 10 12 13

VCC B7

GND

I1I0

AND

ARRAY OUTPUTS

CLK

10 11

D Q

AND

ARRAY

CLK

GND

VCC

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 39

LOGIC DIAGRAM PLUS16L8

NOTES:

1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.

2. Programmable connections.

911

I8I9

PRODUCT TERMS (0–63)

INPUTS (0–31)

0 31

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 40

LOGIC DIAGRAM PLUS16R8

NOTES:

1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.

2. Programmable connections.

911

CLK

I7OE

PRODUCT TERMS (0–63)

INPUTS (0–31)

0 31

D Q

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 41

LOGIC DIAGRAM PLUS16R6

NOTES:

1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.

2. Programmable connections.

911

CLK

I7OE

PRODUCT TERMS (0–63)

INPUTS (0–31)

0 31

D Q

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 42

LOGIC DIAGRAM PLUS16R4

NOTES:

1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.

2. Programmable connections.

911

CLK

I7OE

PRODUCT TERMS (0–63)

INPUTS (0–31)

0 31

D Q

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 43

FUNCTIONAL DESCRIPTIONS

The PLUS16XX series utilizes the familiar

sum-of-products implementation consisting of

a programmable AND array and a fixed OR

array. These devices are capable of replacing

an equivalent of four or more SSI/MSI

integrated circuits to reduce package count

and board area occupancy, consequently

improving reliability and design cycle over

Standard Cell or gate array options. By

programming the security fuse, proprietary

designs can be protected from duplication.

The PLUS16XX series consists of four

PAL-type devices. Depending on the

particular device type, there are a variable

number of combinatorial and registered

outputs available to the designer. The

PLUS16L8 is a combinatorial part with 8 user

configurable outputs (6 bidirectional), while

the other three devices, PLUS16R8,

PLUS16R6, PLUS16R4, have respectively 8,

6, and 4 output registers.

3-State Outputs

The PLUS16XX series devices also feature

3-State output buffers on each output pin

which can be programmed for individual

control of all outputs. The registered outputs

(Qn) are controlled by an external input

(/OE), and the combinatorial outputs (On, Bn)

use a product term to control the enable

function.

Programmable Bidirectional Pins

The PLUS16XX products feature variable

Input/Output ratios. In addition to 8 dedicated

inputs, each combinatorial output pin of the

registered devices can be individually

programmed as an input or output. The

PLUS16L8 provides 10 dedicated inputs and

6 Bidirectional I/O lines that can be

individually configured as inputs or outputs.

Output Registers

The PLUS16R8 has 8 output registers, the

16R6 has 6, and the 16R4 has 4. Each

output register is a D-type flip-flop which is

loaded on the Low-to-High transition of the

clock input. These output registers are

capable of feeding the outputs of the

registers back into the array to facilitate

design of synchronous state machines.

Power-up Reset

By resetting all flip-flops to a logic Low, as the

power is turned on, the PLUS16R8, R6, R4

enhance state machine design and

initialization capability.

Software Support

Like other Programmable Logic Devices from

Philips Semiconductors, the PLUS16XX

series are supported by SLICE, the

PC-based software development tool from

Philips Semiconductors. The PLUS16XX

family of devices are also supported by

standard CAD tools for PAL devices,

including ABEL and CUPL.

SLICE is available free of charge to qualified

users.

Logic Programming

The PLUS16XX series is fully supported by

industry standard (JEDEC compatible) PLD

CAD tools, including Philips Semiconductors

SNAP design software package. ABEL

CUPL and PALASM 90 design software

packages also support the PLUS16XX

architecture.

All packages allow Boolean and state

equation entry formats. SNAP, ABEL and

CUPL also accept, as input, schematic

capture format.

Programming/Software Support

Ref to Section 9

(Development Software)

and

Section 10.

(Third-Party Programmer/

Software Support

) of the PLD data handbook

for additional information.

AND ARRAY – (I, B)

I, B

P, D

I, B

STATE

INACTIVE1, 2CODE

I, B

P, D

I, B

STATE CODE

I, B

P, D

I, B

STATE CODE

I, B

P, D

I, B

STATE CODE

–I, B I, B DON’T CARE

VIRGIN STATE

A factory shipped virgin device contains all

fusible links intact, such that:

1. All outputs are at “H” polarity.

2. All Pn terms are disabled.

3. All Pn terms are active on all outputs.

ABEL is a trademark of Data I/O Corp.

CUPL is a trademark of Logical Devices, Inc.

PALASM is a registered trademark of AMD Corp.

TEMPERATURE

Maximum junction

Maximum ambient

Allowable thermal

rise ambient to

junction

150°C

75°C

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 44

ABSOLUTE MAXIMUM RATINGS1THERMAL RATINGS

RATINGS

SYMBOL PARAMETER MIN MAX UNIT

VCC Supply voltage –0.5 +7 VDC

VIN Input voltage –1.2 +8.0 VDC

VOUT Output voltage –0.5 VCC + 0.5V VDC

IIN Input currents –30 +30 mA

IOUT Output currents +100 mA

Tstg Storage temperature range –65 +150 °C

NOTE:

1. Stresses above those listed may cause malfunction or permanent damage to the device. This

is a stress rating only. Functional operation at these or any other condition above those

indicated in the operational and programming specification of the device is not implied.

OPERATING RANGES

RATINGS

SYMBOL PARAMETER MIN MAX UNIT

VCC Supply voltage +4.75 +5.25 VDC

Tamb Operating free–air temperature 0 +75 °C

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 45

DC ELECTRICAL CHARACTERISTICS

0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V

LIMITS

SYMBOL PARAMETER TEST CONDITIONS MIN TYP1MAX UNIT

Input voltage2

VIL Low VCC = MIN 0.8 V

VIH High VCC = MAX 2.0 V

VIC Clamp VCC = MIN, IIN = –18mA –0.8 –1.5 V

Output voltage

VCC = MIN, VIN = VIH or VIL

VOL Low IOL = 24mA 0.5 V

VOH High IOH = –3.2 mA 2.4 V

Input current

VCC = MAX

IIL Low3VIN = 0.40V –250 µA

IIH High3VIN = 2.7V 25 µA

IIMaximum input current VIN = VCC = VCCMAX 100 µA

Output current

VCC = MAX

IOZH Output leakage VOUT = 2.7V 100 µA

IOZL Output leakage VOUT = 0.4V –100 µA

IOS Short circuit 4, 5VOUT = 0V –30 –90 mA

ICC VCC supply current VCC = MAX 160 180 mA

Capacitance6

CIN Input VCC = 5V

VOUT = 2.0V 8 pF

CBI/O (B) VOUT = 2V, f = 1MHz 8 pF

NOTES:

1. All typical values are at VCC = 5V, Tamb = +25°C.

2. All voltage values are with respect to network ground terminal.

3. Leakage current for bidirectional pins is the worst case of IIL and IOZL or IIH and IOZH.

4. Test one at a time.

5. Duration of short circuit should not exceed 1 second.

6. These parameters are not 100% tested but periodically sampled.

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 46

AC ELECTRICAL CHARACTERISTICS

R1 = 200Ω, R2 = 390Ω, 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V

LIMITS

SYMBOL PARAMETER FROM TO –7 D UNIT

MIN1TYP MAX MIN1MAX

Pulse Width

tCKH Clock High CK+ CK– 5 7 ns

tCKL Clock Low CK– CK+ 5 7 ns

tCKP Period CK+ CK+ 10 14 ns

Setup & Hold time

tIS Input Input or

feedback CK+ 7 9 ns

tIH Input CK+ Input or

feedback 0 0 ns

Propagation delay

tCKO Clock CK±Q±3 6.5 3 7.5 ns

tCKF Clock3CK±Q 3 6.5 ns

tPD Output (16L8, R6, R4)2I, B Output 3 7.5 3 10 ns

tOE1 Output enable4OE Output enable 3 8 3 10 ns

tOE2 Output enable4,5 I Output enable 3 10 3 10 ns

tOD1 Output disable4OE Output disable 3 8 3 10 ns

tOD2 Output disable4,5 I Output disable 3 10 3 10 ns

tSKW Output Q Q 1 1 ns

tPPR Power-Up Reset VCC+ Q+ 10 10 ns

Frequency (16R8, R6, R4)

No feedback 1/ (tCKL + tCKH)6100 71.4 MHz

fMAX Internal feedback 1/ (tIS + tCKF)690 64.5 MHz

External feedback 1/ (tIS + tCKO)674 60.6 MHz

*For definitions of the terms, please refer to the T iming/Frequency Definitions tables.

NOTES:

1. CL = 0pF while measuring minimum output delays.

2. tPD test conditions: CL = 50pF (with jig and scope capacitance), VIH = 3V, VIL = 0V, VOH = VOL = 1.5V.

3. tCKF was calculated from measured Internal fMAX.

4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and

closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output

voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.

5. Same function as tOE1 and tOD1, with the difference of using product term control.

6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the

frequency.

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 47

TEST LOAD CIRCUIT

+5V

NOTE:

C1 and C2 are to bypass VCC to GND.

VCC

GND

CLK

I0B0/O0

DUT

Bn/On

INPUTS

OUTPUT REGISTER SKEW

tSKW

1.5V

CLK

(REGISTERED OUTPUT)

Qn + 1

(REGISTERED OUTPUT)

CLOCK TO FEEDBACK PATH

CLK

tIS

tCKF

ÇÇÇÇÇ

ÇÇÇÇ

ÇÇÇÇÇÇÇ

1.5V 1.5V

1.5V1.5V1.5V

1.5V VT

1.5V1.5V

+3V

VOH

VOL

+3V

I, B

(INPUTS)

CLK

(REGISTERED OUTPUTS)

tIH tIS

tIS tCKH tCKL

tCKP

tCKO tOD1

tOE1

Flip-Flop Outputs

I, B

(INPUTS)

O, B

(COMBINATORIAL

OUTPUTS)

I, B

(OUTPUT

ENABLE)

tPD

tOE2 tOD2

1.5V

+1.5V+1.5V

+3V

VOH

VOL

+3V

Gate Outputs

1.5V 1.5V

1.5V1.5V

1.5V 1.5V 1.5V

VOH

VOL

+3V

VCC

4.5V

VCC

(REGISTERED

OUTPUTS)

I, B

(INPUTS)

CLK

tPPR

tCKO

tIH tIS

tIS tCKH tCKL

tIS+tCKF

Power–Up Reset

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 48

TIMING DIAGRAMS1, 2

NOTES:

1. Input pulse amplitude is 0V to 3V.

2. Input rise and fall times are 2.5ns.

TIMING DEFINITIONS

SYMBOL PARAMETER

tCKH Width of input clock pulse.

tCKL Interval between clock pulses.

tCKP Clock period.

tIS Required delay between

beginning of valid input and

positive transition of clock.

tIH Required delay between

positive transition of clock and

end of valid input data.

tCKF

Delay between positive

transition of clock and when

internal Q output of flip-flop

becomes valid.

tCKO

Delay between positive

transition of clock and when

outputs become valid (with

OE Low).

tOE1 Delay between beginning of

Output Enable Low and when

outputs become valid.

tOD1 Delay between beginning of

Output Enable High and when

outputs are in the Off-State.

tOE2

Delay between predefined

Output Enable High, and

when combinational outputs

become valid.

tOD2

Delay between predefined

Output Enable Low and when

combinational outputs are in

the Off-State.

tPPR

Delay between VCC (after

power-on) and when flip-flop

outputs become preset at “1”

(internal Q outputs at “0”).

tPD Propagation delay between

combinational inputs and

outputs.

FREQUENCY DEFINITIONS

fMAX No feedback: Determined by

the minimum clock period,

1/(tCKL + tCKH).

Internal feedback:

Determined by the internal

delay from flip-flop outputs

through the internal feedback

and array to the flip-flop

inputs, 1/(tIS + tCKF).

External feedback:

Determined by clock-to-output

delay and input setup time,

1/(tIS + tCKO).

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 49

OUTPUT REGISTER PRELOAD

VOH

REGISTERED I/O INPUT OUTPUT

ÉÉ

ÇÇ

VOL

VIH

VIL

VIHH

VIL

VIH

VIL

PIN 1 CLOCK

PIN 11 OE

tsu twtd

NOTE: td = tsu = tw = 100ns to 1000ns.

VIHH = 10.25V to 10.75V.

The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step

through the entire state-machine sequence. Each register is preloaded individually by following the steps given below.

Step 1. With VCC at 5V and Pin 1 at VIL, raise Pin 11 to VIHH.

Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.

Step 3. Pulse Pin 1, clocking in preload data.

Step 4. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage level at the output pin.

Pin number references for DIP package.

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 50

PROGRAMMING/SOFTWARE

Refer to Section 9 (

Development Software

) and Section 10 (

Third-Party Programmer/Software Support

) of this data handbook for additional

information.

SNAP RESOURCE SUMMARY DESIGNATIONS

I0 – I9

DINPAL7 NINPAL7

PROGRAMMABLE AND ARRAY

AND

NOUTPAL7

O0, O7

NOUTPAL7

B1 – B6

NINPAL7

DINPAL7

PLUS16L8

I0 – I7

DINPAL7 NINPAL7

PROGRAMMABLE AND ARRAY

AND

DFFPAL7

NINPAL7

DINPAL7

CLK

CKPAL7

NOEPAL7

DFFPAL7

NOUTPAL7NOUTPAL7

PLUS16R8

Philips Semiconductors Programmable Logic Devices Product specification

PLUS16R8D/-7 SERIES

PAL devices

16L8, 16R8, 16R6, 16R4

September 10, 1993 51

SNAP RESOURCE SUMMARY DESIGNATIONS (Continued)

I0 – I7

DINPAL7 NINPAL7

PROGRAMMABLE AND ARRAY

AND

B0, B7

NINPAL7

DINPAL7

CLK

CKPAL7

NOEPAL7

DFFPAL7

NOUTPAL7

Q1 – Q6

PLUS16R6

PLUS16R4

I0 – I7

DINPAL7 NINPAL7

PROGRAMMABLE AND ARRAY

AND

B0, B1, B6, B7

NINPAL7

DINPAL7

CLK

CKPAL7

NOEPAL7

DFFPAL7

NOUTPAL7

Q2 – Q5