FN2919 Rev 9.00 Page 1 of 13
April 26, 2007
FN2919
Rev 9.00
April 26, 2007
ICL7611, ICL7612
1.4MHz, Low Power CMOS Operational Amplifiers
DATASHEET
The ICL761X series is a family of CMOS operational
amplifiers. These devices provide the designer with high
performance operation at low supply voltages and selectable
quiescent currents, and are an ideal design tool when ultra
low input current and low power dissipation are desired.
The basic amplifier will operate at supply voltages ranging
from 1V to 8V, and may be operated from a single
Lithium cell.
A unique quiescent current programming pin allows setting
of standby current to 1mA, 100A, or 10A, with no external
components. This results in power consumption as low as
20W. The output swing ranges to within a few millivolts of
the supply voltages.
Of particular significance is the extremely low (1pA) input
current, input noise current of 0.01pA/Hz, and 1012 input
impedance. These features optimize performance in very
high source impedance applications.
The inputs are internally protected. Outputs are fully
protected against short circuits to ground or to either supply.
AC performance is excellent, with a slew rate of 1.6V/s, and
unity gain bandwidth of 1MHz at IQ = 1mA.
Because of the low power dissipation, junction temperature
rise and drift are quite low. Applications utilizing these
features may include stable instruments, extended life
designs, or high density packages.
Pinouts
ICL7611, ICL7612
(8 LD PDIP, 8 LD SOIC)
TOP VIEW
Features
• Wide Operating Voltage Range . . . . . . . . . . . 1V to 8V
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1012
• Programmable Power Consumption . . . . . Low as 20W
• Input Current Lower Than BIFETs . . . . . . . . . . . 1pA (Typ)
• Output Voltage Swing . . . . . . . . . . . . . . . . . . . V+ and V-
• Input Common Mode Voltage Range Greater Than Supply
Rails (ICL7612)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Portable Instruments
• Telephone Headsets
• Hearing Aid/Microphone Amplifiers
• Meter Amplifiers
• Medical Instruments
• High Impedance Buffers
BAL
-IN
+IN
V-
1
2
3
4
8
7
6
5
IQ SET
V+
OUT
BAL
+
-
ICL7611, ICL7612
FN2919 Rev 9.00 Page 2 of 13
April 26, 2007
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
ICL7611DCBA 7611 DCBA 0 to +70 8 Ld SOIC (150 mil) M8.15
ICL7611DCBAZ (Note) 7611 DCBAZ 0 to +70 8 Ld SOIC (150 mil) (Pb-free) M8.15
ICL7611DCBA-T 7611 DCBA 0 to +70 8 Ld SOIC (150 mil) Tape and Reel M8.15
ICL7611DCBAZ-T (Note) 7611 DCBAZ 0 to +70 8 Ld SOIC (150 mil) Tape and Reel (Pb-free) M8.15
ICL7611DCPA 7611 DCPA 0 to +70 8 Ld PDIP E8.3
ICL7611DCPAZ (Note) 7611 DCPAZ 0 to +70 8 Ld PDIP* (Pb-free) E8.3
ICL7612BCPA 7612 BCPA 0 to +70 8 Ld PDIP E8.3
ICL7612BCPAZ 7612 BCPAZ 0 to +70 8 Ld PDIP* (Pb-free) E8.3
ICL7612DCBA 7612 DCBA 0 to +70 8 Ld SOIC (150 mil) M8.15
ICL7612DCBA-T 7612 DCBA 0 to +70 8 Ld SOIC (150 mil) Tape and Reel M8.15
ICL7612DCBAZ (Note) 7612 DCBAZ 0 to +70 8 Ld SOIC (150 mil) (Pb-free) M8.15
ICL7612DCBAZ-T (Note) 7612 DCBAZ 0 to +70 8 Ld SOIC (150 mil) Tape and Reel (Pb-free) M8.15
ICL7612DCPA 7612 DCPA 0 to +70 8 Ld PDIP E8.3
ICL7612DCPAZ (Note) 7612 DCPAZ 0 to +70 8 Ld PDIP* (Pb-free) E8.3
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ICL7611, ICL7612
FN2919 Rev 9.00 Page 3 of 13
April 26, 2007
Absolute Maximum Ratings Thermal Information
Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3 to V+ +0.3V
Differential Input Voltage (Note 1) . . . . . . . . [(V+ +0.3) - (V- -0.3)]V
Duration of Output Short Circuit (Note 2). . . . . . . . . . . . . . Unlimited
Operating Conditions
Temperature Range
ICL761XC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Thermal Resistance (Typical, Note 3) JA (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operat i onal sections of this specification is not implied.
NOTES:
1. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time.
2. The outputs may be shorted to ground or to either supply, for VSUPPLY 10V. Care must be taken to insure that the dissipation rating is not
exceeded.
3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications VSUPPLY = 5V, Unless Otherwise Specified.
PARAMETER SYMBOL
TEST
CONDITIONS
TEMP
(°C)
ICL7612B ICL7611D, ICL7612D
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage VOS RS 100k+25 - - 5 - - 15 mV
Full - - 7 - - 20 mV
Temperature Coefficient of VOS VOS/TR
S 100k- - 15 - - 25 - V/°C
Input Offset Current IOS +25 - 0.5 30 - 0.5 30 pA
Full - - 300 - - 300 pA
Input Bias Current IBIAS +25 - 1.0 50 - 1.0 50 pA
Full - - 400 - - 400 pA
Common Mode Voltage Range
(ICL7611 Only)
VCMR IQ = 10A+25---4.4 - - V
IQ = 100A+25---4.2 - - V
IQ = 1mA +25 - - - 3.7 - - V
Extended Common Mode Voltage
Range (ICL7612 Only)
VCMR IQ = 10A+255.3 - - 5.3 - - V
IQ = 100A +25 +5.3,
-5.1
- - +5.3, -
5.1
--V
IQ = 1mA +25 +5.3, -
4.5
- - +5.3, -
4.5
--V
Output Voltage Swing VOUT IQ = 10A, RL = 1M+25 4.9 - - 4.9 - - V
Full 4.8 - - 4.8 - - V
IQ = 100A, RL = 100k+25 4.9 - - 4.9 - - V
Full 4.8 - - 4.8 - - V
IQ = 1mA, RL = 10k+25 4.5 - - 4.5 - - V
Full 4.3 - - 4.3 - - V
Large Signal Voltage Gain AVOL VO = 4.0V, RL=1M,
IQ = 10A
+25 80 104 - 80 104 - dB
Full 75 - - 75 - - dB
VO = 4.0V, RL=100k,
IQ=100A
+25 80 102 - 80 102 - dB
Full 75 - - 75 - - dB
VO = 4.0V, RL= 10k,
IQ = 1mA
+25 76 83 - 76 83 - dB
Full 72 - - 72 - - dB
ICL7611, ICL7612
FN2919 Rev 9.00 Page 4 of 13
April 26, 2007
Unity Gain Bandwidth GBW IQ = 10A +25 - 0.044 - - 0.044 - MHz
IQ = 100A +25 -0.48- -0.48-MHz
IQ = 1mA +25 - 1.4 - - 1.4 - MHz
Input Resistance RIN +25 - 1012 --10
12 -
Common Mode Rejection Ratio CMRR RS 100kIQ = 10A +25 70 96 - 70 96 - dB
RS 100kIQ = 100A +25 70 91 - 70 91 - dB
RS 100kIQ = 1mA +25 60 87 - 60 87 - dB
Power Supply Rejection Ratio
(VSUPPLY = 8V to 2V)
PSRR RS 100kIQ = 10A +25 80 94 - 80 94 - dB
RS 100k
IQ= 100A
+25 80 86 - 80 86 - dB
RS 100kIQ = 1mA +25 70 77 - 70 77 - dB
Input Referred Noise Voltage eNRS = 100, f = 1kHz +25 - 100 - - 100 - nV/Hz
Input Referred Noise Current iNRS = 100, f = 1kHz +25 - 0.01 - - 0.01 - pA/Hz
Supply Current (No Signal, No
Load)
ISUPPLY IQ SET = +5V, Low Bias +25 - 0.01 0.02 - 0.01 0.02 mA
IQ SET = 0V,
Medium Bias
+25 - 0.1 0.25 - 0.1 0.25 mA
IQ SET = -5V, High Bias +25 - 1.0 2.5 - 1.0 2.5 mA
Channel Separation VO1/VO2 AV = 100 +25 - 120 - - 120 - dB
Slew Rate
(AV = 1, CL = 100pF, VIN = 8VP-P)
SR IQ = 10A, RL = 1M+25 - 0.016 - - 0.016 - V/s
IQ = 100A, RL=100k+25 - 0.16 - - 0.16 - V/s
IQ = 1mA, RL = 10k+25 - 1.6 - - 1.6 - V/s
Rise Time
(VIN = 50mV, CL= 100pF)
trIQ = 10A, RL = 1M+25 - 20 - - 20 - s
IQ = 100A,
RL= 100k
+25 - 2 - - 2 - s
IQ = 1mA, RL = 10k+25 - 0.9 - - 0.9 - s
Overshoot Factor
(VIN = 50mV, CL= 100pF)
OS IQ = 10A, RL = 1M+25 - 5 - - 5 - %
IQ = 100A,
RL= 100k
+25 - 10 - - 10 - %
IQ = 1mA, RL = 10k+25 - 40 - - 40 - %
Electrical Specifications VSUPPLY = 5V, Unless Otherwise Specified. (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
TEMP
(°C)
ICL7612B ICL7611D, ICL7612D
UNITSMIN TYP MAX MIN TYP MAX
Electrical Specifications VSUPPLY = 1V, IQ = 10A, Unless Otherwise Specified.
PARAMETER SYMBOL
TEST
CONDITIONS TEMP (°C)
ICL7612B
UNITSMIN TYP MAX
Input Offset Voltage VOS RS 100k+25 - - 5 mV
Full - - 7 mV
Temperature Coefficient of VOS VOS/TR
S 100k--15-V/°C
Input Offset Current IOS +25 - 0.5 30 pA
Full - - 300 pA
Input Bias Current IBIAS +25 - 1.0 50 pA
Full - - 500 pA
Extended Common Mode
Voltage Range
VCMR +25 +0.6 to -1.1 - - V
ICL7611, ICL7612
FN2919 Rev 9.00 Page 5 of 13
April 26, 2007
Schematic Diagram
Output Voltage Swing VOUT RL = 1M+25 0.98 - - V
Full 0.96 - - V
Large Signal Voltage Gain AVOL VO = 0.1V, RL=1M+25 - 90 - dB
Full - 80 - dB
Unity Gain Bandwidth GBW +25 - 0.044 - MHz
Input Resistance RIN +25 - 1012 -
Common Mode Rejection Ratio CMRR RS 100k+25 - 80 - dB
Power Supply Rejection Ratio PSRR RS 100k+25 - 80 - dB
Input Referred Noise Voltage eNRS = 100, f = 1kHz +25 - 100 - nV/Hz
Input Referred Noise Current iNRS = 100, f = 1kHz +25 - 0.01 - pA/Hz
Supply Current ISUPPLY No Signal, No Load +25 - 6 15 A
Slew Rate SR AV = 1, CL = 100pF,
VIN = 0.2VP-P
, RL=1M
+25 - 0.016 - V/s
Rise Time trVIN = 50mV, CL= 100pF RL = 1M+25 - 20 - s
Overshoot Factor OS VIN = 50mV, CL= 100pF, RL = 1M+25 - 5 - %
Electrical Specifications VSUPPLY = 1V, IQ = 10A, Unless Otherwise Specified. (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS TEMP (°C)
ICL7612B
UNITSMIN TYP MAX
INPUT STAGE SETTING STAGE
IQ
OUTPUT STAGE
V+
OUTPUT
V-
QN11
QN10
QN9
CFF = 9pF
CC = 33pF
QP9
QP8
QP7
QP6
6.3V
QN7
QN6
QN5
QN4
V+ IQ SET
QN8
QN3
QN1 QN2
QP1 QP1
3k3k
BAL 100k
900k
QP5
QP4
QP3
+INPUT
-INPUT
V-
V-
V+
V+
BAL 6.3V
ICL7611, ICL7612
FN2919 Rev 9.00 Page 6 of 13
April 26, 2007
Application Information
Static Protection
All devices are static protected by the use of input diodes.
However, strong static fields should be avoided, as it is
possible for the strong fields to cause degraded diode
junction characteristics, which may result in increased input
leakage currents.
Latchup Avoidance
Junction-isolated CMOS circuits employ configurations which
produce a parasitic 4-layer (PNPN) structure. The 4-layer
structure has characteristics similar to an SCR, and under
certain circumstances may be triggered into a low impedance
state resulting in excessive supply current. To avoid this
condition, no voltage greater than 0.3V beyond the supply
rails may be applied to any pin. In general, the op amp
supplies must be established simultaneously with, or before
any input signals are applied. If this is not possible, the drive
circuits must limit input current flow to 2mA to prevent latchup.
Choosing the Proper IQ
The ICL7611 and ICL7612 have a similar IQ set-up scheme,
which allows the amplifier to be set to nominal quiescent
currents of 10A, 100A or 1mA. These current settings
change only very slightly over the entire supply voltage
range. The ICL7611 and ICL7612 have an external IQ
control terminal, permitting user selection of quiescent
current. To set the IQ connect the IQ terminal as follows:
IQ = 10A - IQ pin to V+
IQ = 100A - IQ pin to ground. If this is not possible, any
voltage from V+ - 0.8 to V- +0.8 can be used.
IQ = 1mA - IQ pin to V-
NOTE: The output current available is a function of the quiescent
current setting. For maximum peak-to-peak output voltage swings
into low impedance loads, IQ of 1mA should be selected.
Output Stage and Load Driving Considerations
Each amplifiers’ quiescent current flows primarily in the
output stage. This is approximately 70% of the IQ settings.
This allows output swings to almost the supply rails for
output loads of 1M, 100k, and 10k, using the output
stage in a highly linear class A mode. In this mode,
crossover distortion is avoided and the voltage gain is
maximized. However, the output stage can also be operated
in Class AB for higher output currents. (See graphs under
Typical Operating Characteristics). During the transition from
Class A to Class B operation, the output transfer
characteristic is non-linear and the voltage gain decreases.
Input Offset Nulling
Offset nulling may be achieved by connecting a 25k pot
between the BAL terminals with the wiper connected to V+.
At quiescent currents of 1mA and 100A the nulling range
provided is adequate for all VOS selections; however with
IQ=10A, nulling may not be possible with higher values
of VOS.
Frequency Compensation
The ICL7611 and ICL7612 are internally compensated, and
are stable for closed loop gains as low as unity with
capacitive loads up to 100pF.
Extended Common Mode Input Range
The ICL7612 incorporates additional processing which
allows the input CMVR to exceed each power supply rail by
0.1V for applications where VSUPP 1.5V. For those
applications where VSUPP 1.5V the input CMVR is limited
in the positive direction, but may exceed the negative supply
rail by 0.1V in the negative direction (e.g., for VSUPPLY =1V,
the input CMVR would be +0.6V to -1.1V).
Operation At VSUPPLY = 1V
Operation at VSUPPLY = 1V is guaranteed at IQ = 10A for
A and B grades only.
Output swings to within a few millivolts of the supply rails are
achievable for RL 1M. Guaranteed input CMVR is 0.6V
minimum and typically +0.9V to -0.7V at VSUPPLY = 1V. For
applications where greater common mode range is
desirable, refer to the description of ICL7612 above.
Typical Applications
The user is cautioned that, due to extremely high input
impedances, care must be exercised in layout, construction,
board cleanliness, and supply filtering to avoid hum and
noise pickup.
Note that in no case is IQ shown. The value of IQ must be
chosen by the designer with regard to frequency response
and power dissipation.
ICL7612
+
-
VIN
VOUT
RL 10k
FIGURE 1. SIMPLE FOLLOWER (NOTE 4)
ICL7612
+
-
VIN
VOUT
100k
+5 +5
1M
TO CMOS OR
LPTTL LOGIC
NOTE:
4. By using the ICL7612 in this application, the circuit will follow rail
to rail inputs.
FIGURE 2. LEVEL DETECTOR (NOTE 4)
ICL7611, ICL7612
FN2919 Rev 9.00 Page 7 of 13
April 26, 2007
VOUT
1F
ICL7611
+
-
+
NOTE: Low leakage currents allow integration times up to several
hours.
FIGURE 3. PHOTOCURRENT INTEGRATOR
ICL7611
+
-
1M
ICL7611
+
-
1M
DUTY CYCLE
V- V+
680k
1M
WAVEFORM GENERATOR
NOTE: Since the output range swings exactly from rail to rail, frequency
and duty cycle are virtually independent of power supply variations.
FIGURE 4. PRECISE TRIANGLE/SQUARE WAVE
GENERATOR
FIGURE 5. AVERAGING AC TO DC CONVERTER FOR A/D
CONVERTERS SUCH AS ICL7106, ICL7107,
ICL7109, ICL7116, ICL7117
FIGURE 6. BURN-IN AND LIFE TEST CIRCUIT
FIGURE 7. VOS NULL CIRCUIT
ICL7611
+
-
10F
ICL7611
+
-
20k
VIN
20k
VOH
VOL
1M
2.2M
COMMON
10k0.5F
1.8k = 5%
SCALE
ADJUST
TO
SUCCEED-
ING
INPUT
STAGE
+
-V-
OUT
V+
IQ
V+
-8V
+8V
TA = +125°C
VOUT
25k
V+
-
+BAL
VIN BAL
ICL7611, ICL7612
FN2919 Rev 9.00 Page 8 of 13
April 26, 2007
FIGURE 8. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER
ICL7611
+
-
ICL7611
+
-
INPUT
30k 160k
0.2F0.2F
0.2F
0.2F0.1F0.1F
51k100k680k
360k
360k
1M
1M
OUTPUT
(NOTE 5)
(NOTE 5)
NOTES:
5. Note that small capacitors (25pF to 50pF) may be needed for stability in some cases.
6. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fC = 10Hz, AVCL = 4,
Passband ripple = 0.1dB.
Typical Performance Curves
FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY
VOLTAGE
FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR
TEMPERATURE
FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 12. LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN
vs FREE-AIR TEMPERATURE
10k
1k
100
10
1
SUPPLY CURRENT (A)
0 2 4 6 810121416
SUPPLY VOLTAGE (V)
TA = +25°C
NO LOAD
NO SIGNAL
IQ = 1mA
IQ = 100A
IQ = 1mAIQ = 10A
104
103
102
10
1
SUPPLY CURRENT (A)
-50 -25 0 25 50 75 100 125
FREE-AIR TEMPERATURE (°C)
V+ - V- = 10V
NO LOAD
NO SIGNAL
IQ = 1mA
IQ = 100A
IQ = 10A
-50 -25 0 25 50 75 100 125
FREE-AIR TEMPERATURE (°C)
1000
100
10
1.0
0.1
INPUT BIAS CURRENT (pA)
VS = 5V
-50 -25 0 25 50 75 100 125
FREE-AIR TEMPERATURE (°C)
-75
1000
100
10
1
DIFFERENTIAL VOLTAGE GAIN (kV/V)
VSUPP = 10V
VOUT = 8V
RL = 100k
IQ = 100A
RL = 10k
IQ = 1mA
RL = 1M
IQ = 10A
ICL7611, ICL7612
FN2919 Rev 9.00 Page 9 of 13
April 26, 2007
FIGURE 13. LARGE SIGNAL FREQUENCY RESPONSE FIGURE 14. COMMON MODE REJECTION RATIO vs FREE-AIR
TEMPERATURE
FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREE-AIR
TEMPERATURE
FIGURE 16. EQUIVALENT INPUT NOISE VOLTAGE vs
FREQUENCY
FIGURE 17. OUTPUT VOLTAGE vs FREQUENCY FIGURE 18. OUTPUT VOLTAGE vs FREQUENCY
Typical Performance Curves (Continued)
107
106
104
103
102
10
1
105
DIFFERENTIAL VOLTAGE GAIN (V/V)
0.1 1.0 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
TA = +25°C
VSUPP = 15V
0
45
90
135
180
PHASE SHIFT (°)
IQ = 1mA
IQ = 100A
PHASE SHIFT
(IQ = 1mA)
IQ = 10A
-50 -25 0 25 50 75 100 125
FREE-AIR TEMPERATURE (°C)
-75
105
100
95
90
85
80
75
70
COMMON MODE REJECTION RATIO (dB)
VSUPP = 10V
IQ = 10A
IQ = 100A
IQ = 1mA
100
95
90
85
80
75
70
65
SUPPLY VOLTAGE REJECTION RATIO (dB)
-50 -25 0 25 50 75 100 125-75
FREE-AIR TEMPERATURE (°C)
IQ = 1mA
IQ = 100A
IQ = 10A
VSUPP = 10V
600
500
400
300
200
100
0
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)
10 100 1k 10k 100k
FREQUENCY (Hz)
TA = +25°C
3V VSUPP 16V
16
14
12
10
8
6
4
2
0
MAXIMUM OUTPUT VOLTAGE (VP-P)
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
VSUPP
=8V
VSUPP
=5V
VSUPP
=2V
IQ = 1mA
IQ = 10A
IQ = 100A
TA = +25°C
VSUPP = 10V
IQ = 1mA
16
14
12
10
8
6
4
2
0
MAXIMUM OUTPUT VOLTAGE (VP-P)
10k 100k 1M 10M
FREQUENCY (Hz)
TA = -55°C
TA = +25°C
TA = +125°C
ICL7611, ICL7612
FN2919 Rev 9.00 Page 10 of 13
April 26, 2007
FIGURE 19. OUTPUT VOLTAGE vs SUPPLY VOLTAGE FIGURE 20. OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
FIGURE 21. OUTPUT SOURCE CURRENT vs SUPPLY VOLTAGE FIGURE 22. OUTPUT SINK CURRENT vs SUPPLY VOLTAGE
FIGURE 23. OUTPUT VOLTAGE vs LOAD RESISTANCE FIGURE 24. VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE (IQ = 1mA)
Typical Performance Curves (Continued)
16
14
12
10
8
6
4
MAXIMUM OUTPUT VOLTAGE (VP-P)
2 4 6 8 10 12 14 16
SUPPLY VOLTAGE (V)
TA = +25°C
RL = 100k - 1M
RL = 10k
12
10
8
6
4
2
0
MAXIMUM OUTPUT VOLTAGE (VP-P)
-75 -50 -25 0 25 50 75 100 125
FREE-AIR TEMPERATURE (°C)
RL = 100k
RL = 10k
RL = 2k
VSUPP = 10V
IQ = 1mA
40
30
20
10
0
MAXIMUM OUTPUT SOURCE CURRENT (mA)
0246810121416
SUPPLY VOLTAGE (V)
IQ = 1mA
0.01
0.1
1.0
10
MAXIMUM OUTPUT SINK CURRENT (mA)
0246810121416
SUPPLY VOLTAGE (V)
IQ = 10A
IQ = 100A
IQ = 1mA
16
14
12
10
8
6
4
2
0
MAXIMUM OUTPUT VOLTAGE (VP-P)
0.1 1.0 10 100
LOAD RESISTANCE (k)
V+ - V- = 10V
IQ = 1mA
TA = +25°C
8
6
4
2
0
-2
-4
-6
INPUT AND OUTPUT VOLTAGE (V)
024681012
TIME (s)
TA = +25°C, VSUPP = 10V
RL = 10k, CL = 100pF
OUTPUT
INPUT
ICL7611, ICL7612
FN2919 Rev 9.00 Page 11 of 13
April 26, 2007
FIGURE 25. VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE (IQ = 100A)
FIGURE 26. VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE (IQ = 10A)
Typical Performance Curves (Continued)
8
6
4
2
0
-2
-4
-6
INPUT AND OUTPUT VOLTAGE (V)
020406080100120
TIME (s)
TA = +25°C, VSUPP = 10V
RL = 100k, CL = 100pF
OUTPUT
INPUT
8
6
4
2
0
-2
-4
-6
INPUT AND OUTPUT VOLTAGE (V)
0 200 400 600 800 1000 1200
TIME (s)
TA = +25°C, VSUPP = 10V
RL = 1M, CL = 100pF
OUTPUT
INPUT
ICL7611, ICL7612
FN2919 Rev 9.00 Page 12 of 13
April 26, 2007
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
0° 8° 0° 8° -
Rev. 1 6/05
FN2919 Rev 9.00 Page 13 of 13
April 26, 2007
ICL7611, ICL7612
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
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For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2004-2007. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA
-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93