Description
The CXP921064A is a CMOS 16-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, I2C bus interface, timer, real-time pulse
generator, clock prescaler, remote control receive
circuit, and as well as basic configurations like a 16-
bit CPU, ROM, RAM, and I/O port.
This LSI also provides the sleep/stop functions that
enable lower power consumption.
Features
•An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms,
multiplication and division instructions
•Instruction sets for C language and RTOS
— Highly quadratic instruction system, general-
purpose register of eigth 16-bit ×16-bank
configuration
•Minimum instruction cycle 100ns at 20MHz operation (2.7 to 3.3V)
61µs at 32kMHz operation (2.2 to 3.3V)
•Incorporated ROM capacity 256K bytes
•Incorporated RAM capacity 10K bytes
•Peripheral functions
— A/D converter 8-bit 12 analog input, 2 channels successive approximation system,
automatic scanning function, (Conversion time: 3.4µs at 20MHz)
— Serial interface 128 -byte buffer RAM, 3 channels
8-stage FIFO, 1 channel (supports special mode master/slave)
—I
2C bus interface 64-byte buffer RAM , 2 channels
(supports master/slave and automatic transfer mode)
— Timers 8-bit timer/counter, 2 channels (with timing output)
16-bit timer, 3 channels
— Real-time pulse generator 5-bit output, 1 channel (2-stage FIFO)
— Clock prescaler
— Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO
•Interruption 30 factors, 30 vectors, multi-interruption and priority selection possible
•Standby mode Sleep/stop
•Package 100-pin plastic QFP/LQFP
104-pin plastic LFLGA
•Piggy/evaluation chip CXP921000A
•
FLASH EEPROM incorporated version
CXP921F064A
Structure
Silicon gate CMOS IC
CMOS 16-bit Single Chip Microcomputer
– 1 – E99707D33
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP921064A
100 pin QFP (Plastic) 100 pin LQFP (Plastic)
104 pin LFLGA (Plastic)
– 2 –
CXP921064A
Block Diagram
PA0 to PA7
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE7
PF0 to PF3
PF4 to PF7
PG0 to PG7
PH6, PH7
PH0 to PH5
PI0 to PI7
PJ0 to PJ7
CS0
SO0
SI0
SCK0
SI1
CS1
SCK1
SO1
CS2
SO2
SI2
SCK2
TO
TMO
EC
RMC
PORT A
BUFFER
RAM
I2C BUS
INTERFACE
UNIT (CH1)
BUFFER
RAM
I2C BUS
INTERFACE
UNIT (CH0)
FIFO
SERIAL
INTERFACE
UNIT (CH3)
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH2)
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH1)
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH0)
8
8
PORT B
8
PORT C
8
PORT D
8
PORT E
8
PORT F
4
4
2
8
6
PORT G
8
PORT HPORT IPORT J
8
SPC950
CPU CORE
CLOCK GENERATOR/
SYSTEM CONTROLLER
ROM
256K BYTES
RAM
10K BYTES
PRESCALER/
TIME-BASE TIMER
SO3
SI3
SCK3
SCL0
SDA0
SCL1
SDA1
INT0
to INT7
KS0
to KS15
NMI
RST
TEX
TX
EXTAL
XTAL
VDD
VSS
5
A/D
CONVERTER
(CH1)
A/D
CONVERTER
(CH0)
12 12
REMOCON FIFO
16-BIT TIMER (CH2)
16-BIT TIMER (CH1)
16-BIT TIMER (CH0)
INTERRUPT CONTROLLER
AN0
to AN11
AN12
to AN23
RTO0
to RTO4
AVREF0
AVSS
AVREF1
AVDD
XOUT
8-BIT TIMER/COUNTER (CH0)
8-BIT TIMER (CH1)
3
2
2
2
REALTIME PULSE
GENERATOR
FIFO
CLOCK PRESCALER
16
– 3 –
CXP921064A
Pin Assignment 1 (Top View) 100-pin QFP package
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81828384858687888990919293949596979899
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PE7
PF0
PF1/EC
PF2/CS0
PF3/SI0
PF4/SO0
PF5/SCK0
PF6/TO
PF7/TMO
RST
VSS
XTAL
EXTAL
VDD
PG0/CS1
PG1/SI1
PG2/SO1
PG3/SCK1
PG4/CS2
PG5/SI2
PJ0/AN4/KS8
AVDD
AVREF1
AVREF0
AVss
AN3
AN2
AN1
PI7/AN0
PI6/NMI
PI5/INT7
PI4/INT6
PI3/INT5
PI2/INT4
PI1/INT3
PI0/INT2
PH7/INT1
PH6/INT0
PH5/XOUT
PH4/RTO4
PH3/RTO3
PH2/RTO2
PH1/RTO1
PH0/RTO0
Vss
51
52
53
54
55
56
TX
TEX
VDD
PG7/SCK2
PG6/SO2
PB2/AN22
PB3/AN23
PB4/SI3
PB5/SO3
PB6/SCK3
PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PC4
PC5
PC6
PC7
VSS
PD0/KS0
PD1/KS1
PD2/KS2
PD3/KS3
PD4/KS4
PD5/KS5
PD6/KS6
PD7/KS7
PE0
25
26
27
28
29
PE1
PE2
PE3
PE4
PE5
30
PE6
PB1/AN21
PB0/AN20
PA7/AN19
PA6/AN18
PA5/AN17
PA4/AN16
PA3/AN15
PA2/AN14
PA1/AN13
PA0/AN12
VSS
VDD
NC
PJ7/AN11/KS15
PJ6/AN10/KS14
PJ5/AN9/KS13
PJ4/AN8/KS12
PJ3/AN7/KS11
PJ2/AN6/KS10
PJ1/AN5/KS9
100
Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 15, 41, 56 and 90) must be connected to GND.
3. VDD (Pins 44, 53 and 89) must be connected to VDD.
– 4 –
CXP921064A
Pin Assignment 2 (Top View) 100-pin LQFP package
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81828384858687888990919293949596979899
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PE7
PF0
PF1/EC
PF2/CS0
PF3/SI0
PF4/SO0
PF5/SCK0
PF6/TO
PF7/TMO
RST
VSS
XTAL
EXTAL
VDD
PG0/CS1
PG1/SI1
PG2/SO1
PG3/SCK1
PG4/CS2
PG5/SI2 PJ0/AN4/KS8
AVDD
AVREF1
AVREF0
AVss
AN3
AN2
AN1
PI7/AN0
PI6/NMI
PI5/INT7
PI4/INT6
PI3/INT5
PI2/INT4
PI1/INT3
PI0/INT2
PH7/INT1
PH6/INT0
PH5/XOUT
PH4/RTO4
PH3/RTO3
PH2/RTO2
PH1/RTO1
PH0/RTO0
Vss
51
52
53
54
55
56
TX
TEX
VDD
PB4/SI3
PB5/SO3
PB6/SCK3
PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PC4
PC5
PC6
PC7
VSS
PD0/KS0
PD1/KS1
PD2/KS2
PD3/KS3
PD4/KS4
PD5/KS5
PD6/KS6
PD7/KS7
PE0
25
26 27 28 29
PE1
PE2
PE3
30
PE4
PE5
PE6 PB1/AN21
PB2/AN22
PB3/AN23
PB0/AN20
PA7/AN19
PA6/AN18
PA5/AN17
PA4/AN16
PA3/AN15
PA2/AN14
PA1/AN13
PA0/AN12
VSS
VDD
NC
PJ7/AN11/KS15
PJ6/AN10/KS14
PJ5/AN9/KS13
PJ4/AN8/KS12
PJ3/AN7/KS11
PJ2/AN6/KS10
PJ1/AN5/KS9
100
PG7/SCK2
PG6/SO2
Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 13, 39, 54 and 88) must be connected to GND.
3. VDD (Pins 42, 51 and 87) must be connected to VDD.
– 5 –
CXP921064A
Pin Assignment 3 (Top View) 104-pin LFLGA package
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15 16 17
18 19 20
21 22
23 24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52 53
54 55
56 57 58
59 60 61
62 6364
656667
686970
7172
7374
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
12345678910111213
PB1 PA7 PA4 PA1 VSS NC PJ5 PJ2 PJ0
AA
PB2 PB0 PA5 PA2 VDD PJ7 PJ4 PJ1 AVDD
BB
PB6 PB5 PB3 PA6 PA3 PA0 PJ6 PJ3 AVREF1 AVSS AN3
CC
PC0 PB7 PB4 AVREF0 AN2 AN1
DD
PC3 PC2 PC1 PI7 PI6 PI5
EE
PC6 PC5 PC4 PI4 PI3 PI2
FF
VSS PC7 PD0 PI1 PH7 PI0
GG
PD1 PD2 PD3 PH4 PH5 PH6
HH
PD4 PD5 PD6 PH1 PH2 PH3
JJ
PD7 PE0 PE3 VDD VSS PH0
KK
PE1 PE2 PE4 PF1 PF4 VSS VDD PG2 PG7 TEX TX
LL
PE5 PE7 PF2 PF5 PF7 EXTAL PG1 PG4 PG6
MM
PE6 PF0 PF3 PF6 RST XTAL PG0 PG3 PG5
NN
12345678910111213
Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 13, 39, 54 and 88) must be connected to GND.
3. VDD (Pins 42, 51 and 87) must be connected to VDD.
– 6 –
CXP921064A
Pin Functions
Symbol I/O Functions
PA0/AN12
to PA7/AN19 Output / Input
(Port A)
8-bit output port.
(8 pins)
Output / Input
Output / Input
Output / Output
Output / I/O
Output / Input
I/O / I/O
I/O / I/O
I/O / I/O
I/O / I/O
I/O
(Port B)
8-bit output port.
(8 pins)
PB0/AN20
to PB3/AN23
PB4/SI3
PB5/SO3
PB6/SCK3
PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PC4 to PC7
PF0
PF1/EC
PF2/CS0
PF3/SI0
PF4/SO0
PF5/SCK0
PF6/TO
PF7/TMO
Input
Input / Input
Input / Input
Input / Input
Output / Output
Output / I/O
Output / Output
Output / Output
(Port C)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not
through program in 1-bit units.
(8 pins)
(Port D)
8-bit I/O port.
I/O can be specified in 1-bit units.
Can drive 5mA sink current
(VDD = 2.7 to 3.3V).
(8 pins)
PD0/KS0
to PD7/KS7
PE0 to PE7
I/O / Input
(Port E)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)
(Port F)
8-bit port.
Lower 4 bits are for input;
upper 4 bits are for output.
(8 pins)
I/O
Standby release input function can be
specified in 1-bit units.
(8 pins)
Analog input for A/D converter.
(12 pins)
Serial data (CH3) input.
Serial data (CH3) output.
Serial clock (CH3) I/O.
Remote control receive circuit input.
Data I/O of I2C bus interface (CH0).
Clock I/O of I2C bus interface (CH0).
Data I/O of I2C bus interface (CH1).
Clock I/O of I2C bus interface (CH1).
External event input for 8-bit
timer/counter.
Serial chip select (CH0) input.
Serial data (CH0) input.
Serial data (CH0) output.
Serial clock (CH0) I/O.
8-bit timer/counter output.
16-bit timer (CH0) output.
– 7 –
CXP921064A
Symbol I/O Functions
(Port G)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)
(Port J)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)
Standby release input
function can be specified in
1-bit units.
(8 pins)
I/O / Input
I/O / Input
I/O / Output
I/O / I/O
I/O / Input
I/O / Input
I/O / Output
I/O / Output
Output / Output
Output / Output
Input / Input
Input / Input
Input / Input
Input / Input
Input
I/O / Input /
Input
PG0/CS1
PG1/SI1
PG2/SO1
PG3/SCK1
PG4/CS2
PG5/SI2
PG6/SO2
PG7/SCK2
PH0/RTO0
to PH4/RTO4
PH5/XOUT
PH6/INT0
to PH7/INT1
PI0/INT2
to PI5/INT7
PI6/NMI
PI7/AN0
AN1 to AN3
PJ0/AN4/
KS8
to PJ7/AN11/
KS15
RST
AVDD
AVREF0
AVREF1
AVSS
VDD
VSS
NC
Input
Input
Input
(Port H)
8-bit port.
Lower 6 bits are for output;
upper 2 bits are for input.
(8 pins)
(Port I)
8-bit input port.
(8 pins)
Serial chip select (CH1) input.
Serial data (CH1) input.
Serial data (CH1) output.
Serial clock (CH1) I/O.
Serial chip select (CH2) input.
Serial data (CH2) input.
Serial data (CH2) output.
Serial clock (CH2) output.
Real-time pulse generator output.
(5 pins)
Clock output for clock prescaler buzzer.
External interrupt input.
(8 pins)
Non-maskable external interrupt input.
Analog input for A/D converter.
(12 pins)
Connects a crystal for main clock oscillation.
(When the clock is supplied externally, input it to EXTAL and input an
opposite phase clock to XTAL.)
Connects a crystal for sub clock oscillation.
(When the clock is supplied externally, input it to TEX and input an
opposite phase clock to TX.)
System reset. Active at "L" level.
Positive power supply for A/D converter.
Reference voltage input for A/D converter (CH0).
Reference voltage input for A/D converter (CH1).
GND for A/D converter.
Positive power supply.
(Connect all three VDD pins to positive power supply.)
GND
(Connect all four Vss pins to GND.)
NC.
(NC is used for FLASH EEPROM incorporated version.)
EXTAL
XTAL
TEX
TX
Input
Input
– 8 –
CXP921064A
I/O Circuit Format for Pins
Pin Circuit format After a reset
PA0/AN12
to PA7/AN19 Hi-Z
Internal data bus
Input protection
circuit
IP
RD
PA register
"0" after a reset
PASL register
"0" after a reset
A/D converter
Input multiplexer
PB0/AN20
to PB3/AN23 Hi-Z
Internal data bus
IP
RD
PB register
"0" after a reset
PBSL register
"0" after a reset
A/D converter
Input multiplexer
PB4/SI3
PB7/RMC Hi-Z
Internal data bus
IP
RD
PB register
"0" after a reset
PBSL register
"0" after a reset
SI3, RMC
CMOS Schmitt input
– 9 –
CXP921064A
PB5/SO3 Hi-Z
PB register
"0" after a reset
SO3
MPX
PBSL register
"0" after a reset
SO3 output enable
Internal data bus
RD
0
1
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
Hi-Z
PC register
Underfined after a reset
PULC register
"0" after a reset
SDA0, SCL0, SDA1, SCL1
PCSL register
"0" after a reset
PCD register
"0" after a reset
SDA0, SCL0
SDA1, SCL1 CMOS Schmitt input
∗ Pull-up transistor
approximately 15kΩ (VDD = 2.7 to 3.3V)
IP
MPX
Internal data bus
RD
∗
1
0
PB6/SCK3 Hi-Z
PB register
"0" after a reset
SCK3
MPX
PBSL register
"0" after a reset
SCK3 output enable
SCK3
Internal data bus
RD
CMOS Schmitt input
IP
0
1
Pin Circuit format After a reset
– 10 –
CXP921064A
PD0/KS0
to PD7/KS7 Hi-Z
PE0 to PE7 Hi-Z
IP
PD register
Underfined after a reset
PDD register
"0" after a reset
∗ Large current drive
5mA (VDD = 2.7 to 3.3V)
Internal data bus
Standby release
RD
∗
IP
PE register
Underfined after a reset
PED register
"0" after a reset
Internal data bus
RD
Pin Circuit format After a reset
PC4 to PC7 Hi-Z
PC register
Underfined after a reset
PULC register
"0" after a reset
PCD register
"0" after a reset
∗ Pull-up transistor
approximately 15kΩ (VDD = 2.7 to 3.3V)
IP
Internal data bus
RD
∗
– 11 –
CXP921064A
Hi-Z
PF0
Internal data bus
RD
IP
Hi-Z
PF1/EC
Internal data bus
EC CMOS Schmitt input
RD
IP
Hi-Z
PF2/CS0
PF3/SI0
Internal data bus
CS0, SI0
CMOS Schmitt input
RD
IP
PFSL register
"0" after a reset
PF4/SO0 Hi-Z
PF register
"0" after a reset
SO0
MPX
PFSL register
"0" after a reset
SO0 output enable
PF register write
Reset
Internal
data bus
RD
QS
R
1
0
PF5/SCK0 Hi-Z
PF register
"0" after a reset
SCK0
MPX
PFSL register
"0" after a reset
SCK0 output enable
PF register write
Reset
SCK0
Internal
data bus
RD
CMOS Schmitt input
IP
QS
R
1
0
Pin Circuit format After a reset
– 12 –
CXP921064A
PG2/SO1
PG3/SCK1
PG6/SO2
PG7/SCK2
Hi-Z
PG register
Underfined after a reset
PGSL register
"0" after a reset
MPX
PGD register
"0" after a reset
SCK1
Internal
data bus
RD
SO1, SCK1
SO2, SCK2 output enable
SO1, SCK1
SO2, SCK2
CMOS Schmitt input
(PG3 only)
IP
1
0
PG0/CS1
PG1/SI1
PG4/CS2
PG5/SI2
Hi-Z
IP
PG register
Underfined after a reset
PGD register
"0" after a reset
PGSL register
"0" after a reset
Internal
data bus
CS1, SI1
CS2, SI2
RD
CMOS Schmitt input
Pin Circuit format After a reset
PF6/TO
PF7/TMO
"H" level
("H" level at ON
resistance of pull-
up transistor during
a reset.)
PF register
"0" after a reset
TO, TMO
MPX
PFSL register
"0" after a reset
PF register write
Reset
Internal
data bus
RD
QS
R
∗ Pull-up transistor
approximately 150kΩ (VDD = 2.7 to 3.3V)
∗
1
0
– 13 –
CXP921064A
PH0/RTO0
to PH4/RTO4 Hi-Z
PH register
Underfined after a reset
RTO0 to RTO4
PH register write
Reset
QS
R
Internal
data bus
RD
PH5/XOUT Hi-Z
PH register write
Reset
QS
R
Internal
data bus
RD
MPX
XOUT 1
0
PH register
Underfined after a reset
PHSL register
"0" after a reset
PH6/INT0
to PH7/INT1 Hi-Z
Internal data bus
Interrupt circuit CMOS Schmitt input
RD
IP
PI0/INT2
to PI5/INT7 Hi-Z
Internal data bus
Interrupt circuit CMOS Schmitt input
RD
IP
Pin Circuit format After a reset
– 14 –
CXP921064A
PJ0/AN4/
KS8
to PJ7/AN11/
KS15
Hi-Z
IP
PJ register
Underfined after a reset
PJD register
"0" after a reset
PJSL register
"0" after a reset
Internal data bus
Standby release
A/D converter
RD
Input multiplexer
Pin Circuit format After a reset
PI6/NMI Hi-Z
Internal data bus
Interrupt circuit (NMI)
CMOS Schmitt input
RD
IP
PISL register
"0" after a reset
PI7/AN0 Hi-Z
Internal data bus
A/D converter
RD
IP
PISL register
"0" after a reset
Input multiplexer
AN1 to AN3 Hi-Z
IP
A/D converter
Input multiplexer
– 15 –
CXP921064A
EXTAL
XTAL Oscillation
• Diagram shows circuit
configuration during
oscillation.
• Feedback registor is
removed during stop
mode, and XTAL is
driven at "H" level.
EXTAL
XTAL
Oscillation stop control
IP
Timing generator
TEX
TX Oscillation
Oscillation stop control
Timing generator,
clock prescaler
• TX is driver at Hi-Z
during stop.
TEX
TX
IP
IP
"L" level
(during a reset)
RST
IP
CMOS Schmitt input
∗ Pull-up transistor
approximately 30kΩ (VDD = 2.7 to 3.3V)
∗
Mask option
OP
Pin Circuit format After a reset
– 16 –
CXP921064A
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
VDD
AVDD
AVREF
AVSS
VIN
VOUT
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
–0.3 to +4.6
AVSS to +4.6∗1
AVSS to +4.6∗1
–0.3 to +0.3
–0.3 to +4.6∗2
–0.3 to +4.6∗2
–5
–50
15
20
130
–20 to +75
–55 to +150
600
380
500
V
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
mW
mW
Output (value per pin)
Total for all output pins
All pins excluding large current output
pins (value per pin)
Large current output pins∗3
(value per pin)
Total for all output pins
QFP-100P-L01
LQFP-100P-L01
LFLGA-104P-02
Symbol Rating Unit Remarks
∗1AVDD and AVREF must be the same voltage with VDD.
∗2VIN and VOUT must not exceed VDD + 0.3V.
∗3The large current drive transistor is N-ch transistor of PD.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
(VSS = 0V reference)
– 17 –
CXP921064A
Item
Supply voltage
VDD
AVDD
AVREF
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr
High level input
voltage
Low level input
voltage
Symbol Min.
2.7
2.2
2.2
2.0
2.7
2.7
0.7VDD
0.8VDD
0.7VDD
0
0
–0.3
–20
3.3
3.3
3.3
3.3
3.3
3.3
VDD
VDD
VDD+0.3
0.2VDD
0.2VDD
0.3VDD
+75
V
V
V
V
V
V
V
V
V
V
V
V
°C
Guaranteed operation range with TEX clock
Guaranteed operation range for clock mode
Guaranteed data hold range during stop mode
∗1
∗1
∗2
CMOS Schmitt input∗3
EXTAL, TEX
∗2
CMOS Schmitt input∗3
EXTAL, TEX
Max. Unit Remarks
∗1AVDD and AVREF must be the same voltage with VDD.
∗2PC4 to PC7, PD, PE, PF0, PG2, PG6, PI7, PJ for normal input port.
∗3PB4, PB6, PB7, PC0 to PC3, PF1 to PF3, PF5, PG0, PG1, PG3 to PG5, PG7, PH6, PH7, PI0 to PI6, RST.
(Vss = 0V reference)
Recommended Operating Conditions
Operating temperature
– 18 –
CXP921064A
Electrical Characteristics
DC Characteristics (Topr = –20 to +75°C, Vss = 0V reference)
High level
output
voltage
VOH
VOL
IIHE
IILE
IILR
IIL
Low level
output
voltage
PA, PB, PD, PE,
PF4 to PF7, PG,
PH0 to PH5, PJ
PC
RST∗1
PC∗2
PA, PB,
PD to PG,
PH6, PH7,
PI, PJ,
AN1 to AN3,
TEX, RST∗1
Item Symbol Pins Conditions Min.
Supply
current∗3
IDD1∗4
IIZ
Input
current
Typ. Max. Unit
VDD = 3.0 ± 0.3V, 20MHz crystal
oscillation, A/D off state
(C1 = C2 = 10pF)
IDD2
VDD = 3.0 ± 0.3V, 32kHz crystal
oscillation, 20MHz oscillation stop,
A/D off state (C1 = C2 = 47pF)
IDDS1∗4
VDD = 3.0 ± 0.3V, 20MHz crystal
oscillation, A/D off state
(C1 = C2 = 10pF), sleep mode
VDD, VSS
VDD = 3.3V, VIL = 0.3V
VDD = 2.7V, VIH = 2.4V
VDD = 3.3V, VI= 0, 3.3V
I/O leakage
current
PC∗2
ILOH VDD = 3.3V, VIH = 3.3V
Open drain
output
leakage
current (N-ch
Tr. off state)
0.3
–0.3
–0.9
–1.0
12
25
5
10
5
1.0
20
–20
–250
–250
±10
10
20
50
10
25
15
10
V
µA
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
µA
µA
VDD = 2.7V, IOH = –0.15mA
VDD = 2.7V, IOH = –0.5mA
VDD = 2.7V, IOH = –0.05mA
2.4
2.0
1.3
V
V
V
VDD = 2.7V, IOL = 1.2mA
VDD = 2.7V, IOL = 1.6mA
VDD = 2.7V, IOL = 2.0mA
VDD = 2.7V, IOL = 3.0mA
VDD = 2.7V, IOL = 5.0mA
VDD = 3.3V, VIH = 3.3V
VDD = 3.3V, VIL = 0.3V
0.3
0.5
0.3
0.5
V
V
V
V
PA, PB,
PC4 to PC7, PE,
PF4 to PF7, PG,
PH0 to PH5, PJ
PC0 to PC3
(SCL0, SCL1,
SDA0, SDA1)
PD
EXTAL
IDDS2
VDD = 3.0 ± 0.3V, 32kHz crystal
oscillation, 20MHz oscillation stop,
A/D off state (C1 = C2 = 47pF),
sleep mode
IDDS3
VDD = 3.0V, 32kHz crystal
oscillation, 20MHz oscillation stop
(C1 = C2 = 47pF), clock mode
IDDS4 VDD = 3.0V, stop mode
– 19 –
CXP921064A
Item Symbol Pins Conditions Min. Typ. Max. Unit
Clock 1MHz
0V for all pins excluding measured
pins
CIN
Input
capacitance
PA, PB0 to PB4,
PB6, PB7,
PC to PE,
PF0 to PF3,
PF5, PG, PH6,
PH7, PI, PJ,
AN1 to AN3,
EXTAL, TEX,
RST
10 20 pF
∗1RST specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
∗2PC specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
∗3When all output pins are open.
∗4When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and
the LSI is operated in high-speed mode (2 frequency dividing clock).
– 20 –
CXP921064A
AC Characteristics
(1) Clock timing (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Main clock base oscillation
frequency
Main clock base oscillation
input pulse width
Main clock base oscillation
input rise time, fall time
Sub clock base oscillation
frequency
Sub clock base oscillation
input pulse width
Sub clock base oscillation
input rise time, fall time
fEX
tXH
tXL
tXR
tXF
fTEX
tTH
tTL
tTR
tTF
EXTAL,
XTAL
EXTAL
EXTAL
TEX,
TX
TEX
TEX
Fig.1
Fig.1, Fig.2
External clock
drive
Fig.1, Fig.2
External clock
drive
Fig.1
Fig.1, Fig.2
External clock
drive
Fig.1, Fig.2
External clock
drive
VDD = 3.0 ± 0.3V
VDD = 3.0 ± 0.3V
VDD = 3.0 ± 0.3V
VDD = 2.2 to 3.3V
VDD = 3.3V
VDD = 2.2V
VDD = 3.3V
VDD = 2.2V
15
20
32.735
15.3
15.3
20.5
14
33.096
200
200
MHz
ns
ns
kHz
µs
µs
ns
ns
Symbol
Pins Conditions Min. Max.
20
32.768
Typ. Unit
Note) tsys indicates the four values below according to the upper two bits (PCK1,PCK0) of the clock control
register (CLC: 0002FEh) during main mode and tsys = 2/fTEX = 61.04µs during sub mode.
tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10), 16/fEX (PCK1,
PCK0 = 11)
EXTAL
1/fc
tXH tXF tXL tXR
0.7VDD
0.3VDD
TEX
1/fTEX
tTH tTF tTL tTR
0.7VDD
0.3VDD
Fig.2. Oscillator connection and clock applied conditions
Oscillator connection
example of
sub oscillation circuit
Connection example of
external clock
TEX TX
(TEX)
EXTAL
(TX)
XTAL
74HC04
Oscillator connection
example of
main oscillation circuit
EXTAL XTAL
Fig.1. Clock timing
– 21 –
CXP921064A
Fig.3. Event count input timing
EC
tEH tEL
0.8VDD
0.2VDD
(2) Event count input (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Event count input clock
pulse width
tEH,
tEL EC Fig.3 tsys + 100 ns
Symbol
Pins Conditions Min. Max. Unit
Fig.4. Interruption input timing
0.2VDD
tIH tIL
0.8VDD
NMI
INT0 to INT7
KS0 to KS15
0.2VDD
RST
tRST
Fig.5. Reset input timing
(3) Interruption and reset input (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
External interruption
high, low level width
tIH,
tIL
tRST
NMI
INT0 to INT7
KS0 to KS15
INT4 to INT7
RST
Main mode
Sub mode
Sleep mode
Clock mode
Stop mode
Noise filter
selected
Fig.5
φ
PS4
PS6
ns
µs
ns
ns
tsys + 100
1
2tsys + 100
32/fEX + 100
128/fEX + 100
3tsys + 200
Reset input low level
width
Symbol
Pins Conditions Min. Max. Unit
– 22 –
CXP921064A
Conversion time
Sampling time
Reference input
voltage
Analog input
voltage
AVREF current
tCONV
tSAMP
VREF
VIAN
IREF
IREFS
AVREF0
AVREF1
VDD = AVDD = AVREF = 3.0V
VDD = AVDD = AVREF
Linearity error
Absolute error
Resolution
3.3
AVREF
1.5
10
34tsys
9tsys
2.7
0
Main mode
Sub mode
Clock mode
Stop mode
during ADC off state
Item Symbol Pins Conditions Min. Typ. Max. Unit
Bits
(4) A/D converter characteristics
(Topr = –20 to +75°C, VDD = AVDD = AVREF = 2.7 to 3.3V, Vss = AVss = 0V reference)
8
±1 LSB
LSB
µs
µs
V
V
mA
µA
±3
1.1
AVREF
AN0 to AN23
Fig.6. Definition of A/D converter terms
FFh
FEh
01h
00h
Analog input
Linearity error
Digital conversion value
FFh
(100h)
FEh
01h
00h
Analog input
Digital conversion value
Absolute error
AVREF
Absolute error
VZT∗1VFT∗2
∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa.
∗When Bit 14 (ADOFF) of A/D control status register (ADCS0: 00013Ch,ADCS1: 00014Ch) is specified to "1".
Note) AVDD and AVREF must be the same voltage with VDD.
– 23 –
CXP921064A
External start transfer mode
(SCK = output mode)
External start transfer mode
(SCK = output mode)
External start transfer mode
External start transfer mode
External start transfer mode
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
(5) Serial transfer (CH0, CH1, CH2) (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
CS ↓→SCK
delay time
CS ↑→SCK
float delay time
CS ↓→SO
delay time
CS ↑→SO
float delay time
CS high level width
SCK cycle time
SCK
high, low pulse width
SI input data setup time
(for SCK ↑)
SI input data hold time
(for SCK ↑)
SCK ↓→SO
delay time
Minimum interval time
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
tINT
Symbol Pins Min.
1.5tsys + 200
1.5tsys + 200
1.5tsys + 200
1.5tsys + 200
tsys + 150
100
tsys + 100
2tsys + 200
16/fEX
tsys + 100
8/fEX – 100
100
200 – tsys
tsys + 100
tsys + 100
3tsys + 100
8/fEX – 100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max. UnitConditions
SCK0
SCK1
SCK2
SCK0
SCK1
SCK2
SO0
SO1
SO2
CS0
CS1
CS2
CS0
CS1
CS2
SCK0
SCK1
SCK2
SCK0
SCK1
SCK2
SI0
SI1
SI2
SI0
SI1
SI2
SO0
SO1
SO2
SCK0
SCK1
SCK2
– 24 –
CXP921064A
Fig.7. Serial transfer CH0, CH1, CH2 timing
– 25 –
CXP921064A
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
(6) Serial transfer (CH3) [SIO mode] (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
SCK cycle time
SCK high, low pulse
width
SI input data setup
time (for SCK ↑)
SI input data hold
time (for SCK ↑)
SCK ↓→SO delay
time
tKCY
tKH
tKL
tSIK
tKSI
tKSO
Symbol Pins Min.
tsys + 150
100
2tsys + 200
16/fEX
tsys + 100
8/fEX – 100
100
200
tsys + 100
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max. UnitConditions
SCK3
SI3
SO3
tKCY
0.8VDD
0.8VDD
0.2VDD
0.2VDD
0.8VDD
0.2VDD
tKL
tSIK
tKSO
tKSI
tKH
SCK3
SI3
SO3
Input data
Output data
Fig.8. Serial transfer CH3 timing (SIO mode)
– 26 –
CXP921064A
∗When lower 2 bits (SCK1, SCK0) of serial mode register (SIOM3: 0001A4h) is specified to "00".
Note) The load condition for the SO output delay time is 100pF.
(7) Serial transfer (CH3) [Special mode] (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
SO cycle time∗
SI input setup time
SI input hold time
Input start bit high level
width
SI →SO
delay time
tLCY
tLSU
tLHD
tLSBH
tLIO
Symbol Pins Min.
1
2
2
1
Typ.
104
µs
Max. UnitConditions
SO3
SI3
SI3
SI3
SI3
SO3
Start bit Output data bit
Input data
bit
SO3
tLCY tLCY
0.5VDD
0.2VDD
SI3
tLSU
tLCY/2
tLHD
0.8VDD
Fig.9. Serial transfer CH3 timing (Special mode)
Input data bit
Output data bit
SI3
tLSBH
0.2VDD
0.8VDD
0.5VDD
SO3
tLCY/2
tLSU tLHD
tLSU tLHD
tLCY
tLIO tLCYtLCY
Fig.10. Serial transfer CH3 timing (Special mode)
fEX
= 20MHZ
Communication slave mode
– 27 –
CXP921064A
∗Due to the total capacitance of the bus.
(8) I2C bus (CH0, CH1) (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
SCK clock frequency
Bus free time between
stop and start conditions
Hold time under (resend)
start condition
Hold time in SCL clock
low state
Hold time in SCL clock
high state
Setup time under (resend)
start condition
Data hold time
Data setup time
SCL, SDA signal output
rise time
SCL, SDA signal output
fall time
Setup time under stop
condition
SCL0
SCL1
SDA0
SDA1
SDA0, SDA1
SCL0, SCL1
SCL0
SCL1
SCL0
SCL1
SDA0, SDA1
SCL0, SCL1
SDA0, SDA1
SCL0, SCL1
SDA0, SDA1
SCL0, SCL1
SDA0, SDA1
SCL0, SCL1
SDA0, SDA1
SCL0, SCL1
SDA0, SDA1
SCL0, SCL1
tSCL
tBUF
tHD;STA
tLow
tHigh
tSU;STA
tHD;DAT
tSU;DAT
tRd
tRc
tFd
tFc
tSU;STO
Symbol Pins Min.
Standard mode High-speed mode
400
0.9
300
300
0
1.3
0.6
1.3
0.6
0.6
0
100
20 + α∗
20 + α∗
0.6
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Max.Min.
100
1000
300
0
4.7
4.0
4.7
4.0
4.7
0
250
4.0
Max. Unit
SDA0
SDA1
SCL0
SCL1
tBUF tSU;DAT
tHD;STA
tSCL
tFd
tRd
tRc
tFc
tLow
tHD;STA tHD;DAT tHigh tSU;STA tSU;STO
Fig.11. I2C bus timing
– 28 –
CXP921064A
(9) Remote control reception (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Remote control receive
high, low level width tRMC RMC Main mode
Sub mode
PS5 selected
PS7 selected
PS9 selected
32k selected
ns
128/fEX + 100
512/fEX + 100
2048/fEX + 100
4/fTEX + 100
8/fTEX + 100
Symbol Pins Conditions Min. Max. Unit
0.8VDD
RMC
0.2VDD
tRMC tRMC
Fig.12. Remote control signal input timing
– 29 –
CXP921064A
EXTAL XTAL
C1C2
Rd
TEX TX
C1C2
Rd
EXTAL
(i) Main oscillation circuit (ii) Main oscillation circuit (iii) Sub oscillation circuit
XTAL
C1C2
Rd Rf
Fig.13. Recommended oscillation circuit
Appendix
Manufacturer
MURATA MFG
CO., LTD.
RIVER ELETEC
CO., LTD.
KINSEKI LTD.
HC-49/U03
HC-49/U-S
TDK
Corporation
Model
CSA12.0MG
CSA16.00MXZ040
CSA20.00MXZ040
CST12.0MTW∗
CST16.00MXW0C3
∗
CCR12.0MSC5∗
CCR16.0MSC6∗
CCR20.0MSC6∗
12.0
16.0
20.00
12.0
16.0
12.00
12.0
16.0
20.0
12.0
16.0
20.0
30
15
10
30
15
10
12
12
12
20 (±20%)
10 (±20%)
10 (±20%)
30
15
10
30
15
10
12
12
12
20 (±20%)
10 (±20%)
10 (±20%)
0
0
0
0
0
220
1.0k
470
390
fc (MHz) C1(pF) C2(pF) Rd (Ω)
Circuit example
Remarks
(i)
(ii)
(i)
(ii)
150k Rf = 10MΩ
CL = 12.5pF
Item Content
Reset pin pull-up resistor Non-existent Existent
Mask option table
∗Indicates types with on-chip grounding capacitor (C1, C2). CCR∗∗∗: Surface mounted type ceramic oscillator.
CL : Load capacitor
(i)
0
CL = 12pF
VTC-200
SP-T
Seiko
Instruments Inc. 20 18 (iii)
32.768kHZ
CL = 10pF
– 30 –
CXP921064A
Notes on PF7 Usage
FLASH EEPROM incorporated PF7 is also used as flash mode setting function. Note the followings:
1. "H" is output to PF7 during a reset. That is driven at comparatively high impedance (approximately 150 kΩ),
and take care that VOH should not fall under 0.7 VDD by the partial pressure with external circuit load
impedance.
2. When using software reset functions, PF7 may not rise enough during a reset. Switching PF7 to "H" output
prior to software reset execution or connecting pull-up resistor is recommended.
Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that EEPROM
incorporated type is used, above countermeasure should be performed.
Keep PF7 above 0.7 VDD during
this period.
RST
PF7
Flash mode
Normal operation
– 31 –
CXP921064A
Characteristics Curve
20
18
16
14
IDD – Supply current [mA]
12
10
8
6
2
2.1 2.4 2.7
VDD – Supply voltage [V]
IDD vs. VDD
(fEX = 20MHz, Topr = 25°C, Typical)
3.33 3.6 3.9
4
2 frequency dividing mode
4 frequency dividing mode
8 frequency dividing mode
16 frequency dividing mode
20
18
16
14
12
IDD – Supply current [mA]
10
8
6
4
2
2.1 2.4 2.7 3
VDD – Supply voltage [V]
IDD vs. VDD
(fEX = 20MHz, Topr = 25°C, Typical)
3.3 3.6 3.9
0
Sleep mode (2 frequency division)
Sleep mode (4 frequency division)
30
25
IDD – Supply current [μA]
20
15
10
5
02.1 2.4 2.7
VDD – Supply voltage [V]
IDD vs. VDD
(fTEX = 32kHz, Topr = 25°C, Typical)
3.33 3.6 3.9
32kHz mode
(instruction execution)
32kHz
sleep mode
32kHz
clock mode
20
18
16
14
12
IDD – Supply current [mA]
10
8
6
4
2
0510
fEX – Main clock base oscillation frequency [MHz]
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
15 20 25
0
2 frequency dividing mode
4 frequency dividing mode
8 frequency dividing mode
16 frequency dividing mode
20
18
16
14
12
IDD – Supply current [mA]
10
8
6
4
2
510
fEX– Main clock base oscillation frequency [MHz]
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
15 20 25
00
Sleep mode (2 frequency division)
Sleep mode (4 frequency division)
Sleep mode (8 frequency division)
Sleep mode (16 frequency division)
Sleep mode (8 frequency division)
Sleep mode (16 frequency division)
– 32 –
CXP921064A
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
23.9 ± 0.4
QFP-100P-L01
100PIN QFP (PLASTIC)
20.0 – 0.1
+ 0.4 0.15 – 0.05
+ 0.1
15.8 ± 0.4
17.9 ± 0.4
14.0 – 0.1
+ 0.4
2.75 – 0.15
+ 0.35
A
0.65
M
0.13
QFP100-P-1420
1.7g
1
100
81
80 51
50
31
30
0.3 – 0.1
+ 0.15
DETAIL A
0˚ to 10˚
0.8 ± 0.2 (16.3)
0.15
0.1 – 0.05
+ 0.2
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
23.9 ± 0.4
QFP-100P-L01
100PIN QFP (PLASTIC)
20.0 – 0.1
+ 0.4 0.15 – 0.05
+ 0.1
15.8 ± 0.4
17.9 ± 0.4
14.0 – 0.1
+ 0.4
2.75 – 0.15
+ 0.35
A
0.65
M
0.13
QFP100-P-1420
1.7g
1
100
81
80 51
50
31
30
0.3 – 0.1
+ 0.15
DETAIL A
0˚ to 10˚
0.8 ± 0.2 (16.3)
0.15
0.1 – 0.05
+ 0.2
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL ALLOY 42
LEAD TREATMENT Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18μm
SPEC.
– 33 –
CXP921064A
Package Outline Unit: mm
100PIN LQFP (PLASTIC)
25
26
51
50
75
76
1
100
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 / COPPER ALLOY
PACKAGE STRUCTURE
DETAIL A
LQFP-100P-L01
P-LQFP100-14x14-0.5
16.0 ± 0.2
14.0 ± 0.1
0.5 b
(0.22)
A
1.5 – 0.1
+ 0.2
0.5 ± 0.2 (15.0)
0˚ to 10˚
0.1 ± 0.1
0.5 ± 0.2
0.1
NOTE: Dimension "∗" does not include mold protrusion.
0.7g
0.13 M
b = 0.18 – 0.03
( 0.18 )
(0.127)
+ 0.08
0.127 – 0.02
+ 0.05
DETAIL B
∗
B
100PIN LQFP (PLASTIC)
25
26
51
50
75
76
1
100
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 / COPPER ALLOY
PACKAGE STRUCTURE
DETAIL A
LQFP-100P-L01
P-LQFP100-14x14-0.5
16.0 ± 0.2
14.0 ± 0.1
0.5 b
(0.22)
A
1.5 – 0.1
+ 0.2
0.5 ± 0.2 (15.0)
0˚ to 10˚
0.1 ± 0.1
0.5 ± 0.2
0.1
NOTE: Dimension "∗" does not include mold protrusion.
0.7g
0.13 M
b = 0.18 – 0.03
( 0.18 )
(0.127)
+ 0.08
0.127 – 0.02
+ 0.05
DETAIL B
∗
B
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL ALLOY 42
LEAD TREATMENT Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18μm
SPEC.
– 34 –
CXP921064A
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE PACKAGE MASS
PACKAGE STRUCTURE
LFLGA-104P-02
ORGANIC SUBSTRATE
0.4g
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
104PIN LFLGA
P-LFLGA104-12x12-0.8
DETAIL X
1.4MAX
S
S
0.20
S
0.10
0.01
X
PIN 1 INDEX
12.0
0.2 AS
12.0
0.2 B
S
0.15
x4
1234 56 7 8 910111213
103 – φ0.40 ± 0.05
φ0.08 MSAB
A
B
0.8
A
B
C
D
E
F
G
H
J
K
L
M
N
1.2
0.8
1.2
0.4
0.4
1.6
1.6
NICKEL & GOLD PLATING
COPPER
SONY CODE
EIAJ CODE
JEDEC CODE PACKAGE MASS
PACKAGE STRUCTURE
LFLGA-104P-052
ORGANIC SUBSTRATE
0.4g
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
104PIN LFLGA
P-LFLGA104-12X12-0.8
DETAIL X
1.4MAX
S
S
0.20
S
0.10
0.01
X
PIN 1 INDEX
12.0
0.2 AS
12.0
0.2 B
S
0.15
x4
1234 56 7 8 910111213
104 – φ0.40 ± 0.05
φ0.08 MSAB
A
B
0.8
A
B
C
D
E
F
G
H
J
K
L
M
N
1.2
0.8
1.2
0.4
0.4
1.6
1.6
NICKEL & GOLD PLATING
COPPER
Sony Corporation