TOSHIBA TMP82C55A CMOS PROGRAMMABLE PERIPHERAL INTERFACE TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 1. GENERAL DESCRIPTION AND FEATURES The TMP82C55A (hereinafter referred to as PPI) is a CMOS high Speed programmable input/output interface with three 8-bit I/O ports. 24 I/O Ports are divided into two groups (Port A and Port B) which are programmable independently by control words provided by MPU. The PPI has three operation modes (Mode 0, 1 and 2) and is copable of versatile interface between MPU and peripheral devices. (1) (2) (3) (4) (5) The TMP82C55A is fabricated using Toshibas CMOS Silicon Gate Technology. High Speed Version (TRD = 100ns MAX: TMP82C55AP-10/AM-10) Low power consumption 2mA Type. LOpA Max. (@5V, Stand-by) 5V 10% Single power supply 24 programmable I/O ports Three operation modes (Mode 0, Mode 1, Mode 2) Bit set/reset capability Up to 8 output ports of port B and C are capable of driving a darlington transistor (Min.i.0mA @VOH=1.5V) Extended operating temperature: 40 C to +85 C Available 40pin Standard DIP and SOP MPU85-133TOSHIBA TMP82C55A 2. 3. PIN CONNECTIONS (TOP VIEW) PAg A PA2L PA; T PAgI RDO cst] (GND) Vss 0 Aig Aol Pc; 16 PCe 11 PCs i2 PCy 13 PCo 14 PC, 15 PC? 16 PC3Q 17 PBof] 18 PB, [19 PB2T 20 cow mun wWwnN 1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 PAg PAs PA6 ] PA? WR 1 RESET Do DD, H D2 D3 fH Bg HDs 1 Dg 0 Dz H Vec(+5) NPB ) PBg OU PBs N PBa ] PB3 TMP82C55AP-2/AP- 10 TMP82C55AM-2/AM- 10 BLOCK DIAGRAM D7~Do BIDIRECTIONAL DATA Ay DATA BUS BUFFER READ WRITE CONTROL LOGIC RESET | ' GROUPA GROUP B CONTROL CONTROL INTERNAL 8-BIT BUS ub i GROUP A GROUP B PORT A + PORT C PORT C) PORT B ab fe 1/0 PA7~PAg PCy~PCa 1/0 1/0 PCa~PCg PB7~PBg 050489 050489 MPU85-134TOSHIBA TMP82C55A 4. PIN NAMES AND PIN FUNCTIONS Number |Input/Output : Function of Pin 3-state Pin Name 3-state bidirectional 8-bit data bus. Used for data transfer with Do~D7 8 1/0 3-state |MPU. Also, used for transfer of control words to PPI and status information from PPI. 3-state 8-bit I/O Port A. PAg~PA? 8 /Q 3-state |Operation mode and input/output configuration are defined by software. Port A contains the output latch buffer and input latch. 3-state 8-bit I/O Port 8. PBo~PB7 8 OQ 3-state |Operation mode and input/output configuration are defined by software. Port B contains the output latch buffer and input latch. 3-state 8-bit 1/O Port C. Operation mode and input/output configuration are defined by software. Port C can be divided into two 4-bit ports by the mode control and also, used as the control signal for Port A and Port B. In this case, 3 bits of PCg to PC2 are used for Port B and 5 bits of PC3 to PC; for Port A. PCg~PC7 8 /O 3-state Chip select input. When this terminal is at L level, data transfer PPl and MPU cs 1 In . . . put becomes possible. At H level, the data bus is placed in the high impedance state and control from the processor is ignored. Read signal. RD 1 Input When this terminal is at L" level, data that is input into the port is transferred to MPU. Write signal. WR 1 Input When this terminal is at L level, data or control ward is written into PPI from MPU. Do, At 2 Input Used for selecting Port A, B, and the control registers. Normally, this terminal is connected to low order 2 bits of the address bus. When this terminals is at H level, all internal registers including RESET 1 Input the control register are cleared. In addition, all ports (Port A, B, C) are placed in the input made (high impedance) of mode 0. Vec 1 Power Supply] 5V Vss5 1 Power Supply| GND 050489 MPU85-135TOSHIBA TMP82C55A 5.1 FUNCTIONAL DESCRIPTION The PPI is a programmable peripheral interface device with three 8-bit ports (Port A, B and C) and two control registers. 24 I/O ports are divided into 12-bit group A and group B. Group A consists of Port A and high order 4 bits of Port C, while Group B consists of Port B and low order 4 bits of Port C. Each group is independently programmable by control words provided fram MPU. There are three operation modes available for the PPI. In mode 0, two 8-bit I/O ports and two 4-bit I/O ports can be programmed as input or output ports, respectively. In mode 1, 24 I/O ports are divided into Group A and Group B. & bits of each group are used as input or output port and of the remaining 4 bits, 3 bits are used as handshaking and interrupt control signal. Mode 2 is applicable only to group A and the ports are used as a bidirectional 8-bit data bus and 5-bit control signal. In case of Port C being used as the output, any bits of Port C can be set/reset. There are two control registers; one is used for mode setting and the other for bit set/reset control. The control registers can only be written into. Further, when the reset input (RESET) becomes 1, the control registers are reset and all I/O ports are placed in input mode (high impedance status). Table 5.1 Basic Operation of TMP82C55A Ai | Ao | CS } RO | WR Function 0 0 0 0 1 Data bus < PortA G 1 0 0 1 Data bus PartB 1 0 0 0 1 Data bus < Partc 0 0 0 1 0 PortA < Data bus a 1 0 1 0 Port B < Data bus 1 0 0 1 0 PertC < Data bus 1 1 0 1 0 Controi register Data bus x x 1 x x Data bus = 3-state x x 0 1 1 Data bus = 3-state 1 1 0 0 1 inhibition of combination 0350489 MODE SELECTION There are three basic modes of operation that can be selected by control words. Mode 0-Basic VO (Group A, Group B) Mode 1-Strobe input/Strobe output (Group A, Group B) Mode 2-Twa-way bus (Port A only) Operation modes for Group A and Group B can be independently defined by the control word form the MPU. If D7 is set to 1 in writing a control word into the PPI, operation mode is selected, while of D7 =0, the set/reset function for Port C is selected. MPU85-136TOSHIBA TMP82C55A 5.1.1 Control word to define operation mode Figure 5.1 shows the control words to define operation mode of the TMP82C55A. Control word Group A Control Group B Control D7 Ds | Ds | Da | Ds D3 |r | Do 1 = Designation of mode set flag Ld Input/output selection of low order 4 bits of PortC QO = Output 1 =Input Input/output selection of Port B 0 = Output \'=Input Mode selection of Graup B 0 =Mode 0 1 =Mode 1 Input/output selection of high order 4 bits of Port C 0 = Output "V' = Input Input/output selection of PortA O' = Output 1 = Input Mode Selection GroupA 0'=Mode 0 D6 D5 0 0 =Moded 0 1 =Mode i 1 x =Mode? x: Don't care 050489 Figure 5.1 Control Word for Mode Selection MPU85-137TOSHIBA TMP82C55A 5.1.2 Port C bit set/reset contral word Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset control word. Fig. 5.2 shows the Port C bit set/reset control word. Contrel Word [07 | ds | Os | Oe | Ds | D2 | Oi | Do | L Bit set/reset selection Don't care Q = Reset "1" = Set se setrert fg of fo [re 0 0 1 PC, 0 1 0 PC> 0 i 1 PC3 r Bitselection 1 0 0 PCy 1 0 1 PCs 1 1 0 PC. t 1 1 PC? 050489 Figure 5.2 Control Word for Bit Set/Reset 5.2. OPERATION MODES 5.2.1 Mode 0 (Basic 1/0) This functional configuration is used for simple input or output operations. No handshaking is required and data is simply written to or read from a specified part. Output data to the ports from MPU are latched out but input data from the ports are not latched. In Mode O, 24 I/O terminals are divided into four groups of Port A (8 bits), Port B (8 bits), high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed to be input or output. The configuration of each port are determined according to the contents of Bit 4 (D4), 3 (D3), 1 (D,) and 0 (Do) of the control word for mode selection. The I/O configuration of each port in Mode 0 are shown in Table 5.2. MPU85-138TOSHIBA TMP82C554 Mode Setting Control Word PortC PortC PortA PortB Da D3 D, Do (PC7~PCa) (PC3~PCg) 0 Q 0 0 Out Out Out Out 0 0 0 1 Out Out Out In 0 Q 1 0 Out Out In Out 0 0 1 1 Out Out In In 0 1 0 0 Out In Out Out 0 1 0 ] Out In Out in 0 1 1 0 Out In In Out 0 1 1 1 Out In In in i 0 0 0 In Out Out Out 1 0 0 1 In Out Out In 1 0 1 0 In Out In Out 1 0 1 1} In Out In In 1 1 0 0 In In Out Out i 1 0 1 In In Out In 1 1 1 0 In In In Out 1 1 1 1 In In In In 050489 Figure 5.3 Port Definition in Mode 0 5.2.2 Mode 1 (Strobe I/O) (1) In Mode 1, input/output of port data is performed in conjunction with the strobe signals or handshaking signals, Port C is used to control Port A or Port B. The basic operatings in Mode 1 are as follows: Mode 1 can be set for two groups of Group A and Group B. Each group consist of 8-bit data port and 4-bit control/data port. The 8-bit data port can be set as input or output port. The control/data port is used as control or status of the 8-bit data port. When used as the input port in Mode 1: STB (Strobe Input) At OQ, input data is loaded in the internal input latch in the port. In this case, a control signal from MPU is not concerned and data is input from the port any time. This data is not read out on the data bus unless MPU executes an input instruction. IBF (Input Buffer Full F/F Output) When data is loaded in the internal input latch from the port, this output is set to 1. IBF is set (1) by STB input being reset and is reset (0) by the rising edge of RD input. MPU85-739TOSHIBA TMP82C55A INTR (Interrupt Request Output) Used for the interrupt process of data loaded in the internal input latch. When STB input is at 0 if INTE (INTE flag) in the PPI is in the enabled state (1) , IBF is set to 1. INTR is set to 1 immediately after the rising edge of this STB input and reset to 0 by the falling edge of RD input. The INTE flag of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PC4 INTEB-Control by bit set/reset of PCo (2) When used as the output port in Mode 1: e OBF (Output Buffer Full F/F Output) This is a flag which shows that MPU has written data into a specified port. OBF is set to becomes 0 at the rising edge of WR signal and is set to 1 at the falling edge of ACK (Acknowledge input) signal. e ACK (Acknowledge Input) ACK signal is sent to the PPI as a response from a peripheral device taht received data from the port. e INTR (Interrupt Request Output) When a peripheral device received data from MPU, INTR is set to 1 and the interrupt is requested to MPU. If ACK signal is received when INTE flag is in the enable state, OBF is set to 1 and INTR signal becomes 1 immediately after the rising edge of ACK signal. Further, INTR is reset at the falling edge of WR signal when data is written into the PPI by MPU. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PCg INTEB-Control by bit set/reset of PCa MPU85-140TOSHIBA TMP82C55A MODE 1 {PORT A) CONTROL WORD PAy~ Pag bard Dy Dg Ds Dg D3 Dz Dy Dy INTE | PCy |< STBA Li fofs]t [vol x[x]x] | tp Lecs > ira TB Va | PCs, PC; _ PC3 - INTRA __f O = OUTPUT RO d ; BE 1 = INPUT Plg~ PC? | 1/0 4 MODE 1 (PORT B) INTR __/ 8 RD CONTROL WORD PB7~ PBg |= \ / Dz Dg Ds Dg D3 Dz Di Do tINTE | (pc, |< STRB | \ I I fitx[x[x[x[ifayx} |! pe fec- ise Noort Xt ferns BETTE ------ 50489 PC RO d a Figure 5.4 Example of Strobe Input in Mode 1 MODE 1 (PORT A) CONTROL WORD PA7 ~ PAg Le? D7 Dg D5 Dg Dz Do Dy Do PCy p> OBFA ~ ACKA WR | PCa, PCs __ i> INTRA OBE O= OUTPUT WRd 5 | 1 = INPUT PCy ~ PCy be 1/0 ___ ACK MODE 1 (PORT B) | CONTROL WORD PB7 ~ PBo L INTR D7 Dg Ds Dg D3 Dz Dy Do PC, -- OBFB Cte lx [x [x ToT x] ACK poy OUTPUT Xx __ t INF RB WRd 950489 Figuire 5.5 Example of Strobe Output in Mode 1 MPU85-141TOSHIBA TMP82C55A 8 PAy~ PAg 3 PA ~ PAg <> WwRd PC, | OBFA RD*d PCq J* STBA CONTROL WORD PC, |-~* ACKA CONTROL WORD PC; [> IBFA D7 De Ds Da D3 Dz D1 Do PCa > INTRA D7 De Ds Dg Dz Dz Dy Do PC3 |= INTRA [i fo]s fo filits [x] 2 [i fol+ts fli qolx | 2 PC, ~ PCy be 1/0 Pg ~ PCy We 1/0 8 8 PCa, PCs PRy ~ PBg [~~ PC, PCy PBy ~ PBy b> D= OUTPUT __ _ 0 = OUTPUT __ 1 = INPUT RDG PC) j} STBB 1 = jNPUT WRG PC, --> OBFB PC, p> [BFE PC, |-* ACKB PCy [> iNTRB PCy Po INTRB PORT A (STROBE OUTPUT) PORT A (STROBE INPUT) PORT B (STROBE INPUT} PORT B (STROBE QUTPUT) @50489 Figure5.6 Example of Port A Output, Figure 5.7 Example of Port A Input, Port B Input in Made 1 Port B Output in Mode 1 5.2.3 Mode 2 (Strobed Bidirectional Bus I/O) In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a peripheral device. This mode is applicable only to Group A, which consists of an 8-bit bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The bidirectional bus (Port A) has both the internal input and output registers. When group A is set in Mode 2, Group B can be set independently. There are 5 control signals as follows when Group A is used in Mode 2. e OBF (Output buffer Full F/F Output) When MPU writes data into of Port A, OBF is set to 0 to inform a peripheral device that the PPI is ready to output data. However, Port A is kept in the floating (high impedance) state until ACK input signal is received. e ACK (Acknowledge Input) When ACK signal is set to 0, the data of the 3-state output buffer of Port A is send out. If ACK signal is at 1, Port A is in the high impedance state. e STB (Strobe Input) When STB input is set to 0, the data from peripheral devices are held in the input latch. When the active RD signal is input into the PPI, the latched input data are output on the system data bus (D7-Dg). MPU85-142TOSHIBA TMP82C554 e IBF (Input Buffer Full F/F Output) When data from peripheral devices are held in the input latch, IBF is set to 1. e INTR (Interrupt Request Output) INTR is the output to request the interrupt to MPU and its function is the same as that in Mode 1. There are two interrupt enable flip-flop (INTE), INTE1 corresponds to INTEA in Mode 1 output and INTE2 to INTEA in Mode 1 input. INTE 1-Used to generate INTR signal in conjunction with OBF and ACK signals, and is controlled by PC bit set/reset. INTE 2-Used to generate INTR signal in conjunction with IBF and STB signals, and is controlled by PC, bit set/reset. Fig. 5.8 shows the operating example and the timing diagram in Mode 2. INTR ~_\ 578 STBA L. | IBFA Mf IBF YO PORTA monn nn Gare} Coma) -\ =~ RD 1 f 050489 Figure 5.8 Operating Example in Mode 2 MPU85-143TOSHIBA TMP82C55A Control Word in Mode 2 Cr De Ds Da D3 D2 Dy Do 1 |x | x | x [iw [iw [10 | PC2~PCp 0 = Output x =Dont care 1 =Input PortB 0 = Output 1=Input Group B Mode 0 =Moded 1=Mode 1 050489 Figure 5.9 Control Word and Configuration in Mode 2 Control Words PC3 rg INTRA PAI~PAg [<> PC7 /> OBFA PCg j~* ACKA PCq |~- STBA PC2~PCg ~<__-_ 0 = Output PCs --~ IBFA 1 = Input 3 RD PC2~PCg Jao 1/0 WR PB7~PBo <i PortA- Mode2 = 1/0 PortB- ModeQ Input Control Words PC3 re INTRA PA7~PAg |= PC7 OBFA PCg J* ACKA PCa STBA PCs -_ IBFA PB7~PBo |e PC, }- OBFB PC2 } ACKB PCo }-> INTRB a | mi PortA- Mode2 1/0 PartB- ModeQ = Input 050489 Figure 5.10 Examples in Combination with Mode 2 and Other Mode MPU85-144TOSHIBA TMP82C55A 5.2.4 Precautions for use in mode 1 and 2 When used in Mode 1 and 2, bits which are not used as control or status in Port C can be used as follow. If programmed as the input, they are accessed by normal Port C read. If programmed as the output, high order bits of Port C (PC7-PC4) are accessed using the bit set/reset function. As to low order bits of Port C (PC3-PCo), in additions to access by the bit set/reset function, only 3 bits can be accessed by normal writing. 5.3. READING PORT CSTATUS When Port C is used as the control port, that is, when Port C is used in Mode 1 or Mode 2, the status information of the control word can be read out by a normal read operation of Port C. Table 5.2 Status Word Format of Port C Data Mode D? Dg Ds Da D3 D2 Dy Do Mode 1 Input ifO 1/0 IBFA INTEA | INTRA | INTEB IBFB INTRB Mode 1Output | OBFA | INTEA 1/0 1/0 INTRA | INTEB | OBFB | INTRB Mode 2 OBFA INTE1 IBFA INTE2 | INTRA By Group B Mode 050489 MPU85-145TOSHIBA TMP82C55A 6. ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS Symbol Item Rating Unit Vec Supply Voltage -0.5to7.0 Vv VIN Input Voltage -0.5to Vcc +0.5 Vv Pp Power Dissipation 250 mW TsoipeR Soldering Temperature (10 sec} 260 Cc TstG Storage Temperature -65to +150 c Topr Operating Temperature -40to +85 Cc 050489 6.2 DC ELECTRICAL CHARACTERISTICS TA= -400 to +85, Vec=5Vt10%, Vs5 = OV SYMBOL iTEM TEST CONDITION MIN. TYP. MAX. UNIT VIL Input Low Voltage -0.5 - 0.8 v Vin Input High Voltage 2.2 _ Veco +0.5 Vv Voi Output Low Voltage lol =2.5mA - 0.45 Vv Vout Output High Voltage lon = 400A 2.4 _ - Vv Vou2 Output High Voltage lon =-100pA Vcc-0.8 ~ _ V Ne Input Leak Current O=Vin=Vecc _ _ +10 pA Output Leak Current < + . s = _ - +10 A ILo (High Impedance State) 08 Vout Vcc P (Note) Darlington Drive VexTr=1.5V -1. _ - 5.0 A IDAR Current RextT = 1.1k2 m leer Operating Supply |/Ocycle Time _ 20 5.0 mA Current Tpsec ; CS 2 Vec-0.2V lec2 stand-by Supply Vin = Vcc-0.2V - 10 pA VipS0.2V 050489 Note: Applied for optional 8 I/O terminals in Port B and Port C. MPU85-146TOSHIBA TMP82C55A 6.3. AC ELECTRICAL CHARACTREISTICS TA= -40 to +85, Voc =5V 10%, Veg =0V SYMBOL PARAMETER eee Ae OAM! Unit MIN. | MAX.) MIN. | MAX. tar Address set-up time for RD fall Oo; - 0; - ns tra Address hold time for RD rise 0 0 - ns tar RD pulse width 160 - 150 > ns tro Delay from RD fall to decided data output ~ 140 - 100 | ns tor Time from RD rise to data bus floating 0 40 0 40 1 ns try Time from RD or WR rise to next RD or WR fall 200 - 150 - ns taw Address set-up time for WR fall 0 - 0 ns twa Address holding time for WR rise 0 ~ 0 _ ns tww WR pulse width 120 - 120 ns tow Bus data set-up time for WR rise 100 ~ 100 _ ns two Bus data holding time for WR rise 0 0 _ ns twe Deiay from WR rise to decided data output 350} 350 | ns tir Port data set-up time for RD fall 0 0 ns tHR Port data holding time for RD rise 0 - a) ns tak ACK pulse width 300 | 300 { ns tsT STB puise width 350 ~ 350 - ns tps Port data set-up time for STB rise 0 _ 0 ~ ns teH Port data holding time for STB rise 150} 150] ns tap Delay fram ACK fali to decided data output _ 300 - 300] ns tko toning ACK rise up to port (Port A in Mode 2) 25] 250 270/ 250 ns twoep | Delay fram WR rise to GBF fall _ 300 300 | ns taos Delay fram ACK fall to OBF rise _ 350 ~ 350} ns tsig Delay from STB fall to IBF rise _ 300! ~ 300 | ns trip Delay from RD fall to IBF rise - 300 - 300 ns tert Belay from RD fall to INTR fall _ 400 _ 400 ns tsit Delay from ACK rise to INTR rise 300 300 |] ns taiT Delay from ACK rise to INTR rise - 350 350] ns twit Delay from WR rise ta INTR _ 450 _ 450 | ons 050489 Note: 1. When the power supply is turned ON, reset pulse duration must be active for at least 500 ns or more. 2. AC Measuring Point Input Voltage Vy1=2.4V, Vit=0.45V Output Voltage Voy =2.2V, Vo_=0.8V CL=150pF. MPU85-147TOSHIBA TMP82C55A 6.4 CAPACITANCE TA=25C, Vcc =Vs55 =0V SYMBOL ITEM TEST CONDITION MIN. TYP. MAX. | UNIT Cin Input Capacitance fo=1MHz - - 10 pF Court Output Capacitance (*} _ 20 pF 050489 (*}: All terminals except that to be measured should be earthed. MPU85-148TOSHIBA TMP82C55A 7. TIMING DIAGRAM 0 INPUT GPERATION INPUT CS, At, Ao D7~Dg MODE 0 OUTPUT OPERATION D7~Dg CS, Ar, Ao OUTPUT MODE 1 INPUT OPEARATION tps TPH INPUT PORT K DATA tstT , STB l ~ tsip 45 IBF ~<ts|T trig INTR { en ao Same trr Sy 050449 Figure 7.1 Timing Diagram MPU85-149TOSHIBA TMIP82C55A WR INTR OUTPUT PORT DATA OB Tm | D> A c INTR oO w a ACK PERIPHERAL BUS s Ly < te Figure 7.2. Timing Diagram MODE 1 OUTPUT OPERATION < tww yo W twit e tyWoR 7 p ( twe Pei 4 c vy a i tak a MODE 2 BIDIRECTION OPERATION tww > iC y W iH W twit tsIT. Ps A twos ~x TAR + __ _$____ R i tH tak SJ 4} rt t tps tpy AD KD tstT ~ / . tsiB tris tRR 050489 MPU85-150TOSHIBA TMP82C55A 8. PACKAGE DIMENSION 8.1 PLASTIC PACKGE DIP40-P-600 Unit: mm oS ) TO 50.74+0.2 | | * w ao ot ot | on 2 iat ea 1.22TYP a 270289 Note: Each lead pitch is 2.54mm, and all the leads are located witchin +0.25mm from their theoretical positions with respect to No.1 and No.4 leads. MPU85-151TOSHIBA TMP82C55A 8.2 4OPIN SMALL OUTLINE PACKAGE SSOP40-P-450 Unit: mm 40 IIAADSAABAADRIONBEL ) Vi HEEL WVEHEA ETE | : VISTYP | 0.35401 [U.iSTYP [0.8] f@f{o.16@ | W7502 4 . 0.2 -0-05 a i 40-1 15 0.1940.1]}2.44: 2 BMAX 0.840.2 270289 MPU85-152TOSHIBA TMP8255A PROGRAMMABLE PERIPHERAL INTERFACE TMP8255AP-5 1. GENERAL DESCRIPTION AND FEATURES The TMP8255A (hereinafter referred to as PPI) is a high Speed programmable input/output interface with three 8-bit I/O ports. 24 I/O ports are divided into two groups (Port A and Port B) which are programmable independently by control words provided by MPU. The PPI has three operation modes (Mode 0, 1 and 2) and is capable of versatile interface between MPU and peripheral devices. (1) 5V+5% Single power supply (2) 24 programmable I/O ports (3) Three operation modes (Mode 0, Mode 1, Mode 2) (4) Bit set/reset capability 2. PIN CONNECTIONS {TOP VIEW) PA3q1 ~~ 40 DPAg PA2 0 2 39 NPAs PA, 03 38 1 PAs PAg I 4 37 9 PA? RDS 36 ) WR csd6 35 0 RESET (GND) Vss 7 34 Dp Ai08 33 0D, Ao d9 32 1 D2 PC70 10 31 D3 PC,g C11 30 1D, PCs 412 29 Ds PC4 QJ 13 28 1D, PCo] 14 27 ND; Pc, 15 26 0Vecc(+5V) PC2 [16 25 DPB? PC3 017 24 D PBs PBo 118 23 OPB5 PB,q 19 22 [1 PBa PB 20 21 DPB3 TMP8255AP-5 050489 MPU85-153TOSHIBA TMP8255A 3. BLOCK DIAGRAM D7~Do BIDIRECTIONAL DATA READ WRITE CONTROL LOGIC +d Ag ~ DATA BUS BUFFER Ayo RESET GROUP A GROUP B CONTROL CONTROL INTERNAL 8-BIT BUS itt GROUPA GROUP B PORT A| PORT C PORT C | PORT B 1/O i/o 1/0 1/0 PA7~PAg PC7~PCa PC3~PCo PB7~PBo 050489 MPU85-154TOSHIBA TMP8255A 4. PIN NAMES AND PIN FUNCTIONS Number | input/Output Pin Name . Function of Pin 3-state 0 3-state bidirectional 8-bit data bus. Do~D7 8 3-STATE Used for data transfer with MPU. Also, used for transfer of control wards to PPI and status information from PPI. VO 3-state 8-bit l/O Port A. PA7~PAg 8 3-STATE Operation mode and inpuvoutput configuration are defined by software. Port A contains the output latch buffer and input latch. VO 3-State 8-bit /O Port B. PB7~PBq 8 Operation mode and input/output configuration are defined by 3-STATE . . software. Port B contains the output latch buffer and input latch. 3-state 8-bit /O Port C. Operation mode and input/output configuration are defined by vO software. Port C can be divided into two 4-bit ports by the mode PC7~PC 8 . ; 0 3-STATE control and also, used as the control signal for Port A and Port B. In this case, 3 bits of PCg to PC2 are used for Port B and 5 bits of PC3 to PC7 for Port A. Chip select input. s 1 input When this terminal is at "L" level, data transfer PP] and MPU becomes possible. At "H" level, the data bus is placed in the high impedance state and control from the processor is ignored. _ Read signal. RD 1 Input When this terminal is at L level, data that is input into the port is transferred to MPU. Write signal. WR 1 Input When this terminal is at "L" level, data or control word is written into PPI from MPU. Ao, Ay 2 Input Used for selecting Port A, B, C and the control registers. Nurmailly, this terminal is connected to low order 2 bits of the address bus. When this terminal is at "H" level, all internal registers including the RESET 1 Input control register are cleared. In addition, all ports (Part A, B, C} are placed in the input mode (high impedance) of made 0. Power Ver 1 Supply 5V Power Vv 1 SS Supply GND 050489 MPU85-155TOSHIBA TMP8255A 5. 5.1 FUNCTIONAL DESCRIPTION The PPlis a programmable peripheral interface with three 8-bit ports (Port A, B and C) and two control registers. 24 I/O ports are divided into 12-bit group A and group B. Group A consists of Port A and high order 4 bits of Port C, while Group B consists of Port B and low order 4 bits of Port C. Each group is independently programmable by control words provided from MPU. There are three operation modes available for the PPI. In mode 0, two 8-bit I/O ports and two 4-bit I/O ports can be programmed as input or output ports, respectively. In mode 1, 24 I/O ports are divided into Group A and Group B. 8 bits of each group are used as input or output port and of the remaining 4 bits, 3 bits are used as handshaking and interrupt control signal. Mode 2 is applicable only to group A and the ports are used as a bidirectional 8-bit data bus and 5-bit control signal. In case of Port C being used as the output, any bits of Port C can be set/reset. There are two control registers; one is used for mode setting and the other for bit set/reset control. The control registers can only be written into. Further, when the reset input (RESET) becomes "1", the control registers are reset and all I/O ports are placed in input mode (high impedance status) . Table 5.1 Basic Operation of TMP8255A Ai | Ag | CS | RD | WR Function 0 0 0 0 1 Data bus < Porta 0 1 0 0 1 Data bus < PortB 1 0 0 0 1 Data bus < Portc Q 0 0 1 G Port A < Data bus 0 1 0 1 a) Port B < Data bus 1 0 0 1 0 Pertc < Data bus 1 1 0 1 0 Control register Data bus x x 1 x x Data bus = 3-state x x 0 1 1 Data bus = 3-state 1 1 0 0 1 inhibition of combination 050489 MODE SELECTION There are three basic modes of operation that can be selected by control words. Mode 0-Basic I/O (Group A, Group B) Mode 1-Strobe input/Strobe output (Group A, Group B) Mode 2-Two-way bus (Port A only) Operation modes for Group A and Group B can be independently defined by the control word from the MPU. If D7 is set to "1" in writing a control word into the PPI, on operation mode is selected, while of D7="0", the set/reset function for Port C is selected. MPU85-156TOSHIBA TMP8255A 5.1.1 Control word to define operation mode Figure 5.1 shows the control words to define operation mode of the TMP8255A. Control Word 1 Group A Condtol Group B Contral Dr | De | Ds | Da | D3 | D2 | Dr | Do Ld 1 = Designation of mode set flag Input/output selection of low order 4 bits of Port C O' = Output 1'= Input Input/output selection of PortB O' = Output 'q'= Input Mode selection of Group B 0'=ModeQ '1'=Made 1 Input/output selection of high order 4 bits of Port C 0 = Output "1" = Input input/output selection of PortA O' = Output {'=Input Mode Selection Group A 'O'=Mode 0 D6D5 00=Moded 01=Mode1 1x =Mode 2 x: Don't care 050489 Figure 5.1. Control Word for Mode Selection MPU85-157TOSHIBA TMP8255A 5.1.2 Port C bit set/reset control word Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset control word. Figure 5.2 shows the Port C bit set/reset control word. Control [Ward Lor | os | os | be [os [oe [os | bp | Don'tcare Bit set/reset flag O" = Active L Bit set/reset selection "0" = Reset "1" = Set o | o ] o | Peo] | 0 Q 1 PC, 0 1 0 PC? G 1 1 PC3 t Bitselectian 1 0 0 PCy 1 a 1 PCs 1 1 0 PCg 1 1 1 PC7 _| 050489 Figure 5.2 Control Word for Bit Set/Reset 5.2 OPERATION MODES 5.2.1 Mode Q (Basic I/O) This functional configuration is used for simple input or output operations. No handshaking' is required and data is simply written to or read from a specified part. Output data to the ports from MPU are latched out but input data from the ports are not latched. In Mode 0, 24 I/O ports are divided into four groups of Port A (8 BITS), Port B (8 bits), high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed to be input or output. The configuration of each port are determined according to the contents of Bit 4 (D4), 3 (D3), 1 (Dj) and 0 (Dp) of the control word for mode selection. The I/O configuration of each port in Mode 0 are shown in Table 5.2. MPU85-158TOSHIBA TMP8255A Node Setting Control Word Port A Partc Port B PortC Da D3 Dy Do (PC7~PCa) (PC3~PCg) 0 0 0 0 Out Out Out Out 0 GO 0 4 Out Out Out In 0 0 1 0 Out Cut In Out 0 0 1 1 Out Out In In 0 1 0 0 Out In Out Out 0 1 0 1 Out In Out In 0 1 i 0 Out In In Out 0 1 1 4 Out In In In 1 0 0 0 In Out Out Out 1 0 0 4 In Out Out in 1 0 1 0 In Out In Out 1 0 1 1 In Out In In 1 1 0 0 In In Gut Out 1 1 0 1 in In Out In 1 1 1 0 In In In Out 1 1 1 1 In In In In 050489 Figure 5.3 Port definition in Mode 0 5.2.2 Mode 1 (Strobe I/O) In Mode 1, input/output of port data is performed in conjunction with the strobe signals or handshaking signals. Port C is used ta control Port A or Port B. The basic operatings in Mode i are as follows: Mode 1 can be set for two groups of Group A and Group B. e Each group consist of 8-bit data port and 4-bit contral/data port. e The 8-bit data port can be set as input or output port. The control/data port is used as control or status of the 8-bit data port. (1) When used as the input port in Mode 1: e STB (Strobe Input) At"0", input data is loaded in the internal input latch in the port. In this case, a control signal from MPU is not concerned and data is input from the port any time. This data is not read out on the data bus unless MPU executes an input instruction. e IBF (Input Buffer Full F/F Output) When data is loaded in the internal input latch from the port, this output is set to"1". IBF is set ("1") by STB input being reset and is reset ("0") by the rising edge of RD input. MPU85-159TOSHIBA TMP8255A e INTR Unterrupt Request Output) Used for the interrupt process of data loaded in the internal input latch. When STB input is at "O" if INTE (INTE flag) in the PPI is in the enabled state ("1") , IBF is setto"1". INTRis set to "1" immediately after the rising edge of this STB input and reset to "0" by the falling edge of RD input. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PC, INTEB-Control by bit set/reset of PCo (2) When used as the output port in Mode 1: OBF (Output Buffer Full F/F Output) This ts a flag which shows that MPU has written data into a specified port. OBF is set to becomes "0" at the rising edge of WR signal and is set to "1" at the falling edge of ACK (Acknowledge input) signal. e ACK (Acknowledge Input) ACK signal is sent to the PP1 as a response from a peripheral device that received data from the port. e INTR Unterrupt Request Output) When a peripheral device received data from MPU, INTR is set to "1" and the interrupt is requested to MPU. If ACK signal is received when INTE flag is in the enable state, OBF is set to "1" and INTR signal becomes "1" immediately after the rising edge of ACK signal. Further, INTR is reset at the falling edge of WR signal when data is written into the PPI by MPU. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PCg INTEB-Control by bit set/reset of PCo MPU85-160TOSHIBA TMP8255A MODE 1 {PORT A) CONTROL WORD PAy~ Pay law Dr Dg Os Ds Ds De Oy Oy | LINE? [Peg STBA ~" [521 PCs | IBFA _ ope | oT PC3 [>> INTRA fo 0 = OUTPUT RD +d 5 las = INPUT PCg~ PC? 1/0 MODE 1 (PORT B) INTR __/t 8 RD CONTROL WORD PBy ~ PBg |e "\ / f Dy Dg Ds Dg Dy Dz Dy Dy (INTE?! pc, j< STRE | | ite tx[x[x[[ifx] |! petfec + see Neut x] PCy [> iINTRB 050489 Figure 5.4 Example of Strobe Input in Mode 1 MODE 1 (PORT A) CONTROL WORD PAz~ PAg bx? D7 Dg Ds Dg D3 Dz Dy Do PCy > OBFA ~ ACKA __ WR | PCa, PCs _.. t> INTRA BF = OUTPUT WRd 5 1 = |NPUT PCa~ PCs e150 ACK MODE 7 (PORT B) | CONTROL WORD PBz~ PBy 8 INTR D7 Dg Ds Da D3 D> Dd, Do bones PC OBFB xR Dp] |e ae ogy OUTPUT Xx INTRB 5 050489 Figure 5.5 Example of Strobe Output in Mode 1 MPU85-161TOSHIBA TMP8255A 38 8 PA] ~ PAg PO PAz~ PAg Ine WRdq PC; | > OBFA RD~+d PCy bS STBA CONTROL WORD PC, fe ACKA CONTROL WORD PCs [> IBFA D7 De Bs Da D3 Dz Dy Dp PC, | INTRA D7 Dg Ds Da D3 Dz Dy Do PC; INTRA [i fofa fo lvls fi tx] 2 pt fofais ffs jolx| 2 PCy ~ PCs be 1/0 PC, ~ PC7 be 1/0 8 8 PC4, PCy PB7 ~ PBg [<7 PC5, PCy PB ~ PBg [7 OQ = OUTPUT __ Q= OUTPUT 1 = INPUT RD PC2 i-- STBB 1 = INPUT WR q PC, t OBFB PC, >> IBFB PC |* ACKB PCg [> INTAB PCy [> INTRB PORT A (STROBE OUTPUT) PORT B (STROBE INPUT) Figure 5.6 Example of Port A output, Port B Input in Mode 1 5.2.3 Mode 2 (Strobed Bidirectional Bus I/O) In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a peripheral device. This mode is applicable only to Group A, which consists of an 8-bit bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The bidirectional bus (Port A) has both the internal input and output registers. When group A is set in Mode 2, Group B can be set independently. These are 5 control signals as follows when Group A is used in Mode 2. e BF (Output buffer Full F/F Output) When MPU writes data into of Port A, OBF is set to "0" to inform a peripheral device that the PPlis ready to output data. However, Port A is dept in the floating PORT A (STROBE INPUT) PORT B (STROBE OUTPUT) 050489 Figure 5.7 Example of Port Alnput, Port B Output in Mode 1 (high impedance) state until ACK input signal is received. e ACK (Acknowledge Input) When ACK signal is set to "0", the data of the 3-state output buffer of Port A is send out. If ACK signal is at "1", Port A is in the high impedance state. e STB (Strobe Input) When STB input is set to "0", the data from peripheral devices are held in the input latch. When the active RD signal is input into the PPI, the latched input data are output on the system data bus (D7-Dg) . MPU85-162TOSHIBA TMP8255A e IBF Unput Buffer Full F/F Output) When data from peripheral devices are held in the input latch, IBF is set to "1". INTR (Interrupt Request Output) INTR is the output to request the interrupt to MPU and its function is the same as that in Mode 1. There are two interrupt enable flip-flop (INTE), INTE1 corresponds to INTEA in Mode 1 output and INTE2 to INTEA in Mode 1 input. INTE 1-Used to generate INTR signal in conjunction with OBF and ACK signais, and is controlled by PC bit set/reset. INTE 2-Used to generate INTR signal in conjunction with IBF and STB signals, and is controlled by PC, bit set/reset. Figure 5.8 shows the operating example and the timing diagram in Mode 2. i GUTPUT DATA} = - Lf 050489 Figure 5.8 Operating example in Mode 2 MPU85-163TOSHIBA TMP8255A Control Word in Mode 2 Dy Dg Ds D4 D3 Dz Dy Do Pa [1] x |x |) x [a [i | | PCa~PCo 0 = Output x =Dont care 1 =|Input Port B 0 = Output 1=Input Group B mode 0=Moded 1=Mode i 050489 Figure 5.9 Control Word and Configuration in Mode 2 Control Words PC3 oe INTRA PA7~PAg eo PC7 [-~ OBFA PC6g h ACKA PC2~PCg = <____1 PCq |~ STBA O = Output PCs |[-> IBFA 1 = Input _>| PCa~PCg jar 1/0 _>| PB7~PBo k#> Port A - Mode 2 I/O Port B - Mode Otnput Contral Words PC3 - INTRA 8 PA7~PAg eo PC7 |-> OBFA PCg |< ACKA PCa4 |~_ STBA PCs |--> IBFA PB7~PBo LB PC, +> OBFB > PC |~ ACKB PCg -> INTRB D7 Deg Ds D4 D3 D2 Dy Do S| 3 a O Port A - Mode 2 I/O Port B - Made 1 Output 050489 Figure 5.10 Example in Combination with Mode 2 and Other Mode MPU85-164TOSHIBA TMP8255A 5.2.4 Pecautions for use in Mode 1 and 2 When used in Mode I and 2, bits which are not used as control or status in Port C can be used as follows. If programmed as the input, they are accessed by normal Port C read. If Programmed as the output, high order bits of Port C (PC7-PC4) are accessed using the bit set/reset function. As to low order bits of Port C (PC3-PCg), in additions ot access by the bit set/reset function, 3 bits only can be accessed by normal writing. 5.3. READING PORT C STATUS When Port C is used as the control port, that is, when Port C is used in Mode 1 or Mode 2, the status information of the control word can be read out by a normal read operation of Port C. Table 5.2 Status Word Format of Port C Data Mode D7 Dg Ds Da D3 D2 Dy Do Mode 1 Input i/O 170 IBEA INTEA | INTRA | iNTEB iBFB INTRB Mode i Qutput | OBFA | INTEA 1/0 1/0 INTRA | INTEB | OBFB | INTRB Mode 2 OBFA INTE1 IBFA INTE2 INTRA By Group B Mode 050489 MPU85-165TOSHIBA TMP8255A 6. ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS Symbol Item Rating Unit Vec Supply Voltage 0.5 to 7.0 Vv Vin Input Voltage -O0.5to Vcc + 7.0 Vv Pp Power Dissipation 1 W TSOLDER | Soldering Temperature (10sec) 260 c Tstc Strobe Temperature -65to +150 Cc TopR Operating Temperature Oto +70 c 050489 6.2 DC ELECTRICAL CHARACTERISTICS TA=0C to 70C, Vec =5V+5%, Vgg = OV SYMBOL ITEM TEST CONDITION MIEN. | TYP. | MAX. | UNIT VIL Input Low Voltage -0.5 _ 0.8 Vv Vin Input High Voltage 2.2 Vec Vv Vv Output Low Voltage (DB) lol =2.5mA _ - 0.45 Vv OL (PER) lo =1.7mA - - | 0945] v V Output High Voltage (DB) lon = -400pA 2.4 _ - Vv OH (PER) lou = - 200nA 24 | _ Vv lie Input Leak Current 0S Vin S Vee - _ +10 | pA Output Leak Current | . SV sv _ +7 OFL (High Impedance State) O= Vout Vec 0 pA (Note 1) . . VexT = 1.5V -1 _ -4. loaR Darlington Drive Current Rexr = 7502 0 40) mA lec Operating Supply Current vO cycle Time 1 _ _ 120 mA usec 050489 Note: Applied for optional 8 YO terminals in Port B and Port C. MPU85-166TOSHIBA TMP8255A 6.4 AC ELECTRICAL CHARACTREISTICS TA =0C to 70C, VCC =5V +5%, VSS = OV SYMBOL PARAMETER TMP Beosar UNIT MIN. MAX. tar Address set-up time for RD fall 0 _ ns tra Address hold time for RD rise 0 - ns tre RD pulse width 300 _ ns trp Delay from RD fall ta decided data output - 200 ns tor Time from RD rise to data bus floating 10 100 ns tay Time from RD or WR rise to next RD or WR fall 850 - ns taw Address set-up time for WR fali 0 _ ns twa Address holding time for WR rise 20 ns tww WR pulse width 300 _ ns tow Bus data set-up time for WR rise 100 ns twp Bus data holding time for WR rise 30 - ns twe Delay from WR rise to decided data output 350 ns tik Port data set-up time for RD fall 0 _ ns tHR Port data holding time for RD rise 0 - ns tAK ACK pulse width 300 ns tsT STB pulse width 500 - ns tes Port data set-up time for ST5 rise 8 - ns tH Port data holding time for 5TB rise 180 ~ ns taD Delay from ACK fall to decided data output _ 300 ns tko Time from ACK rise up to port (Port A in Mode2) floating 20 250 ns twos Delay from WR rise to OBF fall 650 ns taos Delay from ACK fali to OBF rise - 350 ns tsiB Delay from STB fal! to IBF rise 300 ns tris Delay from RD fall to IBF rise 300 ns trit Delay from RD fall to INTR fall - 400 ns tsIT Delay from ACK rise to INTR rise - 300 ns taIT Delay from ACK rise to INTR rise _ 350 ns tWIT Delay from WR rise to INTR fall 450 ns 050489 Note: 1. When the power supply is turned ON, reset pulse duration must be active for at 2. AC Measuring Point Input Voltage least 500 ns or more. CL=150pF. Vira 2.0V, Viz =0.8V Output Voltage Vou =2.0V, VoL=0.8V MPU85-167TOSHIBA TMP8255A 6.4 CAPACITANCE TA=25C, Veco =Vs5 = OV SYMBOL ITEM TEST CONDITION MIN. | TYP. | MAX. | UNIT Cin Input Capacitance fo = 1MHz _ 10 pF CuO \/O Capacitance (*) 20 pF 050489 *: All terminals except that to be measured should be earthed, MPU85-168TOSHIBA TMP8255A 7. TIMING DIAGRAM MODE 0 INPUT OPERATION MODE 0 OUTPUT OPERATION tww WR D7~Do CS, Ai, Ao OUTPUT MODE 7 INPUT OPERATION tps tp > INPUT PORT a DATA { tsT STB C . tsiB IBF -<tsIT ~<-tRiB INTR j <trit RD Se ERR 050489 Figure 7.1 Timing diagram MPU85-169TOSHIBA TMP8255A MODE 1 OUTPUT OPERATION < tww >| Kc WR t " twit x twos SALT INTR FF i twe Ww OUTPUT + PORT DATA x 5 om ee OBF \1,-J __ t ACK iy AK yp LY MODE 2 BIDIRECTION OPERATION yw Op r r WR twit tsi iNTR Af ge al twog le trop OBF 5 < ! VF a iy LAK TH ay 1 ACK we t t tps teH fA KD PERIPHERAL ~~~ ~=-f } =f eee ewe BUS tsT it (6 _ _ OO yf i We STB tsip IBF {\ if trig RD = A 4 tRR Figure 7.2. Timing diagram 050489 MPU85-170TOSHIBA TMP8255A 8. PACKAGE DIMENSION 8.1 PLASTIC PACKGE DIP40-P-600 Unit: mm 40 21 Para ran PA ees an oo ean an oo ea ea en ~~ O- 15 13.440.2 Doom aoa ST oo daa aaa 1 20 +0.1 saffo2s ~0.05 50.7 +0.2 +1 1.22TYP 270289 Note: Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoretical positions with respect to No.1 and No.40 leads. MPU85-171