Integrated Circuit Systems, Inc. ICS9248-127 Frequency Generator & Integrated Buffers for PENTIUM/ProTM General Description Features The ICS9248-127 is the single chip clock solution for Desktop designs using the VIA MVP4 and Aladdin 7 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248127 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. * * * * * Up to 124MHz frequency support. Spread Spectrum for EMI control 0 to -0.5% down spread and 0.25% center spread Serial I2C interface for Power Management, Frequency Select, Spread Spectrum. Provides the following system clocks - 4-CPUs @ 3.3V, up to 124MHz. - 13-SDRAMs @3.3V, up to 124MHz (including SDRAM_F) - 6-PCI (including 1 free running, PCICLK_F) @3.3V, CPU/2 or CPU/3. - 1-24MHz @3.3V fixed. - 1-48MHz @3.3V fixed. - 2-REF @3.3V, 14.318MHz. Efficient Power management scheme through PCI and STOP CLOCKS. Block Diagram 48MHz 24MHz /2 X1 X2 XTAL OSC 2 REF (1:0) BUFFER IN CPUCLK_F PLL1 Spread Spectrum FS(3:0) MODE 4 STOP STOP LATCH 3 12 CPUCLK (2:0) SDRAM (11:0) SDRAM_F 4 POR CLK_STOP# PCI_STOP# Control Logic SDATA SCLK PCI CLOCK DIVDER STOP 5 PCICLK (4:0) PCICLK_F Config. Pin Configuration VDDREF *PCI_STOP#/REF0 GND X1 X2 VDDPCI *MODE/PCICLK_F *FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI BUFFER IN GND SDRAM11 SDRAM10 VDDSDR SDRAM9 SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS9248-127 PLL2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS2* VDDCPU CPUCLK_F CPUCLK0 GND CPUCLK1 CPUCLK2 CLK_STOP# GND SDRAM_F SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 VDD48 48MHz/FS0* 24MHz/FS1* Reg. 48-Pin SSOP * Internal Pull-up Resistor of 240K to VDD Power Groups VDDCPU, GNDCPU = CPUCLKS, CPUCLK_F VDDSDR, GNDSDR = SDRAMCLKS, SDRAM_F VDDPCI, GNDPCI = PCICLKS, PCICLK_F VDD48 = 48MHz, 24MHz VDDREF, GNDREF = REF, X1, X2 9248-127 Rev C 8/18/00 Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-127 Pin Descriptions PIN NUMBER P I N NA M E 1, 6, 14, 19, 27, 30, VDD 36, 47 REF0 TYPE PWR OUT 2 PCI_STOP#1 3,9,16,22, 33,40,44 GND IN PWR 4 X1 IN 5 X2 OUT PCICLK_F OUT 7 8 13, 12, 11, 10 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 23 24 25 26 MODE1, 2 IN FS31 IN PCICLK0 OUT PCICLK (4:1) OUT BUFFER IN SDRAM (11:0) I/O IN 24MHz OUT FS1 1, 2 48MHz FS0 1, 2 SDRAM_F 41 CLK_STOP# 46 48 OUT SDATA SCLK 39 42, 43, 45 IN IN OUT IN OUT DESCRIPTION 3.3V power supply 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Free running PCI clock not affected by PCI_STOP# for power management. pin 2 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew (CPU early) PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant 24MHz output clock Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input CPUCLK (2:0) OUT Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK & SDRAM at logic "0" level when driven low. CPU clock outputs, powered by VDDCPU CPUCLK_F REF1 FS21, 2 OUT OUT IN Free running CPU clock. Not affected by the CPU_STOP# 14.318 MHz reference clock. Frequency select pin. Latched Input IN Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9248-127 Mode Pin - Power Management Input Control MODE (Latched Input) Pin 2 PCI_STOP# (Input) REF0 (Output) 0 1 Functionality VDD1,2,3 = 3.3V5%, TA=0 to 70C Crystal (X1, X2) = 14.31818MHz FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 124.00 120.00 114.99 109.99 105.00 83.31 80.00 75.00 100.00 95.19 83.31 97.00 90.00 70.00 66.82 60.00 PCI (MHz) 41.33 40.00 38.33 36.66 35.00 41.65 40.00 37.50 33.33 31.73 27.77 32.33 30.00 35.00 33.41 30.00 3 ICS9248-127 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Bit 7 Bit [2, 6:4] Bit 3 Bit 1 Bit 0 Description 0 - 0.25% Center Spread Spectrum Modulation 1 - 0 to -0.5% Down Spread Spectrum Modulation CPUCLK PCICLK Bit [2, 6:4] (MHz) (MHz) 0000 124.00 41.33 0001 120.00 40.00 0010 114.99 38.33 0011 109.99 36.66 0100 105.00 35.00 0101 83.31 41.65 0110 80.00 40.00 0111 75.00 37.50 1000 100.00 33.33 1001 95.19 31.73 1010 83.31 27.77 1011 97.00 32.33 1100 90.00 30.00 1101 70.00 35.00 1110 66.82 33.41 1111 60.00 30.00 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit [2, 6:4] 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD 1 Note1 0,010 0 Note 2 1 0 Note 1. Default at Power-up will be for latched logic inputs to define frequency. I2C readback of the power up default indicate the revision ID code in bit 2, 6:4 as shown. Note 2. To ensure normal operation, Bit 7 needs to be "0" when in non - spread spectrum mode (Bit 1 = 0). Note: PWD = Power-Up Default. I2C is a trademark of Philips Corporation 4 ICS9248-127 Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 46 39 42 43 45 PWD X 1 1 1 1 1 1 1 Description Latched FS2# CPUCLK_F (Act/Inact) (Reserved) (Reserved) SDRAM_F (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 13 12 11 10 8 PWD X 1 1 1 1 1 1 1 Description Latched FS0# PCICLK_F (Act/Inact) (Reserved) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact) Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 17 18 20 21 28 29 31 32 PWD 1 1 1 1 1 1 1 1 Description SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 5 ICS9248-127 Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - PWD 1 1 1 1 X 1 X 1 Description (Reserved) (Reserved) (Reserved) (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved) Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 35 37 38 26 25 48 2 PWD 1 1 1 1 1 1 1 1 Description SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) 48MHz (Act/Inact) 24MHz (Act/Inact) REF1 (Act/Inact) REF0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 6 ICS9248-127 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAM ETER Input High Voltage Input Low Voltage Supply Current Input frequency Input Capacitance 1 Transition Time 1 Settling Time 1 Clk Stabilization Skew 1 1 1 SYM BOL VIH VIL IDD3 .3 Fi C IN C INX T tran s CONDITIONS C L = 0 pF; Select @ 66M VDD = 3.3 V; Logic Inputs X1 & X2 pins M IN 2 VSS -0.3 27 To 1st crossing of target Freq. Ts From 1st crossing to 1% target Freq. T STAB T CPU-BUS From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; Guarenteed by design, not 100% tested in production. 7 TYP MAX UNITS VDD+0.3 V 0.8 V 77 180 mA 14.318 M Hz 5 pF 36 45 pF 1.5 3 ms ms 1.0 2.2 3 ms 4.0 ns ICS9248-127 Electrical Characteristics - CPU T A = 0 - 70C; VDD=3.3V +/-5%; CL = 20 pF (unles s otherwis e s pecified) PA RA M ETER SYM BOL Output Impedance RD SP 2 B Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time 1 1 Duty Cycle 1 Skew window 1 Jitter, Cycle-to-cycle 1 1 1 CONDITIONS M IN TYP M A X UNITS Vo=VD D *(0.5) 10 20 Vo=VD D *(0.5) IO H = -12 mA IO L = 12 mA VO H = 1.7 V VO L = 0.7 V 10 2.0 20 V V mA mA t r2 B RD SN 2 B VO H 2 B VO L 2 B IO H 2 B IO L 2 B 1 0.4 -19 19.0 2.3 0.2 -41 37.0 VO L = 0.4 V, VO H = 2.4 V 0.4 1.28 2.0 ns t f2 B VO H = 2.4 V, VO L = 0.4 V 0.4 1.49 2.0 ns d t2B VT = 1.5 V 48.0 54.8 58.0 % t sk 2 B VT = 1.5 V 222 250 ps t jcyc-cy c2 B VT = 1.5 V 152 250 ps Guaranteed by des ign, not 100% tes ted in production. Electrical Characteristics - 24MHz, 48MHz, REF T A = 0 - 70C; VD D =3.3V +/-5%; CL = 20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time 1 1 Duty Cycle 1 Jitter 1 1 SYM BOL RD SP 5 1 RD SN 5 VO H 5 VO L 5 IO H 5 IO L 5 1 CONDITIONS M IN TYP M A X UNITS Vo=VD D *(0.5) 20 60 Vo=VD D *(0.5) IO H = -14 mA IO L = 6.0 mA VO H = 2.0 V VO L = 0.8 V 20 2.4 60 V V mA mA 10 2.9 0.25 -42 18 0.4 -20 t r5 VO L = 0.4 V, VO H = 2.4 V 1.74 4.0 ns t f5 VO H = 2.4 V, VO L = 0.4 V 2.05 4.0 ns d t5 VT = 1.5 V, 53.2 55 % t jab s5 VT = 1.5 V 307 800 ps 45 Guaranteed by des ign, not 100% tes ted in production. 8 ICS9248-127 Electrical Characteristics - PCI TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN1 VOH1 VOL1 IOH1 IOL1 TYP Vo=VDD*(0.5) 12 23 55 Vo=VDD*(0.5) IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V 12 2.4 20 2.9 0.2 -58 52 55 V V mA mA 25 MAX UNITS 0.4 -22 tr1 VOL = 0.4 V, VOH = 2.4 V 1.38 2.0 ns 1 tf1 dt1 VOH = 2.4 V, VOL = 0.4 V 1.65 2.0 ns 51.1 55 % VT = 1.5 V 236 500 ps VT = 1.5 V 214 500 ps 1 Duty Cycle Skew window1 VT = 1.5 V tsk1 tjabs1 Jitter 1 1 MIN 1 Rise Time Fall Time 1 1 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM T A = 0 - 70C; VD D =3.3V +/-5%; CL = 30 pF (unless otherwise specified) PA RA M ETER SYM BOL Output Impedance RD SP 2A Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time 1 Duty Cycle 1 Skew W indow 1 1 Skew (Buffer-In to SDRA M ) 1 CONDITIONS M IN Vo=VD D *(0.5) 10 Vo=VD D *(0.5) IO H = -28 mA IO L = 19 mA VO H = 2.0 V VO L = 0.8 V 10 2.4 t r2A RD SN 2A VO H 2A VO L2A IO H 2A IO L 2A 1 1 1 TYP M A X UNITS 20 20 V V mA mA 0.4 -42 33 2.8 0.3 -72 50 VO L = 0.4 V, VO H = 2.4 V 0.5 0.97 1.6 ns t f2A VO H = 2.4 V, VO L = 0.4 V 0.5 1.07 1.6 ns d t2A VT = 1.5 V 45 49.1 55 % t sk2A VT = 1.5 V 145 250 ps t sk2A VT = 1.5 V 3.5 5 ps Guaranteed by design, not 100% tested in production. 9 ICS9248-127 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 10 ICS9248-127 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS9248127 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 11 ICS9248-127 CLK_STOP# Timing Diagram CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-127. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High) IOAPIC SDRAM CPUCLK CPUCLK _F SDRAM_F Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-127. 3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low. 4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-127 CLK_STOP# signal. SDRAM (0:11) are controlled as shown. 5. All other clocks continue to run undisturbed. 12 ICS9248-127 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9248-127. It is used to turn off the PCICLK [4:0] clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-127 internally. The minimum that the PCICLK [4:0] clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK [4:0] clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. CPUCLK (Internal) PCICLK_F (Internal) PCICLK_F (Free-running) CPU_STOP# PCI_STOP# PCICLK Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. 13 ICS9248-127 SYMBOL In Millimeters COMMON DIMENSIONS MIN MAX In Inches COMMON DIMENSIONS MIN MAX A 2.413 2.794 .095 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS .005 .010 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e 0.635 BASIC h 0.381 L 0.508 1.016 SEE VARIATIONS N 0.635 0 .110 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 8 0 8 MIN MAX MIN MAX 28 9.398 9.652 .370 .380 34 11.303 11.557 .445 .455 48 15.748 16.002 .620 .630 56 18.288 18.542 .720 .730 64 20.828 21.082 .820 .830 VARIATIONS N D mm. D (inch) Ordering Information ICS9248yF-127-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 14 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.