(INTERSIL ICL7135 Precision 412 Digit Single Chip A/ D Converter FEATURES Accuracy guaranteed to +1 count over entire +20,000 counts (2.0000 voits full scale) Guaranteed zero reading for 0 volts input 1 pA typical input current True differential input True polarity at zero count for precise null detection Single reference voltage required Over-range and under-range signals available for auto-ranging capability All outputs TTL compatible Blinking display gives visual indication of over- range Six auxillary inputs/outputs are available for interfacing to UARTs, microprocessors or other complex circuitry @ Multiplexed BCD output versatility GENERAL DESCRIPTION The Intersil 1CL7135 precision A/D converter, with its multiplexed BCD output and digit drivers, combines dual- slope conversion reliability with +1 in 20,000 count accuracy and is ideally suited for the visual display DVM/DPM market. The 2.0000V full scale capability, auto-zero and auto-polarity are combined with true ratiometric operation, almost ideal differential linearity and true differential input. All necessary active devices are contained on a single CMOS I.C., with the exception of display drivers, reference, and a clock. The Intersil iCL7135 brings together an unprecedented combination of high accuracy, versatility, and true economy. High accuracy like auto-zero to less than 10V, zero drift of less than 1uV/C, input bias current of 10 pA max., and rollover error of less than one count. The versatility of multiplexed BCD outputs is increased by the addition of several pins which allow it to operate in more sophisticated systems. These include STROBE, OVERRANGE, UNDER- RANGE, RUN/HOLD and BUSY lines, making it possible to interface the circuit to a microprocessor or UART. Veer IN ANALOG GND 100k: 1CL7135, + SIGNAL INPUT 0.1 nF DISPLAY ANODE hPaoeadc ft tt DRIVER TRANSISTORS SEVEN SEG. DECODE 1CL7135 with LED Display ORDERING INFORMATION Part Package Temp. Range | Order Part # 7135 | 28-Pin CERDIP 0C to +70C | ICL7135CUI 7135 | 28-Pin Plastic DIP | 0C to +70C | ICL7135CPI PIN CONFIGURATION [28] UNDERRANGE [27] OVERRANGE ANALOG COMMON [3] (26) STROBE INT out [4] [25] A/H AZIN [5] [24] DIGITAL GND BUFF OUT [6] [23] POL REF. CAP. ~ 1CL7135 [22] CLOCK IN REF. CAP.* BUSY wwro [a] (Outline fq] (iso) v1 nut fio] OW JI PN) Fig) be vt 118] D3 (MSD) D5 [12] D4 (LSB) B1 [13] 16] (MSB) B8 B2 [14] ris] B4 4-58ICL7135 (INTERSIL ABSOLUTE MAXIMUM RATINGS Power Dissipation (Note 2) Supply Voltage V7 oo... cece cece eee eee nen cee +6V Ceramic Package .....-..... ccc cee eee eens 1000 mW Vo cece eee cece nee e ec enneees -9V Plastic Package ........... ccc eee e eee eens 800 mW Anatog Input Voitage (either input) (Note 1) ..... Vt to V7 Operating Temperature ..............005. 0C to +70C Reference Input Voltage (either input) .......... Vt to V7 Storage Temperature .............005 -65C to +160C Clock Input oo... cece eee cree eee e eens Gnd to V* Lead Temperature (Soldering, 10 sec) ............ 300C: Note 1: input voltages may exceed the supply voltages provided the input current is limited to +1004A. Note 2: Dissipation rating assumes device is mounted with ali teacls soldered to printed circuit board. "COMMENT: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the devices. This is a stress rating only and functional operation of the devices at these or any other conditions above those indicated in the operational sections of the specifications is not implid. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ICL7135 ELECTRICAL CHARACTERISTICS (Note 1) Vt=+-5V, V7 = 5V, Ta = 25C, Clock Frequency Set for 3 Reading/Sec CHARACTERISTICS SYMBOL CONDITIONS MIN TYP MAX UNITS A Zero Input Reading Vin = 0.0V -~0.0000 | +0.0000 } +0.0000 | Digital N Full Scale = 2.000V Reading A Ratiometric Reading (2) Vin = VREF +0.9998 | +0.9999 | +1.0000 | Digital L : Full Scale = 2.000V Reading Oo Linearity over + Full Scale Digital G (error of reading from -2V < Vins +2V 0.5 1 Count best straight line) Error Differential Linearity (difference between worse -2V < Vin S +2V 01 LSB case step of adjacent counts and ideal step) Rollover error (Difference in : Digital reading for equal positive & Vin = +Vin = 2V 0.5 1 Count negative voltage near full scale) Error (Note 1) | Noise (P-P value not en Vin = OV (Note 2) | exceeded 95% of time) Full scale = 2.000V 15 uV Leakage Current at Input IitK Vin = OV 1 10 pA Zero Reading Drift L Vin = OV 0.5 2 pV 0 < Ta = 70C Scale Factor Temperature Te . Vin = +2V Coefficient (3) 0=Ta=70C 2 5 ppm/C (ext. ref. 0 ppm/C) INPUTS} Clock in, Run/Hold; See Fig. 2 line Vin =0 0.02 0.1 mA tINH Vin = +5V 0.1 10 pA oO All Outputs VoL lo. = 1.6ma 0.25 0.40 Vv D U Bi, Ba, Ba, Bs VoH lon = ~1mMA 2.4 4.2 Vv T Di, D2, D3, D4, Ds G Pp BUSY, STROBE, Vou lon = -10KA 49 4.99 : Vv 1 U OVER-RANGE, UNDER-RANGE| r T POLARITY Ss A Ss +5V Supply Range vr : +4 +5 +6 v L U ~-5V Supply Range : vo 3 -5 -8 Vv P +5V Supply Current r fo =0 11 3.0 mA P -8V Supply Current r fe = 0 . 08 3:0 L Y Power Dissipation Capacitance Cpp vs. Clock Freq 40 pF Clock} Clock Freq. (Note 4) DC 2000 1200 kHz Note 1: Tested in 4-1/2 digit (20,000 count) circuit shown in Fig. 1, clock frequency 120kHz: Note 2: Tested with a low dielectric absorption integrating capacitor. See Component Selection Section. Note 3: The temperature range can be extended to +70C and beyond as long as the auto-zero and reference capacitors are increased to absorb the higher leakage of the 1CL7135. Note 4: This specification reiates to the clock frequency range over which the ICL7135 will correctly perform its various functions. See Max Clock Frequency betow for limitations on the clock frequency range in a system. 4-591CL7135 TEST CIRCUIT SET Vrer = 1.000V -5V Veer IN oS 100kn: v" REFERENCE ANALOG GND UNDERRANGE [26} OVERRANGE [27] o ANALOG GND 100Kk1) o_| ov Figure 1: 7135 Test Circuit DETAILED DESCRIPTION Analog Section Figure 3 shows the Block Diagram of the Analog Section for the ICL7135. Each measurement cycle is divided into four phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT), (3) deintegrate (DE) and (4) zero integrator (ZI). 1. Auto-zero phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor Caz to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10uV. 2. Signal Integrate phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and CLOCK IN 120kHz INTERSIL vt | >>. DIG GND Figure 2: 7135 Digital Logic Input low are connected to the external pins. The converter then integrates the differential voltage between IN HI and iN LO for a fixed time. This differential voltage can be within a wide common mode range; within one volt of either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common-mode voltage. At the end of this phase, the polarity of the integrated signal is latched into the polarity F/F. 3. De-Integrate phase The Third phase is de-integrate, or reference integrate. In- put Low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed wn) is 10,000 ( VrReF wt Rint Caz Cint + AUTO Crer BUFFER v ZERO INT om ee ---@ _ Se cm cre re ae ee ee 7 6 41 5 4 INTEGRATOR Oya + ZERO- + crc AZ INPUT DETECTOR HIGH A/z T inn G2 &) y COMPARATOR (NT Z-l POLARITY Li FF AZ INPUT Low ANALOG 3 common 4 9 INT A/Z ~ DE(z) + ZI IN LO o" _&} ; Figure 3: Analog Section of ICL7135 4-601CL7135 4. Zero Integrator phase The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, a feedback loop is closed around the system to input high to cause the in- tegrator output to return to zero. Under norma! condition, this phase lasts from 100 to 200 clock pulses, but after an overrange conversion, it is extended to 6200 clock pulses. Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically from 0.5 volts below the positive supply to 1.0 volt above the negative supply. In this range the system hasa CMRR of 86 dB typical. However, since the integrator also swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common- mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the recommended 4V full scale swing with some loss of accuracy. The integrator output can swing within 0.3 volts of either supply without loss of linearity. Analog COMMON Anatog COMMON is used as the input low return during auto- zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in most applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The reference voltage is referenced to analog COMMON. Reference The reference input must be generated as a positive voltage with respect to COMMON, as shown in Fig. 4. vt vt 6.8 VOLT ZENER - REF HI : ICL8069 I 7138 REF H av 7135 REFERENCE common} t | Wz $ COMMON > = 2 = a: (a) {b) Figure 4: Using an External Reference INTERSIL DETAILED DESCRIPTION Digital Section Figure 5 is the Digital Section of the 7135. Itis identical to the 71C03 except that the 4-1/2/3-1/2 digit pin has been eliminated (mask-option; consult factory). The 7135 includes several pins which allow it to operate conveniently in more sophisticated systems. These include: 4. RUN/HOLD (Pin 25). When high (or open) the A/D will free- run with equally spaced measurement cycles every 40,002 clock pulses. if taken low, the converter will continue the full measurement cycle that it is doing and then hold this reading as long as R/H is held low. A short positive pulse (greater than 300ns) will now initiate a new measurement cycie, beginning with between 9,001 and 10,001 counts of auto zero. If the pulse occurs before the full measurement cycle (40,002 counts) is completed, it will not be recognized and the converter will simply complete the measurement it is doing. An external indication that a full measurement cycle has been completed is that the first strobe pulse (see beiow) will occur 101 counts after the end of this cycle. Thus, if Run/Hold is iow and has been tow for at least 101 counts, the converter is holding and ready to start a new measurement when pulsed high. 2. STROBE (Pin 26). This is a negative going output pulse that aids in transferring the BCD data to external latches, UARTs or microprocessors. There are 5 negative going STROBE pulses that occur in the center of each of the digit drive pulses and occur once and only once for each measurement cycle starting 101 pules after the end of the full measurement cycle. Digit 5 (MSD) goes high at the end of the measurement cycle anc stays on for 201 counts. in the center of this digit pulse (to avoid race conditions between changing BCD and digit drives) the first STROBE pulse goes negative for 1/2 clock pulse width. Similarly, after digit 5, digit 4 goes high (for 200 clock pulses) and 100 pulses later the STROBE goes negative for the second time. This continues through digit 1 (LSD) when the fifth and last STROBE pulse is sent. The digit drive will continue to scan (unless the previous signal was overrange) but no additional STROBE pulses will be sent until a new measurement is available. CONTROL LOGIC ve Potarity |ps oa. |p D2 4 pt 1 23 12 7 18 {19 P20 1 [Mise Tse L361 ANALOG 1482 SECTION MULTIPLEXER 5? Ba 16,88 J | POLARITY | FF LATCH}-[LATCcH}-{LaTcH}+[LaTcH}-[LaTcH] = | ZERO | CROSS. | COUNTERS | | DET. t | | { | | J mle _e FE _E__#F_#=__F__#.. DIGITAL CLOCK RUN/ OVER GND IN HOLD RANGE UNDER STROBE BUSY RANGE Figure 5: Digital Section 7135 4-611CL7135 3. BUSY (Pin 21). BUSY goes high at the beginning of signal integrate and stays high until the first clock pulse after zero- crossing (or after end of measurement in the case of an over- range). The internal latches. are, enabled (i.e., loaded) during the first clock pulse after busy and are latched at the end of this clock pulse. The circuit automatically reverts to auto-zero when not BUSY, so it may also be considered a (21+ AZ) signal. A very simple means for transmitting the data down a single wire pair from a remote location would be to AND BUSY with clock and subtract 10,001 counts from the number of pulses received - as mentioned previously there is one NO-count pulse in each reference integrate cycle. 4. OVER-RANGE (Pin 27). This pin goes positive when the input signal exceeds the range (20,000) of the converter. The output F-F is set at the end of BUSY andis reset to zero at the beginning of Reference integrate in the next measurement cycle. 5, UNDER-RANGE (Pin 28). This pin goes positive when the reading is 9% of range or less. The output F-F is set at the end of BUSY -(if the new reading is 1800 or less) and is reset at the beginning of signal integrate of the next reading. 6. POLARITY (Pin 23). This pin is positive for a positive input signal. It is valid even for a zero reading. In other words, +0000 means the signal is positive but less than the least significant bit. The converter can be used as a null detector by forcing equal frequency of (+) and (-) readings. The null at this point should be less than 0.1 LSB. This output becomes valid at the beginning of reference integrate and remains correct until it is re-validated for the next measurement. 7. .Digit Drives (Pins 12, 17, 18, 19 and 20). Each digit driveis a positive going signal that lasts for 200 clock pulses. The scan sequence is Ds (MSD), Da, D3, D2 and D; (LSD). All five digits are scanned and this scan is continuous unless an over-range occurs. Then all digit drives are blanked from the end of the strobe sequence until the beginning of Reference Integrate when Ds will start the scan again. This can give a blinking display as a visual indication of over-range. 8. BCD (Pins 13, 14, 15 and 16). The Binary coded Decimal bits Bg, B4, B2 and Bi are positive logic signals that go on simultaneously with the digit driver signal. COMPONENT VALUE SELECTION For optimum performance of the analog section, care must be taken in the selection of values for the integrator capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to suit the particular application. Integrating Resistor The integrating resistor is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor. Both the buffer amplifier and the integrator have a class A output stage with 100uA of quiescent current. They can supply 20uA of drive current with negligible non-linearity. Values of 5 to 40uA give good results, with a nominal of 20uA, and the exact vaiue of integrating resistor may be chosen by full scale voltage Rint = 20nA 4-62 INTERSIL Integrating Capacitor The product of integrating resistor and capacitor should be selected to give the maximum voitage swing which ensures that the tolerance build-up will not saturate the integrator swing (approx. 0.3 volt from either supply). For +5 volt supplies and analog COMMON tied to supply ground, a+3.5 to +4 volt full scale integrator swing is fine, and 0.10uF is nominal. In general, the value of Cint is given by {10,000 x clock period) >< lint integrator output voltage swing (10,000) (clock period) (20,A) integrator output voltage swing Cint = Avery important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent roll-over or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale 0.9999, and any deviation is probably due to dielectric absorption. Poly- propylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in Jess critical applications. INTEGRATOR OUTPUT AUTO- SIGNAL REFERENCE BEN [CSRS 72800 cou COUNTS MAX. FULL MEASUREMENT CYCLE. 40,002 COUNTS oo OVER-RANGE WHEN APPLICABLE UNDER-RANGE WHEN APPLICABLE | EXPANDED SCALE | BELOW DIGIT SCAN Fy n TL_: FOR OVER-RANGE J l J 1 J lL Da f lL rn J 1 Ds JL_sj1___S oz ny D: . fesoaarea *FIRST Ds OF AZ AND _ REF INT.ONE COUNT LONGER STROBE TTTTT AUTO ZERO REFERENCE piait scan SIGNAL INTEGRATE >= INTEGRATE a D: FOR OVER-RANGE! Lom =! 12 T1 Tr 1 im io 122 rn PL ne nr Figure 6: Timing Diagram for Outputs1CL7135 Auto-Zero and Reference Capacitor The size of the auto-zero capacitor has some influence on the noise of the system, a large capacitor giving less noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. The dielectric absorption of the reference cap and auto-zero cap are only important at power-on or when the circuit is recovering from an overload. Thus, smaller or cheaper caps can be used here if accurate readings are not required for the first few seconds of recovery. Reference Voltage The analog input required to generate a full-scale output is Vin = 2 VREF. The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high quality reference be used where high-accuracy absolute measurements are being made. Rollover Resistor and Diode A small rollover error occurs in the 7135, but this can be easily corrected by adding a diode and resistor in series be- tween the INTegrator OUTput and analog COMMON or ground. The value shown in the schematics is optimum for the recommended conditions, but if integrator swing or clock frequency is modified adjustment may be needed. The diode can be any silicon diode, such as a 1N914. These com- ponents can be eliminated if rollover error is not important, and may be altered in value to correct other (small) sources of rollover as needed. Max Clock Frequency The maximum conversion rate of most dual-slope A/D con- verters is limited by the frequency response of the com- parator. The comparator in this circuit follows the integrator ramp with a 3ys delay, and at a clock frequency of 160kHz (6us period) haif of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50xV input, 1 to 2 with 150,V, 2 to3 at 250uV, etc. This transition at mid-point is considered desirable by most users; however, if the clock frequency is increased appreciably above 160kHz, the instrument will flash 1 on noise peaks even when the input is shorted. For many-dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the non-linearity and noise do not in- crease substantially with frequency, clock rates of up to ~1MHz may be used. For a fixed clock frequency, the extra count or counts caused by comparator delay will be a con- stant and can be subtracted out digitally. The clock frequency may be extended above 160kHz without this error, however, by using a low value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a smal! pedestal voltage on to the integrator out- put at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by approximately a fac- tor of 3. At higher frequencies, ringing and second order breaks will cause significant nonlinearities in the first.few counts of the instrument - see Application Note A017. The minimum clock frequency is established by leakage on the auto-zero and reference caps. With most devices, mea- surement cycles as long as 10 seconds give no measurable leakage error. 4-63 INTERSIL To achieve maximum rejection of 60Hz pickup, the signal in- tegrate cycle should be a multiple of 60Hz. Oscillator fre- quencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz, 40kHz, 33 /akHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 250kHz, 16674kHz, 125kHz, 100kHz, etc. would be suitable. Note that 100kHz (2.5 readings/second) will reject both 50 and 60Hz. The clock used should be free from significant phase or fre- quency jitter. Several suitable low-cost oscillators are shown in the Applications section. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. Zero-Crossing Flip-Flop The flip-flop interrogates the data once every clock pulse after the transients of the previous clock pulse and haif-clock pulse have died down. False zero-crossings caused by clock pulses are not recognized. Of course, the flip-flop delays the true zero-crossing by up to one count in every instance, and if a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of phase 3. This one-count delay compensates for the delay of the zero-crossing flip-flop, and allows the correct number to be latched into the display. Similarly, aone-count delay at the beginning of phase 1 gives an overtoad display of 0000 instead of 0001. No delay occurs during phase 2, so that true ratiometric readings result. EVALUATING THE ERROR SOURCES Errors from the ideal cycle are caused by: 1. Capacitor droop due to leakage. 2. Capacitor voltage change due to charge suck-out (the reverse of charge injection) when the switches turn off. . Non-linearity of buffer and integrator. . High-frequency limitations of buffer, integrator and comparator. . Integrating capacitor non-linearity (dielectric absorption.) . Charge lost by Crer in charging Cstray. . Charge lost by Caz and Cint to charge Cstray. Each of these errors is analyzed for its error contribution to the converter in application notes listed on the back page, specifically A017 and A032. NOOO Pwo NOISE The peak-to-peak noise around zero is approximately 15.V (pk-to-pk value not exceeded 95% of the time). Near full scale, this value increases to approximately 304V. Much of the noise originates in the auto-zero loop, and is proportional to the ratio of the input signal to the reference. ANALOG AND DIGITAL GROUNDS Extreme care must be taken to avoid ground loops in the layout of ICL7135 circuits, especially in high-sensitivity cir- cuits. It is most important that return currents from digital loads are not fed into the analog ground line. POWER SUPPLIES The 7135 is designed to work from +5V supplies. However, in selected applications no negative supply is required. The conditions to use a single +5V supply are: 1. The input signal can be referenced to the center of the common mode range of the converter. 2. The signal is less than + 1.5 volts. See differential input for a discussion of the effects this will have on the integrator swing without loss of linearity.ICL7135 TYPICAL APPLICATIONS The circuits which follow show some of the wide variety.of possibilities, and serve to illustrate the exceptional versatility of this A/D converter. Figure 7 shows the complete circuit for a 4-1/2 digit (2,000V) full scate) A/D with LED readout using the ICL8069 as a 1.2V temperature compensated voitage reference. It uses the band-gap principal to achieve excellent stability and low noise at reverse currents down to 50uA. The circuit also shows a typical R-C input filter. Depending on the application, the time-constant of this filter can be made faster, slower, or the filter deleted completely. The 1/2 digit v" AEFERENCE ANALOG GND (INTERSIL LED is driven from the 7 segment decoder, with a zero reading blanked by connecting a D5 signal to RBI input of the decoder. The 2-gate clock circuit should use CMOS gates to maintain good power supply rejection. Figure 8 is similar except the output drives a multiplexed common cathode LED Display with the 7-Common Emitter Transistor Array, for the digit driver transistors, making a lower component count possible. Both versions of the complete circuit will give a blinking display as a visual indication of overrange. A clock oscillator circuit using the ICM7555 CMOS timer is shown. 1 -O +5V 1508: 7447 Ww cy 1800) Hi | sson_| a b o1 4.7k] c B2 . a Ba e es t 9 RBI 47 r Tr c RC NETWORK For finer resolution on scale factor adjust, use a 10 turn pot or a small pot in series witha fixed resistor. 4 fosc = .45/RC Figure 7: 4-1/2 Digit A-D Converter with a multiplexed common anode LED display SET Vrer = o/ Vrer IN 100K) v- REFERENCE ANALOG GND INT. OUT A-Z IN BUF OUT REF. CAP 1 REF. CAP 2 IN LO- 1N Hi+ vw MSD DS LSB B81 82 UNDERRANGE OVERRANGE STROBE RUN/HOLD DIGITAL GND POLARITY CLOCK IN Busy LsD Dt 02 03 D4 mse BS B4 ANALOG GND O47 LF 100k!) uF SIGNAL PUT O.1nF 107135 +5V ICM7555 10-15kN. ADJUST TO Fet = 120kHZ Figure 8: Driving multiplexed common cathode LED displays 4-64 +5VICL7135 A suitable circuit for driving a plasma-type display is shown in Fig. 9. The high voltage anode driver buffer is made by Dionics. The 3 AND gates and caps driving BI are needed for interdigit blanking of multiple-digit display elements, and can be omitted if not needed. The 2.5k & 3k resistors set the current levels in the display. A similar arrangement can be used with Nixie tubes. . The popular LCD displays can be interfaced to the O/P of the ICL7135 with suitable display drivers, such as the ICM7211A as shown in Figure 11. A standard CMOS 4000 series LCD driver circuit is used for displaying the 1/2 digit, the polarity, Nixie is a registered trademark of Burroughs Corporation. Hi VOLTAGE BUFFER DI 505 1CL7135 Figure 9: 1CL7135 Plasma Display Circuit REF VOLTAGE 1CL7135 ANALOG GND 100Ki: INTERSIL and an overrange flag. A similar circuit can be used with the ICL7212A L.ED driver and the 1CM7235A vacuum fluorescent driver with appropriate arrangements made for the extra outputs. Of course, another full driver circuit could be ganged to the one shown if required. This would be useful if additional annunciators were needed. The Figure shows the ' complete circuit for a 4-1/2 digit (+2.000V) A/D. Figure 10 shows.a more complicated circuit for driving LCD displays. Here the data is latched into the ICM7211 by the STROBE signal and Overrange is indicated by blanking the 4 full digits. +5V 4-1/2 DIGIT LCD DISPLAY ee HE Mme | cm 4161514125 3 4 CD4054A 7 81311109 2 6 > (Oo 1/2 D4030 23 POL ae, Ly 5 eP 20.01 |} _- FS 60408 7! 1/4 CD4030 at bt 19 D2 ++ ID 92 D2 18 D3 | 1D | 17 patti , | nee +1 Tt 34 DA 16 68 Dp cpao71! 30 B3 15 B4 tt I 29 B2 14 B2 i 1D. 2881 3 Bt zt I> 27 BO 12 ps F SST 26 STROBE ICM7211A 27 oR-- 1CL7135 +5V 1/4 CD4030 Figure 10: LCD Display with Digit Blanking on Overrange Ml 28 SEGMENTS D1-D4 rim oc A BACKPLANE 120kC = 3 READINGS/SEC CLOCK IN 5 pp 'CM7211A 31 Dt 32 D2 33 D3 4 D4 30 BS 29 B2 26 Bt 27 BO 35 Vo OPTIONAL CAPACITOR ~ +5V 22-100pF ov. +5V Figure 11: Driving LCD DisplaysICL7135 TYPICAL APPLICATIONS (Contd.) Aproblem sometimes encountered with both LED & plasma- type display driving is that of clock source supply line variations. Since the supply is shared with the display, any variation in voltage due to the display reading may cause clock supply voltage modulation. When in overrange the display alternates between a blank display and the 0000 overrange indication. This shift occurs during the reference integrate phase of conversion causing a low display reading just after overrange recovery. Both of the above circuits have considerable current flowing in the digital supply from drivers, etc. A clock source using Intersils LM311 voltage comparator in positive feedback mode (Figure 12) could minimize any clock frequency shift problem. The 7135 is designed to work from +5 volt supplies. However, g +5V 0.22uFo Figure 12: LM311 Clock Source SERIAL OUTPUT TO RECEIVING UART { TRO UART EPE 1M6402/3 TBRL TBR . ooOoOOH! 4 2 3 4 5 6 7 8 a Da Ds D2 Di 8B 82 Bs Bs nc 1 Ds STROBE 1CL7135 POL AUN/HOLD +5V Figure 14: 1CL7135 to UART Interface STROBE 1CL7135 zamam<o INTERSIL if anegative supply is not available, it can be generated from 2 capacitors, and an inexpensive |.C. (Figure 13). INTERFACING WITH UARTS AND MICROPROCESSORS Figure 14 shows a very simple interface between a free- running I[CL7135 and a UART. The five STROBE pulses start the transmission of the five data words. The digit 5 word is Q000XXXX, digit 4 is 1000XXXxX, digit 3is 0100XXXx, etc. Also the polarity is transmitted indirectly by using it to drive the Even Parity Enable Pin (EPE). If EPE of the receiver is held low, a parity flag at the receiver can be decoded as a positive signal, no flag as negative. A complex arrangementis shown in Figure 15. Here the UART can instruct the A/D to begina measurement sequence by a word on RRI. The BUSY signal resets the Data Ready Reset (DRR). Again STROBE starts the +5V a 4 | iCL7660 Vout = -5V Hi] a] on A Figure 13: Generating Negative Supply from +5V 1OnF i 4 { TRO RRI DRR DR 1M6402/3 PE TBRL TBR oe oF 12345 67 8 Lj 1 2 3Y ENABLE 740157 9 = aad 1A 2A 3A_& 1B 28 38 TTT I I L Dz D3 Dz DO; Bi Bz Ba Bs POU ovN te Os RoR 1CL7135 aT RUN/HOL +8V BUSY keene 100pt 10K Figure 15: Complex 1CL7135 to UART Interface READ 1 IM6101_ M6100 SENSE 1 WRITE 1 Figure 16: (M6100 to 1CL7135 InterfaceICL7135 EN s qv PAO E 7aC157 L 2 PAI Mc6s0x 182838 T 1A2A30 3Y PA2 oR PA MCS650X Mc6820 8 VN eeeeerhy, PAA RE tcL7ias PAS Ri Ds PAG RUN sraose PAT ca CA2 Figure 17: |CL7135 to MC6800, MCS650X Interface transmit sequence. A quad 2 input multiplexer is used to superimpose polarity, over-range, and under-range onto the Ds word since in this instance it is known that Ba = Ba = Bg == 0. For correct operation it is important that the UART clock be fast enough that each word is transmitted before the next STROBE pulse arrives. Parity is locked into the UART at load time but does not change in this connection during an output stream. , 8080/8048 and the MC6800 groups with 8 bit words need to INTERSIL Sl. s 1v PAO 74c157 2v PAI INTERSIL imsoc4s 162038 T 1a2A9a Y PA2 INTEL PAS , 8085, 8255 ETC. (MODE 1) 5 VN Ds 6 Ba BB | PAA the ici 2 PAS R D3 PAG RUN AOtb svaoee PAT STROBE PAG Figure 18: ICL7135 to MCS-48, -80, 85 interface Circuits to interface the ICL7135 directly with three popular microprocessors are shown in Figures 16, 17 and 18. The main differences in the circuits are that the IM6100 with its 12 bit word capability can accept polarity, over-range, under- range, 4 bits of BCD and 5 digits simultaneously where the 4A have polarity, over-range and under-range multiplexed onto the Digit 5 word - as in the UART circuit. In each case the microprocessor can instruct the A/D when to begin a measurement and when to hold this measurement. APPLICATION NOTES A016 Selecting A/D Converters, by David Fullagar A017 The Integrating A/D Converters, by Lee Evans A018 Do's and Don'ts of Applying A/D Converters, by Peter Bradshaw and Skip Osgood A019 4-1/2 Digit Panel Meter Demonstrator/Instrumenta- tion Boards, by Michael Dufort A023 Low Cost Digital Panel Meter Designs, by David Fullagar and Michael Dufort 4-67 A028 Building an Auto-Ranging DMM Using the _ 8052A/7103A A/D Converter Pair, by Larry Goff A030 The 1CL7104 - A Binary Output A/D Converter for Microprocessors, by Peter Bradshaw A032 Understanding the Auto-Zero and Common Mode Performance of the ICL7106 Family, by Peter Bradshaw ROOS interfacing Data Converters & Microprocessors, by Peter Bradshaw et al, Electronics, Dec. 9, 1976