Vishay Siliconix
DG3157
Document Number: 72648
S-70852–Rev. C, 30-Apr-07
www.vishay.com
1
Available
Pb-free
RoHS*
COMPLIANT
High-Speed, Low rON, SPDT Analog Switch
(2:1 Multiplexer/Demultiplexer Bus Switch)
FEATURES
• Direct Cross to Industry Standard
SN74LVC1G3157, NC7SB3157, NLASB3175,
Pl5A3157, and STG3157
• SC-70 6-Lead Package
• 1.65 V to 5.5 V VCC Operation
•5 Ω Connection Between Ports
• Minimal Propagation Delay
• Break-Before-Make Switching
• Zero Bounce In Flow-Through Mode
DESCRIPTION
The DG3157 is a high-speed single-pole double-throw, low
power, TTL-Compatible bus switch. Using sub-micro CMOS
technology, the DG3157 achieves low on-resistance and
negligible propagation delay.
The DG3157 can handle both analog and digital signals and
permits signals with amplitudes of up to VCC to be
transmitted in either direction.
When the Select pin is low, B0 is connected to the output A
pin. When the Select pin is high, B1 is connected to the
output A pin. The path that is open will have a high-
impedance state with respect to the output. Make-before-
break is guaranteed. An eptiaxial layer prevents latch-up.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
* Pb containing terminations are not RoHS compliant, exemptions may apply
S
A
1
2
3
6
Top View
B1
GND
B04
SC-70
6- Pin
5V+
Device Marking: G1
TRUTH TABLE
Logic Input (S) Function
0 B0 Connected to A
1B1 Connected to A
ORDERING INFORMATION
Temp Range Package Part Number
- 40 to 85 °C SC70-6 DG3157DL-T1
DG3157DL-T1-E3
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Document Number: 72648
S-70852–Rev. C, 30-Apr-07
Vishay Siliconix
DG3157
Notes:
a. Signals on A, or B or S exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC Board.
c. Derate 3.1 mW/°C above 70 °C.
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
Reference V+ to GND - 0.3 to + 6 V
S, A, Ba- 0.3 to (V+ + 0.3)
Continuous Current (Any terminal) ± 50 mA
Peak Current (Pulsed at 1 ms, 10 % duty cycle) ± 200
Storage Temperature D Suffix - 65 to 150 °C
Power Dissipation (Packages)b 6-Pin SC70c250 mW
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 3.0 V, VS = 0.25 V to 0.7 V+eTempa
Limits
- 40 to 85 °C
Unit Minb TypcMaxb
DC Characteristics
High Level Input Voltage VSH
V+ = 1.65 to 1.95 V Full 0.75 V+
V
V+ = 2.3 to 5.5 V Full 0.7 V+
Low Level Input Voltage VSL
V+ = 1.65 to 1.95 V Full 0.25 V+
V+ = 2.3 to 5.5 V Full 0.3 V+
On Resistance RON
V+ = 4.5 V
VBN = 0 V, IA = 30 mA Full 6 7
Ω
VBN = 2.3 V, IA = - 30 mA Full 6 12
VBN = 4.5 V, IA = - 30 mA Full 9 15
V+ = 3.0 V VBN = 0 V, IA = 24 mA Full 8 9
VBN = 3.0 V, IA = - 24 mA Full 12 20
V+ = 2.3 V VBN = 0 V, IA = 8 mA Full 9 12
VBN = 2.3 V, IA = - 8 mA Full 13 30
V+ = 1.65 V VBN = 0 V, IA = 4 mA Full 12 20
VBN = 1.8 V, IA = - 4 mA Full 18 50
On Resistance Flatness RFLAT 0 < VBN < V+
V+ = 4.5 V, IA = - 30 mA Room 6
V+ = 3.0 V, IA = - 24 mA Room 12
V+ = 2.3 V, IA = - 8 mA Room 22
V+ = 1.65 V, IA = - 4 mA Room 90
On Resistance Matching
Between Channels ΔRON
V+ = 4.5 V, VBN = 3.15 V, IA = - 30 mA Room 0.32
V+ = 3.0 V, VBN = 2.1 V, IA = - 24 mA Room 0.31
V+ = 2.3 V, VBN = 1.6 V, IA = - 8 mA Room 0.30
V+ = 1.65 V, VBN = 1.15 V, IA = - 4 mA Room 0.29
Input Leakage Current ISV+ = 5.5 V, VA = 5.5 V Room
Full
- 0.1
- 1.0
0.1
- 1.0
µAOff Stage Switch Leakage IBN(off) V+ = 5.5 V, VA/VB = 0 V/5.5 V Room
Full
- 0.1
- 1.0
0.1
- 1.0
On State Switch Leakage IBN(on) V+ = 5.5 V, VA/VB = 0 V/5.5 V Room
Full
- 0.1
- 1.0
0.1
- 1.0
Power Supply
Power Supply Range V+ Full 1.65 5.5 V
Quiescent Supply Current I+ V+ = 5.5 V, VA = VB = V+ or GND Room
Full
1
10 µA
Document Number: 72648
S-70852–Rev. C, 30-Apr-07
www.vishay.com
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Vishay Siliconix
DG3157
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for design aid only, not guaranteed nor subject to production testing.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the
on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 3.0 V, VS = 0.25 V to 0.7 V+eTempa
Limits
- 40 to 85 °C
Unit Minb TypcMaxb
AC Electrical Characteristice
Prop Delay TimeftPHL/tPLH VA = 0 V
V+ = 1.65 to 1.95 V Full
ns
V+ = 2.3 to 2.7 V Full 1.2
V+ = 3.0 to 3.6 V Full 0.8
V+ = 4.5 to 5.5 V Full 0.3
Output Enable TimeftPZL/tPZH
VLOAD = 2 x V+ for tPZL
VLOAD = 0 V for tPZH
V+ = 1.65 to 1.95 V Room
Full
10.2
10.4
V+ = 2.3 to 2.7 V Room
Full
5.9
6.2
V+ = 3.0 to 3.6 V Room
Full
4.1
4.5
V+ = 4.5 to 5.5 V Room
Full
2.6
2.9
Output Disable TimeftPLZ/tPHZ
VLOAD = 2 x V+ for tPLZ
VLOAD = 0 V for tPHZ
V+ = 1.65 to 1.95 V Room
Full
10.2
10.4
V+ = 2.3 to 2.7 V Room
Full
5.9
6.2
V+ = 3.0 to 3.6 V Room
Full
4.1
4.5
V+ = 4.5 to 5.5 V Room
Full
2.6
2.9
Break-Before-Make TimedtBBM
V+ = 1.65 to 1.95 V Full 0.5
V+ = 2.3 to 2.7 V Full 0.5
V+ = 3.0 to 3.65 Full 0.5
V+ = 4.5 to 5.5 V Full 0.5
Charge InjectiondQCL = 0.1 nF, VGEN = 0 V
RGEN = 0 Ω
V+ = 5 V Room 7 pC
V+ = 3.3 V Room 3
Analog Switch Characteristics
Off IsolationdOIRR RL = 50 Ω, f = 10 MHz Room - 57.6 dB
CrosstalkdXTA L K Room - 58.7
- 3-db BandwidthdBW RL = 50 ΩRoom > 250 MHz
Capacitance
Control Pin CapacitancedCIN V+ = 0 V Room 4.9
pF
B Port Off CapacitancedCIO-B
V+ = 5 V
Room < 6.5
A Port Capacitance When
Switch EnabledCIO-A(on) Room < 18.5
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Document Number: 72648
S-70852–Rev. C, 30-Apr-07
Vishay Siliconix
DG3157
LOGIC DIAGRAM (POSITIVE LOGIC)
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Figure 1.
A
B
B
S
4
1
6
3
rON vs. VA vs. VCC
0
5
10
15
20
25
30
35
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
A
(V)
V+ = 1.65 V , I
S
= 4 mA
r
ON – On Resistance (Ω)
V+ = 2.3 V , I
S
= 8 mA
V+ = 3.0 V, IS = 24 mA
V+ = 4.5 V
,
I
S
= 30 mA
Document Number: 72648
S-70852–Rev. C, 30-Apr-07
www.vishay.com
5
Vishay Siliconix
DG3157
AC LOADING AND WAVEFORMS
Notes:
• CL includes probe and jig capacitance.
• Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
• Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
• All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
• The outputs are measured one at a time with one transition per measurement.
• tPLZ and tPHZ are the same as tdis.
• tPZL and tPZH are the same as tdis.
• tPLH and tPHL are the same as tdis.
• VLD = 2 V+.
Figure 2. AC Test Circuit
From Output
Under Test
VLD
RL
500 Ω
CL
50 pF
Load Circuit
RL
500 ΩOpen
GND
SW
tPLH/tPHL Open
tPLZ/tPZL VLD
tPHZ/tPZH GND
TEST SW
Figure 3. AC Waveforms
t
r
= 2.5 ns t
f
= 2.5 ns
t
f
= 2.5 ns t
r
= 2.5 ns
3.0 V
3.0 V
GND
GND
Logic
Input
Switch
Input
10 % 10 %
10 % 10 %
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
90 % 90 %
90 % 90 %
t
w
Output
Output
Output
t
PL H t
PH L
V
OH
V
OL
t
PZ L t
PL Z
t
PZ H t
PH Z
1.5 V
V
OL
+ 0.3 V
V
OL
V
OH
V
OH
0.3 V
V
LD
2
0 V
W aveform 1
SW at V
LD
W aveform 2
SW at GND
Propagation Delay T imes Enable and Disable T ime-Low- and High-Level Enabling
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Document Number: 72648
S-70852–Rev. C, 30-Apr-07
Vishay Siliconix
DG3157
TEST CIRCUITS
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?72648.
Figure 4. Break-Before-Make Interval
CL (includes fixture and stray capacitance)
NC
VNO
NO
VNC
0 V
Logic
Input
Switch
Output
VO
VNC = VNO
tr < 5 ns
tf < 5 ns
90 %
tDtD
IN
COM
V+
GND
V+
CL
35 pF
VO
RL
50 Ω
VINL
VIN
H
Figure 5. Charge Injection
Off OnOn
IN
ΔVOUT
VOUT
Q = ΔV
OUT x CL
CL = 1 nF
Rgen
VOUT
COM
VIN = 0 – V+
IN
Vgen
GND
V+
V+
IN depends on switch configuration: input polarity
determined by sense of switch.
+
NC or NO
Figure 6. Off-Isolation
IN
GND
NC or NO
0 V, 2.4 V
10 nF
COM
Off Isolation = 20 log
V
COM
V
NO/ NC
RL
Analyzer
V+
V+
COM
Figure 7. Channel Off/On Capacitance
NC or NO
f = 1 MHz
IN
COM
GND
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
10 nF
V+
V+
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
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