DS92LV010A
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SNLS007E –MAY 1998–REVISED APRIL 2013
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver
Check for Samples: DS92LV010A
1FEATURES DESCRIPTION
The DS92LV010A is one in a series of transceivers
2• Bus LVDS Signaling (BLVDS) designed specifically for the high speed, low power
• Designed for Double Termination Applications proprietary bus backplane interfaces. The device
• Balanced Output Impedance operates from a single 3.3V or 5.0V power supply
and includes one differential line driver and one
• Lite Bus Loading 5pF Typical receiver. To minimize bus loading the driver outputs
• Glitch Free Power Up/Down (Driver Disabled) and receiver inputs are internally connected. The
• 3.3V or 5.0V Operation logic interface provides maximum flexibility as 4
separate lines are provided (DIN, DE, RE, and
• ±1V Common Mode Range ROUT). The device also features flow through which
• ±100mV Receiver Sensitivity allows easy PCB routing for short stubs between the
• High Signaling Rate Capability (Above 100 bus pins and the connector. The driver has 10 mA
Mbps) drive capability, allowing it to drive heavily loaded
backplanes, with impedance as low as 27 Ohms.
• Low Power CMOS Design
• Product Offered in 8 Lead SOIC Package The driver translates between TTL levels (single-
ended) to Low Voltage Differential Signaling levels.
• Industrial Temperature Range Operation This allows for high speed operation, while
consuming minimal power with reduced EMI. In
addition the differential signaling provides common
mode noise rejection of ±1V.
The receiver threshold is ±100mV over a ±1V
common mode range and translates the low voltage
differential levels to standard (CMOS/TTL) levels.
CONNECTION DIAGRAM
Figure 1. SOIC Package
See Package Number D0008A
BLOCK DIAGRAM
Figure 2.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS92LV010A
SNLS007E –MAY 1998–REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)(2)(3)
Supply Voltage (VCC) 6.0V
Enable Input Voltage (DE, RE) −0.3V to (VCC + 0.3V)
Driver Input Voltage (DIN) −0.3V to (VCC + 0.3V)
Receiver Output Voltage (ROUT)−0.3V to (VCC + 0.3V)
Bus Pin Voltage (DO/RI±) −0.3V to + 3.9V
Driver Short Circuit Current Continuous
ESD (HBM 1.5 kΩ, 100 pF) >2.0 kV
Maximum Package Power Dissipation at 25°C SOIC 1025 mW
Derate SOIC Package 8.2 mW/°C
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 4 sec.) 260°C
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except
VOD, VID, VTH and VTL unless otherwise specified.
(2) Absolute Maximum Ratings are these beyond which the safety of the device cannot be ensured. They are not meant to imply that the
device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
RECOMMENDED OPERATING CONDITIONS Min Max Units
Supply Voltage (VCC), or 3.0 3.6 V
Supply Voltage (VCC) 4.5 5.5 V
Receiver Input Voltage 0.0 2.9 V
Operating Free Air Temperature −40 +85 °C
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SNLS007E –MAY 1998–REVISED APRIL 2013
3.3V DC ELECTRICAL CHARACTERISTICS (1)(2)
TA=−40°C to +85°C unless otherwise noted, VCC = 3.3V ± 0.3V
Parameter Test Conditions Pin Min Typ Max Units
VOD Output Differential Voltage RL= 27Ω, See Figure 3 DO+/RI+, 140 250 360 mV
DO−/RI−
ΔVOD VOD Magnitude Change 3 30 mV
VOS Offset Voltage 1 1.25 1.65 V
ΔVOS Offset Magnitude Change 5 50 mV
IOSD Output Short Circuit Current VO= 0V, DE = VCC −12 −20 mA
VOH Voltage Output High VID = +100 mV I OH =−400 µA R OUT 2.8 3 V
Inputs Open 2.8 3 V
Inputs Shorted 2.8 3 V
Inputs Terminated, RL= 27Ω2.8 3 V
VOL Voltage Output Low IOL = 2.0 mA, VID =−100 mV 0.1 0.4 V
IOS Output Short Circuit Current VOUT = 0V, VID = +100 mV −5−35 −85 mA
VTH Input Threshold High DE = 0V DO+/RI+, +100 mV
DO−/RI−
VTL Input Threshold Low −100 mV
IIN Input Current DE = 0V, VIN = +2.4V, or 0V −20 ±1 +20 µA
VCC = 0V, VIN = +2.4V, or 0V −20 ±1 +20 µA
VIH Minimum Input High Voltage DIN, 2.0 VCC V
DE,RE
VIL Maximum Input Low Voltage GND 0.8 V
IIH Input High Current VIN = VCC or 2.4V ±1 ±10 µA
IIL Input Low Current VIN = GND or 0.4V ±1 ±10 µA
VCL Input Diode Clamp Voltage ICLAMP =−18 mA −1.5 −0.8 V
ICCD Power Supply Current DE = RE = VCC , RL= 27ΩVCC 13 20 mA
ICCR DE = RE = 0V 5 8 mA
ICCZ DE = 0V, RE = VCC 3 7.5 mA
ICC DE = VCC, RE = 0V, RL= 27Ω16 22 mA
Coutput Capacitance @ BUS Pins DO+/RI+, 5 pF
DO−/RI−
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except
VOD, VID, VTH and VTL unless otherwise specified.
(2) All typicals are given for VCC = +3.3V or 5.0 V and TA= +25°C, unless otherwise stated.
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5V DC ELECTRICAL CHARACTERISTICS (1)(2)
TA=−40°C to +85°C unless otherwise noted, VCC = 5.0V ± 0.5V
Parameter Test Conditions Pin Min Typ Max Units
VOD Output Differential Voltage RL= 27Ω, See Figure 3 DO+/RI+, 145 270 390 mV
DO−/RI−
ΔVOD VOD Magnitude Change 3 30 mV
VOS Offset Voltage 1 1.35 1.65 V
ΔVOS Offset Magnitude Change 5 50 mV
IOSD Output Short Circuit Current VO= 0V, DE = VCC −12 −20 mA
VOH Voltage Output High VID = +100 mV IOH =−400 µA ROUT 4.3 5.0 V
Inputs Open 4.3 5.0 V
Inputs Shorted 4.3 5.0 V
Inputs Terminated, RL= 27Ω4.3 5.0 V
VOL Voltage Output Low IOL = 2.0 mA, VID =−100 mV 0.1 0.4 V
IOS Output Short Circuit Current VOUT = 0V, VID = +100 mV −35 −90 −130 mA
VTH Input Threshold High DE = 0V DO+/RI+, +100 mV
DO−/RI−
VTL Input Threshold Low −100 mV
IIN Input Current DE = 0V, VIN = +2.4V, or 0V −20 ±1 +20 µA
VCC = 0V, VIN = +2.4V, or 0V −20 ±1 +20 µA
VIH Minimum Input High Voltage DIN, DE, 2.0 VCC V
RE
VIL Maximum Input Low Voltage GND 0.8 V
IIH Input High Current VIN = VCC or 2.4V ±1 ±10 µA
IIL Input Low Current VIN = GND or 0.4V ±1 ±10 µA
VCL Input Diode Clamp Voltage ICLAMP =−18 mA −1.5 −0.8 V
ICCD Power Supply Current DE = RE = VCC, RL= 27ΩVCC 17 25 mA
ICCR DE = RE = 0V 6 10 mA
ICCZ DE = 0V, RE = VCC 3 8 mA
ICC DE = VCC, RE = 0V, RL= 27Ω20 25 mA
Coutput Capacitance @ BUS Pins DO+/RI+, 5 pF
DO−/RI−
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except
VOD, VID, VTH and VTL unless otherwise specified.
(2) All typicals are given for VCC = +3.3V or 5.0 V and TA= +25°C, unless otherwise stated.
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SNLS007E –MAY 1998–REVISED APRIL 2013
3.3V AC ELECTRICAL CHARACTERISTICS (1)
TA=−40°C to +85°C, VCC = 3.3V ± 0.3V
Parameter Test Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to RL= 27Ω, See Figure 4 and Figure 5 1.0 3.0 5.0 ns
Low CL= 10 pF
tPLHD Differential Prop. Delay Low to 1.0 2.8 5.0 ns
High
tSKD Differential SKEW |t PHLD - 0.2 1.0 ns
tPLHD|
tTLH Transition Time Low to High 0.3 2.0 ns
tTHL Transition Time High to Low 0.3 2.0 ns
tPHZ Disable Time High to Z RL= 27Ω, See Figure 6 and Figure 7 0.5 4.5 9.0 ns
CL= 10 pF
tPLZ Disable Time Low to Z 0.5 5.0 10.0 ns
tPZH Enable Time Z to High 2.0 5.0 7.0 ns
tPZL Enable Time Z to Low 1.0 4.5 9.0 ns
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to See Figure 8 and Figure 9 2.5 5.0 12.0 ns
Low CL= 10 pF
tPLHD Differential Prop. Delay Low to 2.5 5.5 10.0 ns
High
tSKD Differential SKEW |t PHLD - 0.5 2.0 ns
tPLHD|
trRise Time 1.5 4.0 ns
tfFall Time 1.5 4.0 ns
tPHZ Disable Time High to Z RL= 500Ω, See Figure 10 and Figure 11 2.0 4.0 6.0 ns
CL= 10 pF(2)
tPLZ Disable Time Low to Z 2.0 5.0 7.0 ns
tPZH Enable Time Z to High 2.0 7.0 13.0 ns
tPZL Enable Time Z to Low 2.0 6.0 10.0 ns
(1) Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω, tr, tf ≤6.0ns (0%–100%) on control pins and ≤1.0ns
for RI inputs.
(2) For receiver tri-state delays, the switch is set to VCC for tPZL, and tPLZ and to GND for tPZH, and tPHZ.
Copyright © 1998–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
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SNLS007E –MAY 1998–REVISED APRIL 2013
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5V AC ELECTRICAL CHARACTERISTICS (1)
TA=−40°C to +85°C, VCC = 5.0V ± 0.5V
Parameter Test Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to RL= 27Ω, See Figure 4 and Figure 5 0.5 2.7 4.5 ns
Low CL= 10 pF
tPLHD Differential Prop. Delay Low to 0.5 2.5 4.5 ns
High
tSKD Differential SKEW |t PHLD - 0.2 1.0 ns
tPLHD|
tTLH Transition Time Low to High 0.3 2.0 ns
tTHL Transition Time High to Low 0.3 2.0 ns
tPHZ Disable Time High to Z RL= 27Ω, See Figure 6 and Figure 7 0.5 3.0 7.0 ns
CL= 10 pF
tPLZ Disable Time Low to Z 0.5 5.0 10.0 ns
tPZH Enable Time Z to High 2.0 4.0 7.0 ns
tPZL Enable Time Z to Low 1.0 4.0 9.0 ns
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to See Figure 8 and Figure 9 2.5 5.0 12.0 ns
Low CL= 10 pF
tPLHD Differential Prop. Delay Low to 2.5 4.6 10.0 ns
High
tSKD Differential SKEW |t PHLD - 0.4 2.0 ns
tPLHD|
trRise Time 1.2 2.5 ns
tfFall Time 1.2 2.5 ns
tPHZ Disable Time High to Z RL= 500Ω, See Figure 10 and Figure 11 2.0 4.0 6.0 ns
CL= 10 pF(2)
tPLZ Disable Time Low to Z 2.0 4.0 6.0 ns
tPZH Enable Time Z to High 2.0 5.0 9.0 ns
tPZL Enable Time Z to Low 2.0 5.0 7.0 ns
(1) Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω, tr, tf ≤6.0ns (0%–100%) on control pins and ≤1.0ns
for RI inputs.
(2) For receiver tri-state delays, the switch is set to VCC for tPZL, and tPLZ and to GND for tPZH, and tPHZ.
TEST CIRCUITS AND TIMING WAVEFORMS
Figure 3. Differential Driver DC Test Circuit
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3V
0V
20%
80%
80%
0V
20%
DO+
DO-
1.5V 1.5V
Differential0V 0V
tTLH tTHL
VDIFF = (DO+) - (DO-)
tPHLD tPLHD
DIN
DO+, DO-
(DO+) - (DO-)
DS92LV010A
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SNLS007E –MAY 1998–REVISED APRIL 2013
Figure 4. Differential Driver Propagation Delay and Transition Time Test Circuit
Figure 5. Differential Driver Propagation Delay and Transition Time Waveforms
Figure 6. Driver TRI-STATE Delay Test Circuit
Figure 7. Driver TRI-STATE Delay Waveforms
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SNLS007E –MAY 1998–REVISED APRIL 2013
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Figure 8. Receiver Propagation Delay and Transition Time Test Circuit
Figure 9. Receiver Propagation Delay and Transition Time Waveforms
Figure 10. Receiver TRI-STATE Delay Test Circuit
Figure 11. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms
TYPICAL BUS APPLICATION CONFIGURATIONS
Figure 12. Bi-Directional Half-Duplex Point-to-Point Applications
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SNLS007E –MAY 1998–REVISED APRIL 2013
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APPLICATION INFORMATION
There are a few common practices which should be implied when designing PCB for BLVDS signaling.
Recommended practices are:
• Use at least 4 layer PCB board (BLVDS signals, ground, power and TTL signals).
• Keep drivers and receivers as close to the (BLVDS port side) connector as possible.
• Bypass each BLVDS device and also use distributed bulk capacitance. Surface mount capacitors placed
close to power and ground pins work best. Two or three multi-layer ceramic (MLC) surface mount capacitors
(0.1 µF, and 0.01 µF in parallel should be used between each VCC and ground. The capacitors should be as
close as possible to the VCC pin.
• Use the termination resistor which best matches the differential impedance of your transmission line.
• Leave unused LVDS receiver inputs open (floating)
Table 1. Functional Table
MODE SELECTED DE RE
DRIVER MODE H H
RECEIVER MODE L L
TRI-STATE MODE L H
LOOP BACK MODE H L
Table 2. Transmitter Mode(1)
INPUTS OUTPUTS
DE DI DO+ DO−
H L L H
H H H L
H 2 > & > 0.8 X X
L X Z Z
(1) L = Low state
H = High state
Table 3. Receiver Mode(1)
INPUTS OUTPUT
RE (RI+)-(RI−)
L L (< −100 mV) L
L H (> +100 mV) H
L 100 mV > & > −100 mV X
H X Z
(1) X = High or Low logic state
Z = High impedance state
L = Low state
H = High state
Table 4. Device Pin Descriptions
Pin Name Pin No. Input/Output Description
DIN 2 I TTL Driver Input
DO±/RI± 6, 7 I/O LVDS Driver Outputs/LVDS Receiver Inputs
ROUT 3 O TTL Receiver Output
RE 5 I Receiver Enable TTL Input (Active Low)
DE 1 I Driver Enable TTL Input (Active High)
GND 4 NA Ground
VCC 8 NA Power Supply
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SNLS007E –MAY 1998–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS92LV010ATM NRND SOIC D 8 95 Non-RoHS
& Green Call TI Call TI -40 to 85 LV010
ATM
DS92LV010ATM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LV010
ATM
DS92LV010ATMX NRND SOIC D 8 2500 Non-RoHS
& Green Call TI Call TI -40 to 85 LV010
ATM
DS92LV010ATMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LV010
ATM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS92LV010ATMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
DS92LV010ATMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS92LV010ATMX SOIC D 8 2500 367.0 367.0 35.0
DS92LV010ATMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
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PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
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EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
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EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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