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June 1998

Revised February 2001

74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Fl op with 5V Tolerant Inputs

74LCX112

Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop

with 5V Tolerant Inputs

General Description

The LCX11 2 is a dual J-K flip-flop. Each flip-flop has inde-

pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,

Q outputs. These devices are edge sensitive and change

state on the negative going transition of the clock pulse.

Clear an d pres et are indepen dent o f the cl ock an d accom -

plished by a low logic level on the corresponding input.

LCX devices are designed for low voltage (3.3V or 2.5)

operation with the added capability of interfacing to a 5V

signal environment.

The 74LCX112 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■5V tolerant inputs

■2.3V–3.6V VCC specifications provided

■7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max

■Power down high impedance inputs and outputs

■±24 mA output drive (VCC = 3.0V)

■Implements patented noise/EMI reduction circuitry

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human body model > 2000V

Machine model

> 2000V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

74LCX112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

74LCX112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX1 12MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

J1, J2, K1, K2Data Inputs

CP1, CP2Clock Pulse Inputs (Active Falling Edge)

CD1, CD2 Direct Clear Inputs (Active LOW)

SD1, SD2 Direct Set Inputs (Active LOW)

Q1, Q2, Q1, Q2Outputs

www.fairchildsemi.com 2

74LCX112

Truth Table

(Each half)

H(h) = HIGH Voltage Le ve l

L(l) = LOW Voltage Level

X = Immaterial



= HIGH-to-LOW Cloc k Transit ion

QO(QO) = Before HIGH-to-LOW Transition of Clock

Lower case letters indicate the state of the referenced input or output on e setup time prior to the HIGH-to-LOW clock transitio n.

Logic Diagram

Inputs Outputs

SDCDCP JKQQ

LHXXXHL

HLXXXLH

LLXXXHH



hhQ

OQO



lhLH



hlHL



llQ

OQO

HHHXXQ

OQO

3 www.fairchildsemi.com

74LCX112

Absolute Maxim um Ratings(Note 1)

Recommended Operating Conditions (Note 3)

Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute M aximum Ratings. The “Recom-

mended Operating Conditions” table will define the c onditions fo r ac t ual device ope ration.

Note 2: IO Absolu te Maximu m rating must be observed.

Note 3: Unused Inp uts must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage −0.5 to +7.0 V

VIDC Input Voltage −0.5 to +7.0 V

VODC Output Voltage −0.5 to VCC + 0.5 Outpu t in H I GH or L O W St at e ( Not e 2 ) V

IIK DC Input Diode Current −50 VI < GND mA

IOK DC Output Diode Current −50 VO < GND mA

+50 VO > VCC

IODC Output Source/Sink Current ±50 mA

ICC DC Supple Current per Supply Pin ±100 mA

IGND DC Ground Current per Ground Pin ±100 mA

TSTG Storage Temperature −65 to 150 °C

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 05.5V

VOOutput Vo l tag e HIGH or LOW State 0 VCC V

IOH/IOL Output Curr en t VCC = 3.0V − 3.6V ±24 mAVCC = 2.7V − 3.0V ±12

VCC = 2.3V − 2.7V ±8

TAFree-Air Operating Temperature −40 85 °C

∆t/∆V Input Edge Rate, VIN = 0.8V−2.0V, VCC = 3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA = 40 °C to +85°CUnits

(V) Min Max

VIH HIGH Level Input Voltag e 2.3 − 2.7 1.7 V

2.7 − 3.6 2.0

VIL LOW Level Input Voltage 2.3 − 2.7 0.7 V

2.7 − 3.6 0.8

VOH HIGH Level Output Voltage IOH = −100µA2.3 − 3.6 VCC - 0.2 0.7

IOH = -8 mA 2.3 1.8

IOH = −12 mA 2.7 2.2

IOH = −18 mA 3.0 2.4

IOH = −24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL = 100µA2.3 − 3.6 0.6

IOL = 8mA 2.3 0.2

IOL = 12 mA 2.7 0.4 V

IOL = 16 mA 3.0 0.4

IOL = 24 mA 3.0 0.55

IIInput Leakage Current 0 ≤ II ≤ 5.5V 2.3 − 3.6 ±5.0 µA

IOFF Power-Off Leakage Current VI or VO = 5.5V 0 10 µA

ICC Quiescent Supply Current VI = VCC or GND 2.3 − 3.6 10 µA

3.6V ≤ VI ≤ 5.5V 2.3 − 3.6 ±10 µA

∆ICC Increase in ICC per Input VIH = VCC −0.6V 2.3 − 3.6 500 µA

www.fairchildsemi.com 4

74LCX112

AC Electrical Characteristics

Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specif ic ation appl ies t o any outputs s w it c hing in the same direction, eit her HIGH -to -LOW (tOSHL), or LOW-to-HIGH (tOSLH).

Dynamic Switching Characteristics

Capacitance

Symbol Parameters

TA = 40°C to 85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3 V VCC = 2.7V VCC = 2.5V ± 0.2V

CL=50 pF CL = 50 pF CL=30 pF

Min Max Min Max Min Max

fMAX Maximum Clock Frequency 150 150 150 MHz

tPHL Propagation Delay 1.5 7.5 1.5 8.0 1.5 9.0 ns

tPLH CPn to Qn or Qn1.57.51.58.01.59.0

tPHL Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4 ns

tPLH CDn or SDn to Qn or Qn1.57.01.78.01.58.4

tSSetup Time 2.5 2.5 4.0 ns

tHHold Time 1.5 1.5 2.0 ns

tWPulse Width CP 3.3 3.3 4.0 ns

tWPulse Width (CD, SD) 3.3 3.3 4.0 ns

tREC Recovery Time 2.0 2.5 4.5 ns

tOSHL Output to Output Skew 1.0 ns

tOSLH (Note 4) 1.0

Symbol Parameter Conditions VCC TA = 25°CUnits

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6

VOLV Quiet Output Dynamic Valley VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 V

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 7pF

COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8pF

CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 25 pF

5 www.fairchildsemi.com

74LCX112

AC Loading and Waveforms Generic for LCX Family

FIGURE 1. AC Test Circuit

(CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay, Pulse Width and trec Waveforms

3-STATE Output High Enable and

Disable TImes for Logic

3-STATE Output Low Enable and

Disable Times for Logic

Setup Time, Hold TIme and Recovery TIme for Logic

trise and tfall

FIGURE 2. Wav eforms

(Input Puls e Char ac ter is tic s; f=1M H z, tr=tf=3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V

VCC x 2 at VCC = 2.5 ± 0.2V

tPZH,tPHZ GND

Symbol VCC

3.3V ± 0.3V 2.7V 2. 5V ± 0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL + 0.3V VOL + 0.3V VOL + 0.15V

VyVOH − 0.3V VOH − 0.3V VOH − 0.15V

www.fairchildsemi.com 6

74LCX112

Schematic Diag r a m Generic for LCX Family

7 www.fairchildsemi.com

74LCX112

Physical Dim ensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

www.fairchildsemi.com 8

74LCX112

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Sma ll Outline Package (SOP), EIAJ T YPE II, 5. 3mm Wide

Package Number M16D

9 www.fairchildsemi.com

74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Fl op with 5V Tolerant Inputs

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

16-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP), JED EC MO-1 53, 4.4mm Wide

Package Number MTC16

Fairchild does not assume an y responsibility for use of any circuitry descr ib ed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause the fa i lure of the l ife support

device or system, or to affect its safety or effectiveness.

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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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