1
Data sheet acquired from Harris Semiconductor
SCHS122C
Features
• Wide Analog Input Voltage Range . . . . . . . . . .±5V Max
• Low “On” Resistance
-70Ω Typical (VCC - VEE = 4.5V)
-40Ω Typical (VCC - VEE = 9V)
• Low Crosstalk between Switches
• Fast Switching and Propagation Speeds
• “Break-Before-Make” Switching
• Wide Operating Temperature Range . . -55oC to 125oC
• CD54HC/CD74HC Types
- Operation Control Voltage . . . . . . . . . . . . . .2V to 6V
- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V
- High Noise Immunity . . . NIL = 30%, NIH = 30% of VCC,
VCC = 5V
• CD54HCT/CD74HCT Types
- Operation Control Voltage . . . . . . . . . . .4.5V to 5.5V
- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V
- Direct LSTTL Input
Logic Compatibility . . .VIL = 0.8V Max, VIH = 2V Min
- CMOS Input Compatibility. . . . . II≤ 1µA at VOL, VOH
Description
These devices are digitally controlled analog switches which
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL with the low power consumption of
standard CMOS integrated circuits.
These analog multiplexers/demultiplexers control analog
voltages that may vary across the voltage supply range (i.e.
VCC to VEE). They are bidirectional switches thus allowing
any analog input to be used as an output and visa-versa.
The switches have low “on” resistance and low “off” leak-
ages. In addition, all three devices have an enable control
which, when high, disables all switches to their “off” state.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC4051F -55 to 125 16 Ld CERDIP
CD54HC4051F3A -55 to 125 16 Ld CERDIP
CD74HC4051E -55 to 125 16 Ld PDIP
CD74HC4051M -55 to 125 16 Ld SOIC
CD74HC4051NSR -55 to 125 16 Ld SOP
CD54HCT4051F3A -55 to 125 16 Ld CERDIP
CD74HCT4051E -55 to 125 16 Ld PDIP
CD74HCT4051M -55 to 125 16 Ld SOIC
CD54HC4052F -55 to 125 16 Ld CERDIP
CD54HC4052F3A -55 to 125 16 Ld CERDIP
CD74HC4052E -55 to 125 16 Ld PDIP
CD74HC4052M -55 to 125 16 Ld SOIC
CD74HC4052NSR -55 to 125 16 Ld SOP
CD74HCT4052E -55 to 125 16 Ld PDIP
CD74HCT4052M -55 to 125 16 Ld SOIC
CD74HCT4052SM -55 to 125 16 Ld SSOP
CD54HC4053F -55 to 125 16 Ld CERDIP
CD54HC4053F3A -55 to 125 16 Ld CERDIP
CD74HC4053E -55 to 125 16 Ld PDIP
CD74HC4053M -55 to 125 16 Ld SOIC
CD74HC4053NSR -55 to 125 16 Ld SOP
CD74HCT4053E -55 to 125 16 Ld PDIP
CD74HCT4053M -55 to 125 16 Ld SOIC
CD74HCT4053PW -55 to 125 16 Ld TSSOP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel. For the TSSOP package
only, add the suffix R to obtain the variant in the tape and reel.
2. Waferordie isavailablewhich meetsallelectrical specifications.
Please contact your local TI sales office or customer service for
ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2002, Texas Instruments Incorporated
CD54/74HC4051, CD54/74HCT4051,
CD54/74HC4052, CD74HCT4052,
CD54/74HC4053, CD74HCT4053
High Speed CMOS Logic
Analog Multiplexers/Demultiplexers
[ /Title
(CD54
HC405
1,
CD74
HC405
1,
CD74
HCT40
51,
CD74
HC405
2,
November 1997 - Revised March 2002
2
Pinouts
CD54HC4051, CD54HCT4051
(CERDIP)
CD74HC4051
(PDIP, SOIC, SOP)
CD74HCT4051
(PDIP, SOIC)
TOP VIEW
CD54HC4052
(CERDIP)
CD74HC4052
(PDIP, SOIC, SOP)
CD74HCT4052
(PDIP, SOIC)
TOP VIEW
CD54HC4053
(CERDIP)
CD74HC4053
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4053
(PDIP, SOIC, TSSOP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A4
A6
A
A7
A5
E
GND
VEE
VCC
A1
A0
A3
S0
S1
S2
A2
CHANNEL
IN/OUT
CHANNEL
IN/OUT
CHANNEL
IN/OUT
COM OUT/IN
ADDRESS
SELECT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
B0
B2
BN
B3
B1
E
GND
VEE
VCC
A1
AN
A0
A3
S0
S1
A2 CHANNEL
IN/OUT
CHANNEL
IN/OUT
CHANNEL
IN/OUT
COM OUT/IN
CHANNEL
IN/OUT
COM OUT/IN
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
B1
B0
C1
CN
C0
E
GND
VEE
VCC
AN
A1
A0
S0
S1
S2
BN
CHANNEL
IN/OUT
IN/OUT
COM OUT/IN CHANNEL
IN/OUT
COM OUT/IN
COM OUT/IN
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
3
Functional Diagram of HC/HCT4051
TG
TG
TG
TG
TG
TG
TG
3A
COMMON
OUT/IN
BINARY
TO
1 OF 8
DECODER
WITH
ENABLE
11
10
9
6E
S2
S1
S0
LOGIC
LEVEL
CONVERSION
8 7
GND VEE
16
VCC
131415121524
A7A6A5A4A3A2A1A0
CHANNEL IN/OUT
TG
TRUTH TABLE
HC/HCT4051
INPUT STATES “ON”
CHANNELSENABLE S2S1S0
L LLL A0
LLLH A1
LLHL A2
LLHH A3
LHLL A4
LHLH A5
LHHL A6
L HHH A7
H X X X None
X = Don’t care
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
4
Functional Diagram of ’HC4052, CD74HCT4052
TG
TG
TG
TG
TG
TG
TG
TG
13 COMMON A
OUT/IN
BINARY
TO
1 OF 4
DECODER
WITH
ENABLE
10
9
6E
S1
S0
LOGIC
LEVEL
CONVERSION
16
VCC
4251
B0B1B2B3
B CHANNELS IN/OUT
3COMMON B
OUT/IN
8 7
GND VEE
12141511
A3A2A1A0
A CHANNELS IN/OUT
TRUTH TABLE
’HC4052, CD74HCT4052
INPUT STATES “ON”
CHANNELSENABLE S1S0
L L L A0, B0
L L H A1, B1
L H L A2. B2
L H H A3, B3
H X X None
X = Don’t care
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
5
Functional Diagram of ’HC4053, CD74HCT4053
TG
TG
TG
TG
TG
TG
14
11
10
9
6E
S2
S1
S0
7
GND VEE
16
VCC
15
C COMMON
OUT/IN
4
B COMMON
OUT/IN
A COMMON
OUT/IN
LOGIC LEVEL
CONVERSION
BINARY TO
1 OF 2
DECODERS
WITH ENABLE 12132153
C1C0B1B0A1A0
IN/OUT
8
TRUTH TABLE
’HC4053, CD74HCT4053
INPUT STATES “ON”
CHANNELSENABLE S0S1S2
L L L L C0, B0, A0
L H L L C0, B0, A1
L L H L C0, B1, A0
L H H L C0, B1, A1
L L L H C1, B0, A0
L H L H C1, B0, A1
L L H H C1, B1, A0
L H H H C1, B1, A1
H X X X None
X = Don’t care
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
6
Absolute Maximum Ratings (Note 3) Thermal Information
DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . -0.5V to 10.5V
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7V
DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.5V to -7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Switch Diode Current, IOK
For VI < VEE -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . .±20mA
DC Switch Current, (Note 2)
For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
DC VEE Current, IEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20mA
Package Thermal Impedance, θJA (see Note 4):
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108oC/W
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
Recommended Operating Conditions For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges
PARAMETER MIN MAX UNITS
Supply Voltage Range (For TA = Full Package Temperature Range), VCC (Note 5)
CD54/74HC Types 26V
CD54/74HCT Types 4.5 5.5 V
Supply Voltage Range (For TA = Full Package Temperature Range), VCC - VEE
CD54/74HC Types, CD54/74HCT Types (See Figure 1) 2 10 V
Supply Voltage Range (For TA = Full Package Temperature Range), VEE (Note 5)
CD54/74HC Types, CD54/74HCT Types (See Figure 2) 0 -6 V
DC Input Control Voltage, VIGND VCC V
Analog Switch I/O Voltage, VIS VEE VCC V
Operating Temperature, TA-55 125 oC
Input Rise and Fall Times, tr, tf
2V 0 1000 ns
4.5V 0 500 ns
6V 0 400 ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. All voltages referenced to GND unless otherwise specified.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
5. Incertainapplications, theexternalload resistorcurrentmay include bothVCC and signal linecomponents. To avoiddrawingVCC current
when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (cal-
culated from rON values shown in Electrical Specifications table). No VCC current will flow through RLif the switch current flows into
terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14 and 15 on the HC/HCT4053.
Recommended Operating Area as a Function of Supply Voltages
FIGURE 1. FIGURE 2.
HCT
VCC - GND (V)
VCC - VEE (V)
8
6
4
2
0024681012
HC HCT
VCC - GND (V)
VEE - GND (V)
8
6
4
2
00-2-4-6-8
HC
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
7
DC Electrical Specifications
PARAMETER
TEST CONDITIONS AMBIENT TEMPERATURE, TA
UNITS
VIS
(V) VI
(V) VEE
(V) VCC
(V)
25oC -40oC - 85oC -55oC - 125oC
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input Voltage,
VIH 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 0 V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input Voltage,
VIL 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
On Resistance, rON
IO = 1mA, (Figure 11) VCC or VEE VIL or
VIH 0 4.5 - 70 160 - 200 - 240 Ω
0 6 - 60 140 - 175 - 210 Ω
-4.5 4.5 - 40 120 - 150 - 180 Ω
VCC to VEE 0 4.5 - 90 180 - 225 - 270 Ω
0 6 - 80 160 - 200 - 240 Ω
-4.5 4.5 - 45 130 - 162 - 195 Ω
Maximum On Resistance
Between any Two
Channels, ∆rON
04.5-10-----Ω
06-8.5-----Ω
-4.5 4.5 - 5 - ----Ω
Switch On/Off Leakage
Current, IIZ For Switch Off:
When VIS =V
CC,
VOS = VEE;
When VIS =V
EE,
VOS = VCC
For Switch On:
All Applicable
Combinations of
VIS and VOS
Voltage Levels
VIL or
VIH
1 and 2 Channels 0 6 - - ±0.1 - ±1-±1µA
4053 -5 5 - - ±0.1 - ±1-±1µA
4 Channels 0 6 - - ±0.1 - ±1-±1µA
4052 -5 5 - - ±0.2 - ±2-±2µA
8 Channels 0 6 - - ±0.2 - ±2-±2µA
4051 -5 5 - - ±0.4 - ±4-±4µA
Control Input Leakage
Current, IIL VCC or
GND 06 - -±0.1 - ±1-±1µA
Quiescent Device
Current, ICC
IO = 0
When VIS =V
EE,
VOS = VCC VCC or
GND 0 6 - - 8 - 80 - 160 µA
When VIS =V
CC,
VOS = VEE -5 5 - - 16 - 160 - 320 µA
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
8
HCT TYPES
High Level Input Voltage,
VIH 4.5to
5.5 2--2-2-V
Low Level Input Voltage,
VIL 4.5to
5.5 - - 0.8 - 0.8 - 0.8 V
On Resistance, rON
IO = 1mA, (Figure 15) VCC or VEE VIL or
VIH 0 4.5 - 70 160 - 200 - 240 Ω
---------Ω
-4.5 4.5 - 40 120 - 150 - 180 Ω
VCC to VEE 0 4.5 - 90 180 - 225 - 270 Ω
---------Ω
-4.5 4.5 - 45 130 - 162 - 195 Ω
Maximum On Resistance
Between any Two
Channels, ∆rON
04.5-10-----Ω
---------Ω
-4.5 4.5 - 5 - ----Ω
Switch On/Off Leakage
Current, IIZ For Switch Off:
When VIS =V
CC,
VOS = VEE;
When VIS =V
EE,
VOS = VCC
For Switch On:
All Applicable
Combinations of
VIS and VOS
Voltage Levels
VIL or
VIH
1 and 2 Channels 0 6 - - ±0.1 - ±1-±1µA
4053 -5 5 - - ±0.1 - ±1-±1µA
4 Channels 0 6 - - ±0.1 - ±1-±1µA
4052 -5 5 - - ±0.2 - ±2-±2µA
8 Channels 0 6 - - ±0.2 - ±2-±2µA
4051 -5 5 - - ±0.4 - ±4-±4µA
Control Input Leakage
Current, IIL - (Note 7) - 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current, ICC
IO = 0
When VIS =V
EE,
VOS = VCC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
When VIS =V
CC,
VOS = VEE -4.5 5.5 - - 16 - 160 - 320 µA
Additional Quiescent
Device Current, ∆ICC
(Note 6)
Per Input Pin: 1 Unit
Load
VCC -
2.1 4.5to
5.5 - 100 360 - 450 - 490 µA
NOTES:
6. For dual supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
7. Any voltage between VCC and GND.
DC Electrical Specifications (Continued)
PARAMETER
TEST CONDITIONS AMBIENT TEMPERATURE, TA
UNITS
VIS
(V) VI
(V) VEE
(V) VCC
(V)
25oC -40oC - 85oC -55oC - 125oC
MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
TYPE INPUT UNIT LOADS
(NOTE)
4051, 4053 All 0.5
4052 All 0.4
NOTE: Unit load is ∆ICC limit specified in DC Specifications table,
e.g., 360mA max. at 25oC.
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
9
Switching Specifications VCC = 5V, TA = 25oC, Input tr, tr = 6ns
PARAMETER CL
(pF)
TYPICAL
UNITS
4051 4052 4053
HC HCT HC HCT HC HCT
Propagation Delay
Switch IN to OUT, tPHL, tPLH 15444444ns
Switch Turn-Off (S or E), tPHZ,tPLZ 15 19 19 21 21 18 18 ns
Switch Turn-On (S or E), tPZH, tPZL 15 19 23 27 29 18 20 ns
Power Dissipation Capacitance, CPD (Note 8) - 50 52 74 76 38 42 pF
NOTE:
8. CPD is used to determine the dynamic power consumption, per package.
PD = CPD VCC2 fI + ∑ (CL + CS) VCC2 fO
fO = output frequency
fI = input frequency
CL = output load capacitance
CS = switch capacitance
VCC = supply voltage
Switching Specifications CL = 50pF, Input tr, tr = 6ns
PARAMETER VEE
(V) VCC
(V)
AMBIENT TEMPERATURE, TA
UNITS
25oC -40oC - 85oC -55oC - 125oC
HC HCT HC HCT HC HCT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Propagation Delay, Switch
In to Out, tPLH, tPHL 02-60---75---90--ns
0 4.5 - 12 - 12 - 15 - 15 - 18 - 18 ns
06-10---13---15--ns
-4.5 4.5 - 8 - 8 - 10 - 10 - 12 - 12 ns
Maximum Switch
Turn “Off” Delay
from S or E to
Switch Output
tPHZ, tPLZ
4051 0 2 - 225 - - - 280 - - - 340 - - ns
0 4.5 - 45 - 45 - 56 - 56 - 68 - 68 ns
06-38---48---57--ns
-4.5 4.5 - 32 - 32 - 40 - 40 - 48 - 48 ns
4052 0 2 - 250 - - - 315 - - - 375 - - ns
0 4.5 - 50 - 50 - 63 - 63 - 75 - 75 ns
06-43---54---65--ns
-4.5 4.5 - 38 - 38 - 48 - 48 - 57 - 57 ns
4053 0 2 - 210 - - - 265 - - - 315 - - ns
0 4.5 - 42 - 44 - 53 - 55 - 63 - 66 ns
06-36---45---54--ns
-4.5 4.5 - 29 - 31 - 36 - 39 - 44 - 47 ns
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
10
Maximum Switch
Turn “On” Delay
from S or E to
Switch Output
tPZL, tPZH
4051 0 2 - 225 - - - 280 - - - 340 - - ns
0 4.5 - 45 - 55 - 56 - 69 - 68 - 83 ns
06-38---48---57--ns
-4.5 4.5 - 32 - 39 - 40 - 49 - 48 - 59 ns
4052 0 2 - 325 - - - 405 - - - 490 - - ns
0 4.5 - 65 - 70 - 81 - 68 - 98 - 105 ns
06-55---69---83--ns
-4.5 4.5 - 46 - 48 - 58 - 60 - 69 - 72 ns
4053 0 2 - 220 - - - 275 - - - 330 - - ns
0 4.5 - 44 - 48 - 55 - 60 - 66 - 72 ns
06-37---47---56--ns
-4.5 4.5 - 31 - 34 - 39 - 43 - 47 - 51 ns
Input (Control)
Capacitance, CI- - - 10 - 10 - 10 - 10 - 10 - 10 pF
Analog Channel Specifications Typical Values at TA = 25oC
PARAMETER TEST CONDITIONS HC/HCT
TYPES VEE
(V) VCC
(V) HC/
HCT UNITS
Switch Input Capacitance, CIAll - - 5 pF
Common Output Capacitance, CCOM 4051 - - 25 pF
4052 - - 12 pF
4053 - - 8 pF
Minimum Switch Frequency Response at -3dB, fMAX
(Figures 12, 14, 16) See Figure 3, Notes 9, 10 4051
-2.25 2.25
145 MHz
4052 165 MHz
4053 200 MHz
4051
-4.5 4.5
180 MHz
4052 185 MHz
4053 200 MHz
Switching Specifications CL = 50pF, Input tr, tr = 6ns (Continued)
PARAMETER VEE
(V) VCC
(V)
AMBIENT TEMPERATURE, TA
UNITS
25oC -40oC - 85oC -55oC - 125oC
HC HCT HC HCT HC HCT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
11
Crosstalk Between any Two Switches (Note 12) See Figure 4,
Notes 10, 11 4051
-2.25 2.25
N/A dB
4052 (TBE) dB
4053 (TBE) dB
4051
-4.5 4.5
N/A dB
4052 (TBE) dB
4053 (TBE) dB
Sinewave Distortion See Figure 5 All -2.25 2.25 0.035 %
All -4.5 4.5 0.018 %
E or S to Switch Feedthrough Noise See Figure 6
Notes 10, 11 4051
-2.25 2.25 (TBE)
mV
4052 mV
4053 mV
4051
-4.5 4.5 (TBE)
mV
4052 mV
4053 mV
Switch “OFF” Signal Feedthrough (Figures 13, 15, 17) See Figure 7
Notes 10, 11 4051
-2.25 2.25
-73 dB
4052 -65 dB
4053 -64 dB
4051
-4.5 4.5
-75 dB
4052 -67 dB
4053 -66 dB
NOTES:
9. Adjust input voltage to obtain 0dBm at VOS for fIN = 1MHz.
10. VIS is centered at (VCC - VEE)/2.
11. Adjust input for 0dBm.
12. Not applicable for HC/HCT4051.
Analog Channel Specifications Typical Values at TA = 25oC
PARAMETER TEST CONDITIONS HC/HCT
TYPES VEE
(V) VCC
(V) HC/
HCT UNITS
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
12
Test Circuits and Waveforms
FIGURE 3. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 4. CROSSTALK BETWEEN TWO SWITCHES TEST
CIRCUIT
FIGURE 5. SINEWAVE DISTORTION TEST CIRCUIT FIGURE 6. CONTROL TO SWITCH FEEDTHROUGH NOISE
TEST CIRCUIT
FIGURE 7. SWITCH OFF SIGNAL FEEDTHROUGH
VIS 0.1µF
VCC
50Ω
VCC/2
10pF
VOS
SWITCH
ON
dB
METER
VIS
0.1µF
VCC
VCC/2
C
VOS1
SWITCH
ON
R
R
fIS = 1MHz SINEWAVE
R = 50Ω
C = 10pF
VCC
R
VCC/2
C
SWITCH
OFF
R
INPUT
VCC/2
VOS2
dB
METER
VIS 10µF
VCC
10kΩ
VCC/2
50pF
VOS
SWITCH
ON
DISTORTION
METER
SINE-
WAVE
VI = VIH VIS
fIS = 1kHz TO 10kHz
VCC
600Ω
VCC/2 50pF
SWITCH
ALTERNATING
SCOPE
VOS
600Ω
VCC/2
ON AND OFF
tr, tf≤ 6ns
fCONT = 1MHz
50% DUTY
CYCLE
VOS VP-P
E
VIS
0.1µF
VCC
R
VCC/2
C
VOS
SWITCH
OFF
dB
METER
R
VCC/2
VC = VIL
fIS ≥ 1MHz SINEWAVE
R = 50Ω
C = 10pF
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
13
FIGURE 8A.
FIGURE 8B. HC TYPES FIGURE 8C. HCT TYPES
FIGURE 8. SWITCH PROPAGATION DELAY, TURN-ON, TURN-OFF TIMES
FIGURE 9. SWITCH ON/OFF PROPAGATION DELAY TEST
CIRCUIT FIGURE 10. SWITCH IN TO SWITCH OUT PROPAGATION
DELAY TEST CIRCUIT
Test Circuits and Waveforms (Continued)
50%
10%
90%
VCC
SWITCH INPUT
tr = 6ns tf = 6ns
tPHL
tPLH VEE
50%
10%
90%
SWITCH OUTPUT
50% 10%
90%
GND
VCC
10%
90% 50%
50%
E OR Sn
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
SWITCH ON
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
SWITCH ONSWITCH OFF
1.3 0.3
2.7
GND
3V
10%
90% 50%
50%
E OR Sn
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
SWITCH ON
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
SWITCH ONSWITCH OFF
trtf
OUT
VCC FOR
VEE FOR
RL = 1kΩ
CL
50pF
TG
VEE FOR
VCC FOR IN
tPLZ AND tPZL
tPHZ AND tPZH
tPLZ AND tPZL
tPHZ AND tPZH
OUT
50pF
TG
IN
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
14
Typical Performance Curves
FIGURE 11. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE
FIGURE 12. CHANNEL ON BANDWIDTH (HC/HCT4051) FIGURE 13. CHANNEL OFF FEEDTHROUGH (HC/HCT4051)
FIGURE 14. CHANNEL ON BANDWIDTH (HC/HCT4052) FIGURE 15. CHANNEL OFF FEEDTHROUGH (HC/HCT4052)
120
100
80
60
40
20
123456789
ON RESISTANCE (Ω)
INPUT SIGNAL VOLTAGE (V)
VCC - VEE = 4.5V
VCC - VEE = 6V
VCC - VEE = 9V
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
-4
-6
-8
-10
-2
0
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 12 TO 3
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 12 TO 3
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 12 TO 3
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 12 TO 3
-80
-100
-20
0
-40
-60
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
-10
-2
0
-4
-6
-8
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 4 TO 3
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 4 TO 3
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
-80
-100
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 4 TO 3
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 4 TO 3
-20
0
-40
-60
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
15
FIGURE 16. CHANNEL ON BANDWIDTH (HC/HCT4053) FIGURE 17. CHANNEL OFF FEEDTHROUGH (HC/HCT4053)
Typical Performance Curves (Continued)
dB
0
-1
-2
-3
-4
FREQUENCY (Hz)
10K 100K 1M 10M 100M
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 5 TO 4
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 5 TO 4
FREQUENCY (Hz)
10K 100K 1M 10M 100M
-80
-100
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 5 TO 4
0
-40
-60
-20
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 5 TO 4
dB
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
16
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