PW DW
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FEATURES
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
D2
D3
D4
D5
D6
D7
A1
A0
SPD
DVDD
D1
D0
CS
WE
LDAC
PWR
AGND
OUT
REF
AVDD
DW OR PW PACKAGE
(TOP VIEW)
APPLICATIONS
DESCRIPTION
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOGCONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
•12-Bit Voltage Output DAC•Programmable Internal Reference•Programmable Settling Time vs PowerConsumption
– 1 µs in Fast Mode– 3.5 µs in Slow Mode•8-Bit µController Compatible Interface•Differential Nonlinearity . . . <0.5 LSB Typ•Voltage Output Range . . . 2x the ReferenceVoltage
•Monotonic Over Temperature
•Digital Servo Control Loops•Digital Offset and Gain Adjustment•Industrial Process Control•Machine and Motion Control Devices•Mass Storage Devices
The TLV5633 is a 12-bit voltage output digital- to-analog converter (DAC) with an 8-bit microcontrollercompatible parallel interface. The 8 LSBs, the 4 MSBs, and 5 control bits are written using three differentaddresses. Developed for a wide range of supply voltages, the TLV5633 can be operated from 2.7 V to 5.5 V.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class A(slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time ofthe DAC allows the designer to optimize speed versus power dissipation. With its on-chip programmableprecision voltage reference, the TLV5633 simplifies overall system design. Because of its ability to source up to1 mA, the internal reference can also be used as a system reference. The settling time and the referencevoltage can be chosen by a control register.
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It isavailable in 20-pin SOIC and TSSOP packages in standard commercial and industrial temperature ranges.
AVAILABLE OPTIONS
PACKAGE
(1)T
A
SOIC (DW) TSSOP (PW)
0°C to 70°C TLV5633CDW TLV5633CPW-40°C to 85°C TLV5633IDW TLV5633IPW
(1) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI Web site at www.ti.com .
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.MCS is a registered trademark of Intel Corporation .
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Interface
Control
4-Bit
DAC MSW
Holding
Latch
A(0,1)
CS
WE
OUT
Power-On
Reset
x2
4
5-Bit
Control
Latch
5
Powerdown
and Speed
Control
2
Voltage
Bandgap
PGA With
Output Enable
12-Bit
DAC
Register
12 12
REF AGND DVDD
LDAC
2
8-Bit
DAC LSW
Holding
Latch
8 8
4
D(0-7)
PWR
SPD
AVDD
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
Terminal Functions
TERMINAL
I/O/P DESCRIPTIONNAME NO.
A1, A0 7, 8 I Address inputAGND 14 P GroundAV
DD
11 P Positive power supply (analog part)CS 18 I Chip select. Digital input active low, used to enable/disable inputsD0-D1 19, 20 I Data inputD2-D7 1-6 I Data inputDV
DD
10 P Positive power supply (digital part)LDAC 16 I Load DAC. Digital input active low, used to load DAC outputOUT 13 O DAC analog voltage outputPWR 15 I Power down. Digital input active lowREF 12 I/O Analog reference voltage input/outputSPD 9 I Speed select. Digital inputWE 17 I Write enable. Digital input active low, used to latch data
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage (DV
DD
, AV
DD
to AGND) 7 VSupply voltage difference range, AV
DD
- DV
DD
-2.8 V to 2.8 VReference input voltage range -0.3 V to V
DD
+ 0.3 VDigital input voltage range -0.3 V to V
DD
+ 0.3 VTLV5633C 0°C to 70°COperating free-air temperature range, T
A
TLV5633I -40°C to 85°CStorage temperature range, T
stg
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX UNIT
5-V operation 4.5 5 5.5 VSupply voltage, DV
DD
, AV
DD
3-V operation 2.7 3 3.3 VSupply voltage difference, ∆V
DD
= AV
DD
- DV
DD
0 0 0 VPower on reset voltage, POR 0.55 2 VDV
DD
= 2.7 V 2High-level digital input voltage, V
IH
VDV
DD
= 5.5 V 2.4DV
DD
= 2.7 V 0.6Low-level digital input voltage, V
IL
VDV
DD
= 5.5 V 1Reference voltage, V
ref
to REF terminal (5-V supply)
(1)
AGND 2.048 AV
DD
-1.5 VReference voltage, V
ref
to REF terminal (3-V supply)
(1)
AGND 1.024 AV
DD
-1.5 VLoad resistance, R
L
2 k ΩLoad capacitance, C
L
100 pFTLV5633C 0 70Operating free-air temperature, T
A
°CTLV5633I -40 85
(1) Due to the x2 output buffer, a reference input voltage ≥AV
DD/2
causes clipping of the transfer function. The output buffer of the internalreference must be disabled, if an external reference is used.
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ELECTRICAL CHARACTERISTICS
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
over recommended operating free-air temperature range, V
ref
= 2.048 V, V
ref
= 1.024 V (unless otherwise noted)
POWER SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fast 2.3 2.8 mAREF
on
Slow 1.3 1.6 mAAV
DD
= 5 V,DV
DD
= 5 V
Fast 1.9 2.4 mAREFNo load,
off
Slow 0.9 1.2 mAI
DD
Power supply current All inputs = AGND or DV
DD
,
Fast 2.1 2.6 mAREFDAC latch = 0x800
on
Slow 1.2 1.5 mAAV
DD
= 3 V,DV
DD
= 3 V
Fast 1.8 2.3 mAREF
off
Slow 0.9 1.1 mAPower down supply current 0.01 1 µAZero scale, external reference
(1)
-60PSRR Power supply rejection ratio dBFull scale, external reference
(2)
-60
STATIC DAC SPECIFICATIONS
Resolution 12 bitsIntegral nonlinearity, end pointINL R
L
= 10 k Ω, C
L
= 100 pF
(3)
±1.2 ±3 LSBadjustedDNL Differential nonlinearity R
L
= 10 k Ω, C
L
= 100 pF
(4)
±0.3 ±0.5 LSBZero-scale error (offset error atE
ZS
20 mVzero scale)
(5)
Zero-scale-error temperatureE
ZS
TC 20 ppm/°Ccoefficient
(6)
% fullE
G
Gain error
(7)
±0.3
scale VGain error temperatureE
G
TC 20 ppm/°Ccoefficient
(8)
OUTPUT SPECIFICATIONS
V
O
Output voltage R
L
= 10 k ΩAV
DD
-0.4 V% fullOutput load regulation accuracy V
O
= 4.096 V, 2.048 V, R
L
= 2 k Ω±0.29
scale V
(1) Power supply rejection ratio at zero scale is measured by varying AV
DD
and is given by: PSRR = 20 log [(E
ZS
(AV
DD
max) -E
ZS
(AV
DD
min))/AV
DD
max](2) Power supply rejection ratio at full scale is measured by varying AV
DD
and is given by: PSRR = 20 log [(E
G
(AV
DD
max) -E
G
(AV
DD
min))/AV
DD
max](3) The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output fromthe line between zero and full scale excluding the effects of zero code and full-scale errors (see text).(4) The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSBamplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)as a change in the digital input code.(5) Zero-scale error is the deviation from zero voltage output when the digital input code is zero (see text).(6) Zero-scale-error temperature coefficient is given by: E
ZS
TC = [E
ZS
(T
max
)-E
ZS
(T
min
)]/2V
ref
× 10
6
/(T
max
- T
min
).(7) Gain error is the deviation from the ideal output (2V
ref
- 1 LSB) with an output load of 10 k Ωexcluding the effects of the zero-error.(8) Gain temperature coefficient is given by: E
G
TC = [E
G
(T
max
)-E
G
(T
min
)]/2V
ref
× 10
6
/(T
max
- T
min
).
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ELECTRICAL CHARACTERISTICS (continued)
OPERATING CHARACTERISTICS
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
over recommended operating free-air temperature range, V
ref
= 2.048 V, V
ref
= 1.024 V (unless otherwise noted)
REFERENCE PIN CONFIGURED AS OUTPUT (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
ref(OUTL)
Low reference voltage 1.003 1.024 1.045 VV
ref(OUTH)
High reference voltage AV
DD
= DV
DD
> 4.75 V 2.027 2.048 2.069 VI
ref(source)
Output source current 1 mAI
ref(sink)
Output sink current -1 mAPSRR Power supply rejection ratio -48 dB
REFERENCE PIN CONFIGURED AS INPUT (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I
Input voltage 0 AV
DD-1.5
VR
I
Input resistance 10 M ΩC
I
Input capacitance 5 pFFast 900Reference input bandwidth REF = 0.2 V
pp
+ 1.024 V dc kHzSlow 500Fast -8710 kHz dBSlow -77REF = 1 V
pp
+ 2.048 V dc,Harmonic distortion, reference input Fast -74AV
DD
= 5 V
50 kHz dBSlow -61100 kHz Fast -66 dBReference feedthrough REF = 1 V
pp
at 1 kHz + 1.024 V dc
(1)
-80 dB
DIGITAL INPUTS
I
IH
High-level digital input current V
I
= DV
DD
1 µAI
IL
Low-level digital input current V
I
= 0 V -1 µAC
I
Input capacitance 8 pF
(1) Reference feedthrough is measured at the DAC output with an input code = 0x000.
over recommended operating free-air temperature range, V
ref
= 2.048 V, and V
ref
= 1.024 V, (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fast 1 3t
s(FS)
Output settling time, full scale R
L
= 10 k Ω, C
L
= 100 pF
(1)
µsSlow 3.5 7Fast 0.5 1.5t
s(CC)
Output settling time, code to code R
L
= 10 k Ω, C
L
= 100 pF
(2)
µsSlow 1 2Fast 6 10SR Slew rate R
L
= 10 k Ω, C
L
= 100 pF
(3)
V/µsSlow 1.2 1.7Glitch energy DIN = 0 to 1, f
CLK
= 100 kHz, CS = V
DD
5 nV-SSNR Signal-to-noise ratio 73 78SINAD Signal-to-noise + distortion 61 67f
s
= 480 kSPS, f
B
= 20 kHz, f
out
= 1 kHz,
dBR
L
= 10 k Ω, C
L
= 100 pFTHD Total harmonic distortion -69 -62SFDR Spurious free dynamic range 63 74
(1) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of0x020 to 0xFDF or 0xFDF to 0x020 respectively.(2) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of onecount.
(3) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
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DIGITAL INPUT TIMING REQUIREMENTS
PARAMETER MEASUREMENT INFORMATION
X Data X
X Address X
tsu(D)
tsu(A) th(DA)
twH(WE)
tsu(WE-LD) tw(LD)
tsu(CS-WE)
D(0-7)
A(0,1)
CS
WE
LDAC
LSWX X MSW X
0X X 1 X
D(0-7)
A(0,1)
CS
WE
LDAC
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
MIN NOM MAX UNIT
t
su(CS-WE)
Setup time, CS low before negative WE edge 15 nst
su(D)
Setup time, data ready before positive WE edge 10 nst
su(A)
Setup time, addresses ready before positive WE edge 20 nst
h(DA)
Hold time, data and addresses held valid after positive WE edge 5 nst
su(WE-LD)
Setup time, positive WE edge before LDAC low 5 nst
wH(WE)
Pulse duration, WE high 20 nst
w(LD)
Pulse duration, LDAC low 23 ns
Figure 1. Timing Diagram
Figure 2. Example of a Complete Write Cycle (MSW, LSW) Using LDAC for Update
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LSW
X X Control X
0
X X 3X
D(0−7)
A(0−1)
CS
WE
LDAC
X
X
MSW
1
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Example of a Complete Write Cycle (MSW, LSW, Control)
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TYPICAL CHARACTERISTICS
4.078
4.077
4.076
4.0755 0 0.5 1 1.5 2 2.5 3
4.079
4.0795
4.08
3.5 4 4.5
4.0785
4.0775
4.0765
- Output Voltage - V
Load Current - mA
VO
Fast Mode, Source
Slow Mode, Source
AVDD = 5 V,
Vref = Int. 2 V,
Input Code = 0xFFF
2.0385
2.037
2.036
2.0355 0 0.5 1 1.5 2 2.5 3
- Output Voltage - V
2.039
2.0395
Load Current - mA
2.04
3.5 4 4.5
2.038
2.0375
2.0365
VO
Fast Mode, Source
Slow Mode, Source
AVDD = 3 V,
Vref = Int. 1 V,
Input Code = 0xFFF
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
DIFFERENTIAL NONLINEARY ERROR
Figure 4.
INTEGRAL NONLINEARTIY ERROR
Figure 5.
MAXIMUM OUTPUT VOLTAGE MAXIMUM OUTPUT VOLTAGEvs vsLOAD CURRENT LOAD CURRENT
Figure 6. Figure 7.
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0.1
0.05
00 0.5 1 1.5 2 2.5 3
0.15
0.2
0.25
3.5 4 4.5
- Output Voltage - V
Load Current - mA
VO
Fast Mode, Sink
Slow Mode, Sink
AVDD = 5 V,
Vref = Int. 2 V,
Input Code = 0x000
0.1
0.05
00 0.5 1 1.5 2 2.5 3
0.15
0.2
0.25
3.5 4 4.5
- Output Voltage - V
Load Current - mA
VO
Fast Mode, Sink
Slow Mode, Sink
AVDD = 3 V,
Vref = Int. 1 V,
Input Code = 0x000
-40
-60
-80
-100100 1000
THD - Total Harmonic Distortion - dB
-30
-10
f - Frequency - Hz
0
10000 100000
-20
-50
-70
-90
Slow Mode
Fast Mode
AVDD = 5 V,
REF = 1 V dc + 1 V pp Sinewave,
Output Full Scale
-40
-60
-80
-100100 1000
THD+N - Total Harmonic Distortion and Noise - dB
-30
-10
f - Frequency - Hz
0
10000 100000
-20
-50
-70
-90
Slow Mode
Fast Mode
AVDD = 5 V,
REF = 1 V dc + 1 V pp Sinewave,
Output Full Scale
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)
MINIMUM OUTPUT VOLTAGE MINIMUM OUTPUT VOLTAGEvs vsLOAD CURRENT LOAD CURRENT
Figure 8. Figure 9.
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION AND NOISEvs vsFREQUENCY FREQUENCY
Figure 10. Figure 11.
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0.5
0.4
0.2
00 10 20 30 40 50 60
- Supply Current - mA
0.7
0.9
1
70 80 90
0.8
0.6
0.3
0.1
t - Time - µs
IDD
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)
POWER DOWN SUPPLY CURRENT
vs
TIME
Figure 12.
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APPLICATION INFORMATION
GENERAL FUNCTION
2 REF CODE
0 1000 [V]
PARALLEL INTERFACE
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
The TLV5633 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallelinterface, a speed and power down control logic, a programmable internal reference, a resistor string, and arail-to-rail output buffer. The output voltage (full scale determined by reference) is given by:
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A poweron reset initially puts the internal latches to a defined state (all bits zero).
The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is writtento one of the DAC holding latches (MSW, LSW) or the control register depends on the address bits A1 and A0.LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be heldlow, if a separate update is not necessary. However, to control the DAC using the load feature, there should beapproximately a 5 ns delay after the positive WE edge before driving LDAC low. Two more asynchronous inputs,SPD and PWR control the settling times and the power-down mode:
SPD: Speed control 1 →fast mode 0 →slow modePWR: Power control 1 →normal operation 0 →power down
It is also possible to program the different modes (fast, slow, power down) and the DAC update latch using thecontrol register. The following tables list the possible combinations of control signals and control bits.
PIN BIT
MODESPD SPD
0 0 Slow0 1 Fast1 0 Fast1 1 Fast
PIN BIT
POWERPWR PWD
0 0 Down0 1 Down1 0 Normal1 1 Down
PIN BIT
LATCHLDAC RLDAC
0 0 Transparent0 1 Transparent1 0 Hold1 1 Transparent
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DATA FORMAT
LAYOUT CONSIDERATIONS
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
The TLV5633 writes data either to one of the DAC holding latches or to the control register depending on theaddress bits A1 and A0.
ADDRESS BITS
A1 A0 REGISTER
0 0 DAC LSW holding0 1 DAC MSW holding1 0 Reserved1 1 Control
The following table lists the meaning of the bits within the control register.D7 D6 D5 D4 D3 D2 D1 D0X X X REF1 REF0 RLDAC PWR SPDX
(1)
X
(1)
X
(1)
0
(1)
0
(1)
0
(1)
0
(1)
0
(1)
(1) Default values: X = Don't Care
SPD: Speed control bit 1 →fast mode 0 →slow modePWR: Power control bit 1 →power down 0 →normal operationRLDAC: Load DAC latch 1 →latch transparent 0 →DAC latch controlled by LDAC pin
REF1 and REF0 determine the reference source and the reference voltage.
REFERENCE BITS
REF1 REF0 REFERENCE
0 0 External0 1 1.024 V1 0 2.048 V1 1 External
If an external reference voltage is applied to the REF pin, external reference must be selected.
To achieve the best performance, it is recommended to have separate power planes for GND, AV
DD
, and DV
DD
.Figure 13 shows how to lay out the power planes for the TLV5633. As a general rule, digital and analog signalsshould be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed inparallel. The two positive power planes (AV
DD
and DV
DD
) should be connected together at one point with aferrite bead.
A 100-nF ceramic low series inductance capacitor between DV
DD
and GND and a 1-µF tantalum capacitorbetween AV
DD
and GND placed as close as possible to the supply pins are recommended for optimalperformance.
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DVDD AVDD
LINEARITY, OFFSET, AND AGAIN ERROR USING SINGLE END SUPPLIES
DAC Code
Output
Voltage
0 V
Negative
Offset
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
Figure 13. TLV5633 Board Layout
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative.With a positive offset, the output voltage changes on the first code change. With a negative offset the outputvoltage may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negativesupply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage remains at zero until the input code value produces a sufficient positive output voltage toovercome the negative offset voltage, resulting in the transfer function shown in Figure 14 .
Figure 14. Effect of Negative Offset (Single Supply)
The offset error, not the linearity error, produces this breakpoint. The transfer function would have followed thedotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) afteroffset and full scale are adjusted out or accounted for in some way. However, single supply operation does notallow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity ismeasured between full scale code and the lowest code that produces a positive output voltage.
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TLV5633 INTERFACED to an Intel MCS
®
51 Controller
P2 A(15-8)
P0 AD(7-0)
ALE
WR
D(7-0)
A
B
C
G1
G2A
G2B
A(1-0)
D(7-0)
CS
WE
REF
A(15-0)
AD(7-0)
CS(7-0)
DVDD DVDD
8
8
8
16
8
8
RL
74AC373
8xC51
74AC138
TLV5633
A15
A2
A3
A4
2
Q(7-0)
Y(7-0)
G2A SPD
PWR
LDAC
LE OE
OUT
To Other Devices Requiring
Voltage Reference
P3.5
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
The circuit in Figure 15 shows how to interface the TLV5633 to an Intel MCS
®
51 microcontroller. The addressbus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. To separatethe address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), whichis connected to a latch at port 0.
An address decoder is required to generate the chip select signal for the TLV5633. In this example, a simple3-to-8 decoder (74AC138) is used for the interface as shown in Figure 15 . The DAC is memory mapped ataddresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations(0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used togenerate the chip select signals for the entire system.
The data pins and the WE pin of the TLV5633 can be connected directly to the multiplexed address and databus and the WR signal of the controller.
The application uses the TLV5633 device's internal reference at 2.048 V. The LDAC pin is connected to P3.5and is used to update the DAC after both data bytes have been written.
Figure 15. TLV5633 Interfaced to an Intel MCS
®
51 Controller
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SOFTWARE
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
In the following example, the code generates a waveform at 20 KSPS with 32 samples stored in a table withinthe program memory space of the microcontroller.
The waveform data is located in the program memory space at segment SINTBL beginning with the MSW of thefirst 16-bit word (the 4 MSBs are ignored), followed by the LSW. Two bytes are required for each DAC word (thetable is not shown in the code example).
The program consists of two parts:•A main routine, which is executed after reset and which initializes the timer and the interrupt system of themicrocontroller.
•An interrupt service routine, which reads a new value from the waveform table and writes it to the DAC.;--------------------------------------------------------------------------------------
; File: WAVE.A51; Function: wave generation with TLV5633; Processors: 80C51 family (running at 12 MHz); Software: ASM51 assembler, Keil BL51 code-banking linker;(C) 1999 Texas Instruments;--------------------------------------------------------------------------------------
;--------------------------------------------------------------------------------------
; Program function declaration;--------------------------------------------------------------------------------------
NAME WAVEMAIN SEGMENT CODEISR SEGMENT CODEWAVTBL SEGMENT CODEVAR1 SEGMENT DATASTACK SEGMENT IDATA;--------------------------------------------------------------------------------------
; Code start at address 0, jump to start;--------------------------------------------------------------------------------------
CSEG AT 0LJMP start ; Execution starts at address 0 on power-up.;--------------------------------------------------------------------------------------
; Code in the timer0 interrupt vector;--------------------------------------------------------------------------------------
CSEG AT 0BH
LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh;--------------------------------------------------------------------------------------
; Define program variables;--------------------------------------------------------------------------------------
RSEG VAR1rolling_ptr: DS 1;--------------------------------------------------------------------------------------
; Interrupt service routine for timer 0 interrupts;--------------------------------------------------------------------------------------
RSEG ISRTIMER0ISR:
PUSH PSWPUSH ACC; The signal to be output on the dac is stored in a table; as 32 samples of msb, lsb pairs (64 bytes).; The pointer, rolling_ptr, rolls round the table of samples; incrementing by 2 bytes (1 sample) on each interrupt; (at the end of this routine).MOV DPTR, #wavetable ; set DPTR to the start of the tableMOV R0, #001H ; R0 selects DAC MSWMOV A,rolling_ptr ; ACC loaded with the pointer into the wave tableMOVC A,@A+DPTR ; get msb from the tableMOVX @R0, A ; write DAC MSWMOV R0, #000H ; R0 selects DAC LSWMOV A,rolling_ptr ; move rolling pointer back in to ACCINC A ; increment ACC holding the rolling pointerMOVC A,@A+DPTR ; which is the lsb of this sample, now in ACCMOVX @R0, A ; write DAC LSWMOV A,rolling_ptr ; load ACC with rolling pointer againINC A ; increment the ACC twice, to get next sampleINC AANL A,#003FH ; wrap back round to 0 if &gt;64MOV rolling_ptr,A ; move value held in ACC back to the rolling pointer
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TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
CLR T1 ; set LDACB = 0 (update DAC)SETB T1 ; set LDACB = 1POP ACCPOP PSWRETI;--------------------------------------------------------------------------------------
; Set up stack;--------------------------------------------------------------------------------------
RSEG STACKDS 10h ; 16 Byte Stack!;--------------------------------------------------------------------------------------
; Main Program;--------------------------------------------------------------------------------------
RSEG MAINstart:
MOV SP,#STACK-1 ; first set Stack PointerCLR AMOV rolling_ptr,A ; set rolling pointer to 0MOV TMOD,#002H ; set timer 0 to mode 2 - auto-reloadMOV TH0,#0CEH ; set timer 2 re-load value for 20 kHz interruptsMOV P2, #080H ; set A15 of address bus high to 'memory map'; device up beyond used address spaceSETB T1 ; set LDACB = 1 (on P3.5); TLV5633 setupMOV R0, #003H ; R0 selects control registerMOV A, #011H ; LOAD ACC with control register value:; REF1=1, REF0=0 -&gt; 2.048V internal reference; RLDAC=0 -&gt; use LDACB pin to control DAC; PD=0 -&gt; DAC enabled; SPD=1 -&gt; FAST mode; write control word:MOVX @R0, A ; write DAC control wordSETB ET0 ; enable timer 0 interruptsSETB EA ; enable all interruptsSETB TR0 ; start timer 0always:
SJMP always
RET;--------------------------------------------------------------------------------------
; Table of 32 wave samples used as DAC data;--------------------------------------------------------------------------------------
RSEG WAVTBLwavetable:
;...insert 32 samples here....END
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DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error (E
ZS
)
Gain Error (E
G
)
Signal-To-Noise Ratio + Distortion (SINAD)
Spurious Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximumdeviation of the output from the line between zero and full scale excluding the effects of zero code and full-scaleerrors.
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between themeasured and ideal 1-LSB amplitude change of any two adjacent codes. Monotonic means the output voltagechanges in the same direction (or remains constant) as a change in the digital input code.
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
Gain error is the error in slope of the DAC transfer function.
Signal-to-noise ratio + distortion is the ratio of the rms value of the output signal to the rms sum of all otherspectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD isexpressed in decibels.
Spurious free dynamic range is the difference between the rms value of the output signal and the rms value ofthe spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of thefundamental signal and is expressed in decibels.
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TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
Revision history
Revision Date Description
A 01/2001 Minor typographical changes.Changed the High-level and Low-level digital input voltage in the Recommended Operating ConditinsB 08/2003
table.C 09/2006 Changed the positions of LSW and MSW in Figure 2 and Figure 3 .
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PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV5633CDW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5633CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5633CPW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5633CPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5633CPWR ACTIVE TSSOP PW 20 TBD Call TI Call TI
TLV5633CPWRG4 ACTIVE TSSOP PW 20 TBD Call TI Call TI
TLV5633IDW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5633IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5633IPW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5633IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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