August 2004 ASM4SSTVF32852
rev 2.0
Alliance Semiconductor
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject
to change without notice.
DDR 24-Bit to 48-Bit Registered Buffer
Features
Differential clock signals.
Supports SSTL_2 class II specifications on
inputs and outputs.
Low voltage operation.
VDD = 2.3V to 2.7V.
Available in 114 ball BGA package.
Industrial temperature range also available.
Product Description
The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal
bus driver designed for 2.3V to 2.7V VDD operation and
SSTL_2 I/O levels except for the LVCMOS RESETB
input.
Data flow from D to Q is controlled by the differential
clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow,
and CLKBis used to maintain sufficient noise margins,
whereas the RESETB, an LVCMOS asynchronous
signal is intended for use at the time of power-up only.
The ASM4SSTVF32852 supports a low power standby
mode of operation. A logic “Low” level at RESETB,
assures that all internal registers and outputs (Q) are
reset to a logic “Low” state, and that all input receivers,
data (D) buffers, and clock (CLK/CLKB) are switched
off. Please note that RESETBmust always be
supported with a LVCMOS levelsat a valid logic state
since VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state
before a stable clock has been supplied, RESETB must
be held at a logic “Low” level during power-up.
In the DDR DIMM application, RESETB is specified to
be asynchronous with respect to CLK/CLKB. Therefore,
no timing relationship can be guaranteed between the
two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be
driven to a logic “Low” level quickly relative to the time
to disable the differential input receivers. This ensures
there are no “glitches” on any output. However, when
coming out of low power standby state, the register will
become active quickly relative to the time taken to
enable the differential input receivers. When the data
inputs are at a logic level “Low” and the clock is stable
during the “Low-to-High”transition of RESETBuntil the
input receivers are fully enabled, the design ensures
that the outputs will remain at a logic “Low” level.
Applications
DDR Memory Modules.
Provides complete DDR DIMM logic solution
with ASM5CVF857, ASM4SSTVF16857 and
ASM4SSTVF16859.
SSTL_2 compatible data registers.
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 2 of 13
Block Diagram
Pin Configurations
114-Pin Ball BGA
Q1B
Q1A
CLK
CLK
RESETB
D1
VREF
CLK
B
D1
To 23 Other Channels
B
E
F
G
J
K
T
U
P
M
A
L
V
W
1 2 3 4 5 6
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 3 of 13
Pin Description
Pin # Pin Name Type Description
R1, P1, N1, N2, M1, L2, L1, K1, K2, J2, J1, H1,
G1, G2, F1, F2, E1, D1, D2, C1, C2, B1, A1, A2 Q (24:1)A O Data output.
R6, P6, N6,N5,M6, L5, L6, K6, K5, J5, J6, H6, G6,
G5, F6, F5, E6, D6, D5, C6, C5, B6, A6, A5 Q (24:1)B O Data output.
E2, B3, D3, G3, J3, L3, M3, P3, B4, D4, G4, J4,
L4, M4, P4, E5 GND P Ground.
B2, M2, P2, C3, E3, F3, H3, K3, N3, C4, E4, F4,
H4, K4, N4, B5, M5, P5 VDDQ P Output supply voltage, 2,5V nominal.
W4, V4, U4, W5, W6, V5, T4, V6, U6, U5, T6, T5,
W3, V3, U3, W2, W1, V2, T3, V1, U1, U2, T1, T2 D(24:1) I Data input.
A3 CLK I Positive master clock input.
A4 CLKB I Negative master clock input.
H2, H5, R2, R5 VDD P Core supply voltage, 2.5V nominal.
R3 RESETB I Reset (Active Low).
R4 VREF I Input reference, 1.25V nominal.
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 4 of 13
Pin Configuration Assignments
1 2 3 4 5 6
A Q2A Q1A CLK CLKB Q1B Q2B
B Q3A VDDQ GND GND VDDQ Q3B
C Q5A Q4A VDDQ VDDQ Q4B Q5B
D Q7A Q6A GND GND Q6B Q7B
E Q8A GND VDDQ VDDQ GND Q8B
F Q10A Q9A VDDQ VDDQ Q9B Q10B
G Q12A Q11A GND GND Q11B Q12B
H Q13A VDD VDDQ VDDQ VDD Q13B
J Q14A Q15A GND GND Q15B Q14B
K Q17A Q16A VDDQ VDDQ Q16B Q17B
L Q18A Q19A GND GND Q19B Q18B
M Q20A VDDQ GND GND VDDQ Q20B
N Q22A Q21A VDDQ VDDQ Q21B Q22B
P Q23A VDDQ GND GND VDDQ Q23B
R Q24A VDD RESETB VREF VDD Q24B
T D2 D1 D6 D18 D13 D14
U D4 D3 D10 D22 D15 D16
V D5 D7 D11 D23 D19 D17
W D8 D9 D12 D24 D21 D20
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 5 of 13
Truth Table1
Inputs Q Outputs
RESET# CLK CLK# D Q
L X or floating X or floating X or floating L
H ↑ ↓ H H
H ↑ ↓ L L
H L or H L or H X Q02
Note: 1. H=High signal level, L=Low signal level, ↑= transition from low to high, ↓= transition from high to low, X = don’t care 2.
Output level before the indicated steady state input conditions were established.
Absolute Maximum Ratings
Parameter Min Max Unit
Storage Temperature -65 +150 °C
Supply Voltage -0.5 3.6 V
Input Voltage1-0.5 VDD + 0.5 V
Output Voltage1,2 -0.5 VDD +0.5 V
Input Clamp Current ± 50 mA
Output Clamp Current ±50 mA
Continuous Output Current ±50 mA
VDD, VDDQ or GND current/pin 100 mA
Package Thermal Impedance355 °C/W
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0> VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged
periods can affect device reliability.
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 6 of 13
Recommended Operating Conditions
Guaranteed by design. Not 100% tested in production.
Parameter Description Min Typ Max Unit
VDD Supply voltage 2.3 2.5 2.7 V
VDDQ Output supply voltage 2.3 2.5 2.7 V
VREF Reference voltage 1.15 1.25 1.35 V
VTT Termination voltage VREF -0.04 VREF VREF + 0.04 V
VIInput voltage 0 VDDQ V
VIH(DC) DC input high voltage VREF + 0.15 V
VIH(AC) AC input high voltage VREF + 0.31 V
VIL(DC) DC input low voltage VREF -0.15 V
VIL(AC) AC input low voltage
Data
Inputs
VREF -0.31 V
VIH Input high voltage level 1.7 V
VIL Input low voltage level
RESETB
0.7 V
VICR Common mode input range CLK 0.97 1.53 V
VID Differential input voltage CLKB 0.36 V
VIX Cross-point voltage of differential clock pair (VDDQ/2) -0.2 (VDDQ/2) +0.2 V
IOH High-level output current -19 mA
IOl Low-level output current 19 mA
TAOperating free-air temperature 0 70 °C
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 7 of 13
DC Electrical Characteristics
TA= 0°C to 70°C, VDD = 2.5 ± 0.2V, and VDDQ = 2.5±0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
Symbol Parameter Test conditions VDDQ Min Typ Max Units
VIK II= -18 mA 2.3 V -1.2 V
IOH = -100 A2.3 V to 2.7 V VDD -0.2 V
VOH
IOH = -16 mA 2.3 V2.05 V
IOL = 100 A2.3 V to 2.7 V0.2 V
VOL
IOL = 16 mA 2.3 V 0.20 V
IIAll inputs VI= VDD or GND 2.7 V± 5A
Standby
(static) RESETB = GND 0.01 A
IDD
Operating
(static) VI= VIH(AC) or VIL(AC),
RESETB = VDD 40 mA
Dynamic
operating
(clock only)
RESETB = VDD,
VI= VIH(AC) or VIL(AC),
CLK and CLKB switching
50% duty cycle
35 A/clock
MHz
IDDD
Dynamic
operating
(per each
data input)
RESETB = VDD, VI= VIH(AC) or
VIL(AC), CLK and CLKB =
switching 50% duty cycle;
One data input switching at half
clock frequency, 50% duty cycle
IO= 02.5V
7
/clock
MHz/data
input
rOH Output high IOH = -20 mA 2.3 V to 2.7 V 12
rOL Output low IOL = 20 mA 2.3 V to 2.7 V 10
rO(D)
|rOH - rOL|
each
separate bit IO= 20 mA, TA= 25C2.5 V 4
Data inputs 2.5 V2.5 3.5 pF
Ci
CLK & CLKB
VI= VREF ± 350 mV, VICR = 1.25 V,
VI(PP) = 360 mV 2.5 V2.5 3.5 pF
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 8 of 13
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted).
Switching Characteristics
(Over recommended operating free-air temperature range unless otherwise noted.)
VDD = 2.5 V ± 0.2 V
Symbol From (input) To (output)
Min Typ Max
Units
fmax 200 – – MHz
tPD CLK, CLKB Q 1.9 2.7 ns
tphl RESETB Q– – 4.5 ns
VDD = 2.5V±0.2V
Symbol Parameters
Min Max
Unit
fCLOCK Clock frequency 200 MHz
TPD Clock to output time 1.9 2.7 ns
TRST Reset to output time 4.5 ns
Setup time, fast slew rate 2,4 0.5
tSSetup time, slow slew rate 3,4 Data before CLK, CLKB
0.7
ns
ns
Hold time, fast slew rate 2,4 0.3
thHold time, slow slew rate 3,4 Data after CLK, CLKB
0.5
ns
ns
tSL Output slew rate 1 4 V/ns
Note:
1. Guaranteed by design, not 100% tested in production.
2. For data signal input slew rate >= 1V/ns
3. For data signal input slew rate >= 0.5 V/ns and < 1V/ns
4. CLK,CLKB signals input slew rates are >=1V/ns
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 9 of 13
tw
Input VIH
VIL
VREF VREF
Input VIH
VIL
VREF VREF
VICR
Timing input
tsth
VI(pp)
Parameter Measurement Information (VDD = 2.5 V ± 0.2V)
VTT
RL= 50
Test point
CL= 30 pF1
Load circuit
From output under test
1CLincludes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics:
PRR 10 MHz, Zo= 50 , input slew rate = 1 V/ns ± 20% (unless otherwise specified).
The outputs are measured one at a time with one transition per measurement.
VTT = VREF = VDDQ/2.
VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
VIL = VREF -310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
tPLH and tPHL are the same as tpd.
Input active and inactive times
LVCMOS RESETB
IDD1
1IDD tested with clock and data inputs held at VDD or GND, and IO= 0 mA.
VDD
0 V
IDDH
IDDL
VDD/2
10%
VDD/2
90%
tinact tact
Input
Pulse duration
Setup and hold times
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 10 of 13
Propagation delay times
VICR VICR
Timing input
Output VTT VTT VOH
VOL
tPLH tPHL
VI(pp)
LVCMOS RESETB
Input
Output
VIH
VIL
VOH
VOL
tPHL
VDD/2
VTT
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 11 of 13
Package Dimensions
114-Pin Ball BGA
BALL GRID REF. DIMENSIONS
D E T Min/Max eHORIZ VERT TOTAL dh Min/Max b c
16.00
BSC 5.50
BSC 1.30/1.50 0.80
BSC 6 19 114 0.46 0.31/0.41 0.80 0.75
d (TYP)
A1
T
E
h (TYP)
C
c (REF)
-
e
-
TYP
-
e
-
TYP
b (REF
)
A
B
1
2
3
4
Numeric Designations for
Horizontal Grid
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
are not used)
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 12 of 13
Ordering Codes
Ordering Number Marking Package Type Quantity
per reel Temperature
ASM4SSTVF32852-114BT AS4SSTVF32852B114-pin Ball, BGA, tray/tube 0C to 70C
ASM4SSTVF32852-114BR AS4SSTVF32852B114-pin Ball, BGA, tape and reel 2500 0C to 70C
ASM4ISSTVF32852-114BT AS4ISSTVF32852B 114-pin Ball, BGA, tray/tube -40°C to +85°C
ASM4ISSTVF32852-114BR AS4ISSTVF32852B 114-pin Ball, BGA, tape and reel 2500 -40°C to +85°C
August 2004 ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer 13 of 13
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and
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products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance.
Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is
under development, significant changes to these specifications are possible. The information in this product data
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Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright ÿ Alliance Semiconductor
All Rights Reserved
Advance Information
Part Number: ASM4SSTVF32852
Document Version: v1.1