ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER General Description Features The ICS853111-02 is a low skew, high performance 1-to-10 Differential-to-2.5V/3.3V LVPECL/ECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS853111-02 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853111-02 ideal for those clock distribution applications demanding well defined performance and repeatability. * * * Ten differential 2.5V, 3.3V LVPECL/ECL outputs * * Maximum output frequency: 3.2GHz * * * * Output skew: 25ps (typical) * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V ICS * * Block Diagram PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input Part-to-part skew: 85ps (typical) Propagation delay: 680ps (typical) LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Q4 17 Q4 24 23 22 21 20 19 18 VDDO GND SEL3 1 Q0 VDDA PCLK1 Pulldown Pullup/Pulldown VDD 0 PLL_SEL Pin Assignment PCLK0 Pulldown nPCLK0 Pullup/Pulldown nQ0 nQ1 Q2 nQ2 25 16 VCCO nQ2 26 15 Q7 Q2 27 14 nQ7 13 Q8 nQ8 11 Q9 Q0 31 10 nQ9 VCCO 32 9 VCCO Q4 nQ4 Q5 nQ5 Q6 nQ6 1 2 3 4 5 6 7 8 VEE 12 30 nPCLK1 29 nQ0 VBB Q1 nQ3 PCLK1 nQ3 PCLK0 nQ1 28 nPCLK0 VBB VCCO VCC CLK_SEL Pulldown Q1 CLK_SEL nPCLK1 Two selectable differential input pairs ICS853111-02 Q7 32-Lead TSSOP, E-Pad nQ7 7mm x 7mm x 1mm package body nQ8 Y Package Top View nQ8 Q9 nQ9 IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 1 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1 VCC Power 2 CLK_SEL Input Pulldown Clock select input. When HIGH, selects PCLK1/nPCLK1 inputs. When LOW, selects PCLK0/nPCLK0 inputs. LVTTL / LVCMOS interface levels. 3 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. 4 nPCLK0 Input Pullup/ Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating. 5 VBB Output 6 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK1 Input Pullup/ Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating. 8 VEE Power Negative supply pin. 9, 16, 25, 32 VCCO Power Output supply pins. 10, 11 nQ9, Q9 Output Differential output pair. LVPECL/ECL interface levels. 12, 13 nQ8, Q8 Output Differential output pair. LVPECL/ECL interface levels. 14, 15 nQ7, Q7 Output Differential output pair. LVPECL/ECL interface levels. 17, 18 nQ6, Q6 Output Differential output pair. LVPECL/ECL interface levels. 19, 20 nQ5, Q5 Output Differential output pair. LVPECL/ECL interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVPECL/ECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL/ECL interface levels. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL/ECL interface levels. 28, 29 nQ1, Q1 Output Differential output pair. LVPECL/ECL interface levels. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL/ECL interface levels. Positive supply pin. Bias voltage. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter RPULLDOWN Input Pulldown Resistor 75 k RVCC/2 Pullup/Pulldown Resistors 50 k IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Test Conditions 2 Minimum Typical Maximum Units ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Function Tables Table 3A. Clock Input Function Table Inputs Outputs PCLK0 or PCLK1 nPCLK0 or nPCLK1 Q0:Q9 nQ0:nQ9 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting 0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting 1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting Table 3B. Control Input Function Table Inputs CLK_SEL Selected Source 0 PCLK0, nPCLK0 1 PCLK1, nPCLK1 IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 3 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0V) Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0V) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA VBB Sink//Source, IBB 0.5mA Operating Temperature Range, TA -40C to +85C Package Thermal Impedance, JA 49.5C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 4 Minimum Typical Maximum Units 2.375 3.3 3.8 V 85 mA ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Table 4B. DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40C to 85C -40C Symbol Parameter 25C 80C Min Typ Max Min Typ Max Min Typ Max Units VOH Output High Voltage; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365 V VOL Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V VIH Input High Voltage (Single-ended) 2.075 2.36 2.075 2.36 2.075 2.36 V VIL Input Low Voltage (Single-ended) 1.43 1.765 1.43 1.765 1.43 1.765 V VBB Output Voltage Reference; NOTE 2 1.86 1.98 1.86 1.98 1.86 1.98 V VPP Peak-to-Peak Input Voltage 150 1200 150 1200 150 1200 V VCMR Input High Voltage Common Mode Range; NOTE 3, 4 1.2 3.3 1.2 3.3 1.2 3.3 V IIH Input High Current PCLK0, PCLK1 nPCLK0, nPCLK1 200 A IIL Input Low Current PCLK0, PCLK1 nPCLK0, nPCLK1 800 800 200 -200 800 200 -200 -200 A Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V .Table 4C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40C to 85C -40C Symbol Parameter 25C 80C Min Typ Max Min Typ Max Min Typ Max Units VOH Output High Voltage; NOTE 1 1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565 V VOL Output Low Voltage; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83 V VIH Input High Voltage (Single-ended) 1.275 1.56 1.275 1.56 1.275 -0.8 V VIL Input Low Voltage (Single-ended) 0.63 0.965 0.63 0.965 0.63 0.965 V VPP Peak-to-Peak Input Voltage 150 1200 150 1200 150 1200 V VCMR Input High Voltage Common Mode Range; NOTE 2, 3 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input High Current PCLK0, PCLK1 nPCLK0, nPCLK1 200 A IIL Input Low Current PCLK0, PCLK1 nPCLK0, nPCLK1 800 200 -200 800 200 -200 -200 800 A Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V. IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 5 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Table 4D. ECL DC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V, TA = -40C to 85C -40C Symbol Parameter 25C 80C Min Typ Max Min Typ Max Min Typ Max Units VOH Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VIH Input High Voltage (Single-ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V VIL Input Low Voltage (Single-ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V VBB Output Voltage Reference; NOTE 2 -1.486 -1.386 -1.486 -1.386 -1.486 -1.386 V VPP Peak-to-Peak Input Voltage 150 1200 150 1200 150 1200 V VCMR Input High Voltage Common Mode Range; NOTE 3, 4 VEE+1.2 0 VEE+1.2 0 VEE+1.2 0 V IIH Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 200 A IIL Input Low Current PCLK0, PCLK1 nPCLK0, nPCLK1 800 200 -200 800 200 -200 -200 800 A Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 6 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER AC Electrical Characteristics Table 5. AC Characteristics, VCC = -3.8V to -2.375V or , VCC = 2.375V to 3.8V; VEE = 0V, TA = -40C to 85C -40C Symbol Parameter Min fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Typ 25C Max 3.2 680 750 Output Skew; NOTE 2, 4 25 tsk(pp) Part-to-Part Skew; NOTE 3, 4 85 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jjitter Section 0.03 tR / tF Output Rise/Fall Time 20% to 80% Min 600 60 200 Typ 80C Max Min Typ Max Units 3.2 GHz 790 890 ps 3.2 650 725 790 690 37 25 37 25 37 ps 225 85 225 85 225 ps 0.03 325 100 200 0.03 280 130 200 ps 270 ps All parameters are measured at f 1GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 7 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. 0 Additive Phase Jitter @ 155.52MHz = 0.03ps (typical) -10 -20 -30 -40 SSB Phase Noise dBc/Hz -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 100 10k 1k 100k 1M 10k 100k 10M 1M 10M 100M 100M Offset Frequency (Hz) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 8 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Parameter Measurement Information 2V VCC VCC, VCCO Qx SCOPE nPCLK V Cross Points PP V CMR PCLKx LVPECL nQx VEE VEE - -1.8V to -0.375V LVPECL Output Load AC Test Circuit nQx Differential Input Level nQx Par t 1 Qx Qx nQy nQy Par t 2 Qy Qy tsk(o) tsk(pp) Part-to-Part Skew Output Skew nPCLKx 80% PCLKx 80% VSW I N G Clock Outputs nQ0:nQ9 20% 20% tR Q0:Q9 tF tPD Output Rise/Fall Time IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Propagation Delay 9 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Application Information Wiring the Differential Input to Accept Single-ended LVCMOS Levels Figure 1A shows an example of the differential input that can be wired to accept single-ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be loacted as close as possible to the input pin. VCC R1 1K Single Ended Clock Input PCLKx V_REF C1 0.1u nPCLKx R2 1K Figure 1A. Single-Ended LVCMOS Signal Driving Differential Input Wiring the Differential Input to Accept Single-ended LVPECL Levels negative input. The C1 capacitor should be loacted as close as possible to the input pin. Figure 2 shows an example of the differential input that can be wired to accept single-ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the VCC C1 0.1uF CLK_IN PCLK VBB nPCLK Figure 2. Single-Ended LVPECL Signal Driving Differential Input IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 10 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER LVPECL Clock Input Interface (with VBB) most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the 3.3V 3.3V 3.3V 3.3V R1 50 3.3V Zo = 50 R2 50 Zo = 50 PCLK PCLK R1 100 Zo = 50 nPCLK Zo = 50 nPCLK CML HiPerClockS PCLK/nPCLK CML Built-In Pullup HiPerClockS PCLK/nPCLK Figure 3A. HiPerClockS PCLK/nPCLK Input Driven by a CML Driver Figure 3B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 3.3V LVPECL Zo = 50 Zo = 50 C1 Zo = 50 C2 PCLK PCLK Zo = 50 VBB nPCLK nPCLK LVPECL R1 84 PCLK/nPCLK HiPerClockS Input R2 84 R5 100 - 200 Figure 3C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver R6 100 - 200 R1 50 R2 50 Figure 3D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 Zo = 50 R4 120 C1 PCLK Zo = 60 R5 100 PCLK VBB C2 nPCLK Zo = 50 Zo = 60 nPCLK SSTL R1 120 R2 120 PCLK/nPCLK LVDS R1 1k HiPerClockS PCLK/nPCLK R2 1k C3 0.1F Figure 3E. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Figure 3F. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver 11 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Recommendations for Unused Output Pins Inputs: Outputs: PCLK/nPCLK INPUTS LVPECL Outputs For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. For applications All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 3.3V Zo = 50 125 FOUT FIN Zo = 50 Zo = 50 FOUT 50 RTT = 125 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 Figure 4A. 3.3V LVPECL Output Termination IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 84 Figure 4B. 3.3V LVPECL Output Termination 12 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Termination for 2.5V LVPECL Outputs ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 R3 250 50 + 50 + 50 - 50 2.5V LVPECL Driver - R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 5A. 2.5V LVPECL Driver Termination Example Figure 5B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50 + 50 - 2.5V LVPECL Driver R1 50 R2 50 Figure 5C. 2.5V LVPECL Driver Termination Example IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 13 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER PIN LAND PATTERN (GROUND PAD) SOLDER PIN PAD Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 14 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Schematic Example This application note provides a general design guide using ICS853111-02 LVPECL buffer. Figure 7 shows a schematic example of the ICS853111-02 LVPECL clock buffer. In this example, the input is driven by an LVPECL driver. CLK_SEL is set at logic high to select PCLK0/nPCLK0 input. Zo = 50 + Zo = 50 R2 50 VCC 32 31 30 29 28 27 26 25 C6 (Option) 0.1u Zo = 50 Ohm 1 2 3 4 5 6 7 8 Zo = 50 Ohm R4 1K R10 50 C8 (Option) 0.1u R11 50 9 10 11 12 13 14 15 16 R9 50 VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO 3.3V LVPECL VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO VCC - Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 R1 50 R3 50 24 23 22 21 20 19 18 17 U1 ICS853111 VCC Zo = 50 + VCC=3.3V Zo = 50 (U1-9) VCC C1 0.1uF (U1-16) C2 0.1uF (U1-25) (U1-32) C3 0.1uF - (U1-1) C4 0.1uF R8 50 C5 0.1uF C7 (Option) 0.1u R7 50 R13 50 Figure 7. ICS853111-02 Example LVPECL Clock Output Buffer Schematic IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 15 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS853111-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853111-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 85mA = 323mW * Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is10 * 30.94mW = 309.4mW Total Power_MAX (3.8V, with all outputs switching) = 323mW + 309.4mW = 632.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.632W * 49.5C/W = 116.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance JA for 32 Lead TQFP, E-Pad Forced Convection JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 69.3C/W 57.8C/W 52.1C/W Multi-Layer PCB, JEDEC Standard Test Boards 49.5C/W 43.8C/W 41.3C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 16 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. VCC Q1 VOUT RL 50 VCC - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCCO - 2V. * For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.935V (VCC_MAX - VOH_MAX) = 0.935V * For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.67V (VCC_MAX - VOL_MAX) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.935V)/50] * 0.935V = 19.92mW Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/RL] * (VCOC_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 17 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Reliability Information Table 7. JA vs. Air Flow Table for a 32 Lead TQFP, E-Pad JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 69.3C/W 57.8C/W 52.1C/W Multi-Layer PCB, JEDEC Standard Test Boards 49.5C/W 43.8C/W 41.3C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS853111-02 is: 1340 Pin compatible with MC100EP111 and MC100LVEP111 IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 18 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Package Outline and Package Dimensions Package Outline - G Suffix for 32 Lead TQFP, E-Pad -HD VERSION EXPOSED PAD DOWN Table 8. Package Dimensions 32 Lead TQFP, E-Pad Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 D3 & E3 e L ccc JEDEC Variation: ABC - HD All Dimensions in Millimeters Minimum Nominal Maximum 32 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.35 0.40 0.09 0.20 9.00 Basic 7.00 Basic 5.60 Ref. 3.0 4.0 0.80 Basic 0.45 0.60 0.75 0 7 0.10 Reference Document: JEDEC Publication 95, MS-026 IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 19 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number ICS853111AY-02 ICS853111AY-02T ICS853111AY-02LF ICS853111AY-02LFT Marking ICS853111A02 ICS853111A02 ICS853111A02L ICS853111A02L Package 32 Lead TQFP, E-Pad 32 Lead TQFP, E-Pad "Lead-Free" 32 Lead TQFP, E-Pad "Lead-Free" 32 Lead TQFP, E-Pad Shipping Packaging Tube 1000 Tape & Reel Tube 1000 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 20 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Revision History Sheet Rev A B Table Page T9 10 17 Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added Lead-Free marking. 1/10/06 T4B 5 T4C 5 T4D 6 3.3V LVPECL DC Characteristics - changed IIH max. from 150A to 200A. Changed IIL min. from -150A to -200A. 2.5V LVPECL DC Characteristics - changed IIH max. from 150A to 200A. Changed IIL min. from -150A to -200A. ECL DC Characteristics - changed IIH max. from 150A to 200A. Changed IIL min. from -150A to -200A. Updated LVPECL Clock Input Interface Section. Updated EPAD Thermal Release Path Section. Power Considerations - updated Junction Temperature equation with worst case thermal resistance of 49.5C/W. 2/13/08 11 14 16 Description of Change IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Date 21 ICS853111AY-02 REV. B FEBRUARY 13, 2008 ICS853111-02 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology IDT (S) Pte. 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