LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853111-02
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 1
ICS853111AY-02 REV. B FEBRUARY 13, 2008
General Description
The ICS853111-02 is a low skew, high performance
1-to-10 Differential-to-2.5V/3.3V LVPECL/ECL
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS853111-02 is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS853111-02 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
Features
•Ten differential 2.5V, 3.3V LVPECL/ECL outputs
•Two selectable differential input pairs
•PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•Maximum output frequency: 3.2GHz
•Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
•Output skew: 25ps (typical)
•Part-to-part skew: 85ps (typical)
•Propagation delay: 680ps (typical)
•LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
•ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
ICS853111-02
32-Lead TSSOP, E-Pad
7mm x 7mm x 1mm package body
Y Package
Top View
Pin Assignment
Block Diagram
Q0
nQ0
Q1
nQ1
CLK_SEL
PCLK0
nPCLK0 0
1
Pulldown
Pullup/Pulldown
Pulldown
VBB
Q2
nQ2
nQ3
nQ3
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
nQ8
nQ8
Q9
nQ9
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
VCCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
VCCO
VCC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
PLL_SEL
VDDA
SEL3
VDDO
Q4
Q4
GND
VDD
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 2
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1V
CC Power Positive supply pin.
2 CLK_SEL Input Pulldown Clock select input. When HIGH, selects PCLK1/nPCLK1 inputs. When LOW,
selects PCLK0/nPCLK0 inputs. LVTTL / LVCMOS interface levels.
3 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.
4 nPCLK0 Input Pullup/
Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating.
5V
BB Output Bias voltage.
6 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.
7 nPCLK1 Input Pullup/
Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating.
8V
EE Power Negative supply pin.
9, 16, 25, 32 VCCO Power Output supply pins.
10, 11 nQ9, Q9 Output Differential output pair. LVPECL/ECL interface levels.
12, 13 nQ8, Q8 Output Differential output pair. LVPECL/ECL interface levels.
14, 15 nQ7, Q7 Output Differential output pair. LVPECL/ECL interface levels.
17, 18 nQ6, Q6 Output Differential output pair. LVPECL/ECL interface levels.
19, 20 nQ5, Q5 Output Differential output pair. LVPECL/ECL interface levels.
21, 22 nQ4, Q4 Output Differential output pair. LVPECL/ECL interface levels.
23, 24 nQ3, Q3 Output Differential output pair. LVPECL/ECL interface levels.
26, 27 nQ2, Q2 Output Differential output pair. LVPECL/ECL interface levels.
28, 29 nQ1, Q1 Output Differential output pair. LVPECL/ECL interface levels.
30, 31 nQ0, Q0 Output Differential output pair. LVPECL/ECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistor 75 kΩ
RVCC/2 Pullup/Pulldown Resistors 50 kΩ
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 3
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Function Tables
Table 3A. Clock Input Function Table
Table 3B. Control Input Function Table
Inputs Outputs
Input to Output Mode PolarityPCLK0 or PCLK1 nPCLK0 or nPCLK1 Q0:Q9 nQ0:nQ9
0 1 LOW HIGH Differential to Differential Non-Inverting
1 0 HIGH LOW Differential to Differential Non-Inverting
0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting
1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting
Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting
Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting
Inputs
CLK_SEL Selected Source
0 PCLK0, nPCLK0
1 PCLK1, nPCLK1
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 4
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Item Rating
Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0V)
Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0V)
Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V
Inputs, VI (ECL mode) 0.5V to VEE – 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
VBB Sink//Source, IBB ± 0.5mA
Operating Temperature Range, TA-40°C to +85°C
Package Thermal Impedance, θJA 49.5°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Positive Supply Voltage 2.375 3.3 3.8 V
IEE Power Supply Current 85 mA
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 5
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Table 4B. DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V
.Table 4C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
Symbol Parameter
-40°C 25°C 80°C
UnitsMin Typ Max Min Typ Max Min Typ Max
VOH Output High Voltage; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365 V
VOL Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V
VIH Input High Voltage (Single-ended) 2.075 2.36 2.075 2.36 2.075 2.36 V
VIL Input Low Voltage (Single-ended) 1.43 1.765 1.43 1.765 1.43 1.765 V
VBB
Output Voltage Reference;
NOTE 2 1.86 1.98 1.86 1.98 1.86 1.98 V
VPP Peak-to-Peak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V
VCMR
Input High Voltage Common
Mode Range; NOTE 3, 4 1.2 3.3 1.2 3.3 1.2 3.3 V
IIH
Input
High Current
PCLK0, PCLK1
nPCLK0, nPCLK1 200 200 200 µA
IIL
Input
Low Current
PCLK0, PCLK1
nPCLK0, nPCLK1 -200 -200 -200 µA
Symbol Parameter
-40°C 25°C 80°C
UnitsMin Typ Max Min Typ Max Min Typ Max
VOH Output High Voltage; NOTE 1 1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565 V
VOL Output Low Voltage; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83 V
VIH Input High Voltage (Single-ended) 1.275 1.56 1.275 1.56 1.275 -0.8 V
VIL Input Low Voltage (Single-ended) 0.63 0.965 0.63 0.965 0.63 0.965 V
VPP Peak-to-Peak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V
VCMR
Input High Voltage Common
Mode Range; NOTE 2, 3 1.2 2.5 1.2 2.5 1.2 2.5 V
IIH
Input
High Current
PCLK0, PCLK1
nPCLK0, nPCLK1 200 200 200 µA
IIL
Input
Low Current
PCLK0, PCLK1
nPCLK0, nPCLK1 -200 -200 -200 µA
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 6
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Table 4D. ECL DC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V, TA = -40°C to 85°C
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V
Symbol Parameter
-40°C 25°C 80°C
UnitsMin Typ Max Min Typ Max Min Typ Max
VOH Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V
VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V
VIH Input High Voltage (Single-ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V
VIL Input Low Voltage (Single-ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V
VBB
Output Voltage Reference;
NOTE 2 -1.486 -1.386 -1.486 -1.386 -1.486 -1.386 V
VPP Peak-to-Peak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V
VCMR
Input High Voltage Common
Mode Range; NOTE 3, 4 VEE+1.2 0 VEE+1.2 0 VEE+1.2 0 V
IIH
Input
High Current
PCLK0, PCLK1
nPCLK0, nPCLK1 200 200 200 µA
IIL
Input
Low Current
PCLK0, PCLK1
nPCLK0, nPCLK1 -200 -200 -200 µA
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 7
ICS853111AY-02 REV. B FEBRUARY 13, 2008
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = -3.8V to -2.375V or , VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
All parameters are measured at f ≤ 1GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter
-40°C 25°C 80°C
UnitsMin Typ Max Min Typ Max Min Typ Max
fMAX Output Frequency 3.2 3.2 3.2 GHz
tPD Propagation Delay; NOTE 1 600 680 750 650 725 790 690 790 890 ps
tsk(o) Output Skew; NOTE 2, 4 25 37 25 37 25 37 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 85 225 85 225 85 225 ps
tjit
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jjitter Section
0.03 0.03 0.03 ps
tR / tF
Output
Rise/Fall Time 20% to 80% 60 200 325 100 200 280 130 200 270 ps
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 8
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
1k 10k 100k 1M 10M 100M
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Additive Phase Jitter @ 155.52MHz
= 0.03ps (typical)
100 1k 10k 100k 1M 10M 100M
Offset Frequency (Hz)
SSB Phase Noise dBc/Hz
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 9
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Parameter Measurement Information
LVPECL Output Load AC Test Circuit
Part-to-Part Skew
Output Rise/Fall Time
Differential Input Level
Output Skew
Propagation Delay
SCOPE
Qx
nQx
LVPECL
VEE
VCC,
2V
-1.8V to -0.375V
VCCO
tsk(pp)
Part 1
Part 2
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
tRtF
VSWING
-
VCC
VEE
VCMR
Cross Points
VPP
nPCLK
PCLKx
tsk(o)
nQx
Qx
nQy
Qy
tPD
nQ0:nQ9
Q0:Q9
nPCLKx
PCLKx
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 10
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Application Information
Wiring the Differential Input to Accept Single-ended LVCMOS Levels
Figure 1A shows an example of the differential input that can be
wired to accept single-ended LVCMOS levels. The reference
voltage level VBB generated from the device is connected to the
negative input. The C1 capacitor should be loacted as close as
possible to the input pin.
Figure 1A. Single-Ended LVCMOS Signal Driving Differential Input
Wiring the Differential Input to Accept Single-ended LVPECL Levels
Figure 2 shows an example of the differential input that can be
wired to accept single-ended LVPECL levels. The reference
voltage level VBB generated from the device is connected to the
negative input. The C1 capacitor should be loacted as close as
possible to the input pin.
Figure 2. Single-Ended LVPECL Signal Driving Differential Input
Single Ended Clock Input
VCC
PCLKx
nPCLKx
R1
C1
0.1u R2
1K
1K
V_REF
PCLK
nPCLK
V
BB
C1
0.1uF
CLK_IN
V
CC
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 11
ICS853111AY-02 REV. B FEBRUARY 13, 2008
LVPECL Clock Input Interface (with VBB)
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface
examples for the HiPerClockS PCLK/nPCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 3A. HiPerClockS PCLK/nPCLK Input
Driven by a CML Driver
Figure 3C. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3E. HiPerClockS PCLK/nPCLK Input
Driven by an SSTL Driver
Figure 3B. HiPerClockS PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
Figure 3D. HiPerClockS PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
Figure 3F. HiPerClockS PCLK/nPCLK Input Driven by
a 3.3V LVDS Driver
PCLK
nPCLK
HiPerClockS
PCLK/nPCL
K
CML
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
3.3V
R1
50
R2
50
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
3.3V
3.3V
LVPECL HiPerClockS
Input
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
SSTL
2.5V
Zo = 60Ω
Zo = 60Ω
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
3.3V
R1
100
CML Built-In Pullup
PCLK
nPCLK
3.3V
HiPerClockS
PCLK/nPCLK
Zo = 50Ω
Zo = 50Ω
R1
50
R2
50
R5
100 - 200
R6
100 - 200
PCLK
VBB
nPCLK
3.3V LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
PCLK/nPCLK
C1
C2
PCLK
nPCLK
VBB
3.3V
PCLK/nPCLK
R1
1k
R2
1k
3.3V
Zo = 50Ω
Zo = 50Ω
C1
C2
R5
100
LVDS
C3
0.1µF
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 12
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Recommendations for Unused Output Pins
Inputs:
PCLK/nPCLK INPUTS
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground. For applications
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
VCC - 2V
50Ω50Ω
RTT
Zo = 50Ω
Zo = 50Ω
FOUT FIN
RTT = Zo
1
((VOH + VOL) / (VCC – 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 13
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Termination for 2.5V LVPECL Outputs
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to
ground level. The R3 in Figure 5B can be eliminated and the
termination is shown in Figure 5C.
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5C. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
VCC = 2.5V
2.5V
2.5V
50Ω
50Ω
R1
250
R3
250
R2
62.5
R4
62.5
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50
R2
50
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50
R2
50
R3
18
+
–
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 14
ICS853111AY-02 REV. B FEBRUARY 13, 2008
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 6. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as many
vias connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz
copper via barrel plating. This is desirable to avoid any solder
wicking inside the via during the soldering process which may
result in voids in solder between the exposed pad/slug and the
thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, refer to the Application Note on the Surface
Mount Assembly of Amkor’s Thermally/Electrically Enhance
Leadfame Base Package, Amkor Technology.
Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
GROUND PLANE LAND PATTERN
SOLDER
THERMAL VIA
EXPOSED HEAT SLUG
(GROUND PAD)
PIN
PIN PAD
SOLDER PIN
PIN PAD
SOLDER
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 15
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Schematic Example
This application note provides a general design guide using
ICS853111-02 LVPECL buffer. Figure 7 shows a schematic
example of the ICS853111-02 LVPECL clock buffer. In this
example, the input is driven by an LVPECL driver. CLK_SEL is set
at logic high to select PCLK0/nPCLK0 input.
Figure 7. ICS853111-02 Example LVPECL Clock Output Buffer Schematic
C4
0.1uF
C6 (Option)
0.1u
Zo = 50
R7
50
Zo = 50
R2
50
VCC
R1
50
VCC
VCC=3.3V
C7 (Option)
0.1u
R3
50
(U1-16)
U1
ICS853111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
VCC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
VCCO
nQ9
Q9
nQ8
Q8
nQ7
Q7
VCCO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
VCCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
VCCO
R4
1K
Zo = 50
C2
0.1uF
(U1-9)
R8
50
Zo = 50 Ohm
C8 (Option)
0.1u
+
-
C5
0.1uF
R10
50
R11
50
3.3V LVPECL
+
-
VCC
(U1-32)
R13
50
C1
0.1uF
Zo = 50 Ohm
R9
50
C3
0.1uF
(U1-25)
VCC
Zo = 50
(U1-1)
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 16
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853111-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853111-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 85mA = 323mW
• Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 323mW + 309.4mW = 632.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 49.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.632W * 49.5°C/W = 116.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 32 Lead TQFP, E-Pad Forced Convection
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
θJA by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 69.3°C/W 57.8°C/W 52.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 49.5°C/W 43.8°C/W 41.3°C/W
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 17
ICS853111AY-02 REV. B FEBRUARY 13, 2008
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCCO – 2V.
• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.935V
(VCC_MAX – VOH_MAX) = 0.935V
• For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.67V
(VCC_MAX – VOL_MAX) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCOC_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
VOUT
VCC
VCC
- 2V
Q1
RL
50Ω
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 18
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Reliability Information
Table 7. θJA vs. Air Flow Table for a 32 Lead TQFP, E-Pad
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS853111-02 is: 1340
Pin compatible with MC100EP111 and MC100LVEP111
θJA vs. Air Flow
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 69.3°C/W 57.8°C/W 52.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 49.5°C/W 43.8°C/W 41.3°C/W
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 19
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Package Outline and Package Dimensions
Package Outline - G Suffix for 32 Lead TQFP, E-Pad
Table 8. Package Dimensions 32 Lead TQFP, E-Pad
Reference Document: JEDEC Publication 95, MS-026
-HD VERSION
EXPOSED PAD DOWN
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N32
A1.20
A1 0.05 0.10 0.15
A2 0.95 1.00 1.05
b0.30 0.35 0.40
c0.09 0.20
D & E 9.00 Basic
D1 & E1 7.00 Basic
D2 & E2 5.60 Ref.
D3 & E3 3.0 4.0
e0.80 Basic
L0.45 0.60 0.75
θ0° 7°
ccc 0.10
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 20
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Ordering Information
Table 9. Ordering Information
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
ICS853111AY-02 ICS853111A02 32 Lead TQFP, E-Pad Tube -40°C to 85°C
ICS853111AY-02T ICS853111A02 32 Lead TQFP, E-Pad 1000 Tape & Reel -40°C to 85°C
ICS853111AY-02LF ICS853111A02L “Lead-Free” 32 Lead TQFP, E-Pad Tube -40°C to 85°C
ICS853111AY-02LFT ICS853111A02L “Lead-Free” 32 Lead TQFP, E-Pad 1000 Tape & Reel -40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 21
ICS853111AY-02 REV. B FEBRUARY 13, 2008
Revision History Sheet
Rev Table Page Description of Change Date
AT9
10
17
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added Lead-Free marking. 1/10/06
B
T4B
T4C
T4D
5
5
6
11
14
16
3.3V LVPECL DC Characteristics - changed IIH max. from 150µA to 200µA.
Changed IIL min. from -150µA to -200µA.
2.5V LVPECL DC Characteristics - changed IIH max. from 150µA to 200µA.
Changed IIL min. from -150µA to -200µA.
ECL DC Characteristics - changed IIH max. from 150µA to 200µA.
Changed IIL min. from -150µA to -200µA.
Updated LVPECL Clock Input Interface Section.
Updated EPAD Thermal Release Path Section.
Power Considerations - updated Junction Temperature equation with worst
case thermal resistance of 49.5°C/W.
2/13/08
ICS853111-02
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
www.IDT.com
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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