STA8090FG Fully integrated GPS/Galileo/GLONASS/BeiDou/QZSS receiver with embedded RF and in-package Flash Datasheet - production data 1 Secure-Digital Multimedia Memory Card Interfaces (SDMMC) 1 Multichannel Serial Port (MSP) Power Management Unit (PMU) embedding switching regulator 5'#(" YYNN ("1($'5 Features Operating condition: - Main voltage regulator (VINL): 1.6V to 4.3V - Backup voltage (VINB): 1.6V to 4.3V - Digital voltage (VDD): 1.0 V to 1.32 V - RF core voltage (VCC): 1.2 V 10% - IO Ring Voltage (VddIO): 1.8 V 5% or 3.3 V 10% STMicroelectronics(R) positioning receiver with 48 tracking channels and 2 fast acquisition channels supporting GPS, Galileo, GLONASS, BeiDou and QZSS systems Package: - TFBGA99 (5 x 6 x 1.2 mm) 0.5 mm pitch Single die standalone receiver embedding RF Front-End and low noise amplifier Description -162 dBm indoor sensitivity (tracking mode) Fast TTFF < 1 s in Hot start and 30 s in Cold Start High performance ARM946 MCU (up to 196 MHz) 256 Kbyte embedded SRAM In-Package SQI Flash Memory (16 or 32 Mbits) Real Time Clock (RTC) circuit 32-bit Watch-dog timer 3 UARTs 1 I2C master interface 1 Synchronous Serial Port (SSP, Motorola-SPI supported) USB2.0 full speed (12 MHz) with integrated physical layer transceiver Ambient temperature range: -40/+85C STA8090FG belongs to Teseo III family products. STA8090FG is a single die standalone positioning receiver IC working on multiple constellations (GPS/Galileo/GLONASS/BeiDou/QZSS). STA8090FG, thanks to the ARM9 and wide IOs availability, can be used as microcontroller with GNSS capability, allowing a very compact design offering 256 kByte of internal RAM and 16 Mbits or 32 Mbits of internal Flash. The minimal BOM makes STA8090FG the ideal solution for cost competitive and small footprint products such as OBD dongle, insurance boxes, trackers, telematics, portable, hands-held portable and sports accessories. STA8090FGBD can also run TESEO-DRAW the STMicroelectronics dead reckoning firmware. 2 Controller Area Network (CAN) 2 channels ADC (10 bits) May 2017 This is information on a product in full production. DocID027181 Rev 5 1/40 www.st.com Contents STA8090FG Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 TFBGA99 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6 Communication interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 Multimedia card pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8 General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.9 RF Front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 RF front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+) processor . . . . . . 17 3.3 MCU Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 3.4 4 APB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.1 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.2 SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.3 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.5 SDMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.6 MTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.7 WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.8 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.9 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.10 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.11 MSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 2/40 AHB slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DocID027181 Rev 5 STA8090FG 5 Contents 4.2 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.7 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.8.1 RF electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.8.2 Oscillator electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.8.3 OSCI oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.8.4 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.8.5 Flash specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2 TFBGA99 5 x 6 x 1.2 mm package information . . . . . . . . . . . . . . . . . . . . 35 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DocID027181 Rev 5 3/40 3 List of tables STA8090FG List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. 4/40 TFBGA99 connection diagram (with CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TFBGA99 connection diagram (no CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Communication interface pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Multimedia card pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RF Front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TCM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Frequency limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SMPS DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LDO1 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LDO2 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Low voltage detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O buffers DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.0 V I/O buffers DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 RFACHAIN - GALGPS filter and VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 RFCHAIN - GLONASS/BeiDou filter and VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Crystal recommended specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Oscillator amplifier specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Characteristics of external slow clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SARADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TFBGA99 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DocID027181 Rev 5 STA8090FG List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. STA8090FG system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 32.768 kHz crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SARADC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TFBGA99 5 x 6 x 1.2 mm package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID027181 Rev 5 5/40 5 Overview 1 STA8090FG Overview STA8090FG is one of the part number of Teseo III STA8090x series. STA8090FG is a highly integrated single-chip standalone GNSS receiver designed for positioning system applications. STA8090FG embeds the new ST GNSS positioning engine capable of receiving signals from multiple satellite navigation systems, including the US GPS, European Galileo, Russia's GLONASS, Chinese BeiDou and Japan's QZSS. The STA8090FG ability of tracking simultaneously the signals from multiple satellites regardless of their constellation, makes this chip capable of delivering exceptional accuracy in urban canyons and in the environments where buildings and other obstructions make satellite visibility challenging. STA8090FG embeds innovative power management with switching regulator for power consumption optimization. The extended voltage supply ranges from 1.6 V to 4.3 V, the 1.8 V and 3.3 V I/O compliance support makes the STA8090FG the suitable solution for different user applications. The STA8090FG combines a high performance ARM946 microprocessor with I/O capabilities and enhanced peripherals. It supports USB2.0 standard at full speed (12 Mbps) with on-chip PHY. The chip embeds backup logic with real time clock. STA8090FG can host customer code on top of STMicroelectronics GNSS library. Customers can develop on TeseoIII their application code by using a software development kit based on different real time operating systems. STA8090FGBD can be offered also bundled with STMicroelectronics dead reckoning firmware called TESEO-DRAW; TESEO-DRAW firmware is a multi-sensors data fusion hub for Teseo family IC's. The STA8090FG, using STMicroelectronics CMOSRF Technology, is housed in a TFBGA99 (5 x 6 x 1.2 mm) package with stacked 16 Mbit or 32 Mbit Flash memory. 6/40 DocID027181 Rev 5 STA8090FG Pin description 2 Pin description 2.1 Block diagram Figure 1. STA8090FG system block diagram *5),3 *%%&RUUHODWRU (QJLQH 7UN &KDQQHOV $3% %ULGJH )DVW$FT &KDQQHO **,) 0X[ $FT 5$0V $'& ** /1$ 6HFWLRQ $'& *& 5) 6HFWLRQ $QWHQQD 6HQVLQJ &/2&.B*(1 26&, 3// *&,) 63,,) $+% )/$6+ 0ERU0E 5LQJ 26&, $3% %ULGJH ,2V &$1 64, ,) &$1 8$57 )XOO 8$57 5[7[ 8$57 5[7[ 6'00& 663 $3% 7HVW FRQWUROOHU $3% %ULGJH :' *3,2 ()7 078 86% ,) ,& 063 $'& -7$* 9,& 308 %.B'RPDLQ +,*+63((''7&0 .% ,'6:,7&+$%/( [.% ,&DFKH .% $50 '&DFKH .% +,*+63((',7&0 .% %.5$0.% 35&& ,62 &(// $3% %ULGJH 57& 26&, %./'2 /'2 /'2 6036 %DQGJDS%LDV2VFLOODWRU/9'V ("1($'5 DocID027181 Rev 5 7/40 39 Pin description 2.2 STA8090FG TFBGA99 pin configuration Table 1. TFBGA99 connection diagram (with CAN) 1 2 3 4 5 6 7 8 9 A VINM VINM SPI_CLK SPI_CSN VINL1 VOL1 GND VINB VOB B VLX VLX SPI_DI UART0_ TX UART0_ CTS UART2_ RX GPIO1 GPIO0 GND C GND GND SPI_DO VDDIO_ R1 UART2_ TX UART0_ RTS VDD_SQI VDD_ ADC Reserved D VOM GND TMS UART0_ DSR UART0_ DTR GND ADC_IN2 GND RTC_XTO E VDD_ANA TDO TRSTn UART0_ DCD VDDD UART0_ RX ADC_IN1 WAKEUP0 RTC_XTI F GND TDI VDDD VDDD GND GND WAKEUP1 STDBYn RSTn G USB_DP TCK VDDD GND GND GND STDBY_ OUT PMU_ CFG XTAL_ OUT H USB_DM GPIO10 MMC_D3 MMC_ CLK TP_IF_N GND GND VCC_PLL XTAL_IN J CAN0_TX GPIO11 MMC_D2 MMC_ CMD TP_IF_P GND GND ANT_ SENSE2 VCC_ CHAIN K CAN0_RX VDDIO_ R2 GPIO2 MMC_D1 GND_LNA GND_LNA GND_LNA GND ANT_ SENSE1 L GND I2C_SD I2C_CLK MMC_D0 VINL2 GND 8/40 VCC_RF LNA_IN DocID027181 Rev 5 VOL2 STA8090FG Pin description Table 2. TFBGA99 connection diagram (no CAN) 1 2 3 4 5 6 7 8 9 A VINM VINM SPI_CLK SPI_CSN VINL1 VOL1 GND VINB VOB B VLX VLX SPI_DI UART0_ TX UART0_ CTS UART2_ RX GPIO1 GPIO0 GND C GND GND SPI_DO VDDIO_ R1 UART2_ TX UART0_ RTS VDD_SQI VDD_ ADC Reserved D VOM GND TMS UART0_ DSR UART0_ DTR GND ADC_IN2 GND RTC_XTO E VDD_ANA TDO TRSTn UART0_ DCD VDDD UART0_ RX ADC_IN1 F GND TDI VDDD VDDD GND GND WAKEUP1 STDBYn RSTn G USB_DP TCK VDDD GND GND GND STDBY_ OUT PMU_ CFG XTAL_ OUT H USB_DM GPIO10 MMC_D3 MMC_ CLK TP_IF_N GND GND VCC_PLL XTAL_IN J UART0_ TX GPIO11 MMC_D2 MMC_ CMD TP_IF_P GND GND ANT_ SENSE2 VCC_ CHAIN K UART0_ RX VDDIO_ R2 GPIO2 MMC_D1 GND GND GND GND_LNA ANT_ SENSE1 L GND I2C_SD I2C_CLK MMC_D0 VCC_RF LNA_IN VOL2 VINL2 GND 2.3 WAKEUP0 RTC_XTI Power supply pins Table 3. Power supply pins Symbol I/O voltage I/O VCC_CHAIN 1.2 V PWR Analog supply voltage for RF chain (1.2V) J9 VCC_PLL 1.2 V PWR Analog supply voltage for PLL RF (1.2V) H8 VCC_RF 1.2 V PWR Analog supply voltage for RF (1.2V) L5 VDD_ADC 1.8 V PWR Digital supply voltage for ADC (1.8V) C8 VDD_SQI 1.8 V PWR Digital supply voltage for SQI C7 VDDD 1.1 V PWR Digital supply voltage VDDIO_R1 1.8 V or 3.3 V PWR Digital supply voltage for I/O ring 1 (1.8 V or 3.3 V) C4 VDDIO_R2 3.3V PWR Digital supply voltage for I/O ring 2 (3.3 V) K2 VINB 1.6 V - 4.3 V PWR Backup LDO input supply voltage (1.6 V to 4.3 V) A8 VINL1 1.6 V - 4.3 V PWR LDO1 input supply voltage (1.6 V to 4.3 V) A5 VINL2 1.6 V - 4.3 V PWR LDO2 input supply voltage (1.6 V to 4.3 V) L8 Description DocID027181 Rev 5 STA8090FG E5, F3, F4, G3 9/40 39 Pin description STA8090FG Table 3. Power supply pins (continued) Symbol I/O voltage I/O VINM 1.6 V - 4.3 V PWR SMPS coil input supply (1.6 V to 4.3 V) VDD_ANA 1.6 V - 4.3 V PWR SMPS input supply (1.6 V to 4.3 V) VLX 0 V - 4.3 V PWR SMPS coil output VOB 1.0V PWR LDO backup output voltage (1.0 V) A9 A6 Description STA8090FG A1, A2 E1 B1, B2 VOL1 1.1 V or 1.8 V PWR LDO1 output voltage: PMU_CFG = high -> 1.1 V (it can be also configured to 1.2 V) PMU_CFG = low -> 1.8 V VOL2 1.2 V PWR LDO2 output voltage (1.2 V) L7 PWR SMPS output voltage PMU_CFG = high -> 1.8 V PMU_CFG = low -> 1.1 V (it can be also configured to 1.2 V) D1 VOM 1.1 V or 1.8 V GND GND GND Ground A7, B9, C1, C2, D2, D6, D8, F1, F5, F6, G4, G5, G6, H6, H7, J6, J7, K8, L1, L9 GND_LNA GND GND Ground K5, K6, K7 2.4 Main function pins Table 4. Main function pins Symbol I/O voltage I/O ADC_IN1 1.4 V - 0 V typ range I ADC Analog input [1] E7 ADC_IN2 1.4 V - 0 V typ range I ADC Analog input [2] D7 PMU_CFG 1.0 V I Power management unit config pin High -> VOL1 = 1.1 V, VOM = 1.8 V Low -> VOL1 = 1.8 V, VOM = 1.1 V G8 RSTn 1.0 V I Reset Input with Schmitt-Trigger characteristics and noise filter. F9 RTC_XTI 1.0 V (max) I Input of the 32 KHz oscillator amplifier circuit and input of the internal real time clock circuit. E9 RTC_XTO 1.0 V (max) O Output of the oscillator amplifier circuit. D9 STDBY_OUT 1.0 V O When low, indicates the chip is in Standby mode G7 STDBYn 1.0 V I When low, the chip is forced in Standby Mode - All pins in high impedance except the ones powered by Backup supply F8 10/40 Description DocID027181 Rev 5 STA8090FG STA8090FG Pin description Table 4. Main function pins (continued) Symbol I/O voltage I/O WAKEUP0 1.0 V I WAKEUP from STANDBY mode E8 WAKEUP1 1.0 V I WAKEUP from STANDBY mode F7 2.5 Description STA8090FG Test/emulated dedicated pins Table 5. Test/emulated dedicated pins Symbol I/O voltage I/O TCK VDDIO_R2 I JTAG Test Clock G2 TDI VDDIO_R2 I JTAG Test Data In F2 TDO VDDIO_R2 O JTAG Test Data Out E2 TMS VDDIO_R2 I JTAG Test Mode Select D3 TRSTn VDDIO_R2 I JTAG Test Circuit Reset E3 TP_IF_N 1.2 V O Diff.Test Point for IF - Negative H5 TP_IF_P 1.2 V O Diff.Test Point for IF - Positive J5 2.6 Description STA8090FG Communication interface pins Table 6. Communication interface pins Symbol CAN0_RX(1) CAN0_TX(1) I2C_CLK I/O voltage VDDIO_R2 VDDIO_R2 VDDIO_R2 I/O Alternative function Function I AF0 (default) CAN0_RX(1) CAN0 receive data input I AF1 UART0_RX UART0 Rx data Description I AF2 Tsense External temperature capture port I/O AF3 I2C_SD I2C serial data O AF0 (default) CAN0_TX(1) CAN0 transmit data output O AF1 UART0_TX UART0 Tx data I/O AF2 GPIO7 O AF3 I2C_CLK I2C clock O AF0 (default) I2C_CLK I2C clock I/O AF1 GPIO8 STA8090FG K1 J1 General purpose I/O #7 General purpose I/O #8 (1) O AF2 CAN1_TX O AF3 SPI_CLK L3 CAN1 transmit data output SPI clock DocID027181 Rev 5 11/40 39 Pin description STA8090FG Table 6. Communication interface pins (continued) Symbol I2C_SD SPI_CLK SPI_CSN SPI_DI SPI_DO I/O voltage VDDIO_R2 VDDIO_R1 VDDIO_R1 VDDIO_R1 VDDIO_R1 UART0_CTS VDDIO_R1 UART0_DCD VDDIO_R1 12/40 I/O Alternative function Function I/O AF0 (default) I2C_SD I/O AF1 GPIO9 Description STA8090FG I2C serial data General purpose I/O #9 (1) CAN1_RX L2 CAN1 receive data input I AF2 O AF3 SPI_CSN SPI chip select active low O AF0 (default) SPI_CLK SPI clock I/O AF1 GPIO25 General purpose I/O #25 O AF2 SQI_CLK O AF3 MMC_CLK O AF0 (default) SPI_CSN I/O AF1 GPIO24 O AF2 SQI_CEN I/O AF3 MMC_CMD I AF0 (default) SPI_DI SPI serial data input / BOOT2 I/O AF1 Tsense External temperature capture port I/O AF2 I/O AF3 MMC_D0 Multimedia card data 0 O AF0 (default) SPI_DO SPI serial data output I/O AF1 GPIO27 General purpose I/O #27 I/O AF2 SQI_SIO0/SI I/O AF3 MMC_D1 I AF0 (default) UART0_CTS I/O AF1 GPIO15 General purpose I/O #15 O AF2 i2s_out_sclk MSP serial clock output O AF3 Clock GNSS GNSS clock out I AF0 (default) UART0_DCD UART0 data carrier detect I/O AF1 GPIO17 General purpose I/O #17 O AF2 O AF3 A3 SQI Flash clock Multimedia Clock line SPI chip select active low / IO_Power Sel Ring 1 General purpose I/O #24 A4 SQI Flash chip enable Multimedia card command line B3 SQI_SIO1/SO SQI Flash data IO 1 / ser. output Multimedia card data 1 UART0 clear to send i2s_out_sdata MSP serial data output Clock GNSS C3 SQI Flash data IO 0 / ser. input GNSS clock out DocID027181 Rev 5 B5 E4 STA8090FG Pin description Table 6. Communication interface pins (continued) Symbol I/O voltage UART0_DSR VDDIO_R1 UART0_DTR VDDIO_R1 UART0_RTS VDDIO_R1 UART0_RX UART0_TX UART2_RX VDDIO_R1 VDDIO_R1 VDDIO_R1 I/O Alternative function Function I AF0 (default) UART0_DSR I/O AF1 GPIO16 O AF2 i2s_out_lrclk O AF3 Sign GC O AF0 (default) UART0_DTR UART0 data terminal read I/O AF1 GPIO18 General purpose I/O #18 I AF2 Timer_ICAPA O AF3 Mag_1 GG O AF0 (default) UART0_RTS UART0 request to send I/O AF1 GPIO14 General purpose I/O #14 O AF2 TCXO_OUT O AF3 Sign GG I AF0 (default) UART0_RX O AF1 SPI_DO I/O AF2 SQI_SIO2 I AF3 Timer_ICAPA O AF0 (default) UART0_TX I AF1 SPI_DI I/O AF2 SQI_SIO3 O AF3 Timer_OCMPA I AF0 (default) UART2_RX I/O AF1 GPIO28 General purpose I/O #28 I/O AF2 I2C_SD I2C serial data I/O AF3 MMC_D2 Description STA8090FG UART0 data set ready General purpose I/O #16 MSP left/right clock output D4 GLONASS and BeiDou 3-bit coding output (Sign) Extended function timer - input capture A D5 GPS and Galileo 3-bit coding Output (MAG1) TCXO out clock C6 GPS and Galileo 3-bit coding output (Sign) UART0 Rx data SPI serial data output SQI Flash data IO 2 E6 Extended Function Timer - Input Capture A UART0 Tx data / BOOT1 Serial data input SQI Flash data IO 3 B4 Extended Function Timer - Output Compare A UART 2 Rx data B6 Multimedia card data 2 DocID027181 Rev 5 13/40 39 Pin description STA8090FG Table 6. Communication interface pins (continued) Symbol UART2_TX USB_DM USB_DP I/O voltage VDDIO_R1 VDDIO_R2 VDDIO_R2 I/O Alternative function Function O AF0 (default) UART2_TX UART 2 Tx data / BOOT0 I/O AF1 GPIO29 General purpose I/O #29 O AF2 I2C_CLK I2C clock I/O AF3 MMC_D3 Multimedia card data 2 USB AF0 USB_DM USB D- signal I AF1 (default) UART1_RX UART1 Rx data I AF2 CAN1_RX(1) CAN1 receive data input I/O AF3 I2C_SD I2C serial data USB AF0 USB_DP USB D+ signal O AF1 (default) UART1_TX UART1 Tx data Description (1) O AF2 CAN1_TX O AF3 I2C_CLK STA8090FG C5 H1 G1 CAN1 transmit data output I2C clock 1. Only for STA8090FGB and STA8090FGBD. 2.7 Multimedia card pins Table 7. Multimedia card pins Symbol MMC_CLK MMC_CMD 14/40 I/O voltage VDDIO_R2 VDDIO_R2 I/O Alternative function Function O AF0 (default) MMC_CLK O AF1 i2s_out_lrclk MSP left/right clock output I AF2 Timer_ICAPA Extended Function Timer Input Capture A I/O AF3 GPIO4 I/O AF0 (default) MMC_CMD O AF1 i2s_out_sdata Description STA8090FG Multimedia Clock line H4 General purpose I/O #4 (1) O AF2 CAN0_TX I/O AF3 GPIO5 DocID027181 Rev 5 Multimedia card command line MSP serial data output CAN0 transmit data output General purpose I/O #5 J4 STA8090FG Pin description Table 7. Multimedia card pins (continued) Symbol MMC_D0 MMC_D1 MMC_D2 MMC_D3 I/O voltage VDDIO_R2 VDDIO_R2 VDDIO_R2 VDDIO_R2 I/O Alternative function Function I/O AF0 (default) MMC_D0 Multimedia card data 0 O AF1 i2s_out_sclk MSP serial clock output I/O AF2 I2C_SD I2C serial data I/O AF3 GPIO20 General purpose I/O #20 I/O AF0 (default) MMC_D1 I AF1 i2s_in_sdata O AF2 Sign GC GLONASS and BeiDou 3-bit coding output (Sign) I/O AF3 GPIO21 General purpose I/O #21 I/O AF0 (default) MMC_D2 Multimedia card data 2 I/O AF1 Reserved Reserved I AF2 CAN0_RX(1) I/O AF3 Tsense I/O AF0 (default) MMC_D3 Multimedia card data 2 I/O AF1 Reserved Reserved O AF2 Sign GG GPS 3-bit coding output (Sign) I/O AF3 GPIO23 General purpose I/O #23 Description STA8090FG L4 Multimedia card data 1 MSP serial data input CAN0 receive data input K4 J3 External temperature capture port H3 1. Only for STA8090FGB. 2.8 General purpose pins Table 8. General purpose pins Symbol GPIO0 I/O voltage VDDIO_R1 I/O Alternative function Function I/O AF0 (default) GPIO0 General purpose I/O #0 I AF1 PPS_IN Pulse per second input O AF2 Timer_OCMPB Extended Function Timer - Output Compare B O AF3 Mag_0 GC GLONASS and BeiDou 3-bit coding Output (MAG0) Description DocID027181 Rev 5 STA8090FG B8 15/40 39 Pin description STA8090FG Table 8. General purpose pins (continued) Symbol GPIO1 GPIO2 GPIO10 GPIO11 I/O voltage VDDIO_R1 VDDIO_R2 VDDIO_R2 VDDIO_R2 2.9 I/O Alternative function Function I/O AF0 (default) GPIO1 I AF1 i2s_in_sdata O AF2 PPS_OUT I/O AF3 Tsense External temperature capture port I/O AF0 (default) GPIO2 General purpose I/O #2 I/O AF1 Reserved I AF2 Timer_ICAPB O AF3 Mag_1 GC I/O AF0 (default), AF1 GPIO10 I AF2 Timer_ICAPA O AF3 Timer_OCMPB I/O AF0 (default), AF1 GPIO11 O AF2 Timer_OCMPA Extended Function Timer - Output Compare A I AF3 Timer_ICAPB Extended Function Timer - Input Capture B Description STA8090FG General purpose I/O #1 / BOOT3 MSP serial data input Pulse per second output B7 Reserved Extended Function Timer - Input Capture B K3 GLONASS and BeiDou 3-bit coding Output (MAG1) General purpose I/O #10 Extended Function Timer - Input Capture A H2 Extended Function Timer - Output Compare B General purpose I/O #11 J2 RF Front-end pins Table 9. RF Front-end pins Symbol I/O voltage I/O ANT_SENSE1 3.3 V I Antenna sensing input 1 K9 ANT_SENSE2 3.3 V I Antenna sensing input 2 J8 LNA_IN 1.2 V I Low Noise Amplifier Input L6 XTAL_IN 1.2 V I Input Side of Crystal Oscillator or TCXO Input H9 XTAL_OUT 1.2 V O Output Side of Crystal Oscillator G9 16/40 Description DocID027181 Rev 5 STA8090FG STA8090FG General description 3 General description 3.1 RF front end The RF front-end is able to down-convert both the GPS-Galileo signal from 1575.42 MHz to 4.092 MHz (4 Fo, being F0 = 1.023 MHz), the GLONASS signal from 1601.718 MHz to 8.57 MHz and the BeiDou signal from 1561.098 MHz to 10.23 MHz. It embeds high performance LNA minimizing external component count and two LDOs to supply the internal core facilitating requirements for external power supply. A three bits ADC converts the IF signals to sign (SIGN) and magnitude (MAG0 and MAG1). They can be sampled or not by SPI. The magnitude bits are internally integrated in order to control the variable gain amplifiers. The VGA gain can be also set by the SPI interface. The RF tuner accepts a wide range of reference clocks (10 to 52 MHz) and can generate 64 Fo sampling clock for the baseband and 192 Fo clock for MCU subsystem. 3.2 GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+) processor STA8090FG integrates G3BB+ proprietary IP, which is the ST last generation highsensitivity Baseband processor fully compliant with GPS, Galileo, GLONASS and BeiDou systems. The baseband receives, from the embedded RF Front-End, two separate IF signals coded in sign-magnitude digital format on 3 bits and the related clocks. The Galileo/GPS (GALGPS) and GLONASS/BeiDou (GNSCOM) signals at the base band inputs are centered on 4.092 MHz, 8.57 MHz and 10.23 MHz. The baseband processes the two IF signals performing data codification, sample rate conversion and final frequency conversion to zero IF before acquisition and tracking correlations. The baseband processor has the capability of acquiring and tracking the Galileo, GPS, GLONASS and BeiDou signals in a simultaneous or single way, or a combination of three, being GLONASS and BeiDou mutually exclusive. The number of tracking channels to be used is programmable; the unused tracking channels can be powered down. A complete multi-OS software library is provided by ST to handle GPS processing, managing satellite acquisition, tracking, pseudo-range calculation and positioning, generating the output in the standard NMEA message format or in a ST binary format. The library includes support of ST self-trained assisted GPS (ST-AGPS), a complete and scalable solution for assisting GPS start-up with autonomous and server-based ephemeris prediction and extension. 3.3 MCU Subsystem The implemented sub-system includes an AHB Lite bus matrix. An ARM946 core is embedded in the sub-system and masters the AHB bus. The totally available TCM SRAM is 256 KB. The amount of memory on ITCM and DTCM can be configured by the ARM946 (see Table 10: TCM Configuration). ITCM can be configured as DocID027181 Rev 5 17/40 39 General description STA8090FG Ni x 16 KB; DTCM can be configured as 128 + Nd x 16 KB, where Ni + Nd = 8, Ni 1. Table 10. TCM Configuration 3.3.1 TCMcfg [2] TCMcfg [1] TCMcfg [0] ITCM DTCM 0 0 0 16 KB 240 KB 0 0 1 32 KB 224 KB 0 1 0 48 KB 208 KB 0 1 1 64 KB 192 KB 1 0 0 80 KB 176 KB 1 0 1 96 KB 160 KB 1 1 0 112 KB 144 KB 1 1 1 128 KB 128 KB AHB slaves G3 APB port that allows to interface with the G3BB acquisition memory and control registers. 512 Kbytes ROM Vectored Interrupt Controller (VIC). SQI flash memory controller 3 x ARM946 APB peripheral bus (APB1, APB2, APB3). Vectored Interrupt Controller (VIC) This Vectored Interrupt Controller (VIC) allows the operative system interrupt handler to quickly dispatch interrupt service routines in response to peripheral interrupts. It provides a software interface to the interrupt system. There are up to 64 interrupt lines. The VIC uses a bit position for each different interrupt source. The software can control each request line to generate software interrupts. Each interrupt line can be independently enabled and configured to trigger a non-vectored Normal Interrupt Request (IRQ) or Fast Interrupt Request (FIQ) to the ARM946 CPU. Sixteen interrupt lines can also be selected to trigger a vectored IRQ. The VIC has two operation modes: the user mode and the privilege mode, in order to have the possibility to set (or not) one level of protection during execution. FS USB device controller Full speed USB device with transceiver. It is an AHB slave. When active it requires a 48 MHz clock XTAL_IN. 18/40 DocID027181 Rev 5 STA8090FG General description 3.4 APB peripherals 3.4.1 CAN The 2 CAN(a) cores perform communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1 MBit/s. For the connection to the physical layer, additional transceiver hardware is required. CAN consists of the CAN core, message RAM, message handler, control registers and module. For communication on a CAN network, individual message objects are configured. The message objects and identifier masks for acceptance filtering of received messages are stored in the message RAM. All functions concerning the handling of messages are implemented in the message handler. These functions include acceptance filtering, the transfer of messages between the CAN core and the message RAM, and the handling of transmission requests as well as the generation of the module interrupt. The register set of the CAN can be accessed directly by the CPU through the module interface. These registers are used to control/configure the CAN core and the message handler and to access the message RAM. CAN features 3.4.2 Supports CAN protocol version 2.0 part A and B 32 messages objects Each message object has its own identifier mask Maskable interrupt Disabled automatic re-transmission mode for time triggered CAN applications Programmable loop-back mode for self-test operation Two 16-bit module interfaces to the AMBA APB bus from ARM SSP The SSP is a master interface for synchronous serial communication with peripheral devices that have Motorola SPI. The SSP performs serial-to-parallel conversion on data received from a peripheral device on SPI_DI pin, and parallel-to-serial conversion on data written by CPU for transmission on SPI_DO pin. The transmit and receive paths are buffered with internal FIFO memories allowing up to 32 x 32-bit values to be stored independently in both transmit and receive modes. FIFOs may be burst-loaded or emptied by the system processor or DMA, from one to eight words per transfer. Each 32-bit word from the system fills one entry in FIFO. The SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SSPCLK from the on-chip clock. One combined interrupt is delivered, which is asserted from several internal maskable events. a. STA8090FGB and STA8090FGBD only (see Figure 5: Ordering information scheme). DocID027181 Rev 5 19/40 39 General description STA8090FG SSP features The SSP has the following features: Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep transmit FIFO Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location deep receive FIFO Programmable data frame size from 4 to 32 bits Programmable clock bit rate and prescaler Programmable clock phase and polarity in SPI mode 3.4.3 UART The UARTx (x = 0|1|2) performs serial-to-parallel conversion on data asynchronously received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64 data byte with 4-bit status (break, frame, parity, and overrun) for receive. UART features The UARTx (x = 0|1|2) are Universal Asynchronous Receiver/Transmitter that support much of the functionality of the industry-standard 16C650 UART. The main features are: Programmable baud rates up to UARTCLK / 16 (1.5 Mbps with UARTCLK at 24 MHz), or up to UARTCLK / 8 (3.0 Mbps with UARTCLK at 24 MHz), with fractional baud-rate generator 5, 6, 7 or 8 bits of data Even, odd, stick or no-parity bit generation and detection 1 or 2 stop bit generation Support of the modem control functions CTS, RTS, plus DCD, DSR, RTS, DTS and RI (UART0 only) Support of software flow control using programmable Xon/Xoff characters False start bit detection Line break generation and detection Separate 8-bit wide, 64-deep transmit FIFO and 12-bit wide, 64-deep receive FIFO Programmable FIFO disabling for 1-byte depth data path These UARTs vary from industry-standard 16C650 on some minor points which are: Receive FIFO trigger levels The internal register map address space, and the bit function of each register differ The deltas of the modem status signals are not available 1.5 stop bits is not supported Independent receive clock feature is not supported 20/40 DocID027181 Rev 5 STA8090FG 3.4.4 General description Flash The STA8090FG integrates 16 Mbits or 32 Mbits of Flash Memory. This eliminates the need of the external Flash simplifying the routing associated to integrate a GPS receiver into a customer board. 3.4.5 SDMMC STA8090FG features an SD/MMC host. 3.4.6 MTU The 2 Multi Timer Units provide access to eight interrupt generating programmable 32-bit Free-Running decrementing Counters (FRCs). The FRCs have their own clock input, allowing the counters to run from a much slower clock than the system clock. The FRC is the part of the timer that performs the counting. There are four instantiations of the FRC block in each MTU, allowing eight counts to be performed in parallel. The 32-bit counter in the FRC is split up into two 16-bit counters. 3.4.7 WDT Watchdog Timer (WDT) provides a way of recovering from software crashes. The watchdog clock is used to generate a regular interrupt (WDOGINT), depending on a programmed value. The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt remains unserviced for the entire programmed period. You can enable or disable the watchdog unit as required. Note: Watchdog is stalled when the ARM processor is in Debug mode. 3.4.8 GPIO The GPIO block provides twenty-one (21) programmable inputs or outputs. Each input or output can be controlled in two modes: software mode through an APB bus interface alternate mode, where GPIO becomes a peripheral input or output line Any GPIO input can be independently enabled or disabled (masked) for interrupt generation. User can select for each GPIO which edge (rising, falling, both) will trigger an interrupt. 3.4.9 ADC 10 bit SAR ADC operating at 1.8 V analog supply. It can convert up to 2 single ended channels with analog input multiplexer at 500KSPS 3.4.10 RTC This is an always-on power domain dedicated to RTC logic (backup system) with 32 Kbyte SRAM and supplied with a dedicated voltage regulator. The RTC provides a high resolution clock which can be used for GPS. It keeps the time when the system is inactive and can be used to wake the system up when a programmed DocID027181 Rev 5 21/40 39 General description STA8090FG alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update. RTC features 3.4.11 47-bit counter clocked by 32.768 kHz clock 32-bit for the integer part (seconds) and 15-bit for the fractional part The integer part and the fractional part are readable independently The counter, once enabled, can be stopped Integer part load register (32-bit) Fractional part load register (15-bit) Load bit to transfer the content of the entire load register (integer+fractional part) to the 47-bit counter. Once set by the MCU this bits is cleared by the hardware to signal to the MCU that the RTC has been updated. MSP The STA8090FG provides one MSP transmitter block. Element (data) size from 8 to 32 bits, LSB or MSB first Programmable frequency shift clock for data transfer Direct interface to: - Industry-standard codecs and serially connected A/D and D/A devices - IIS compliant devices - SPI compliant devices Transmit first-in, first-out memory buffers (FIFOs), 32 bits wide, 8 locations deep 22/40 DocID027181 Rev 5 STA8090FG Electrical characteristics 4 Electrical characteristics 4.1 Parameter conditions Unless otherwise specified, all voltages are referred to GND. 4.2 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25C. 4.3 Typical values Unless otherwise specified, typical data are based on TA = 25C, Vddio = 1.8 V, Vdd = 1.20 V. They are given only as design guidelines and are not tested. 4.4 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 4.5 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. Table 11 lists the absolute maximum rating for STA8090FG. Table 11. Voltage characteristics Symbol Parameter VCC_CHAIN Analog supply voltage for RF chain (1.2 V) Min. Max. Unit -0.3 1.32 V VCC_PLL Analog supply voltage for PLL RF (1.2 V) -0.3 1.32 V VCC_RF Analog supply voltage for RF (1.2 V) -0.3 1.32 V VDD_ADC Digital supply voltage for ADC (1.8 V) -0.3 1.98 V VDD_SQI Digital supply voltage for SQI -0.3 1.95 V Power supply pins for the core logic. -0.3 1.32 V VDDIO_R1 Digital supply voltage for I/O ring 1 (1.8 V or 3.3 V) -0.3 3.63 V VDDIO_R2 Digital supply voltage for I/O ring 2 (3.3 V) -0.3 3.63 V VINB Backup LDO input supply voltage (1.6 V to 4.3 V) -0.3 4.8 V VINL1 LDO1 input supply voltage (1.6 V to 4.3 V) -0.3 4.8 V VDDD DocID027181 Rev 5 23/40 39 Electrical characteristics STA8090FG Table 11. Voltage characteristics (continued) Symbol Parameter Min. Max. Unit VINL2 LDO2 input supply voltage (1.6 V to 4.3 V) -0.3 4.8 V VINM SMPS coil input supply (1.6 V to 4.3 V) -0.3 4.8 V -0.3 4.8 V -2 2 kV -250 250 V SMPS input supply (1.6 V to 4.3 V) VDD_ANA VESD-HBM VESD-CDM (1) Electrostatic discharge, human body model . (2) Electrostatic discharge, charge device model . 1. Balls sustaining only 500 V are: A1, A2, A5, A6, A7, A8, A9, B1, B2, B9, C1, C2, D1, D2, D9, E1, E9, F1, L7 and L8. 2. Ball L6 (LNA_IN) sustains only 150 V. Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 12. Thermal characteristics Symbol Parameter Min. Max. Unit Toper Operative ambient temperature -40 85 C Tj Operative junction temperature -40 125 C Tst Storage temperature -55 150 C 41 C/W Rj-amb Thermal resistance junction to ambient(1) 1. According to JEDEC specification on a 2 layers board. Table 13. Frequency limits Symbol Parameter FCLK Operating ARM9 CPU frequency FAHB AHB frequency Test condition VDDD = 1.2 V; TC = 85 C(1) 1. Not tested in production. 24/40 DocID027181 Rev 5 Min. Typ. Max. Unit -- -- 196 MHz -- -- 49 MHz STA8090FG Electrical characteristics Table 14. Power consumption Symbol Parameter Test condition RFIP power (total VINL2) PRF Min. Typ. Max. Unit G2 = GPS/Galileo; Tamb = 25 C; VINL2 = 1.8 V -- 25 mW G2 + GLONASS; Tamb = 25 C; VINL2 = 1.8 V -- 35 mW G2 + COMPASS; Beidou2 Tamb = 25 C; VINL2 = 1.8 V -- 35 mW -- 90 mW PMVR(1) Switchable area power; (total VINL1) fARM = 196 MHz; fAHB = 49 MHz; Tamb = 25 C; VINL1 = 1.8 V; UART active; other peripherals inactive PLPVR(1) Always ON area power (total VINB) fARM = 196 MHz; fAHB = 49 MHz; Tamb = 25 C; VINB = 3.3 V -- 1 mW PIO(1) IO rings power (total VDDIO_R1 + VDDIO_R2) fARM = 196 MHz; fAHB = 49 MHz; Tamb = 25 C; VINL1 = 1.8 V; UART active; other peripherals inactive -- 4 mW IDStandby Standby mode supply current -- 29 -- A -- 7 -- A IDDeepStandby Deep standby mode supply current(2) RTC running = 32.768 KHz; Tamb = 25 C; VINB = 1.8 V 1. Not tested in production. 2. STDBY_OUT pin not supported in deep standby. 4.6 Recommended DC operating conditions Table 15 lists the functional recommended operating DC parameters for STA8090FG. Table 15. Recommended DC operating conditions Symbol Parameter VCC_CHAIN Analog supply voltage for RF chain (1.2 V) Min. Typ. Max. Unit 1.08 1.20 1.32 V VCC_PLL Analog supply voltage for PLL RF (1.2 V) 1.08 1.20 1.32 V VCC_RF Analog supply voltage for RF (1.2 V) 1.08 1.20 1.32 V VDD_ADC Digital supply voltage for ADC (1.8 V) 1.71 1.80 1.89 V VDD_SQI Flash power supply. 1.71 1.80 1.89 V DocID027181 Rev 5 25/40 39 Electrical characteristics STA8090FG Table 15. Recommended DC operating conditions (continued) Symbol VDDD VDDIO_R1 VDDIO_R2 VINB VINL1 VINL2 VINM VDD_ANA TC 4.7 Parameter Min. Typ. Max. Unit Power supply pins for the core logic. 1.00 1.10 1.32 V Digital supply voltage for I/O ring 1 (1.8 V) 1.71 1.80 1.89 V Digital supply voltage for I/O ring 1 (3.3 V) 3.00 3.30 3.60 V Digital supply voltage for I/O ring 2 (3.3 V) 3.00 3.30 3.60 V Backup LDO input supply voltage (1.6 V to 4.3 V) 1.60 4.30 V LDO1 input supply voltage to generate 1.1 V and 1.2 V 1.60 4.30 V LDO1 input supply voltage to generate 1.8 V 2.10 4.30 V LDO2 input supply voltage to generate 1.2 V 1.60 4.30 V SMPS coil input supply voltage to generate 1.1 V and 1.2 V 1.60 4.30 V SMPS coil input supply voltage to generate 1.8 V 2.10 4.30 V SMPS input supply (1.6 V to 4.3 V) 1.60 4.30 V Operating case temperature -40 85 C DC characteristics Table 16 specifies the SMPS voltage regulator characteristics. Table 16. SMPS DC characteristics Symbol VOM IOM Parameter Test condition Min. Typ. Max. Unit Output voltage (1.2 V) 1.6 V VINM 4.3 V; IOM 100 mA 1.08 1.20 1.32 V Output voltage (1.1 V) 1.6 V VINM 4.3 V; IOM 100 mA 1.0 1.10 1.21 V Output voltage (1.8 V) 2.1 V VINM 4.3 V; IOM 100 mA 1.71 1.80 1.89 V 0 -- 100 mA Output current Table 17 specifies the LDO1 voltage regulator characteristics. 26/40 DocID027181 Rev 5 STA8090FG Electrical characteristics Table 17. LDO1 DC characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Output voltage (1.2V) 1.6 V VINL1 4.3 V; IOL1 70 mA 1.08 1.20 1.32 V Output voltage (1.1V) 1.6 V VINL1 4.3 V; IOL1 70 mA 1 1.10 1.21 V Output voltage (1.8V) 2.1 V VINL1 4.3 V; IOL1 70 mA 1.71 1.80 1.89 V 0 -- 70 mA Min. Typ. Max. Unit 1.08 1.20 1.32 V 0 -- 30 mA Min. Typ. Max. Unit Input LVD always Upper voltage threshold on and main VRs(1) Lower voltage threshold -- 1.680 -- V -- 1.650 -- V Output LVD always Upper voltage threshold on VR(1) Lower voltage threshold -- 0.995 -- V -- 0.935 -- V Upper voltage threshold @ VOL1/M = 1.2 V -- 1.142 -- V Lower voltage threshold @ VOL1/M = 1.2 V -- 1.076 -- V Upper voltage threshold @ VOL1/M = 1.1 V -- 1.048 -- V Lower voltage threshold @ VOL1/M = 1.1 V -- 0.986 -- V Upper voltage threshold @ VOL1/M = 1.8 V -- 1.645 -- V Lower voltage threshold @ VOL1/M = 1.8 V -- 1.626 -- V VOL1 IOL1 Output current Table 18 specifies the LDO2 voltage regulator characteristics. Table 18. LDO2 DC characteristics Symbol Parameter VOL2 Output voltage IOL2 Output current Test condition 1.6 V VINL2 4.3 V; IOL2 30 mA Table 19 specifies the low voltage detection thresholds Table 19. Low voltage detection thresholds Parameter Output LVD main VR(1) Output LVD main VR(1) 1. Not tested in production. Table 20 lists the DC characteristics for all the IO digital buffers expect for the following input buffers: STBYn (F8), STDBY_OUT (G7), WAKEUP0 (E8), WAKEUP1 (F7), PMU_CFG (G8) and RSTn (F9). DocID027181 Rev 5 27/40 39 Electrical characteristics STA8090FG Table 20. I/O buffers DC characteristics Symbol Parameter VIL(1) Logical input low level voltage VIH(1) Logical input high level voltage VHYST(2) Schmitt-trigger hysteresis VOL Low level output voltage VOH High level output voltage Test conditions Min. Typ. Max. Unit VDDIO = 1.8 V -0.3 -- 0.3 * VDDIO V VDDIO = 3.3V -0.3 -- 0.8 V VDDIO = 1.8 V 0.7 * VDDIO -- VDDIO + 0.3 V VDDIO = 3.3V 2.0 -- VDDIO + 0.3 V - 50 -- mV VDDIO = 1.8 V -- 0.4 V VDDIO = 3.3V -- 0.4 V VDDIO = 1.8 V VDDIO - 0.4 -- V VDDIO = 3.3V VDDIO - 0.4 -- V 1. Excludes oscillator inputs RTC_XTI and XTAL_IN. Refer to oscillator electrical specifications. 2. Apply to all digital inputs unless specified otherwise. Table 21 lists the DC characteristics for the 1.0 V IO digital buffers input buffers: STBYn (F8), STDBY_OUT (G7), WAKEUP0 (E8), WAKEUP1 (F7), PMU_CFG (G8) and RSTn (F9). Table 21. 1.0 V I/O buffers DC characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VIL Logical input low level voltage VOB = 1.0 V -0.3 -- 0.35 * VOB V VIH Logical input high level voltage VOB = 1.0 V 0.65 * VOB -- VOB + 0.3 V VOL Low level output voltage VOB = 1.0 V -- 0.2 V VOH High level output voltage VOB = 1.0 V 4.8 AC characteristics 4.8.1 RF electrical specifications VOB - 0.2 -- V Table 22. RFACHAIN - GALGPS filter and VGA Symbol S11(1) 28/40 Parameter Test conditions Min Typ Max Unit Input return loss GPS band -- -8 dB fIF IF frequency PLL in default condition with 26Mhz as reference -- 4.045 MHz NF Noise figure NF overall chain with AGC set at 0 dB -- 2(1) dB Conversion gain from RF input to ADC input VGA at max gain -- 119 dB CG VGA at min gain -- 69 dB DocID027181 Rev 5 STA8090FG Electrical characteristics Table 22. RFACHAIN - GALGPS filter and VGA (continued) Symbol IP1dB IRR BWGPS BWGAL ATT TgGPS TgGAL Parameter Test conditions Min Typ -- -80 dBm -- 20 dB GPS mode -- 2.4 MHz Galileo mode -- 4.8 MHz Alias frequency rejection F = 60 MHz (fs = 65.474 MHz) -- 30 dB IF filter group delay variation GPS mode -- 200(1) ns -- 30(1) ns RF-IF-VGA input compression point VGA min Image rejection ratio -3dB IF bandwidth Galileo mode Max Unit 1. Not tested in production. DocID027181 Rev 5 29/40 39 Electrical characteristics STA8090FG Table 23. RFCHAIN - GLONASS/BeiDou filter and VGA Symbol S11(1) fIFGNS/BDU Parameter Test conditions Input return loss IF frequency for GLONASS IF frequency for BeiDou NF Noise figure CG Conversion gain from RF input to ADC input IP1dB IRR RF-IF-VGA input compression point Min GLONASS band -10 BeiDou band -7 PLL in default condition with 26 Mhz as reference TgGNS/BDU Unit dB 8.519 -- 10.277 NF overall chain with AGC set at 0 dB -- 2(1) dB VGA at max gain -- 118 dB VGA at min gain -- 68 dB VGA min -- -80 dBm -- 25 dB -- 10 MHz -- 30 dB Image rejection ratio Alias frequency rejection Max -- BWGNS/BDU -3dB IF bandwidth ATT Typ F = 53 MHz (fs = 65.474 MHz) IF filter group delay variation MHz 20(1) -- ns 1. Not tested in production. Table 24. Synthesizer Symbol Parameter Typ. Max. Unit MHz Input frequency for xtal amplifier (1) 10 52 RDIV Reference divider range 1 63 NDIV Loop divider range 56 2047 FLO LO operating frequency FTCXO_XTAL 1. That amplifier can be used as a TCXO input buffer. 30/40 Min. DocID027181 Rev 5 3142.656 MHz STA8090FG 4.8.2 Electrical characteristics Oscillator electrical specifications This device contains two oscillators: a 32.768 kHz oscillator/buffer for RTC circuit. an OSCI oscillator/buffer in the RF Front-End When used in oscillator mode, each oscillator requires a specific crystal, with parameters that must be as close as possible to the following recommended values. When used in input buffer mode, an external clock source must be applied. 32.768 kHz OSCI32 oscillator specifications The 32.768 kHz OSCI32 oscillator is connected between RTC_XTI (oscillator amplifier input) and RTC_XTO (oscillator amplifier output). It also requires two external capacitors of 18 pF(b), as shown on Figure 2. OSCI32 is disabled by default and must be enabled by setting bit28-OSCI_EN of PRCC_BACKUP_REG0 to have 32.768KHz oscillation when an XTAL pi-network is connected to RTC_XTI/RTC_XTO pins. The recommended oscillator specifications are shown in Table 25: Table 25. Crystal recommended specifications Symbol FSXTAL Parameter Crystal frequency(1) inductance(1) LMSXTAL Motion CMSXTAL Motional capacitance(1) COSXTAL ESR CL Shunt capacitance(1) Resonance resistance (1) External load capacitance (1) Min. Typ. Max. Unit -- 32.768 -- kHz -- 5 -- kH -- 5.0 -- fF -- 1.3 -- pF -- -- 80 k -- 18 -- pF 1. Not tested in production. The oscillator amplifier specifications are shown in the following table: Table 26. Oscillator amplifier specifications Symbol TS DL Parameter Startup time(1) Drive level (1) RLC Required load capacitance GM Startup transconductance (1) Min. Typ. Max. Unit -- 0.3 0.6 s -- -- <0.1 W -- 12.5 -- pF 22.5 33.6 -- A/V 1. Not tested in production. b. Using crystal with recommended characteristics as per Table 25. DocID027181 Rev 5 31/40 39 Electrical characteristics STA8090FG Figure 2. 32.768 kHz crystal connection Device RCT_XTO RTC_XTII CL = 18 pF 32.768 kHz Crystal CL = 18 pF To drive the 32.768 kHz crystal pins from an external clock source: Disable the oscillator (bit28-OSCI_EN = 0b in PRCC_BACKUP_REG0 register). This disables the internal inverter, thus reducing the power consumption to minimum. Drive the RTC_XTI pin with a square signal or a sine wave. Table 27. Characteristics of external slow clock input Symbol Min. Typ. Max. Unit TJIT (cc) Cycle-to-cycle jitter -70 -- 70 ps TJIT (per) Period jitter -70 -- 70 ps Variation -500 -- 500 ppm 45 -- 55 % TDUTY 4.8.3 Parameter Duty cycle OSCI oscillator specifications The supported values of the embedded BOOT ROM are 16.368 MHz, 24.00 MHz, 26.00 MHz and 48.00 MHz. The default values supported by the GNSS binary image is 26 MHz and 48 MHz, to enable USB peripheral the 48 MHz is mandatory. 4.8.4 ADC specifications This section gives the AC specification of the 10 bit Successive Approximation Register ADC embedded in STA8090FG device. It is controlled by the ARM9 MCU through a wrapper and an APB bridge as depicted in Figure 3 and it has a maximum conversion rate of 1MSPS with 8 muxed analog input channels capability. An internal voltage reference is used and analog/digital power supplies connections are implemented inside the device without any needs of dedicated external pins. 32/40 DocID027181 Rev 5 STA8090FG Electrical characteristics Figure 3. SARADC connections GND VINL1 VDD GND AGND AVDD REFP APB Bridge2 D[9:0] CLK REFN START AIN7 VREF EOC ADC_IN8 AIN1 EN ADC_IN2 SARADC AIN0 SEL[2:0] ADC_IN1 VDD12_MVR ADC WRAPPER Table 28. SARADC specifications Symbol Parameter Min. Typ. Max. Unit VGND-0.3 -- VINL1+0.3 V VADCIN ADC_IN input range VADCCR Conversion range VGND -- VREF V VREF Voltage reference 1.35 1.4 1.45 V 5.5 7.0 8.5 pF 2.0 2.5 k 15 MHz capacitance(1) CIN Input RIN Input mux resistance (total equivalent sampling resistance)(2) 1.5 FCLK Clock frequency 2.5 CLK Clock duty cycle 45 50 55 % -- -- 20 s TSUP Start up time(1)(3) TC Conversion time -- 14 cycles TS Sampling time -- 3 cycles INL DNL Performance < +/- 2 LSB < +/- 2 LSB 1. Not tested in production. 2. Pad input capacitance included. 3. From EN=1. DocID027181 Rev 5 33/40 39 Electrical characteristics 4.8.5 STA8090FG Flash specifications This section gives the AC specification of the embedded Flash in STA8090FG device. Table 29. Flash specifications Symbol Parameter Test conditions fC Serial clock frequency QPI mode - 4 read instructions -- tSE Sector erase cycle time Size = 16 Mb -- Size = 32 Mb Block erase (32 KB) cycle time tBE32 tBE tCE tPP 34/40 Min. Typ. Max. Unit 78 MHz 60 200 ms -- 35 200 ms Size = 16 Mb -- 0.25 1 s Block erase (32 KB) cycle time Size = 32 Mb -- 0.2 1 s Block erase (64 KB) cycle time Size = 16 Mb -- 0.5 2 s Block erase (64 KB) cycle time Size = 32 Mb -- 0.35 2 s Size = 16 Mb -- 12.5 25 s Size = 32 Mb -- 25 50 s Size = 16 Mb -- 0.008 + (n x 0.004) 3 ms Size = 32 Mb -- 0.008 + (n x 0.004) 3 ms Chip erase time Page program cycle time DocID027181 Rev 5 STA8090FG Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 TFBGA99 5 x 6 x 1.2 mm package information Table 30. TFBGA99 package dimensions Symbol Min. Typ. A A1 Max 1.20 0.15 A2 0.28 A4 0.60 b 0.25 0.30 0.35 D 5.85 6.00 6.15 D1 E 5.00 4.85 5.00 E1 4.00 e 0.50 F 0.50 5.15 ddd 0.08 eee 0.15 fff 0.05 DocID027181 Rev 5 35/40 39 Package and packing information STA8090FG Figure 4. TFBGA99 5 x 6 x 1.2 mm package dimension ("1($'5 36/40 DocID027181 Rev 5 STA8090FG 6 Ordering information Ordering information Figure 5. Ordering information scheme Example code: STA8090F Family identifier 4 Flash size G GNSS B D Qualified Grade Draw /CAN Bus Support TR Packing TR = Tape and Reel <blank> = Tray D = GNSS + DRAW <blank> = GNSS only B = Industrial Grade (with CAN) <blank> = Industrial Grade (no CAN) G = GPS/Galileo/GLONASS/BeiDou/QZSS 4 = 32 Mbit <blank> = 16 Mbit Teseo III with Stacked Flash DocID027181 Rev 5 37/40 39 Revision history 7 STA8090FG Revision history Table 31. Document revision history Date Revision 21-Nov-2014 1 Initial release. 2 Table 5: Test/emulated dedicated pins - TDI, TMS: updated description Table 6: Communication interface pins - SPI_DI: updated description Table 8: General purpose pins - GPIO1: updated description Table 19: Low voltage detection thresholds - Input LVD always on and main VRs: removed minimum and maximun values 3 Updated Features and Description Updated Chapter 1: Overview Updated Figure 1: STA8090FG system block diagram Table 3: Power supply pins: - VOL1 VOM, VDDD: updated description Updated Section 3.4.3: UART and Section 3.4.4: Flash Added Section 3.4.5: SDMMC and Section 3.4.11: MSP Table 11: Voltage characteristics: - VESD-HBM, VESD-CDM: updated values Table 14: Power consumption: - PRF: updated typical value for GPS/Galileo - PMVR, PLPVR, PIO: added note - IDSLEEP: updated value Table 15: Recommended DC operating conditions: - VINL1, VINL2, VINM: updated parameter Table 16: SMPS DC characteristics: - VOM: set min and max values as TBD, removed condition for Output voltage at 1.0 V Table 17: LDO1 DC characteristics: - VOL1: set min and max values as TBD, removed condition for Output voltage at 1.0 V Table 18: LDO2 DC characteristics: - VOL2: set min and max values as TBD Table 19: Low voltage detection thresholds: - Output LVD main VR: removed condition for Output voltage at 1.0 V Table 22: RFACHAIN - GALGPS filter and VGA: - S11: Added note - CG: updated values Table 23: RFCHAIN - GLONASS/BeiDou filter and VGA: - S11: Added note - CG: updated values Table 26: Oscillator amplifier specifications: - TS: updated minimum value Updated Section 4.8.3: OSCI oscillator specifications, Section 4.8.5: Flash specifications and Chapter 6: Ordering information 04-Dec-2014 05-Nov-2015 38/40 Changes DocID027181 Rev 5 STA8090FG Revision history Table 31. Document revision history (continued) Date Revision Changes 22-Mar-2017 4 Added STA8090FGBD option for DRAW support. Updated Section 1: Overview Table 14: Power consumption - Updated Min., Typ. and Max. values Table 16: SMPS DC characteristics - Updated Min., Typ. and Max. values Table 17: LDO1 DC characteristics - Updated Min., Typ. and Max. values Table 18: LDO2 DC characteristics - Updated Min., Typ. and Max. values Updated Figure 5: Ordering information scheme 29-May-2017 5 Updated: Table 14: Power consumption: removed IDSLEEP and added IDStandby and IDDeepStandby parameters. DocID027181 Rev 5 39/40 39 STA8090FG IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved 40/40 DocID027181 Rev 5