74VHCT04AMX_NL - Fairchild Semiconductor

June 1997

Revised February 2005

74VHCT04A Hex Inverter

74VHCT04A

Hex Inverter

General Descript ion

The VHC T04A i s an advan ced high speed CMO S Invert er

fabricated with silicon gate CMOS technology. It achieves

the high speed operation similar to equivalent Bipolar

Schottky TTL while maintaining the CMOS low power dissi-

pation.

The internal circuit is composed of 3 stages including buffer

output, which provide high noise immunity and stable out-

put.

Protection circuits ensure th at 0V to 7V can be applied to

the input pins without regard to the supply voltage and to

the output pins with VCC

0V. These circuits prevent

device destruction due to mismatched supply and input/

output voltages. This de vice can be used to inte rfa c e 3V to

5V systems and two supply systems such as battery

backup.

Features

■High speed: tPD

4.7 ns (typ) at TA

■High noise immunity: VIH

2.0V, VIL

0.8V

■Power down protection is provided on all inputs and

outputs

■Low noise: VOLP

1.0V (max)

■Low power dissipation :

ICC

A (max) @ TA

■Pin and function compatible with 74HCT04

Ordering Code:

Surface m ount pack ages are also avai lable on Tape and Reel . Specify by append ing the suffix let t er “X” to the o rdering c ode.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicat es Pb-Fre e pac k age (per JE D EC J -STD-0 20B). Used t his number to order device .

Order Number Package Package Description

Number

74VHCT04AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHCT04AMX_NL

(Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHCT04ASJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHCT04AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHCT04AMTCX_NL

(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74VHCT04AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74VHCT04ANX_NL

(Note 1) N14A Pb-Free 14- Lead Plastic Du al-I n-L i ne Packag e (P DIP ), JED EC MS-0 01 , 0.300 " Wid e

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74VHCT04A

Logic Symbol

Pin Descriptions

Connection Diagram

Truth Table

Pin Names Description

AnInputs

OnOutputs

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74VHCT04A

Absolute Maxim um Ratings(Note 2) Recommended Operating

Conditions (Note 6)

Note 2: Absolute Maximum Ratings are values beyond which the device

may be damaged or have its useful life impaired. The databook specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 3: HIGH or LOW state. IOUT absolute maximum rating must be

observed.

Note 4: VCC

0V.

Note 5: VOUT



GND, VOUT

VCC (Outputs Active)

Note 6: Unused inputs must b e held HIGH or LOW. They may not float.

DC Electrical Characteristics

Noise Characteri stics

Note 7: Parameter guaranteed by design.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Vo ltage (VIN)



0.5V to



7.0V

DC Output V oltage (VOUT)

(Note 3)



0.5V to VCC



0.5V

(Note 4)



0.5V to 7.0V

Input Diode Current (IIK)



20 mA

Output Diode Current (IOK)

(Note 5)

20 mA

DC Output Current (IOUT)

25 mA

DC VCC/GND Current (ICC)

50 mA

Storage Temperature (TSTG)



C to



150

Lead Temperature (TL)

(Soldering, 10 seconds) 260

Supply Voltage (VCC) 4.5V to



5.5V

Input Voltage (VIN) 0V to



5.5V

Output Voltage (VOUT)

(Note 3) 0V to VCC

(Note 4) 0V to 5.5V

Operating Temperature (TOPR)



C to



Input Rise and Fall Time (tr, tf)

VCC

5.0V

0.5V 0 ns/V

20 ns/V

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level 4.5 2.0 2.0 V

Input Voltage 5.5 2.0 2.0

VIL LOW Level 4.5 0.8 0.8 V

Input Voltage 5.5 0.8 0.8

VOH HIGH Level 4.5 4.40 4.50 4.40 V VIN

VIL IOH



Output Voltage 3.94 3.80 V IOH



8 mA

VOL LOW Level 4.5 0.0 0.1 0.1 V VIN

VIH IOL

Output Voltage 0.36 0.44 V IOL

8 mA

IIN Input Leakage Current 0



5.5

0.1

1.0

A V

5.5V or GND

ICC Quiescent Supply Current 5.5 2.0 20.0

A V

VCC or GND

ICCT Maximum ICC/Input 5.5 1.35 1.50 mA VIN

3.4V

Other Inputs

VCC or GND

IOFF Output Leakage Current 0.0 0.5 5.0

OUT

5.5V

(Power Down State)

Symbol Parameter VCC

(V)

CUnits Conditions

Typ Limits

VOLP

(Note 7) Quiet Output Maximum Dynamic VOL 5.0 0.8 1.0 V C

50 pF

VOLV

(Note 7) Quiet Output Minimum Dynamic VOL 5.0



0.8 1.0 V CL

50 pF

VIHD

(Note 7) Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL

50 pF

VILD

(Note 7) Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL

50 pF

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74VHCT04A

AC Electrical Characteristics

Note 8: CPD is defined as t he value of t he internal equivalent capacitance w hich is calculate d f rom the operating current consumption without load. Average

operating current can be obtained by the equation: ICC (o pr.)

CPD * VCC * f IN



ICC/6 ( p er g ate ) .

Symbol Parameter VCC T

C T



C to



CUnits Conditions

(V) Min Typ Max Min Max

tPHL Propagation Delay 5.0

0.5 4.7 6.7 1.0 7.5 ns CL

15 pF

tPLH 5.5 7.7 1.0 8.5 CL

50 pF

CIN Input Capacitance 4 10 10 pF VCC

OPEN

CPD Power Dissipation 11 pF (Note 8)

Capacitance

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74VHCT04A

Physical Dim ensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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74VHCT04A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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74VHCT04A

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

14-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC14

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74VHCT04A Hex Inverter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.