‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Features
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 1©2006 Micron Technology, Inc. All rights reserved.
DDR2 SDRAM Registered MiniDIMM
MT18HTS12872(P)K – 1GB
MT18HTS25672(P)K – 2GB
MT18HTS51272(P)K – 4GB (Advance‡)
For component specifications, refer to Micron’s Web sit e: www.micron.com
Features
• 244-pin, mini dual in-line memory module
(MiniDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, or PC2-
5300
• Supports EC C error detection and correction
• 1GB (256 Meg x 72), 2GB (512 Meg x 72), and 4GB
(1,024 Meg x 72)
•V
DD = VDDQ = +1.8V
•V
DDSPD = +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differe ntial data strobe (DQS, DQS#) option
• Four-bit pr efetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Supports duplicate output strobe (RDQS/RDQS#)
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmabl e burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge cont acts
• Dual rank, TwinDieTM (2COB) DRAM devices
• Phase-lock loop (PLL) to reduce loading on system
clock
Figure 1: 244-Pin DIMM (MO-244)
Notes: 1. CL = CAS (READ) latency.
2. Contact Micron for product availability.
Options Marking
•Parity P
•Package
244-pin DIMM (lead-free) Y
•Frequency/CL
1
3ns @ CL = 5 (DDR2-667)2-667
3.75ns @ CL = 4 (DDR2-533) -53E
5.0ns @ CL = 3 (DDR2-400) -40E
•PCB height
30.0mm (1.18in)
Table 1: Address Table
1GB 2GB 4GB
Refresh count 8K 8K 8K
Row addressing 16K (A0–A13) 16K (A0–A13) 32K (A0–A14)
Device bank addressing 4 (BA0, BA1) 8 (BA0– BA2) 8 (BA0–BA2)
Device page size per bank 1KB 1KB 1KB
TwinDie device config uration 1Gb (64 Meg x 8, 2 Ranks) 2Gb (128 Meg x 8, 2 Ranks) 4Gb (256 Meg x 8, 2 Ranks)
Column addressing 1K (A0–A9) 1K (A0–A9) 1K (A0–A9)
Module rank addressing 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#)
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 2©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Features
Notes: 1. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT1 8HTS25672(P)KY-40EC2.
Table 2: Key Timing Parameters
Speed Grade
Data Rate (MT/s) tRCD
(ns) tRP
(ns) tRC
(ns)CL = 5 CL = 4 CL = 3
-667 667 533 400 15 15 55
-53E – 533 400 15 15 55
-40E – 400 400 15 15 55
Table 3: Part Numbers and Timing Parameters For 1GB Modules
Base Device: MT47H128M8 1Gb DDR2 SDRAM (16 Meg x8, x4 device banks, 2 ranks)
Part Number1Module
Density Configuration Module
Bandwidth Memory Clock/
Data Rate Latency
(CL-tRCD-tRP)
MT18HTS12872(P)KY-667__ 1GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT18HTS12872(P)KY-53E__ 1GB 256 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT18HTS12872(P)KY-40E__ 1GB 256 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 4: Part Numbers and Timing Parameters For 2GB Modules
Base Device: MT47H256M8 2Gb DDR2 SDRAM (16 Meg x8, x8 device banks, 2 ranks)
Part Number1Module
Density Configuration Module
Bandwidth Memory Clock/
Data Rate Latency
(CL-tRCD-tRP)
MT18HTS25672(P)KY-667__ 2GB 512 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT18HTS25672(P)KY-53E__ 2GB 512 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT18HTS25672(P)KY-40E__ 2GB 512 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 5: Part Numbers and Timing Parameters For 4GB Modules
Base Device: MT47H512M8 4Gb DDR2 SDRAM (32 Meg x8, x8 device banks, 2 ranks)
Part Number1Module
Density Configuration Module
Bandwidth Memory Clock/
Data Rate Latency
(CL-tRCD-tRP)
MT18HTS51272(P)KY-667__ 4GB 1,024 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT18HTS51272(P)KY-53E__ 4GB 1,024 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT18HTS51272(P)KY-40E__ 4GB 1,024 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 3©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Notes: 1. Pin 177 is NC for 1GB and 2GB, or A14 for 4GB.
Table 6: Pin Assignments
244-Pin MiniDIMM Front 244-Pin MiniDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1V
REF 32 VSS 63 VDDQ 94 DQS5# 123 VSS 154 DQ28 185 A3 216 RDQS#
2V
SS 33 DQ24 64 A2 95 DQS5 124 DQ4 155 DQ29 186 A1 217 VSS
3DQ034 DQ25 65 VDD 96 VSS 125 DQ5 156 VSS 187 VDD 218 DQ46
4DQ135VSS 66 VSS 97 DQ42 126 VSS 157 DM3/
RDQS3 188 CK0 219 DQ47
5VSS 36 DQS3# 67 VSS 98 DQ43 127 DM0/
RDQS0 158 NC/
RDQS#3 189 CK0# 220 VSS
6 DQS0# 37 DQS3 68 NC 99 VSS 128 NC/
RDQS#0 159 VSS 190 VDD 221 DQ52
7DQS038 VSS 69 VDD 100 DQ48 129 VSS 160 DQ30 191 A0 222 DQ53
8VSS 39 DQ26 70 A10/AP 101 DQ49 130 DQ6 161 DQ31 192 BA1 223 VSS
9 DQ2 40 DQ27 71 BA0 102 VSS 131 DQ7 162 VSS 193 VDD 224 RFU
10 DQ3 41 VSS 72 VDD 103 SA2 132 VSS 163 CB4 194 RAS# 225 RFU
11 VSS 42 CB0 73 WE# 104 NC (Test) 133 DQ12 164 CB5 195 VDDQ226 VSS
12 DQ8 43 CB1 74 VDDQ105 Vss 134 DQ13 165 VSS 196 S0# 227 DM6/
RDQS6
13 DQ9 44 VSS 75 CAS# 106 DQS6# 135 VSS 166 DM8/
RDQS8 197 VDDQ228 NC/
RDQS#6
14 VSS 45 DQS8# 76 VDDQ 107 DQS6 136 DM1/
RDQS1 167 NC/
RDQS#8 198 ODT0 229 VSS
15 DQS1# 46 DQS8 77 S1# 108 VSS 137 NC/
RDQS#1 168 VSS 199 A13 230 DQ54
16 DQS1 47 VSS 78 NC 109 DQ50 138 VSS 169 CB6 200 VDD 231 DQ55
17 Vss 48 CB2 79 VDDQ110 DQ51 139 RFU 170 CB7 201 NC 232 VSS
18 NC 49 CB3 80 NC 111 VSS 140 RFU 171 VSS 202 VSS 233 DQ60
19 NC 50 VSS 81 VSS 112 DQ56 141 VSS 172 NC 203 DQ36 234 DQ61
20 VSS 51 NC 82 DQ32 113 DQ57 142 DQ14 173 VDDQ204 DQ37 235 VSS
21 DQ10 52 VDDQ83 DQ33 114 VSS 143 DQ15 174 NC/CKE1 205 VSS 236 DM7/
RDQS7
22 DQ11 53 CKE0 84 VSS 115 DQS7# 144 VSS 175 VDD 206 DM4/
RDQS4 237 NC/
RDQS#7
23 VSS 54 VDD 85 DQS4# 116 DQS7 145 DQ20 176 NC 207 NC/
RDQS#4 238 VSS
24 DQ16 55 BA2 86 DQS4 117 VSS 146 DQ21 177 NC/A14 208 VSS 239 DQ62
25 DQ17 56 NC 87 VSS 118 DQ58 147 VSS 178 VDDQ209 DQ38 240 DQ63
26 VSS 57 VDDQ88 DQ34 119 DQ59 148 DM2/
RDQS2 179 A12 210 DQ39 241 VSS
27 DQS2# 58 A11 89 DQ35 120 VSS 149 NC/
RDQS#2 180A9211VSS 242 SDA
28 DQS2 59 A7 90 VSS 121 SA0 150 VSS 181 VDD 212 DQ44 243 SCL
29 VSS 60 VDD 91 DQ40 122 SA1 151 DQ22 182 A8 213 DQ45 244 VDDSPD
30 DQ18 61 A5 92 DQ41 152 DQ23 183 A6 214 VSS
31 DQ19 62 A4 93 VSS 153 VSS 184 VDDQ 215 DM5/
RDQS5
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 4©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Pin Assignments and Descriptions
Table 7: Pin Descriptions
Pin numbers may not correlate with symbols; refer to pin assignment table on page 3 for more information
Symbol Type Description
ODT0, ODT1 Input On-Die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM. When enabled, ODT is only applied to each of the fo llowing pins: DQ , DQS,
DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
CK0, CK0# Input Clock: CK and CK# are different ial cloc k inputs. All address and control input signals are
sampled on the crossing of the pos itive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE0, CKE1 Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on
the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE power-
down and SELF REFRESH operations (all device banks idle), or ACTI VE power-down (row
ACTIVE in any device bank). CKE is synchronous for power-down entry, power-down exit,
output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input
buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers
(excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a
LVCMOS LOW level when VDD is applied during first power-up. After VREF has become stable
during the power-on and initialization sequence, it must be maintained for proper operation
of the CKE receiver. For proper self-refresh operation, VREF must be maintained to this input.
S0#, S1# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
All commands are masked when S# is registered HIGH. S# provides for external rank selection
on systems with multiple ranks. S# is considered part of the command code.
RAS#, CAS#,
WE# Input C ommand inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
BA0, BA1, BA2 Input Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0–BA1 define which mode register including MR,
EMR, EMR (2), and EMR (3) is loaded during the LOAD MODE command.
A0–A13
(1GB, 2GB)
A0–A14
(4GB)
Input Address inputs : P rovide the row address fo r ACTIVE commands, and the column address and
auto precharge bit (A10) for READ/WRITE commands, to select one loc ation out of the
memory array in the respective bank. A10 sampled during a P RE CHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1/B A2) or all d evice ban ks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MO DE command.
DQ0–DQ63 I/O Data input/output: Bidirectional data bus.
DQS0–DQS8 I/O Data strobe: Output with read data, input with write data for source synchronous operation.
Edge-aligned with read data, center aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE command.
DM0–DM8/
RDQS0–RDQS8 I/O Input data mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. If RDQS is disabled, DQS0–DQS17 become DM0–DM8 and DQS9#–DQS17# are
not used.
CB0–CB7 I/O Check bits.
SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer
to and from the module.
SA0–SA2 Input Presence-detect address inputs: These pins are used to conf igure the presence-detect device.
SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into
and out of the presence-detect portion of the module.
VDD Supply Power supply: 1.8V ±0.1V.
VDDQ Supply DQ power supply: 1.8V ±0.1V.
VREF Supply SSTL_18 reference voltage.
VSS Supply Ground.
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 5©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Functional Block Diagram
Functional Block Diagram
Unless otherwise noted, resistor values are 22Ω. Micron module part numbers are
explained in the module part numbering guide at www.micron.com/support/
numbering.html. Modules use the following DDR2 SDRAM devices: MT47H256M4
(1GB); MT47H512M4 (2GB); and TBD (4GB).
VDDSPD Supply Serial EEPROM posi tive power supply: +1.7V to +3.6V.
NC – No connect: These pins should be left unconnected.
RFU – Reserved for future use.
Table 7: Pin Descriptions (Continued)
Pin numbers may not correlate with symbols; refer to pin assignment table on page 3 for more information
Symbol Type Description
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 6©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Functional Block Diagram
Figure 2: Functional Block Diagram
R
E
G
I
S
T
E
R
S
PAR_IN
S0#
S1#
BA0-BA1/BA2
A0–A13/A14
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
RESET# CK
CK#
ERR_OUT
RS0#: Rank0
RS1#: Rank1
RBA0-RBA1/RBA2: DDR2 SDRAMs
RA0-RA12/RA13: DDR2 SDRAMs
RRAS#: DDR2 SDRAMs
RCAS#: DDR2 SDRAMs
RWE#: DDR2 SDRAMs
RCKE0: Rank0
RCKE1: Rank1
RODT0: Rank0
RODT1: Rank1
U4, U10
VREF
VSS
DDR2 SDRAMs
DDR2 SDRAMs
VDD
DDR2 SDRAMs
VDDSPD Serial PD
VDDQ
DDR2 SDRAMs
A0
Serial PD
A1 A2
SA0 SA1 SA2
SDA
SCL
WP
PLL
CK0
CK0#
120
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
REGISTER xs 2
RESET#
U11
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U1b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U1t
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U5b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U5t
DQS0
DQS0#
DM0/RDQS0
NC/RDQS0#
DQS4
DQS4#
DM4/RDQS4
NC/RDQS4#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U13b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U13t
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U9b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U9t
DQS1
DQS1#
DM1/RDQS1
NC/RDQS1#
DQS5
DQS5#
DM5/RDQS5
NC/RDQS5#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U2b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U2t
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U6b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U6t
DQS2
DQS2#
DM2/RDQS2
NC/RDQS2#
DQS6
DQS6#
DM6/RDQS6
NC/RDQS6#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U3b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U3t
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U8b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U8t
DQS3
DQS3#
DM3/RDQS3
NC/RDQS3#
DQS7
DQS7#
DM7/RDQS7
NC/RDQS7#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U12b
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U12t
DQS8
DQS8#
DM8/RDQS8
NC/RDQS8#
RS1#
RS0#
Rank0 = U1b - U3b, U5b , U6b, U8b, U9b, U12b, U13b
Rank1 = U1t - U3t, U5t , U6t, U8t, U9t, U12t, U13t
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 7©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
General Description
General Description
The MT18HTS12872(P)K, MT18HTS25672(P)K, and MT18HTS51272(P)K DDR2 SDRAM
modules are high-speed, CMOS, dynamic r andom-access 1GB, 2GB, and 4GB memory
modules organized in x72 configuration. DDR2 SDRAM module s use internally config-
ured quad-bank (1GB) or eight-bank (2GB, 4GB) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate archi t ecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consis ts of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modul es operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (addre ss and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQ S, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
PLL and Register Operation
DDR2 SDRAM modules operate in registered mode, where the command/addr ess input
signals ar e latched in the regi sters on the risi ng clock ed ge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock lo op (PLL) on the module receives and redrives the differential clock sig n al s
(CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and
clock loading. R egistered mode will add one clock cycle to CL.
Serial Presence-Detect Op eration
DDR2 SDRAM modules incorporate seri al presence-d et ect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed b y M icron to i dentify the module type and
various SDRAM organizat ions and timing parame ters . The remaining 128 b y tes of
storage are available for use by the customer. Sy stem READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
pro vide eight unique DIMM/EEPR OM addresses . Write protect (WP) is tied to ground on
the module, permanently disabling hard ware write protect.
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 8©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Electrical Specifications
Electrical Specifications
S tresses greater than those listed in Table 8 may caus e permanent damage to the devi ce.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this spec ifi cat ion is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reli ability.
Capacitance
At DDR2 data rates, Micron encourages design ers to simulate the performance of the
module to achieve optimum values. When inductance and delay parameters associated
with trace lengths are used in simulations, they are significantly more accurate and real-
istic than a gross estimation of module capacitance. Simulations can then render a
considerably more accurate result. JEDEC modules are now designed by using simula-
tions to close timing budgets.
Table 8: Absolute Maximum DC Ratings
Parameter Symbol Min Max Units
VDD supply voltage relative to VSS VDD –1.0 2.3 V
VDDQ supply voltage relative to VSS VDDQ–0.52.3 V
VDDL supply voltage relative to Vss VDDL–0.52.3V
Voltage on any pin relative to VSS VIN, VOUT –0.5 2.3 V
Storage temperature TSTG –55 100 °C
DDR2 SDRAM device operating temperature (ambient) Tcase 085°C
Operating temperature (ambient) TOPR 055°C
Input leakage current; any input 0V ≤ VIN ≤ VDD; VREF
input 0V ≤ VIN ≤0.95V;
(all other pins not under test = 0V)
Command/address,
RAS#, CAS#, WE# S#,
CKE
II–5 5 µA
CK, CK# –10 10
DM –10 10
Output leakage current; 0V ≤ V OUT ≤ VDDQ; DQs and
ODT are disabled DQ, DQS, DQS# IOZ –10 10 µA
VREF leakage current; VREF = Valid VREF level IVREF –36 36 µA
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 9©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
I
DD
Specifications and Conditions
IDD Specifications and Conditions
Table 9: IDD Specifications and Conditions – 1GB
Values shown for DDR2 TwinDie SDRAM components only
Parameter/Condition Symbol -667 -53E -40E Units
Operating one device bank active-precharge current; tCK = tCK (IDD), tRC
= tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD0 918 828 828 mA
Operating one device bank active-read-precharge current; IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
address bus inputs are switching; Data pattern is same as IDD4W
ICDD1 1,053 963 918 mA
Precharge power-down current; All device banks idle ; tCK = tCK (IDD); CKE
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
ICDD2P 126 126 126 mA
Precha rge quiet standby curr ent ; All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
ICDD2Q 513 468 423 mA
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bu s inputs ar e switching; Data bus
inputs are switching
ICDD2N 558 513 468 mA
Active power-down current; All device banks open; tCK =
tCK (IDD); CKE is LOW; other control and address bus inputs
are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0 ICDD3P 378 333 288 mA
Slow PDN exit
MR[12] = 1 171 171 171 mA
Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
ICDD3N 693 603 513 mA
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP
= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
ICDD4W 1,638 1,368 1,143 mA
Operating burst read current; All device banks open; Continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
ICDD4R 1,728 1,413 1,143 mA
Burst refr esh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs ar e switching
ICDD5 1,728 1,638 1,593 mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs ar e floating ICDD6 126 126 126 mA
Operating device bank interleave read current; All device banks
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE
is HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during DESELECTs; Data bus inputs are switching
ICDD7 2,268 2,133 2,088 mA
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 10 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
I
DD
Specifications and Conditions
Table 10: IDD Specifications and Conditions – 2GB
Values shown for DDR2 SDRAM components only
Parameter/Condition Symbol -667 -53E -40E Units
Operating one device bank active-pr echar ge curr ent; tCK = tCK (IDD), tRC
= tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD0 918 828 738 mA
Operating one device bank active-read-precharge current; IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
address bus inputs are switching; Data pattern is same as IDD4W
ICDD1 1,008 963 828 mA
Precharge power -down current; All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
ICDD2P 126 126 126 mA
Precha rge quiet standby cur r ent; All dev ice banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
ICDD2Q 603 477 423 mA
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
ICDD2N 648 513 468 mA
Active power-down current; All device banks open; tCK =
tCK (IDD); CKE is LOW; other control and address bus inputs
are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0 ICDD3P 468 378 333 mA
Slow PDN exit
MR[12] = 1 153 153 153 mA
Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
ICDD3N 738 603 513 mA
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP
= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
ICDD4W 1,548 1,278 1,098 mA
Operating burst read current; All device banks open; Continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
ICDD4R 1,548 1,413 1,098 mA
Burst refresh current; tCK = tCK (IDD); REFRES H c ommand at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs ar e switching
ICDD5 2,448 2,358 2,088 mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs ar e floating ICDD6 126 126 126 mA
Operating device bank interleave read current; All device banks
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE
is HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during DESELECTs; Data bus inputs are switching
ICDD7 2,808 2,718 2,448 mA
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 11 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
I
DD
Specifications and Conditions
Table 11: IDD Specifications and Conditions – 4GB
Values shown for DDR2 SDRAM components only
Parameter/Condition Symbol -667 -53E -40E Units
Operating one device bank active-precharge current; tCK = tCK (IDD), tRC
= tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD0 1,017 927 927 mA
Operating one device bank active-read-precharge current; IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
address bus inputs are switching; Data pattern is same as IDD4W
ICDD1 1,422 1,062 1,062 mA
Precharge power-down current; All devi ce banks idle; tCK = tCK (I DD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
ICDD2P 144 144 144 mA
Precha rge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
ICDD2Q 567 477 432 mA
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
ICDD2N 657 567 522 mA
Active power-down current; All device banks open; tCK =
tCK (IDD); CKE is LOW ; other control and address bus inputs are
stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0 ICDD3P 432 387 342 mA
Slow PDN exit
MR[12] = 1 162 162 162 mA
Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
ICDD3N 612 522 477 mA
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP
= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
ICDD4W 1,467 1,287 1,242 mA
Operating burst read current; All device banks open; Continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
ICDD4R 1,647 1,467 1,377 mA
Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs ar e switching
ICDD5 2,637 2,457 2,367 mA
Self re fresh curr ent; CK and CK# at 0V; CKE ≤ 0.2V ; Other control and address
bus inputs are floating; Data bus inputs ar e floating ICDD6 144 144 144 mA
Operating device bank interleave read current; All device banks
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during DESELECTs; Data bus inputs are switching
ICDD7 3,177 2,772 2,772 mA
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 12 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
AC Operating Specifications
AC Operating Specifications
Re commended AC operating conditions are given in the DDR2 component data sheets.
Component specifications ar e available on Micr on ’s Web site: www.micron.com. Mod ule
speed grades correlate with component speed grades as shown in Table 12.
Table 12: Module and Component Speed Grade Table
Module Speed Grade Component Speed Grade
-667 -3
-53E -37E
-40E -5E
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 13 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Register and PLL Specifications
Register and PLL Specifications
Notes: 1. Timing and switching specifications for the register listed above are critical for proper oper-
ation of the DDR2 SDRAM Registered DIMMs. These are meant to be a subset of the param-
eters for the specific device used on the module. Detailed information for this register is
available in JEDEC Standard JESD82.
2. This parameter is not necessarily production tested.
3. Data inputs must be low a minimum time of tACT (MAX), after RESET# is taken HIGH.
4. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT
(MAX), after RESET# is taken LOW.
5. Total IDD = IDDQ = IADD = FCK × CPD × VDDQ, solving for CPD = (IDDQ + IADD)/ (FCK × VDDQ)
where FCK is the input frequency, VDDQ is the power supply and CPD is the power dissipation
capacitance.
Table 13: Register (SSTU32866 devices or Equivalent JESD82-16)
Parameter Symbol Pins Condition Min Max Units
DC high-level
input voltage VIH (DC) Address, control,
command SSTL_18 VREF (DC) + 125 VDDQ + 250 mV
DC low-level
input voltage VIL (DC) Address, control,
command SSTL_18 0 VREF (DC) - 125 mV
AC high-level
input voltage VIH (AC) Address, control,
command SSTL_18 VREF (DC) + 250 VDD mV
AC low-level
input voltage VIL (AC) Address, control,
command SSTL_18 0 VREF (DC) - 250 mV
Output high voltage VOH Parity output LVCMOS 1.2 – mV
Output low voltage VOL Parity outp ut LVCMOS – 0.5 mV
Input current IIAll pins VI = VDDQ or VSSQ–5 5µA
Static standby IDD All pins RESET# = VSSQ (I/O = 0) – 1 00 µA
Static operating IDD All pins RESET# = VSSQ;
VI = VIH (AC) or VIL (DC)
I/O = 0
–40mAµA
Dynamic operating –
clock tree IDDD N/A RESET# = VDD, VI = V IH (AC)
or VIL (AC), I0 = 0; CK and
CK# switching 50% duty
cycle
–Varies by
manufacturer µA
Dynamic operating
(per each input) IDDD N/A RESET# = VDD, VI = V IH (AC)
or VIL (AC), I0 = 0; CK and
CK# switching 50% duty
cycle; One data input
switching at tC K/2, 50%
duty cycle
–Varies by
manufacturer µA
Input capacitance
(per device, per pin) CIAll inputs except
RESET# VI = VREF ±250mV;
VDDQ = 1.8V 2.5 3.5 pF
Input capacitance
(per device, per pin) RESET# VI = VDDQ or VSSQ–Varies by
manufacturer pF
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 14 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Register and PLL Specifications
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC Standard JESD82.
2. Static phase offset does not include jitter.
3. Period jitter and half-period jitter specifications are separate specific at ions that must be
met independently of each other.
4. Design target is 60ps, unless it is unachievable.
5. VOX specified at the DRAM clock input, or the test load.
6. The output slew rate is determined from the IBIS model:
Table 14: PLL (CU877 device or Equivalent JESD82-8.01)
Parameter Symbol Pins Condition Min Max Units
DC high-level input voltage VIH RESET# LVCMOS 0.65 × VDD –mV
DC low-level input voltage VIL RESET# LVCMOS – 0.35 × VDD mV
Input voltage (limits) VIN RESET#, CK, CK# –0.3 VDDQ + 0.3 mV
DC high-level input voltage VIH CK, CK# Differential Input 0.65 × VDD –mV
DC low-level input voltage VIL CK, CK# Differentia l Input – 0.35 × VDD mV
Input differential-pair cross
voltage VIX CK, CK# Differential Input (VDDQ/2) - 0.15 (VDDQ/2) +
0.15 V
Input differential voltage VID (DC) CK, CK# Differential Inp ut 0.3 VDDQ + 0.4 V
Input differential voltage VID (AC) CK, CK# Differential Inp ut 0.6 VDDQ + 0.4 V
Input current IIRESET# VI = VDDQ or VSSQ –10 10 µA
CK, CK# VI = VDDQ or VSSQ –250 250 µA
Output disabled current IODL RESET# = VSSQ; VI = VIH
(AC) or VIL (DC)100 – µA
Static supply current IDDLD CK = CK# = LOW – 500 µA
Dynamic supply IDD N/A CK, CK# = 270 MHz, all
outputs open
(not connected to
PCB)
–300mA
Input capacitance CIN Each input VI = VDDQ or VSSQ2 3pF
Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
Parameter Symbol
0°C ≤ TOPR ≤ +55°C
VDD = +1.8V ±0.1V
UnitsMin Max
Stabilization time tL–15µs
Input clock slew rate tLSI1.0 4 V/ns
SSC modulation frequency 30 33 kHZ
SSC clock input frequ ency deviation 0.0 –0.50 %
PLL loop bandwidth (-3dB from unity gain) 2.0 – MHz
V
DD
2
GND
V
DD
CU878
R = 60
R = 60
V
CK
V
CK
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 15 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tor, and the EEPROM does not respond to its slave address.
Table 16: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units
Supply voltage VDDSPD 1.7 3.6 V
Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA VOL –0.4V
Input leakage current: VIN = GND to VDD ILI 0.10 3 µA
Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA
Standby current ISB 1.6 4 µA
Power supply current, READ: SCL clock frequenc y = 100 KHz ICCR0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 KHz ICCW23mA
Table 17: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start tBUF 1.3 – µs
Data-out hold time tDH 200 – ns
SDA and SCL fall time tF – 300 ns 2
Data-in hold time tHD:DAT 0 – µs
Start condition hold time tHD:STA 0.6 – µs
Clock HIGH period tHIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs tI–50ns
Clock LOW period tLOW 1.3 – µs
SDA and SCL rise time tR–0.3µs2
SCL clock frequency fSCL – 400 KHz
Data-in setup time tSU:DAT 100 – ns
Start condition setup time tSU:STA 0.6 – µs 3
Stop condition setup time tSU:STO 0.6 – µs
WRITE cycle time tWRC – 10 ms 4
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 16 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Serial Presence-Detect
Table 18: Serial Presence-Detect Matrix
“1”/“0”: Serial data, “driven to HIGH”/“driv en to LOW”; table notes located on page 17
Byte Description Entry
(Version)
MT18HTS12872(P)K MT18HTS25672(P)K MT18HTS51272(P)K
0Number of SPD bytes used by Micron 128808080
1Total number of bytes in SPD device 256080808
2Fundamental memory type DDR2 SDRAM080808
3Number of row addresses on DRAM 14, 15 0E 0F 0F
4Number of column addresses on DRAM 10 0A 0A 0A
5DIMM height and module ranks 30mm, dual
rank 61 61 61
6Module data width 72 48 48 48
7Reserved 0000000
8Module voltage interface levels SSTL 1.8V 05 05 05
9SDRAM cycle time, tCK (CL = MAX
value, see byte 18) -667
-53E
-40E
30
3D
50
30
3D
50
30
3D
50
10 SDRAM access from clock,tAC (CL =
MAX value, see byte 18) -667
-53E
-40E
45
50
60
45
50
60
45
50
60
11 Module configuration t ype ECC
ECC and Parity 02
06 02
06 02
06
12 Refresh rate/type 7.81µs/SELF 82 82 82
13 DDR2 device width (primary DDR2) 8080808
14 Error-checking DDR2 data width 8080808
15 Reserved 00 00 00
16 Burst lengths supported 4, 80C0C0C
17 Number of banks on DDR2 device 4 or 8 4 8 8
18 CAS latencies supported -667 (5, 4, 3)
-53E/-40E (4, 3) 38
18 38
18 38
18
19 Module thickness 01 01 01
20 DDR2 DIMM type Registered
MiniDIMM 10 10 10
21 DDR2 module attributes 05 05 05
22 DDR2 device attributes: weak driver
(01) and 50Ω ODT (03) -667
-53E/-40E 03
01 03
01 03
01
23 DDR2 cycle time, tCK, MAX CL - 1 -667
-53E/-40E 3D
50 3D
50 3D
50
24 DDR2 access from CK, tAC, MAX CL - 1 -667
-53E
-40E
45
50
60
45
50
60
45
50
60
25 DDR2 cycle time, tCK, MAX CL - 2 -667
-53E/-40E (N/A) 50
00 50
00 50
00
26 DDR2 access from CK, tAC, MAX CL - 2 -667
-53E/-40E (N/A) 45
00 45
00 45
00
27 MIN row precharge time, tRP 3C 3C 3C
28 MIN row active-to-row active, tRRD 1E 1E 1E
29 MIN RAS#-to-CAS# delay, tRCD 3C 3C 3C
30 MIN RAS# pulse width, tRAS (see note
1) -667/-53E
-40E 2D
28 2D
28 2D
28
31 Module rank density 512MB, 1GB,
2GB 80 01 02
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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 17 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Serial Presence-Detect
Notes: 1. tRAS SPD value shown is based on the JEDEC standard value of 45ns; actual device specifica-
tion is tRAS = 40ns.
32 Address and command setup time, tISb-667
-53E
-40E
20
25
35
20
25
35
20
25
35
33 Address and command hold time, tIHb-667
-53E
-40E
27
37
47
27
37
47
27
37
47
34 Data/Data mask input setup time, tDSb-667/-53E
-40E 10
15 10
15 10
15
35 Data/Data mask input hold time, tDHb-667
-53E
-40E
17
22
27
7
22
27
7
22
27
36 WRITE recovery time, tWR 3C 3C 3C
37 WRITE-to-READ command delay, tWTR -667/-53E
-40E 1E
28 1E
28 1E
28
38 READ-to-PRECHARGE command delay,
tRTP 1E 1E 1E
39 Memory analysis probe 00 00 00
40 Extension for bytes 41 and 42 00 06 06
41 MIN active auto refresh time, tRC -667/-53E
-40E 3C
37 3C
37 3C
37
42 MIN auto refresh-to-active/AUTO
REFRESH command period, tRFC 69 7F C5
43 DDR2 device MAX cycle time, tCKMAX 8.0ns 80 80 80
44 DDR2 device MAX DQS-DQ skew time,
tDQSQ -667
-53E
-40E
18
1E
23
18
1E
23
18
1E
23
45 DDR2 device MAX read da ta hold skew
factor, tQHS -667
-53E
-40E
22
28
2D
22
28
2D
22
28
2D
46 PLL relock time 15µs0F0F0F
47–61 Optional features, not supported 00 00 00
62 SPD revision Release 1.2 12 12 12
63 Checksum for bytes 0–62
ECC / ECC and Pa r it y -667
-53E
-40E
80 / 84
2B / 2F
92 / 96
21 / 25
CC / D0
33 / 37
69 / 6G
14 / 18
7B / 7F
64 Manufacturer’s JEDEC ID code MICRON 2C 2C 2C
65–71 Manufacturer’s JEDEC I D code (Continued) FF FF FF
72 Manufacturing location 01–12 Variable data Variable data Va riable data
73–90 Module part number (ASCII) Variable data Variable data Variable data
91 PCB identification code 1–9 01–09 01–09 01–09
92 Identification code (continued) 0000000
93 Year of manufacture in BCD Variable data Variable data Variable data
94 Week of manufac ture in BCD Variable data Variable data Variable data
95–98 Module serial number Variable data Variable data Variable data
99–127 Manufacturer-specific data (RSVD) 00 00 00
Table 18: Serial Presence-Detect Matrix (Continued)
“1”/“0”: Serial data, “driven to HIGH”/“driv en to LOW”; table notes located on page 17
Byte Description Entry
(Version)
MT18HTS12872(P)K MT18HTS25672(P)K MT18HTS51272(P)K
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Te l: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-49 92
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Advance: For the 4GB device, this data sheet contains initial descriptions of products still under development.
For the 1GB and 2GB devices, this data sheet contains minimum and maximum limits specified over the complete power
supply and temperature range for production devices. Alt hough consider ed final, the se specific ations ar e subjec t to change,
as further product development and data characterization sometimes occur.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
Module Dimensions
PDF: 09005aef82218d23/Source: 09005aef82218d00 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 18 ©2006 Micron Technology, Inc. All rights reserved.
Module Dimensions
Figure 3: 244-Pin DIMM DDR2 Module Dimensions
Notes: 1. All dimensions are in inches (millimeters); or typical where noted. The dimensional
diagram is for reference only. Re fer to the MO document for complete design dimensions.
3.233 (82.127)
3.223 (81.873)
FRONT VIEW
1.187 (30.152)
1.175 (29.848)
0.787 (20.0)
TYP
0.394 (10.0)
TYP
0.039 (1.0)
TYP
0.079 (2.00) R
X2
0.039 (1.00) R
X2
0.02 (0.50) R
0.071 (1.80) D
X2
0.236 (6.0)
TYP
0.079 (2.0)
TYP
3.071 (78.0)
TYP
0.024 (0.60)
TYP 0.018 (0.45)
TYP
PIN 1 PIN 122
1.689 (42.9)
TYP
BACK VIEW
0.130 (3.3)
TYP 0.142 (3.6) TYP
0.130 (3.3)
TYP
1.323 (33.6)
TYP 1.512 (38.4)
TYP
0.126 (3.2)
TYP
0.150 (3.80)
MAX
0.043 (1.10)
0.035 (0.90)
PIN 244 PIN 123
U1 U2 U3
U4
U5 U6
U7
U8 U9
U10
U11
U12 U13
MAX
MIN
