1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Features DDR2 SDRAM Registered MiniDIMM MT18HTS12872(P)K - 1GB MT18HTS25672(P)K - 2GB MT18HTS51272(P)K - 4GB (Advance) For component specifications, refer to Micron's Web site: www.micron.com Features Figure 1: * 244-pin, mini dual in-line memory module (MiniDIMM) * Fast data transfer rates: PC2-3200, PC2-4200, or PC25300 * Supports ECC error detection and correction * 1GB (256 Meg x 72), 2GB (512 Meg x 72), and 4GB (1,024 Meg x 72) * VDD = VDDQ = +1.8V * VDDSPD = +1.7V to +3.6V * JEDEC standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * Four-bit prefetch architecture * DLL to align DQ and DQS transitions with CK * Multiple internal device banks for concurrent operation * Supports duplicate output strobe (RDQS/RDQS#) * Programmable CAS latency (CL) * Posted CAS additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst lengths: 4 or 8 * Adjustable data-output drive strength * 64ms, 8,192-cycle refresh * On-die termination (ODT) * Serial presence-detect (SPD) with EEPROM * Gold edge contacts * Dual rank, TwinDieTM (2COB) DRAM devices * Phase-lock loop (PLL) to reduce loading on system clock Table 1: 244-Pin DIMM (MO-244) Options Marking P * Parity * Package 244-pin DIMM (lead-free) * Frequency/CL1 3ns @ CL = 5 (DDR2-667)2 3.75ns @ CL = 4 (DDR2-533) 5.0ns @ CL = 3 (DDR2-400) * PCB height 30.0mm (1.18in) Y -667 -53E -40E Notes: 1. CL = CAS (READ) latency. 2. Contact Micron for product availability. Address Table 1GB Refresh count Row addressing Device bank addressing Device page size per bank TwinDie device configuration Column addressing Module rank addressing PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 2GB 4GB 8K 8K 8K 16K (A0-A13) 16K (A0-A13) 32K (A0-A14) 4 (BA0, BA1) 8 (BA0- BA2) 8 (BA0-BA2) 1KB 1KB 1KB 1Gb (64 Meg x 8, 2 Ranks) 2Gb (128 Meg x 8, 2 Ranks) 4Gb (256 Meg x 8, 2 Ranks) 1K (A0-A9) 1K (A0-A9) 1K (A0-A9) 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#) 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Features Table 2: Key Timing Parameters Data Rate (MT/s) Speed Grade CL = 5 CL = 4 CL = 3 RCD (ns) t RP (ns) -667 -53E -40E 667 - - 533 533 400 400 400 400 15 15 15 15 15 15 Table 3: t t RC (ns) 55 55 55 Part Numbers and Timing Parameters For 1GB Modules Base Device: MT47H128M8 1Gb DDR2 SDRAM (16 Meg x8, x4 device banks, 2 ranks) Part Number1 MT18HTS12872(P)KY-667__ MT18HTS12872(P)KY-53E__ MT18HTS12872(P)KY-40E__ Table 4: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 1GB 1GB 1GB 256 Meg x 72 256 Meg x 72 256 Meg x 72 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 Part Numbers and Timing Parameters For 2GB Modules Base Device: MT47H256M8 2Gb DDR2 SDRAM (16 Meg x8, x8 device banks, 2 ranks) Part Number1 MT18HTS25672(P)KY-667__ MT18HTS25672(P)KY-53E__ MT18HTS25672(P)KY-40E__ Table 5: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 2GB 2GB 2GB 512 Meg x 72 512 Meg x 72 512 Meg x 72 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 Part Numbers and Timing Parameters For 4GB Modules Base Device: MT47H512M8 4Gb DDR2 SDRAM (32 Meg x8, x8 device banks, 2 ranks) Part Number1 MT18HTS51272(P)KY-667__ MT18HTS51272(P)KY-53E__ MT18HTS51272(P)KY-40E__ Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 4GB 4GB 4GB 1,024 Meg x 72 1,024 Meg x 72 1,024 Meg x 72 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18HTS25672(P)KY-40EC2. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 6: Pin Assignments 244-Pin MiniDIMM Front 244-Pin MiniDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 VREF VSS DQ0 DQ1 32 33 34 35 VSS DQ24 DQ25 VSS 63 64 65 66 VDDQ A2 VDD VSS 94 95 96 97 DQS5# DQS5 VSS DQ42 123 124 125 126 VSS DQ4 DQ5 VSS 5 VSS 36 DQS3# 67 VSS 98 DQ43 127 6 DQS0# 37 DQS3 68 NC 99 VSS 128 7 8 9 10 11 12 DQS0 VSS DQ2 DQ3 VSS DQ8 38 39 40 41 42 43 VSS DQ26 DQ27 VSS CB0 CB1 69 70 71 72 73 74 VDD A10/AP BA0 VDD WE# VDDQ 13 DQ9 44 VSS 75 14 VSS 45 DQS8# 15 DQS1# 46 16 17 18 19 20 21 DQS1 Vss NC NC VSS DQ10 22 154 155 156 157 DQ28 DQ29 VSS DM3/ RDQS3 158 NC/ RDQS#3 159 VSS 185 186 187 188 A3 A1 VDD CK0 216 217 218 219 RDQS# VSS DQ46 DQ47 189 CK0# 220 VSS 190 VDD 221 DQ52 160 161 162 163 164 165 191 192 193 194 195 196 A0 BA1 VDD RAS# VDDQ S0# 222 223 224 225 226 227 166 DM8/ 197 RDQS8 167 NC/ 198 RDQS#8 168 VSS 199 VDDQ ODT0 A13 230 169 CB6 170 CB7 171 VSS 172 NC 173 VDDQ 174 NC/CKE1 200 201 202 203 204 205 VDD NC VSS DQ36 DQ37 VSS 231 232 233 234 235 236 100 DQ48 101 DQ49 102 VSS 103 SA2 104 NC (Test) 105 Vss 129 130 131 132 133 134 DM0/ RDQS0 NC/ RDQS#0 VSS DQ6 DQ7 VSS DQ12 DQ13 CAS# 106 DQS6# 135 VSS 76 VDDQ 107 DQS6 136 DQS8 77 S1# 108 VSS 137 47 48 49 50 51 52 VSS CB2 CB3 VSS NC VDDQ 78 79 80 81 82 83 NC VDDQ NC VSS DQ32 DQ33 109 110 111 112 113 114 DQ50 DQ51 VSS DQ56 DQ57 VSS 138 139 140 141 142 143 DM1/ RDQS1 NC/ RDQS#1 VSS RFU RFU VSS DQ14 DQ15 DQ11 53 CKE0 84 VSS 115 DQS7# 144 VSS 175 VDD 206 23 VSS 54 VDD 85 DQS4# 116 DQS7 145 DQ20 176 NC 207 24 25 26 DQ16 DQ17 VSS 55 56 57 BA2 NC VDDQ 86 87 88 DQS4 VSS DQ34 117 118 119 VSS DQ58 DQ59 146 147 148 177 178 179 NC/A14 VDDQ A12 208 209 210 27 DQS2# 58 A11 89 DQ35 120 VSS 149 180 A9 211 VSS 242 SDA 28 29 30 31 DQS2 VSS DQ18 DQ19 59 60 61 62 A7 VDD A5 A4 90 91 92 93 VSS DQ40 DQ41 VSS 121 122 SA0 SA1 150 151 152 153 DQ21 VSS DM2/ RDQS2 NC/ RDQS#2 VSS DQ22 DQ23 VSS 181 182 183 184 VDD A8 A6 VDDQ 212 213 214 215 DQ44 DQ45 VSS DM5/ RDQS5 243 244 SCL VDDSPD Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN DQ30 DQ31 VSS CB4 CB5 VSS DQ53 VSS RFU RFU VSS DM6/ RDQS6 228 NC/ RDQS#6 229 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/ RDQS7 237 NC/ RDQS#7 238 VSS DM4/ RDQS4 NC/ RDQS#4 VSS 239 DQ38 240 DQ39 241 DQ62 DQ63 VSS 1. Pin 177 is NC for 1GB and 2GB, or A14 for 4GB. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Pin Assignments and Descriptions Table 7: Pin Descriptions Pin numbers may not correlate with symbols; refer to pin assignment table on page 3 for more information Symbol Type Description ODT0, ODT1 Input CK0, CK0# Input CKE0, CKE1 Input S0#, S1# Input RAS#, CAS#, WE# BA0, BA1, BA2 Input On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE powerdown and SELF REFRESH operations (all device banks idle), or ACTIVE power-down (row ACTIVE in any device bank). CKE is synchronous for power-down entry, power-down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level when VDD is applied during first power-up. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh operation, VREF must be maintained to this input. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. A0-A13 (1GB, 2GB) A0-A14 (4GB) Input DQ0-DQ63 DQS0-DQS8 I/O I/O DM0-DM8/ RDQS0-RDQS8 I/O CB0-CB7 SCL I/O Input SA0-SA2 SDA Input I/O VDD VDDQ VREF VSS Supply Supply Supply Supply Input PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN Bank address inputs: BA0-BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0-BA1 define which mode register including MR, EMR, EMR (2), and EMR (3) is loaded during the LOAD MODE command. Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0-BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Data input/output: Bidirectional data bus. Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. If RDQS is disabled, DQS0-DQS17 become DM0-DM8 and DQS9#-DQS17# are not used. Check bits. Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-detect address inputs: These pins are used to configure the presence-detect device. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Power supply: 1.8V 0.1V. DQ power supply: 1.8V 0.1V. SSTL_18 reference voltage. Ground. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Functional Block Diagram Table 7: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to pin assignment table on page 3 for more information Symbol Type VDDSPD NC RFU Supply - - Description Serial EEPROM positive power supply: +1.7V to +3.6V. No connect: These pins should be left unconnected. Reserved for future use. Functional Block Diagram Unless otherwise noted, resistor values are 22. Micron module part numbers are explained in the module part numbering guide at www.micron.com/support/ numbering.html. Modules use the following DDR2 SDRAM devices: MT47H256M4 (1GB); MT47H512M4 (2GB); and TBD (4GB). PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Functional Block Diagram Figure 2: Functional Block Diagram RS1# RS0# DQS0 DQS0# DM0/RDQS0 NC/RDQS0# DQS4 DQS4# DM4/RDQS4 NC/RDQS4# DM/ RDQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U1b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1t DQS1 DQS1# DM1/RDQS1 NC/RDQS1# NU/ CS# DQS DQS# RDQS# U5b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U5t DQS5 DQS5# DM5/RDQS5 NC/RDQS5# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U13b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U13t DQS2 DQS2# DM2/RDQS2 NC/RDQS2# NU/ CS# DQS DQS# RDQS# U9b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U9t DQS6 DQS6# DM6/RDQS6 NC/RDQS6# DM/ RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U2b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2t DQS3 DQS3# DM3/RDQS3 NC/RDQS3# NU/ CS# DQS DQS# RDQS# U6b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U6t DQS7 DQS7# DM7/RDQS7 NC/RDQS7# DM/ RDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U3b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U3t DQS8 DQS8# DM8/RDQS8 NC/RDQS8# DM/ RDQS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U12b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NU/ CS# DQS DQS# RDQS# NU/ CS# DQS DQS# RDQS# U8b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ Rank1 = U1t - U3t, U5t , U6t, U8t, U9t, U12t, U13t U12t DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 REGISTER xs 2 U11 120 CK0 CK0# PLL U7 U4, U10 R E G I S T E R S RESET# CK# PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN SCL ERR_OUT RS0#: Rank0 Serial PD WP A0 RS1#: Rank1 RBA0-RBA1/RBA2: DDR2 SDRAMs RA0-RA12/RA13: DDR2 SDRAMs RRAS#: DDR2 SDRAMs RCAS#: DDR2 SDRAMs RODT0: Rank0 RODT1: Rank1 CK 6 A1 SDA A2 SA0 SA1 SA2 VDDSPD RWE#: DDR2 SDRAMs RCKE0: Rank0 RCKE1: Rank1 U8t Rank0 = U1b - U3b, U5b , U6b, U8b, U9b, U12b, U13b RESET# PAR_IN S0# S1# BA0-BA1/BA2 A0-A13/A14 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 NU/ CS# DQS DQS# RDQS# Serial PD VDD DDR2 SDRAMs VDDQ DDR2 SDRAMs VREF DDR2 SDRAMs VSS DDR2 SDRAMs Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM General Description General Description The MT18HTS12872(P)K, MT18HTS25672(P)K, and MT18HTS51272(P)K DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 1GB, 2GB, and 4GB memory modules organized in x72 configuration. DDR2 SDRAM modules use internally configured quad-bank (1GB) or eight-bank (2GB, 4GB) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. PLL and Register Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and clock loading. Registered mode will add one clock cycle to CL. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 8 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 8: Absolute Maximum DC Ratings Parameter Symbol Min Max Units VDD supply voltage relative to VSS VDDQ supply voltage relative to VSS VDDL supply voltage relative to Vss Voltage on any pin relative to VSS Storage temperature DDR2 SDRAM device operating temperature (ambient) Operating temperature (ambient) Input leakage current; any input 0V VIN VDD; VREF Command/address, RAS#, CAS#, WE# S#, input 0V VIN 0.95V; (all other pins not under test = 0V) CKE CK, CK# DM Output leakage current; 0V VOUT VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = Valid VREF level VDD VDDQ VDDL VIN, VOUT TSTG Tcase TOPR II -1.0 -0.5 -0.5 -0.5 -55 0 0 -5 2.3 2.3 2.3 2.3 100 85 55 5 V V V V C C C A IOZ -10 -10 -10 10 10 10 A IVREF -36 36 A Capacitance At DDR2 data rates, Micron encourages designers to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM IDD Specifications and Conditions IDD Specifications and Conditions Table 9: IDD Specifications and Conditions - 1GB Values shown for DDR2 TwinDie SDRAM components only Parameter/Condition Symbol -667 -53E -40E Units Operating one device bank active-precharge current; tCK = tCK (IDD), tRC ICDD0 = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD1 Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; address bus inputs are switching; Data pattern is same as IDD4W ICDD2P Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE ICDD2Q is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating ICDD2N Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching ICDD3P Active power-down current; All device banks open; tCK = Fast PDN exit tCK (IDD); CKE is LOW; other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS ICDD3N MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD4W Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD4R Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) ICDD5 interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD6 Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating ICDD7 Operating device bank interleave read current; All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching 918 828 828 mA 1,053 963 918 mA 126 126 126 mA 513 468 423 mA 558 513 468 mA 378 333 288 mA 171 171 171 mA 693 603 513 mA 1,638 1,368 1,143 mA 1,728 1,413 1,143 mA 1,728 1,638 1,593 mA 126 126 126 mA 2,268 2,133 2,088 mA PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM IDD Specifications and Conditions Table 10: IDD Specifications and Conditions - 2GB Values shown for DDR2 SDRAM components only Parameter/Condition Symbol -667 -53E -40E Units Operating one device bank active-precharge current; tCK = tCK (IDD), tRC ICDD0 = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD1 Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is ICDD2P LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE ICDD2Q is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating ICDD2N Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching ICDD3P Active power-down current; All device banks open; tCK = Fast PDN exit tCK (IDD); CKE is LOW; other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 ICDD3N Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD4W Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD4R Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD5 Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD6 Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating ICDD7 Operating device bank interleave read current; All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching 918 828 738 mA 1,008 963 828 mA 126 126 126 mA 603 477 423 mA 648 513 468 mA 468 378 333 mA 153 153 153 mA 738 603 513 mA 1,548 1,278 1,098 mA 1,548 1,413 1,098 mA 2,448 2,358 2,088 mA 126 126 126 mA 2,808 2,718 2,448 mA PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM IDD Specifications and Conditions Table 11: IDD Specifications and Conditions - 4GB Values shown for DDR2 SDRAM components only Parameter/Condition Symbol -667 -53E -40E Units ICDD0 Operating one device bank active-precharge current; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD1 Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is ICDD2P LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE ICDD2Q is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating ICDD2N Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching ICDD3P Active power-down current; All device banks open; tCK = Fast PDN exit tCK (IDD); CKE is LOW; other control and address bus inputs are MR[12] = 0 stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 ICDD3N Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD4W Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD4R Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD5 Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address ICDD6 bus inputs are floating; Data bus inputs are floating ICDD7 Operating device bank interleave read current; All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching 1,017 927 927 mA 1,422 1,062 1,062 mA 144 144 144 mA 567 477 432 mA 657 567 522 mA 432 387 342 mA 162 162 162 mA 612 522 477 mA 1,467 1,287 1,242 mA 1,647 1,467 1,377 mA 2,637 2,457 2,367 mA 144 144 144 mA 3,177 2,772 2,772 mA PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM AC Operating Specifications AC Operating Specifications Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site: www.micron.com. Module speed grades correlate with component speed grades as shown in Table 12. Table 12: Module and Component Speed Grade Table PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN Module Speed Grade Component Speed Grade -667 -53E -40E -3 -37E -5E 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Register and PLL Specifications Register and PLL Specifications Table 13: Register (SSTU32866 devices or Equivalent JESD82-16) Parameter Symbol Pins Condition Min Max Units DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage Output high voltage Output low voltage Input current Static standby Static operating VIH (DC) Address, control, command Address, control, command Address, control, command Address, control, command Parity output Parity output All pins All pins All pins SSTL_18 VREF (DC) + 125 VDDQ + 250 mV SSTL_18 0 VREF (DC) - 125 mV SSTL_18 VREF (DC) + 250 VDD mV SSTL_18 0 VREF (DC) - 250 mV 1.2 - -5 - - - 0.5 5 100 40mA mV mV A A A Dynamic operating - clock tree IDDD - Varies by manufacturer A Dynamic operating (per each input) IDDD - Varies by manufacturer A 2.5 3.5 pF - Varies by manufacturer pF VIL (DC) VIH (AC) VIL (AC) Input capacitance (per device, per pin) Input capacitance (per device, per pin) VOH VOL II IDD IDD CI Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN LVCMOS LVCMOS VI = VDDQ or VSSQ RESET# = VSSQ (I/O = 0) RESET# = VSSQ; VI = VIH (AC) or VIL (DC) I/O = 0 N/A RESET# = VDD, VI = VIH (AC) or VIL (AC), I0 = 0; CK and CK# switching 50% duty cycle N/A RESET# = VDD, VI = VIH (AC) or VIL (AC), I0 = 0; CK and CK# switching 50% duty cycle; One data input switching at tCK/2, 50% duty cycle All inputs except VI = VREF 250mV; RESET# VDDQ = 1.8V RESET# VI = VDDQ or VSSQ 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2 SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. 2. This parameter is not necessarily production tested. 3. Data inputs must be low a minimum time of tACT (MAX), after RESET# is taken HIGH. 4. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT (MAX), after RESET# is taken LOW. 5. Total IDD = IDDQ = IADD = FCK x CPD x VDDQ, solving for CPD = (IDDQ + IADD)/ (FCK x VDDQ) where FCK is the input frequency, VDDQ is the power supply and CPD is the power dissipation capacitance. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Register and PLL Specifications Table 14: PLL (CU877 device or Equivalent JESD82-8.01) Parameter Symbol Pins Condition Min Max Units DC high-level input voltage DC low-level input voltage Input voltage (limits) DC high-level input voltage DC low-level input voltage Input differential-pair cross voltage Input differential voltage Input differential voltage Input current VIH VIL VIN VIH VIL VIX RESET# RESET# RESET#, CK, CK# CK, CK# CK, CK# CK, CK# LVCMOS LVCMOS 0.65 x VDD - -0.3 0.65 x VDD - (VDDQ/2) - 0.15 mV mV mV mV mV V VID (DC) VID (AC) II CK, CK# CK, CK# RESET# CK, CK# 0.3 0.6 -10 -250 100 - 0.35 x VDD VDDQ + 0.3 - 0.35 x VDD (VDDQ/2) + 0.15 VDDQ + 0.4 VDDQ + 0.4 10 250 - - - 500 300 A mA 2 3 pF Output disabled current IODL Static supply current Dynamic supply IDDLD IDD N/A CIN Each input Input capacitance Table 15: Differential Input Differential Input Differential Input Differential Input Differential Input VI = VDDQ or VSSQ VI = VDDQ or VSSQ RESET# = VSSQ; VI = VIH (AC) or VIL (DC) CK = CK# = LOW CK, CK# = 270 MHz, all outputs open (not connected to PCB) VI = VDDQ or VSSQ V V A A A PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 0C TOPR +55C VDD = +1.8V 0.1V Parameter Stabilization time Input clock slew rate SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (-3dB from unity gain) Notes: Symbol Min Max Units tL - 1.0 30 0.0 2.0 15 4 33 -0.50 - s V/ns kHZ % MHz tLS I 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information is available in JEDEC Standard JESD82. 2. Static phase offset does not include jitter. 3. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 4. Design target is 60ps, unless it is unachievable. 5. VOX specified at the DRAM clock input, or the test load. 6. The output slew rate is determined from the IBIS model: VDD CU878 VCK R = 60 R = 60 VDD 2 VCK GND PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Serial Presence-Detect Serial Presence-Detect Table 16: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current Power supply current, READ: SCL clock frequency = 100 KHz Power supply current, WRITE: SCL clock frequency = 100 KHz Table 17: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD x 0.7 -0.6 - 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 VDDSPD x 0.3 0.4 3 3 4 1 3 V V V V A A A mA mA Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 - 0 0.6 0.6 - 1.3 - - 100 0.6 0.6 - 0.9 - - 300 - - - 50 - 0.3 400 - - - 10 s s ns ns s s s ns s s KHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT tSU:STA t SU:STO tWRC 2 2 3 4 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Serial Presence-Detect Table 18: Serial Presence-Detect Matrix "1"/"0": Serial data, "driven to HIGH"/"driven to LOW"; table notes located on page 17 Byte Description 0 1 2 3 4 5 Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on DRAM Number of column addresses on DRAM DIMM height and module ranks 6 7 8 9 Module data width Reserved Module voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) 10 SDRAM access from clock,tAC (CL = MAX value, see byte 18) 11 Module configuration type 12 13 14 15 16 17 18 Refresh rate/type DDR2 device width (primary DDR2) Error-checking DDR2 data width Reserved Burst lengths supported Number of banks on DDR2 device CAS latencies supported 19 20 Module thickness DDR2 DIMM type 21 22 23 DDR2 module attributes DDR2 device attributes: weak driver (01) and 50 ODT (03) DDR2 cycle time, tCK, MAX CL - 1 24 DDR2 access from CK, tAC, MAX CL - 1 25 DDR2 cycle time, tCK, MAX CL - 2 26 DDR2 access from CK, tAC, MAX CL - 2 27 28 29 30 MIN row precharge time, tRP MIN row active-to-row active, tRRD MIN RAS#-to-CAS# delay, tRCD MIN RAS# pulse width, tRAS (see note 1) Module rank density 31 PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN Entry (Version) 128 256 DDR2 SDRAM 14, 15 10 30mm, dual rank 72 0 SSTL 1.8V -667 -53E -40E -667 -53E -40E ECC ECC and Parity 7.81s/SELF 8 8 4, 8 4 or 8 -667 (5, 4, 3) -53E/-40E (4, 3) Registered MiniDIMM -667 -53E/-40E -667 -53E/-40E -667 -53E -40E -667 -53E/-40E (N/A) -667 -53E/-40E (N/A) -667/-53E -40E 512MB, 1GB, 2GB 16 MT18HTS12872(P)K MT18HTS25672(P)K MT18HTS51272(P)K 80 08 08 0E 0A 61 80 08 08 0F 0A 61 80 08 08 0F 0A 61 48 00 05 30 3D 50 45 50 60 02 06 82 08 08 00 0C 4 38 18 01 10 48 00 05 30 3D 50 45 50 60 02 06 82 08 08 00 0C 8 38 18 01 10 48 00 05 30 3D 50 45 50 60 02 06 82 08 08 00 0C 8 38 18 01 10 05 03 01 3D 50 45 50 60 50 00 45 00 3C 1E 3C 2D 28 80 05 03 01 3D 50 45 50 60 50 00 45 00 3C 1E 3C 2D 28 01 05 03 01 3D 50 45 50 60 50 00 45 00 3C 1E 3C 2D 28 02 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Serial Presence-Detect Table 18: Serial Presence-Detect Matrix (Continued) "1"/"0": Serial data, "driven to HIGH"/"driven to LOW"; table notes located on page 17 Byte Entry (Version) Description t 32 Address and command setup time, ISb 33 Address and command hold time, tIHb 34 Data/Data mask input setup time, tDSb 35 Data/Data mask input hold time, tDHb 36 37 WRITE recovery time, tWR WRITE-to-READ command delay, tWTR 38 READ-to-PRECHARGE command delay, tRTP Memory analysis probe Extension for bytes 41 and 42 MIN active auto refresh time, tRC 39 40 41 42 43 44 45 MIN auto refresh-to-active/AUTO REFRESH command period, tRFC DDR2 device MAX cycle time, tCKMAX DDR2 device MAX DQS-DQ skew time, tDQSQ DDR2 device MAX read data hold skew factor, tQHS 46 47-61 62 63 PLL relock time Optional features, not supported SPD revision Checksum for bytes 0-62 ECC / ECC and Parity 64 65-71 72 73-90 91 92 93 94 95-98 99-127 Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Manufacturer-specific data (RSVD) Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN -667 -53E -40E -667 -53E -40E -667/-53E -40E -667 -53E -40E -667/-53E -40E -667/-53E -40E 8.0ns -667 -53E -40E -667 -53E -40E 15s Release 1.2 -667 -53E -40E MICRON (Continued) 01-12 1-9 0 MT18HTS12872(P)K MT18HTS25672(P)K MT18HTS51272(P)K 20 25 35 27 37 47 10 15 17 22 27 3C 1E 28 1E 20 25 35 27 37 47 10 15 7 22 27 3C 1E 28 1E 20 25 35 27 37 47 10 15 7 22 27 3C 1E 28 1E 00 00 3C 37 69 00 06 3C 37 7F 00 06 3C 37 C5 80 18 1E 23 22 28 2D 0F 00 12 80 / 84 2B / 2F 92 / 96 2C FF Variable data Variable data 01-09 00 Variable data Variable data Variable data 00 80 18 1E 23 22 28 2D 0F 00 12 21 / 25 CC / D0 33 / 37 2C FF Variable data Variable data 01-09 00 Variable data Variable data Variable data 00 80 18 1E 23 22 28 2D 0F 00 12 69 / 6G 14 / 18 7B / 7F 2C FF Variable data Variable data 01-09 00 Variable data Variable data Variable data 00 1. tRAS SPD value shown is based on the JEDEC standard value of 45ns; actual device specification is tRAS = 40ns. 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM Module Dimensions Module Dimensions Figure 3: 244-Pin DIMM DDR2 Module Dimensions FRONT VIEW 0.150 (3.80) MAX 3.233 (82.127) 3.223 (81.873) 0.079 (2.00) R X2 U4 U1 U2 U3 U5 U6 0.039 (1.00) R X2 0.071 (1.80) D X2 1.187 (30.152) 1.175 (29.848) 0.787 (20.0) TYP 0.394 (10.0) TYP 0.236 (6.0) TYP 0.039 (1.0) TYP 0.079 (2.0) TYP PIN 1 0.02 (0.50) R 0.024 (0.60) 0.018 (0.45) TYP TYP PIN 122 0.043 (1.10) 0.035 (0.90) 1.689 (42.9) TYP 3.071 (78.0) TYP BACK VIEW U7 U10 U8 U9 U12 U13 U11 0.130 (3.3) TYP 0.142 (3.6) TYP PIN 123 PIN 244 1.323 (33.6) TYP 1.512 (38.4) TYP 0.126 (3.2) TYP Notes: MAX 1. All dimensions are in inches (millimeters); MIN or typical where noted. The dimensional diagram is for reference only. Refer to the MO document for complete design dimensions. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Advance: For the 4GB device, this data sheet contains initial descriptions of products still under development. For the 1GB and 2GB devices, this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.