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HTS18C256_512_1024x72K.fm - Rev. A 5/06 EN 11 ©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB: (x72, DR) 244-Pin DDR2 Registered MiniDIMM
I
DD
Specifications and Conditions
Table 11: IDD Specifications and Conditions – 4GB
Values shown for DDR2 SDRAM components only
Parameter/Condition Symbol -667 -53E -40E Units
Operating one device bank active-precharge current; tCK = tCK (IDD), tRC
= tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD0 1,017 927 927 mA
Operating one device bank active-read-precharge current; IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
address bus inputs are switching; Data pattern is same as IDD4W
ICDD1 1,422 1,062 1,062 mA
Precharge power-down current; All devi ce banks idle; tCK = tCK (I DD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
ICDD2P 144 144 144 mA
Precha rge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
ICDD2Q 567 477 432 mA
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
ICDD2N 657 567 522 mA
Active power-down current; All device banks open; tCK =
tCK (IDD); CKE is LOW ; other control and address bus inputs are
stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0 ICDD3P 432 387 342 mA
Slow PDN exit
MR[12] = 1 162 162 162 mA
Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
ICDD3N 612 522 477 mA
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP
= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
ICDD4W 1,467 1,287 1,242 mA
Operating burst read current; All device banks open; Continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
ICDD4R 1,647 1,467 1,377 mA
Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs ar e switching
ICDD5 2,637 2,457 2,367 mA
Self re fresh curr ent; CK and CK# at 0V; CKE ≤ 0.2V ; Other control and address
bus inputs are floating; Data bus inputs ar e floating ICDD6 144 144 144 mA
Operating device bank interleave read current; All device banks
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during DESELECTs; Data bus inputs are switching
ICDD7 3,177 2,772 2,772 mA