ADC10D020CIVSX - Texas Instruments High-Performance Analog

ADC10D020

September 29, 2010

Dual 10-Bit, 20 MSPS, 150 mW A/D Converter

General Description

The ADC10D020 is a dual low power, high performance

CMOS analog-to-digital converter that digitizes signals to 10

bits resolution at sampling rates up to 30 MSPS while con-

suming a typical 150 mW from a single 3.0V supply. No

missing codes is guaranteed over the full operating temper-

ature range. The unique two stage architecture achieves 9.5

Effective Bits over the entire Nyquist band at 20 MHz sample

rate. An output formatting choice of offset binary or 2's com-

plement coding and a choice of two gain settings eases the

interface to many systems. Also allowing great flexibility of

use is a selectable 10-bit multiplexed or 20-bit parallel output

mode. An offset correction feature minimizes the offset error.

To ease interfacing to most low voltage systems, the digital

output power pins of the ADC10D020 can be tied to a sepa-

rate supply voltage of 1.5V to 3.6V, making the outputs com-

patible with other low voltage systems. When not converting,

power consumption can be reduced by pulling the PD (Power

Down) pin high, placing the converter into a low power state

where it typically consumes less than 1 mW and from which

recovery is less than 1 ms. Bringing the STBY (Standby) pin

high places the converter into a standby mode where power

consumption is about 27 mW and from which recovery is 800

ns.

The ADC10D020's speed, resolution and single supply oper-

ation makes it well suited for a variety of applications, includ-

ing high speed portable applications.

Operating over the industrial (−40° ≤ TA ≤ +85°C) tempera-

ture range, the ADC10D020 is available in a 48-pin TQFP. An

evaluation board is available to ease the design effort.

Features

■Internal sample-and-hold

■Internal reference capability

■Dual gain settings

■Offset correction

■Selectable offset binary or 2's complement output

■Multiplexed or parallel output bus

■Single +2.7V to 3.6V operation

■Power down and standby modes

Key Specifications

■Resolution 10 Bits

■Conversion Rate 20 MSPS

■ENOB 9.5 Bits (typ)

■DNL 0.35 LSB (typ)

■Conversion Latency Parallel Outputs 2.5 Clock Cycles

■—Multiplexed Outputs, I Data Bus 2.5 Clock Cycles

—Multiplexed Outputs, Q Data Bus 3 Clock Cycles

■PSRR 90 dB

■Power Consumption—Normal Operation 150 mW (typ)

■—Power Down Mode <1 mW (typ)

—Fast Recovery Standby Mode 27 mW (typ)

Applications

■Digital Video

■CCD Imaging

■Portable Instrumentation

■Communications

■Medical Imaging

■Ultrasound

Ordering Information

Device Temperature Range NS Package

ADC10D020CIVS −40°C to +85°C 48-Pin TQFP

250 Count Tray

ADC10D020CIVSE −40°C to +85°C 48-Pin TQFP

250 Count Tape and Reel

ADC10D020CIVSX −40°C to +85°C 48-Pin TQFP

1000 Count Tape and Reel

ADC10D020EVAL Evaluation Board

ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter

Connection Diagram

20025501

TOP VIEW

Block Diagram

20025502

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ADC10D020

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

I+

I−

Analog inputs to “I” ADC. Nominal conversion range is 1.25V to

1.75V with GAIN pin low, or 1.0V to 2.0V with GAIN pin high.

Q+

Q−

Analog inputs to “Q” ADC. Nominal conversion range is 1.25V to

1.75V with GAIN pin low, or 1.0V to 2.0V with GAIN pin high.

1VREF

Analog Reference Voltage input. The voltage at this pin should be

in the range of 0.8V to 1.5V. With 1.0V at this pin and the GAIN pin

low, the full scale differential inputs are 1 VP-P. With 1.0V at this pin

and the GAIN pin high, the full scale differential inputs are 2 VP-P.

This pin should be bypassed with a minimum 1 µF capacitor.

45 VCMO

This is an analog output which can be used as a reference source

and/or to set the common mode voltage of the input. It should be

bypassed with a minimum of 1 µF low ESR capacitor in parallel with

a 0.1 µF capacitor. This pin has a nominal output voltage of 1.5V

and has a 1 mA output source capability.

43 VRP

Top of the reference ladder. Do not drive this pin. Bypass this pin

with a 10 µF low ESR capacitor and a 0.1 µF capacitor.

44 VRN

Bottom of the reference ladder. Do not drive this pin. Bypass this

pin with a 10 µF low ESR capacitor and a 0.1 µF capacitor.

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ADC10D020

Pin No. Symbol Equivalent Circuit Description

33 CLK Digital clock input for both converters. The analog inputs are

sampled on the falling edge of this clock input.

2 OS

Output Bus Select. With this pin at a logic high, both the “I” and the

“Q” data are present on their respective 10-bit output buses

(Parallel mode of operation). When this pin is at a logic low, the “I”

and “Q” data are multiplexed onto the “I” output bus and the “Q”

output lines all remain at a logic low (multiplexed mode).

31 OC

Offset Correct pin. A low-to-high transition on this pin initiates an

independent offset correction sequence for each converter, which

takes 34 clock cycles to complete. During this time 32 conversions

are taken and averaged. The result is subtracted from subsequent

conversions. Each input pair should have 0V differential value

during this entire 34 clock period.

32 OF

Output Format pin. When this pin is LOW the output format is Offset

Binary. When this pin is HIGH the output format is 2's complement.

This pin may be changed asynchronously, but this will result in

errors for one or two conversions.

34 STBY

Standby pin. The device operates normally with a logic low on this

and the PD (Power Down) pin. With this pin at a logic high and the

PD pin at a logic low, the device is in the standby mode where it

consumes just 27 mW of power. It takes just 800 ns to come out of

this mode after the STBY pin is brought low.

35 PD

Power Down pin that, when high, puts the converter into the Power

Down mode where it consumes less than 1 mW of power. It takes

less than 1 ms to recover from this mode after the PD pin is brought

low. If both the STBY and PD pins are high simultaneously, the PD

pin dominates.

36 GAIN

This pin sets the internal signal gain at the inputs to the ADCs. With

this pin low the full scale differential input peak-to-peak signal is

equal to VREF. With this pin high the full scale differential input peak-

to-peak signal is equal to 2 x VREF..

8 thru 27 I0–I9 and Q0–Q9

3V TTL/CMOS-compatible Digital Output pins that provide the

conversion results of the I and Q inputs. I0 and Q0 are the LSBs,

I9 and Q9 are the MSBs. Valid data is present just after the rising

edge of the CLK input in the Parallel mode. In the multiplexed

mode, I-channel data is valid on I0 through I9 when the I/Q output

is high and the Q-channel data is valid on I0 through I9 when the

I/Q output is low.

28 I/Q

Output data valid signal. In the multiplexed mode, this pin

transitions from low to high when the data bus transitions from Q-

data to I-data, and from high to low when the data bus transitions

from I-data to Q-data. In the Parallel mode, this pin transitions from

low to high as the output data changes.

40, 41 VA

Positive analog supply pin. This pin should be connected to a quiet

voltage source of +2.7V to +3.6V. VA and VD should have a

common supply and be separately bypassed with 10 µF to 50 µF

capacitors in parallel with 0.1 µF capacitors.

4VD

Digital supply pin. This pin should be connected to a quiet voltage

source of +2.7V to +3.6V. VA and VD should have a common supply

and be separately bypassed with 10 µF to 50 µF capacitors in

parallel with 0.1 µF capacitors.

6, 30 VDR

Digital output driver supply pins. These pins should be connected

to a voltage source of +1.5V to VD and be bypassed with 10 µF to

50 µF capacitors in parallel with 0.1 µF capacitors.

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ADC10D020

Pin No. Symbol Equivalent Circuit Description

3, 39, 42, 46 AGND The ground return for the analog supply. AGND and DGND should

be connected together close to the ADC10D020 package.

5 DGND The ground return for the digital supply. AGND and DGND should

be connected together close to the ADC10D020 package.

7, 29 DR GND The ground return of the digital output drivers.

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ADC10D020

Absolute Maximum Ratings

(Note 1, Note 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Positive Supply Voltages 3.8V

Voltage on Any Pin −0.3V to (VA or VD +0.3V)

Input Current at Any Pin (Note 3) ±25 mA

Package Input Current (Note 3) ±50 mA

Package Dissipation at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model 2500V

Machine Model 250V

Soldering Temperature,

Infrared, 10 sec. (Note 6) 235°C

Storage Temperature −65°C to +150°C

Operating Ratings (Note 1, Note 2)

Operating Temperature Range −40°C ≤ TA ≤ +85°C

VA, VD Supply Voltage +2.7V to +3.6V

VDR Supply Voltage +1.5V to VD

VIN Differential Voltage Range

GAIN = Low ±VREF/2

GAIN = High ±VREF

VCM Input Common Mode Range

GAIN = Low VREF/4 to (VA–VREF/4)

GAIN = High VREF/2 to (VA–VREF/2)

VREF Voltage Range 0.8V to 1.5V

Digital Input Pins Voltage

Range −0.3V to (VA +0.3V)

Converter Electrical Characteristics

The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (a.c. coupled)

= FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits

apply for TA = TMIN to TMAX: all other limits TA = 25°C (Note 7).

Symbol Parameter Conditions Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

STATIC CONVERTER CHARACTERISTICS

INL Integral Non-Linearity ±0.65 ±1.8 LSB (max)

DNL Differential Non-Linearity ±0.35 +1.2

−1.0

LSB (max)

LSB (min)

Resolution with No Missing Codes 10 Bits

VOFF Offset Error

Without Offset Correction −5 +10

−16

LSB (max)

LSB (min)

With Offset Correction +0.5 +2.0

−1.5

LSB (max)

LSB (min)

GE Gain Error −4 +6

−14

%FS (max)

%FS (min)

DYNAMIC CONVERTER CHARACTERISTICS

ENOB Effective Number of Bits

fIN = 1.0 MHz, VIN = FSR −0.1 dB 9.5 Bits

fIN = 4.7 MHz, VIN = FSR −0.1 dB 9.5 9.0 Bits (min)

fIN = 9.5 MHz, VIN = FSR −0.1 dB 9.5 Bits

fIN = 19.5 MHz, VIN = FSR −0.1 dB 9.5 Bits

SINAD Signal-to-Noise Plus Distortion Ratio

fIN = 1.0 MHz, VIN == FSR −0.1 dB 59 dB

fIN = 4.7 MHz, VIN = FSR −0.1 dB 59 56 dB (min)

fIN = 9.5 MHz, VIN = FSR −0.1 dB 59 dB

fIN = 19.5 MHz, VIN = FSR −0.1 dB 59 dB

SNR Signal-to-Noise Ratio

fIN = 1.0 MHz, VIN = FSR −0.1 dB 59 dB

fIN = 4.7 MHz, VIN = FSR −0.1 dB 59 56 dB (min)

fIN = 9.5 MHz, VIN = FSR −0.1 dB 59 dB

fIN = 19.5 MHz, VIN = FSR −0.1 dB 59 dB

THD Total Harmonic Distortion

fIN = 1.0 MHz, VIN = FSR −0.1 dB −73 dB

fIN = 4.7 MHz, VIN = FSR −0.1 dB −73 −62 dB (min)

fIN = 9.5 MHz, VIN = FSR −0.1 dB −73 dB

fIN = 19.5 MHz, VIN = FSR −0.1 dB −73 dB

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ADC10D020

Symbol Parameter Conditions Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

HS2 Second Harmonic

fIN = 1.0 MHz, VIN = FSR −0.1 dB −84 dB

fIN = 4.7 MHz, VIN = FSR −0.1 dB −92 dB

fIN = 9.5 MHz, VIN = FSR −0.1 dB −87 dB

fIN = 19.5 MHz, VIN = FSR −0.1 dB −87 dB

HS3 Third Harmonic

fIN = 1.0 MHz, VIN = FSR −0.1 dB −80 dB

fIN = 4.7 MHz, VIN = FSR −0.1 dB −78 dB

fIN = 9.5 MHz, VIN = FSR −0.1 dB −78 dB

fIN = 19.5 MHz, VIN = FSR −0.1 dB −78 dB

SFDR Spurious Free Dynamic Range

fIN = 1.0 MHz, VIN = FSR −0.1 dB 76 dB

fIN = 4.7 MHz, VIN = FSR −0.1 dB 75 dB

fIN = 9.5 MHz, VIN = FSR −0.1 dB 75 dB

fIN = 19.5 MHz, VIN = FSR −0.1 dB 74 dB

IMD Intermodulation Distortion fIN1 < 4.9 MHz, VIN = FSR −6.1 dB

fIN2 < 5.1 MHz, VIN = FSR −6.1 dB 65 dB

Overrange Output Code (VIN+−VIN−) > 1.1V 1023

Underrange Output Code (VIN+−VIN−) < −1.1V 0

FPBW Full Power Bandwidth 140 MHz

INTER-CHANNEL CHARACTERISTICS

Crosstalk 1 MHz input to tested channel, 4.75 MHz input to

other channel −90 dB

Channel - Channel Aperture Delay

Match fIN = 8 MHz 8.5 ps

Channel - Channel Gain Matching 0.03 %FS

REFERENCE AND ANALOG CHARACTERISTICS

VIN Analog Differential Input Range Gain Pin = AGND 1 VP-P

Gain Pin = VA2 VP-P

CIN

Analog Input Capacitance (each

input)

Clock High 6 pF

Clock Low 3 pF

RIN Analog Differential Input Resistance 27 kΩ

VREF Reference Voltage 1.0 0.8 V (min)

1.5 V (max)

IREF Reference Input Current <1 µA

VCMO Common Mode Voltage Output 1 mA load to ground (sourcing current) 1.5 1.35 V (min)

1.6 V (max)

VCMO

Common Mode Voltage Temperature

Coefficient

20 ppm/°C

DIGITAL INPUT CHARACTERISTICS

VIH Logical “1” Input Voltage VD = +2.7V 2.0 V (min)

VIL Logical “0” Input Voltage VD = +3.6V 0.5 V (max)

IIH Logical “1” Input Current VIH = VD<1 µA

IIL Logical “0” Input Current VIL = DGND >−1 µA

DIGITAL OUTPUT CHARACTERISTICS

VOH Logical “1” Output Voltage VDR = +2.7V, IOUT = −0.5 mA VDR

−0.3V V (min)

VOL Logical “0” Output Voltage VDR = +2.7V, IOUT = 1.6 mA 0.4 V (max)

+ISC Output Short Circuit Source Current VOUT = 0V Parallel Mode −7 mA

Multiplexed Mode −14 mA

−ISC Output Short Circuit Sink Current VOUT = VDR

Parallel Mode 7 mA

Multiplexed Mode 14 mA

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ADC10D020

Symbol Parameter Conditions Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

POWER SUPPLY CHARACTERISTICS

IA + IDCore Supply Current

PD = LOW, STBY = LOW, dc input 47.6 55 mA (max)

PD = LOW, STBY = HIGH 8.8 mA

PD = HIGH, STBY = LOW or HIGH 0.22 mA

IDR

Digital Output Driver Supply Current

(Note 10)

PD = LOW, STBY = LOW, dc input 1.3 1.4 mA (max)

PD = LOW, STBY = HIGH 0.1 mA

PD = HIGH, STBY = LOW or HIGH 0.1 mA

PWR Power Consumption

PD = LOW, STBY = LOW, dc input 150 169 mW (max)

PD = LOW, STBY = LOW, 1 MHz Input 178 mW

PD = LOW, STBY = HIGH 27 mW

PD = HIGH, STBY = LOW or HIGH <1 mW

PSRR1 Power Supply Rejection Ratio Change in Full Scale with 2.7V to 3.6V Supply

Change 90 dB

PSRR2 Power Supply Rejection Ratio Rejection at output with 20 MHz, 250 mVP-P

Riding on VA and VD

52 dB

AC Electrical Characteristics OS = Low (Multiplexed Mode)

The following specifications apply for VA = VD = VDR = +3.0VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 0V, VIN (a.c. coupled) =

FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply

for TA = TMIN to TMAX: all other limits TA = 25°C (Note 7)

Symbol Parameter Conditions Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

fCLK1Maximum Clock Frequency 30 20 MHz (min)

fCLK2Minimum Clock Frequency 1 MHz

Duty Cycle 50 30

% (min)

% (max)

Pipeline Delay (Latency)

I Data 2.5 Clock Cycles

Q Data 3.0 Clock Cycles

tr, tfOutput Rise and Fall Times 4 ns

tOC Offset Correction Pulse Width 10 ns (min)

tOD

Output Delay from CLK Edge to Data

Valid 13 18 ns (max)

tDIQ I/Q Output Delay 13 ns

tSKEW I/Q to Data Delay ±200 ps

tAD Sampling (Aperture) Delay 2.4 ns

tAJ Aperture Jitter <10 ps (rms)

tVALID Data Valid Time 21 ns

Overrange Recovery Time Differential VIN step from 1.5V to 0V 50 ns

tWUPD

PD Low to 1/2 LSB Accurate Conversion

(Wake-Up Time)

<1 ms

tWUSB

STBY Low to 1/2 LSB Accurate

Conversion (Wake-Up Time)

800 ns

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ADC10D020

AC Electrical Characteristics OS = High (Parallel Mode)

The following specifications apply for VA = +3.0 VDC, VD = +3.0 VDC, VDR = +3.0VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V,

VIN (a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.

Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (Note 7)

Symbol Parameter Conditions Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

fCLK1Maximum Clock Frequency 30 20 MHz (min)

fCLK2Minimum Clock Frequency 1 MHz

Duty Cycle 50 30

% (min)

% (max)

Pipeline Delay (Latency) 2.5 Conv Cycles

tr, tfOutput Rise and Fall Times 7 ns

toc OC Pulse Width 10 ns

tOD

Output Delay from CLK Edge to Data

Valid 15 21 ns (max)

tDIQ I/Q Output Delay 13 ns

tAD Sampling (Aperture) Delay 2.4 ns

tAJ Aperture Jitter <10 ps (rms)

tVALID Data Valid Time 43 ns

Overrange Recovery Time Differential VIN step from 1.5V to 0V 50 ns

tWUPD

PD Low to 1/2 LSB Accurate Conversion

(Wake-Up Time)

<1 ms

tWUSB

STBY Low to 1/2 LSB Accurate

Conversion (Wake-Up Time)

800 ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The

50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 48-

pin TQFP, θJA is 76°C/W, so PDMAX = 1,645 mW at 25°C and 855 mW at the maximum operating ambient temperature of 85°C. Note that the power dissipation

of this device under normal operation will typically be about 170 mW (150 mW quiescent power + 20 mW due to 1 LVTTL load on each digital output). The values

for maximum power dissipation listed above will be reached only when the ADC10D020 is operated in a severe fault condition (e.g. when input or output pins are

driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Note 7: The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device. However, errors

in the A/D conversion can occur if the input goes beyond the limits given in these tables.

20025506

Note 8: Typical figures are at TJ = 25°C, and represent most likely parametric norms.

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ADC10D020

Note 9: Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Performance is guaranteed only at VREF = 1.0V and a clock duty cycle

of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are performed and limits guaranteed

with clock low and high levels of 0.3V and VD − 0.3V, respectively.

Note 10: IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply

voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR (CO x fO + C1 x f1 + ... + C9 x f9) where VDR is the output driver

power supply voltage, Cn is the total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.

Timing Diagrams

20025508

ADC10D020 Timing Diagram for Multiplexed Mode

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ADC10D020

20025507

ADC10D020 Timing Diagram for Parallel Mode

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FIGURE 1. AC Test Circuit

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ADC10D020

Specification Definitions

APERTURE (SAMPLING) DELAY is that time required after

the fall of the clock input for the sampling switch to open. The

Sample/Hold circuit effectively stops capturing the input sig-

nal and goes into the “hold” mode tAD after the clock goes low.

APERTURE JITTER is the variation in aperture delay from

sample to sample. Aperture jitter shows up as input noise.

CLOCK DUTY CYCLE is the ratio of the time that the clock

waveform is high to the total time of one clock period.

CROSSTALK is coupling of energy from one channel into the

other channel.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

Measured at 20 MSPS with a ramp input.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio, or SINAD. ENOB is defined as (SINAD −

1.76)/6.02 and says that the converter is equivalent to a per-

fect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH (FPBW) is the frequency at

which the magnitude of the reconstructed output fundamental

drops 3 dB below its 1 MHz value.

GAIN ERROR is the difference between the ideal and actual

differences between the input levels at which the first and last

code transitions occur. That is, how far this difference is from

Full Scale.

INTEGRAL NON LINEARITY (INL) is a measure of the max-

imum deviation of each individual code from a line drawn from

zero scale (½ LSB below the first code transition) through

positive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value. The end point test method

is used. Measured at 20 MSPS with a ramp input.

INTERMODULATION DISTORTION (IMD) is the creation of

spectral components that are not present in the input as a

result of two sinusoidal frequencies being applied to the ADC

input at the same time. It is defined as the ratio of the power

in the second and third order intermodulation products to the

total power in one of the original frequencies. IMD is usually

expressed in dB.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-

est value of weight of all bits. This value is

m * VREF/2n

where “m” is the reference scale factor and “n” is the ADC

resolution, which is 10 in the case of the ADC10D020. The

value of “m” is determined by the logic level at the gain pin

and has a value of 1 when the gain pin is at a logic low and a

value of 2 when the gain pin is at a logic high.

MISSING CODES are those output codes that are skipped or

will never appear at the ADC outputs. These codes cannot be

reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest

value or weight. Its value is one half of full scale.

OFFSET ERROR is a measure of how far the mid-scale tran-

sition point is from the ideal zero voltage input.

OUTPUT DELAY is the time delay after the rising edge of the

input clock before the data update is present at the output

pins.

OVERRANGE RECOVERY TIME is the time required after

the differential input voltages goes from 1.5V to 0V for the

converter to recover and make a conversion with its rated ac-

curacy.

PIPELINE DELAY (LATENCY) is the number of clock cycles

between initiation of conversion and when that data is pre-

sented to the output driver stage. New data is available at

every clock cycle, but the data output lags the input by the

Pipeline Delay plus the Output Delay.

POWER SUPPLY REJECTION RATIO (PSRR) can be one

of two specifications. PSRR1 (DC PSRR) is the ratio of the

change in full scale gain error that results from a power supply

voltage change from 2.7V to 3.6V. PSRR2 (AC PSRR) is

measured with a 20 MHz, 250 mVP-P signal riding upon the

power supply and is the ratio of the signal amplitude on the

power supply pins to the amplitude of that frequency at the

output. PSRR is expressed in dB.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the fundamental signal at the output

to the rms value of the sum of all other spectral components

below one-half the sampling frequency, not including har-

monics or dc.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or

SINAD) is the ratio, expressed in dB, of the rms value of the

fundamental signal at the output to the rms value of all of the

other spectral components below half the clock frequency,

including harmonics but excluding dc.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the funda-

mental signal at the output and the peak spurious signal,

where a spurious signal is any signal present in the output

spectrum that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dB, of the rms total of the first 9 harmonic levels to

the level of the input frequency. THD is calculated as

where f1 is the RMS power of the fundamental (output) fre-

quency and f2 through f10 are the RMS power of the first 9

harmonic frequencies in the output spectrum.

www.national.com 12

ADC10D020

Typical Performance Characteristics VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified

Typical INL

20025511

INL vs. Supply Voltage

20025512

INL vs. VREF

20025513

INL vs. fCLK

20025514

13 www.national.com

ADC10D020

INL vs. Clock Duty Cycle

20025515

INL vs. Temperature

20025516

Typical DNL

20025517

DNL vs. Supply Voltage

20025518

DNL vs. VREF

20025519

DNL vs. fCLK

20025520

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ADC10D020

DNL vs. Clock Duty Cycle

20025521

DNL vs. Temperature

20025522

SNR vs. Supply Voltage

@ fIN = 1 MHz to 9.5 MHz

20025523

SNR vs. VREF

@ fIN = 4.7 MHz

20025524

SNR vs. fCLK @ fIN = 9.5 MHz

20025525

SNR vs. fIN

20025526

15 www.national.com

ADC10D020

SNR vs. Clock Duty Cycle

@ fIN = 4.7 MHz

20025527

SNR vs. VDR @ fIN = 9.5 MHz

20025528

SNR vs. VCM @ fIN = 9.5 MHz

20025529

SNR vs. Temperature @ fIN = 1 MHz to 9.5 MHz

20025530

SINAD & ENOB vs. Supply Voltage @ fIN = 1 MHz

to 9.5 MHz

20025531

SINAD & ENOB vs. VREF @ fIN = 4.7 MHz

20025532

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ADC10D020

SINAD & ENOB vs. @ fCLK (fIN = 9.5 MHz)

20025533

SINAD & ENOB vs. fIN

20025534

SINAD & ENOB vs. Clock Duty Cycle @ fIN = 4.7 MHz

20025535

SINAD & ENOB vs. VDR @ fIN = 9.5 MHz

20025536

SINAD & ENOB vs. VCM @ fIN = 9.5 MHz

20025537

SINAD & ENOB vs. Temperature @ fIN = 1 MHz to

9.5 MHz

20025538

17 www.national.com

ADC10D020

Distortion vs. Supply Voltage @ fIN = 4.7 MHz

20025539

Distortion vs. VREF @ fIN = 4.7 MHz

20025540

Distortion vs. fCLK @ fIN = 9.5 MHz

20025541

Distortion vs. fIN

20025542

Distortion vs. Clock Duty Cycle @ fIN = 4.7 MHz

20025543

Distortion vs. VDR @ fIN = 4.7 MHz

20025544

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ADC10D020

Distortion vs. VCM @ fIN = 4.7 MHz

20025545

Distortion vs. Temperature

20025546

SFDR vs. Supply Voltage @ fIN = 4.7 MHz

20025547

SFDR vs. VREF @ fIN = 4.7 MHz

20025548

SFDR vs. fCLK @ fIN = 9.5 MHz

20025549

SFDR vs. fIN

20025550

19 www.national.com

ADC10D020

SFDR vs. Clock Duty Cycle @ fIN = 4.7 MHz

20025551

SFDR vs. VDR @ fIN = 4.7 MHz

20025552

SFDR vs. VCM @ fIN = 4.7 MHz

20025553

SFDR vs. Temperature @ fIN = 4.7 MHz

20025554

Crosstalk vs. fIN

20025555

Crosstalk vs. VDR @ fIN = 4.7 MHz

20025556

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ADC10D020

Crosstalk vs. VCM @ fIN = 4.7 MHz

20025557

Crosstalk vs. Temperature

20025558

Power Consumption vs. Temperature

20025561

Spectral Response @ fIN = 1 MHz

20025562

Spectral Response @ fIN = 4.7 MHz

20025563

Spectral Response @ fIN = 9.5 MHz

20025564

21 www.national.com

ADC10D020

Spectral Response @ fIN = 21 MHz

20025565

Spectral Response @ fIN = 49 MHz

20025566

Spectral Response @ fIN = 99 MHz

20025581

IMD Response @ fIN = 4.9 MHz, 5.1 MHz

20025568

Functional Description

Using a subranging architecture, the ADC10D020 achieves

9.5 effective bits over the entire Nyquist band at 20 MSPS

while consuming just 150 mW. The use of an internal sample-

and-hold amplifier (SHA) not only enables this sustained

dynamic performance, but also lowers the converter's input

capacitance and reduces the number of external components

required.

Analog signals at the “I” and “Q” inputs that are within the

voltage range set by VREF and the GAIN pin are digitized to

ten bits at up to 30 MSPS. VREF has a range of 0.8V to 1.5V

providing a differential peak-to-peak input range of 0.8 VP-P

to 1.5 VP-P with the GAIN pin at a logic low, or an input range

of 1.6 VP-P to 3.0 VP-P with the GAIN pin at a logic high. Dif-

ferential input voltages less than −VREF/2 with the GAIN pin

low, or less than −VREF with the GAIN pin high will cause the

output word to indicate a negative full scale. Differential input

voltages greater than VREF/2 with the GAIN pin low, or greater

than VREF with the GAIN pin high, will cause the output word

to indicate a positive full scale.

Both “I” and “Q” channels are sampled simultaneously on the

falling edge of the clock input, while the timing of the data

output depends upon the mode of operation.

In the parallel mode, the “I” and “Q” output busses contain the

conversion result for their respective inputs. The “I” and “Q”

channel data are present and valid at the data output pins

tOD after the rising edge of the input clock. In the multiplexed

mode, “I” channel data is available at the digital outputs tOD

after the rise of the clock edge, while the “Q” channel data is

available at the digital outputs tOD after the fall of the clock.

However, a delayed I/Q output signal should be used to latch

the output for best, most consistent results.

Data latency in the parallel mode is 2.5 clock cycles. In the

multiplexed mode data latency is 2.5 clock cycles for the “I”

channel and 3.0 clock cycles for the “Q” channel. The AD-

C10D020 will convert as long as the clock signal is present

and the PD and STBY pins are low.

Throughout this discussion, VCM refers to the Common Mode

input voltage of the ADC10D020 while VCMO refers to its Com-

mon Mode output voltage.

www.national.com 22

ADC10D020

Applications Information

1.0 THE ANALOG SIGNAL INPUTS

Each of the analog inputs of the ADC10D020 consists of a

switch (transmission gate) followed by a switched capacitor

amplifier. The capacitance seen at each input pin changes

with the clock level, appearing as about 3 pF when the clock

is low, and about 6 pF when the clock is high. A switched

capacitance is harder to drive than is a larger, fixed capaci-

tance.

The CLC409 and the CLC428 dual op amp have been found

to be a good amplifiers to drive the ADC10D020 because of

their wide bandwidth and low distortion. They also have good

Differential Gain and Differential Phase performance.

Care should be taken to avoid driving the inputs beyond the

supply rails, even momentarily, as during power-up.

The ADC10D020 is designed for differential input signals for

best performance. With a 1.0V reference and the GAIN pin at

a logic low, differential input signals up to 1.0 VP-P are digi-

tized. See Figure 2. For differential signals, the input common

mode is expected to be about 1.5V, but the inputs are not

sensitive to the common-mode voltage and can be anywhere

within the supply rails (ground to VA) with little or no perfor-

mance degradation, as long as the signal swing at the indi-

vidual input pins is no more than 300 mV beyond the supply

rails. For single ended drive, operate the ADC10D020 with

the GAIN pin at a logic low, connect one pin of the input pair

to 1.5V (VCM) and drive the other pin of the input pair with 1.0

VP-P centered around 1.5V.

Because of the larger signal swing at one input for single-

ended operation, distortion performance will not be as good

as with a differential input signal. Alternatively, single-ended

to differential conversion with a transformer provides a quick.

easy solution for those applications not requiring response to

dc and low frequencies. See Figure 3. The 36Ω resistors and

110 pF capacitor values are chosen to provide a cutoff fre-

quency near the clock frequency to compensate for the ef-

fects of input sampling. A lower time constant should be used

for undersampling applications.

20025569

FIGURE 2. The ADC10D020 is designed for use with

differential signals of 1.0 VP-P with a common mode

voltage of 1.5V. The signal swing should not cause any

pin to experience a swing more than 300 mV beyond the

supply rails.

2.0 REFERENCE INPUTS

The VRP and VRN pins should each be bypassed with a 5 µF

(or larger) tantalum or electrolytic capacitor and a 0.1 µF ce-

ramic capacitor. Use these pins only for bypassing. DO NOT

connect anything else to these pins.

Figure 4 shows a simple reference biasing scheme with min-

imal components. While this circuit will suffice for many ap-

plications, the value of the reference voltage will depend upon

the supply voltage.

The circuit of Figure 5 is an improvement over the circuit of

Figure 4 because the reference voltage is independent of

supply voltage. This reduces problems of reference voltage

variability. The reference voltage at the VREF pin should be

bypassed to AGND with a 5 µF (or larger) tantalum or elec-

trolytic capacitor and a 0.1 µF ceramic capacitor.

The circuit of Figure 6 may be used if it is desired to obtain a

precise reference voltage not available with a fixed reference

source. The 240Ω and 1k resistors can be replaced with a

potentiometer, if desired.

20025570

FIGURE 3. Use of an input transformer for single-ended

to differential conversion can simplify circuit design for

single-ended signals.

23 www.national.com

ADC10D020

20025571

FIGURE 4. Simple Reference Biasing

www.national.com 24

ADC10D020

20025572

FIGURE 5. Improved Low Component Count Reference Biasing

The VCMO output can be used as the ADC reference source

as long as care is taken to prevent excessive loading of this

pin. However, the VCMO output was not designed to be a pre-

cision reference and has more variability than does a preci-

sion reference. Refer to VCMO, Common Mode Voltage

Output, in the Electrical Characteristics table. Since the ref-

erence input of the ADC10D020 is buffered, there is virtually

no loading on the VCMO output by the VREF pin. While the AD-

C10D020 will work with a 1.5V reference voltage, it is fully

specified for a 1.0V reference. To use the VCMO for a refer-

ence voltage at 1.0V, the 1.5V VCMO output needs to be

divided down. The divider resistor values need to be carefully

chosen to prevent excessive VCMO loading. See Figure 7.

While the average temperature coefficient of VCMO is 20 ppm/

°C, that temperature coefficient can be broken down to a typ-

ical 50 ppm/°C between −40°C and +25°C and a typical −12

ppm/°C between +25°C and +85°C.

25 www.national.com

ADC10D020

20025573

FIGURE 6. Setting An Accurate Reference Voltage

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ADC10D020

20025574

FIGURE 7. The VCMO output pin may be used as an internal reference source if its output is divided down and not loaded

excessively.

2.1 REFERENCE VOLTAGE

The reference voltage should be within the range specified in

the Operating Ratings table (0.8V to 1.5V). A reference volt-

age that is too low could result in a noise performance that is

less than desired because the quantization level falls below

other noise sources. On the other hand, a reference voltage

that is too high means that an input signal that produces a full

scale output uses such a large input range that the input stage

is less linear, resulting in a degradation of distortion perfor-

mance. Also, for large reference voltages, the internal ladder

buffer runs out of head-room, leading to a reduction of gain in

that buffer and causing gain error degradation.

The Reference bypass pins VRP and VRN are output compen-

sated and should each be bypassed with a parallel combina-

tion of a 5 µF (minimum) and 0.1 µF capacitors.

As mentioned in the previous section, the VCMO output can be

used as the ADC reference.

2.2 VCMO OUTPUT

The VCMO output pin is intended to provide a common mode

bias for the differential input pins of the ADC10D020. It can

also be used as a voltage reference source. Care should be

taken, however, to avoid loading this pin with more than 1 mA.

A load greater than this could result in degraded long term

and temperature stability of this voltage. The VCMO pin is out-

put compensated and should be bypassed with a

2 µF/0.1 µF combination, minimum. See 2.0 REFERENCE

INPUTS for more information on using the VCMO output as a

reference source.

3.0 DIGITAL INPUT PINS

The seven digital input pins are used to control the function

of the ADC10D020.

3.1 CLOCK (CLK) INPUT

The clock (CLK) input is common to both A/D converters. This

pin is CMOS/LVTTL compatible with a threshold of about

VA/2. Although the ADC10D020 is tested and its performance

is guaranteed with a 20 MHz clock, it typically will function well

with low-jitter clock frequencies from 1 MHz to 30 MHz. The

clock source should be series terminated to match the source

impedance with the characteristic impedance, ZO, of the clock

27 www.national.com

ADC10D020

line and the ADC clock pin should be AC terminated, near the

clock input, with a series RC to ground. The resistor value

should equal the characteristic impedance, ZO, of the clock

line and the capacitor should have a value such that C × ZO

≥ 4 × tPD, where tPD is the time of propagation of the clock

signal from its source to the ADC clock pin. The typical prop-

agation rate on a board of FR4 material is about 150 ps/inch.

The rise and fall times of the clock supplied to the ADC clock

pin should be no more than 4 ns. The analog inputs I = (I+) –

(I−) and Q = (Q+) – (Q−) are simultaneously sampled on the

falling edge of this input to ensure the best possible aperture

delay match between the two channels.

3.2 OUTPUT BUS SELECT (OS) PIN

The Output Bus Select (OS) pin determines whether the AD-

C10D020 is in the parallel or multiplexed mode of operation.

A logic high at this pin puts the device into the parallel mode

of operation where “I” and “Q” data appear at their respective

output buses. A logic low at this pin puts the device into the

multiplexed mode of operation where the “I” and “Q” data are

multiplexed onto the “I” output bus and the “Q” output lines all

remain at a logic low.

3.3 OFFSET CORRECT (OC) PIN

The Offset Correct (OC) pin is used to initiate an offset cor-

rection sequence. This procedure should be done after power

up and need not be performed again unless power to the AD-

C10D020 is interrupted. An independent offset correction

sequence for each converter is initiated when there is a low-

to-high transition at the OC pin. This sequence takes 34 clock

cycles to complete, during which time 32 conversions are tak-

en and averaged. The result is subtracted from subsequent

conversions. Because the offset correction is performed dig-

itally at the output of the ADC, the output range of the ADC is

reduced by the offset amount.

Upon power up, the offset correction coefficients are set to

zero. The Electrical Table indicates the Offset Error with and

without performing an offset correction.

Each input pair should have a 0V differential voltage value

during this entire 34 clock period, but the “I” and “Q” input

common mode voltages do not have to be equal to each other.

Because of the uncertainty as to exactly when the correction

sequence starts, it is best to allow 35 clock periods for this

sequence.

3.4 OUTPUT FORMAT (OF) PIN

The Output Format (OF) pin provides a choice of offset binary

or 2's complement output formatting. With this pin at a logic

low, the output format is offset binary. With this pin at a logic

high, the output format is 2's complement.

3.5 STANDBY (STBY) PIN

The Standby (STBY) pin may be used to put the ADC10D020

into a low power mode where it consumes just 27 mW and

can quickly be brought to full operation. In this mode, most of

the ADC10D020 is powered down, but the bias and reference

circuitry remained powered up to allow for a faster recovery

from a low power standby condition. The device operates

normally with a logic low on this and the PD pins.

While in the Standby mode the data outputs contain the re-

sults of the last conversion before going into this Mode.

3.6 POWER DOWN (PD) PIN

The Power Down (PD) pin puts the device into a low-power

“sleep” state where it consumes less than 1 mW when the PD

pin is at a logic high. Power consumption is reduced more

when the PD pin is high than when the STBY pin is high, but

recovery to full operation is much quicker from the standby

state than it is from the power down state. When the STBY

and PD pins are both high, the ADC10D020 is in the power

down mode.

While in the Power Down mode the data outputs contain the

results of the last conversion before going into this mode.

3.7 GAIN PIN

The GAIN pin sets the internal signal gain of the “I” and “Q”

inputs. With this pin at a logic low, the full scale differential

peak-to-peak input signal is equal to VREF. With the GAIN pin

at a logic high, the full scale differential peak-to-peak input

signal is equal to 2 times VREF.

4.0 INPUT/OUTPUT RELATIONSHIP ALTERNATIVES

The GAIN pin of the ADC10D020 offers input range selection,

while the OF pin offers a choice of offset binary or 2's com-

plement output formatting.

The relationship between the GAIN, OF, analog inputs and

the output code are as defined in Table 1. Keep in mind that

the input signals must not exceed the power supply rails.

TABLE 1. ADC10D020 Input/Output Relationships

GAIN OF I+ / Q+ I− / Q− Output Code

0 0 VCM + 0.25*VREF VCM − 0.25*VREF 11 1111 1111

0 0 VCM VCM 10 0000 0000

0 0 VCM − 0.25*VREF VCM + 0.25*VREF 00 0000 0000

0 1 VCM + 0.25*VREF VCM − 0.25*VREF 01 1111 1111

0 1 VCM VCM 00 0000 0000

0 1 VCM − 0.25*VREF VCM + 0.25*VREF 10 0000 0000

1 0 VCM + 0.5*VREF VCM − 0.5*VREF 11 1111 1111

1 0 VCM VCM 10 0000 0000

1 0 VCM − 0.5*VREF VCM + 0.5*VREF 00 0000 0000

1 1 VCM + 0.5*VREF VCM − 0.5*VREF 01 1111 1111

1 1 VCM VCM 00 0000 0000

1 1 VCM − 0.5*VREF VCM + 0.5*VREF 10 0000 0000

www.national.com 28

ADC10D020

5.0 POWER SUPPLY CONSIDERATIONS

A/D converters draw sufficient transient current to corrupt

their own power supplies if not adequately bypassed. A

10 µF to 50 µF tantalum or aluminum electrolytic capacitor

should be placed within half an inch (1.2 centimeters) of the

A/D power pins, with a 0.1 µF ceramic chip capacitor placed

as close as possible to each of the converter's power supply

pins. Leadless chip capacitors are preferred because they

have low lead inductance.

While a single voltage source should be used for the analog

and digital supplies of the ADC10D020, these supply pins

should be well isolated from each other to prevent any digital

noise from being coupled to the analog power pins. A choke

is recommended between the VA and VD supply lines. VDR

should have a separate supply from VA and VD to avoid noise

coupling.

The VDR pins are completely isolated from the other supply

pins. Because of this isolation, a separate supply can be used

for these pins. This VDR supply can be significantly lower than

the three volts used for the other supplies, easing the interface

to lower voltage digital systems. Using a lower voltage for this

supply can also reduce the power consumption and noise as-

sociated with the output drivers.

The converter digital supply should not be the supply that is

used for other digital circuitry on the board. It should be the

same supply used for the ADC10D020 analog supply.

As is the case with all high speed converters, the ADC10D020

should be assumed to have little high frequency power supply

rejection. A clean analog power source should be used.

No pin should ever have a voltage on it that is more than

300 mV in excess of the supply voltages or below ground, not

even on a transient basis. This can be a problem upon appli-

cation of power to a circuit and upon turn off of the power

source. Be sure that the supplies to circuits driving the CLK,

or any other digital or analog inputs do not come up any faster

than does the voltage at the ADC10D020 power pins.

6.0 LAYOUT AND GROUNDING

Proper routing of all signals and proper ground techniques are

essential to ensure accurate conversion. Separate analog

and digital ground planes may be used if adequate care is

taken with signal routing, but may result in EMI/RFI. A single

ground plane with proper component placement will yield

good results while minimizing EMI/RFI.

Analog and digital ground current paths should not coincide

with each other as the common impedance will cause digital

noise to be added to analog signals. Accordingly, traces car-

rying digital signals should be kept as far away from traces

carrying analog signals as is possible. Power should be rout-

ed with traces rather than the use of a power plane. The

analog and digital power traces should be kept well away from

each other. All power to the ADC10D020, except VDR, should

be considered analog. The DR GND pin should be considered

a digital ground and not be connected to the ground plane in

close proximity with the other ground pins of the ADC10D020.

Each bypass capacitor should be located as close to the ap-

propriate converter pin as possible and connected to the pin

and the appropriate ground plane with short traces. The ana-

log input should be isolated from noisy signal traces to avoid

coupling of spurious signals into the input. Any external com-

ponent (e.g., a filter capacitor) connected between the

converter's input and ground should be connected to a very

clean point in the ground return.

The clock line should be properly terminated, as discussed in

Section 3.1, and be as short as possible.

Figure 8 gives an example of a suitable layout and bypass

capacitor placement. All analog circuitry (input amplifiers, fil-

ters, reference components, etc.) and interconnections

should be placed in an area reserved for analog circuitry. All

digital circuitry and I/O lines should be placed in an area re-

served for digital circuitry. Violating these rules can result in

digital noise getting into the analog circuitry, which will de-

grade accuracy and dynamic performance (THD, SNR,

SINAD).

20025575

FIGURE 8. An Acceptable Layout Pattern

29 www.national.com

ADC10D020

7.0 DYNAMIC PERFORMANCE

The ADC10D020 is a.c. tested and its dynamic performance

is guaranteed. To meet the published specifications, the clock

source driving the CLK input must be free of jitter. For best

dynamic performance, isolating the ADC clock from any dig-

ital circuitry should be done with adequate buffers, as with a

clock tree. See Figure 9.

20025576

FIGURE 9. Isolating the ADC Clock from Digital Circuitry

8.0 COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power

supply rails. For proper operation, no input should go more

than 300 mV beyond the supply pins. Exceeding these limits

on even a transient basis can cause faulty or erratic operation.

It is not uncommon for high speed digital circuits (e.g., 74F

and 74AC devices) to exhibit overshoot and undershoot that

goes a few hundred millivolts beyond the supply rails. A re-

sistor of 50Ω to 100Ω in series with the offending digital input,

close to the source, will usually eliminate the problem.

Care should be taken not to overdrive the inputs of the AD-

C10D020 (or any device) with a device that is powered from

supplies outside the range of the ADC10D020 supply. Such

practice may lead to conversion inaccuracies and even to de-

vice damage.

Attempting to drive a high capacitance digital data bus.

The more capacitance the output drivers have to charge for

each conversion, the more instantaneous digital current is re-

quired from VDR and DR GND. These large charging current

spikes can couple into the analog section, degrading dynamic

performance. Adequate bypassing and attention to board lay-

out will reduce this problem. Buffering the digital data outputs

(with a 74ACTQ841, for example) may be necessary if the

data bus to be driven is heavily loaded. Dynamic performance

can also be improved by adding series resistors of 47Ω to

56Ω at each digital output, close to the ADC output pins.

Using a clock source with excessive jitter. This will cause

the sampling interval to vary, causing excessive output noise

and a reduction in SNR and SINAD performance. The use of

simple gates with RC timing as a clock source is generally

inadequate.

Using the same voltage source for VD and external digital

logic. As mentioned in Section 5.0, VD should use the same

power source used by VA and other analog components, but

should be decoupled from VA.

www.national.com 30

ADC10D020

Physical Dimensions inches (millimeters) unless otherwise noted

NOTES UNLESS OTHERWISE SPECIFIED

1. STANDARD LEAD FINISH

7.62 MICROMETERS MINIMUM SOLDER PLATING (85/15)

THICKNESS ON ALLOY 42/COPPER.

2. DIMENSION DOES NOT INCLUDE MOLD PROTRUSION.

MAXIMUM ALLOWABLE MOLD PROTRUSION 0.15 mm PER SIDE.

3. REFERENCE JEDEC REGISTRATION MS-026, VARIATION ABC,

DATED FEBRUARY 1999.

48-Lead TQFP Package

Ordering Number ADC10D020CIVS

NS Package Number VBA48A

31 www.national.com

ADC10D020

Notes

ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter

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to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

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