DS90CR215MTDX - National Semiconductor

DS90CR215,DS90CR216

DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel

Link - 66 MHz

Literature Number: SNLS129C

DS90CR215/DS90CR216

June 5, 2009

+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link -

66 MHz

General Description

The DS90CR215 transmitter converts 21 bits of CMOS/TTL

data into three LVDS (Low Voltage Differential Signaling) data

streams. A phase-locked transmit clock is transmitted in par-

allel with the data streams over a fourth LVDS link. Every

cycle of the transmit clock 21 bits of input data are sampled

and transmitted. The DS90CR216 receiver converts the

LVDS data streams back into 21 bits of CMOS/TTL data. At

a transmit clock frequency of 66 MHz, 21 bits of TTL data are

transmitted at a rate of 462 Mbps per LVDS data channel.

Using a 66 MHz clock, the data throughput is 1.386 Gbit/s

(173 Mbytes/s).

The multiplexing of the data lines provides a substantial cable

reduction. Long distance parallel single-ended buses typically

require a ground wire per active signal (and have very limited

noise rejection capability). Thus, for a 21-bit wide data and

one clock, up to 44 conductors are required. With the Channel

Link chipset as few as 9 conductors (3 data pairs, 1 clock pair

and a minimum of one ground) are needed. This provides a

80% reduction in required cable width, which provides a sys-

tem cost savings, reduces connector physical size and cost,

and reduces shielding requirements due to the cables' smaller

form factor.

The 21 CMOS/TTL inputs can support a variety of signal

combinations. For example, five 4-bit nibbles plus 1 control,

or two 9-bit (byte + parity) and 3 control.

Features

■Single +3.3V supply

■Chipset (Tx + Rx) power consumption <250 mW (typ)

■Power-down mode (<0.5 mW total)

■Up to 173 Megabytes/sec bandwidth

■Up to 1.386 Gbps data throughput

■Narrow bus reduces cable size

■290 mV swing LVDS devices for low EMI

■+1V common mode range (around +1.2V)

■PLL requires no external components

■Low profile 48-lead TSSOP package

■Rising edge data strobe

■Compatible with TIA/EIA-644 LVDS standard

■ESD Rating > 7 kV

■Operating Temperature: −40°C to +85°C

Block Diagrams

DS90CR215

1290901

Order Number DS90CR215MTD

See NS Package Number MTD48

DS90CR216

1290927

Order Number DS90CR216MTD

See NS Package Number MTD48

See DS90CR216AMTD with Improved AC Specifications

Recommended Alternative Device

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz

Connection Diagrams

1290921

DS90CR215

1290922

DS90CR216

Typical Application

1290923

www.national.com 2

DS90CR215/DS90CR216

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (VCC)−0.3V to +4V

CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V)

CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V)

LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V)

LVDS Driver Output Voltage −0.3V to (VCC + 0.3V)

LVDS Output Short

Circuit Duration Continuous

Junction Temperature +150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature

(Soldering, 4 sec.) +260°C

Maximum Package Power Dissipation @ +25°C

MTD48 (TSSOP) Package:

DS90CR215 1.98 W

DS90CR216 1.89 W

Package Derating

DS90CR215 16 mW/°C above +25°C

DS90CR216 15 mW/°C above +25°C

ESD Rating

(HBM, 1.5 kΩ, 100 pF) > 7 kV

Recommended Operating

Conditions

Min No

Max Units

Supply Voltage (VCC) 3.0 3.3 3.6 V

Operating Free Air

Temperature (TA) −40 +25 +85 °C

Receiver Input Range 0 2.4 V

Supply Noise Voltage (VCC) 100 mVPP

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

VIH High Level Input Voltage 2.0 VCC V

VIL Low Level Input Voltage GND 0.8 V

VOH High Level Output Voltage I OH = −0.4 mA 2.7 3.3 V

VOL Low Level Output Voltage I OL = 2 mA 0.06 0.3 V

VCL Input Clamp Voltage I CL = −18 mA −0.79 −1.5 V

IIN Input Current V IN = VCC, GND, ±5.1 ±10 μA

2.5V or 0.4V

IOS Output Short Circuit Current V OUT = 0V -60 −120 mA

LVDS DRIVER DC SPECIFICATIONS

VOD Differential Output Voltage R L = 100Ω 250 290 450 mV

ΔVOD Change in V OD between Complimentary

Output States

35 mV

VOS Offset Voltage (Note 4) 1.125 1.25 1.375 V

ΔVOS Change in V OSbetween Complimentary Output

States

35 mV

IOS Output Short Circuit Current V OUT = 0V, −3.5 −5 mA

R L = 100Ω

IOZ Output TRI-STATE® Current PWR DWN = 0V, ±1 ±10 μA

V OUT = 0V or VCC

LVDS RECEIVER DC SPECIFICATIONS

VTH Differential Input High Threshold V CM = +1.2V +100 mV

VTL Differential Input Low Threshold −100 mV

I IN Input Current V IN = +2.4V, VCC = 3.6V ±10 μA

V IN = 0V, VCC = 3.6V ±10 μA

TRANSMITTER SUPPLY CURRENT

3 www.national.com

DS90CR215/DS90CR216

Symbol Parameter Conditions Min Typ Max Units

ICCTW Transmitter Supply Current Worst Case (with

Loads)

RL = 100Ω,

CL = 5 pF,

Worst Case Pattern

(Figures 1, 2)

, TA = −10°C to +70°C

f = 32.5 MHz 31 45 mA

f = 37.5 MHz 32 50 mA

f = 66 MHz 37 55 mA

RL = 100Ω,

CL = 5 pF,

Worst Case Pattern

(Figures 1, 2)

, TA = −40°C to +85°C

f = 40 MHz 38 51 mA

f = 66 MHz 42 55 mA

ICCTZ Transmitter Supply Current Power Down PWR DWN = Low

Driver Outputs in TRI-STATE

under Powerdown Mode

10 55 μA

RECEIVER SUPPLY CURRENT

ICCRW Receiver Supply Current Worst Case CL = 8 pF,

Worst Case Pattern

(Figures 1, 3)

, TA = −10°C to +70°C

f = 32.5 MHz 49 65 mA

f = 37.5 MHz 53 70 mA

f = 66 MHz 78 105 mA

CL = 8 pF,

Worst Case Pattern

(Figures 1, 3)

, TA = −40°C to +85°C

f = 40 MHz 55 82 mA

f = 66 MHz 78 105 mA

ICCRZ Receiver Supply Current Power Down PWR DWN = Low

Receiver Outputs Stay Low during

Powerdown Mode

10 55 μA

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for VCC = 3.3V and TA = +25°C.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise

specified (except VOD and ΔVOD).

Note 4: VOS previously referred as VCM.

Transmitter Switching Characteristics

Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

LLHT LVDS Low-to-High Transition Time (Figure 2) 0.5 1.5 ns

LHLT LVDS High-to-Low Transition Time (Figure 2) 0.5 1.5 ns

TCIT TxCLK IN Transition Time (Figure 4) 5 ns

TCCS TxOUT Channel-to-Channel Skew (Figure 5) 250 ps

TPPos0 Transmitter Output Pulse Position for Bit0

(Note 7) (Figure 16)

f = 40 MHz −0.4 0 0.4 ns

TPPos1 Transmitter Output Pulse Position for Bit1 3.1 3.3 4.0 ns

TPPos2 Transmitter Output Pulse Position for Bit2 6.5 6.8 7.6 ns

TPPos3 Transmitter Output Pulse Position for Bit3 10.2 10.4 11.0 ns

TPPos4 Transmitter Output Pulse Position for Bit4 13.7 13.9 14.6 ns

TPPos5 Transmitter Output Pulse Position for Bit5 17.3 17.6 18.2 ns

TPPos6 Transmitter Output Pulse Position for Bit6 21.0 21.2 21.8 ns

TPPos0 Transmitter Output Pulse Position for Bit0

(Note 6) (Figure 16)

f = 66 MHz −0.4 0 0.3 ns

TPPos1 Transmitter Output Pulse Position for Bit1 1.8 2.2 2.5 ns

TPPos2 Transmitter Output Pulse Position for Bit2 4.0 4.4 4.7 ns

TPPos3 Transmitter Output Pulse Position for Bit3 6.2 6.6 6.9 ns

TPPos4 Transmitter Output Pulse Position for Bit4 8.4 8.8 9.1 ns

www.national.com 4

DS90CR215/DS90CR216

Symbol Parameter Min Typ Max Units

TPPos5 Transmitter Output Pulse Position for Bit5 10.6 11.0 11.3 ns

TPPos6 Transmitter Output Pulse Position for Bit6 12.8 13.2 13.5 ns

TCIP TxCLK IN Period (Figure 6) 15 T 50 ns

TCIH TxCLK IN High Time (Figure 6) 0.35T 0.5T 0.65T ns

TCIL TxCLK IN Low Time (Figure 6) 0.35T 0.5T 0.65T ns

TSTC TxIN Setup to TxCLK IN (Figure 6) 2.5 ns

THTC TxIN Hold to TxCLK IN (Figure 6) 0 ns

TCCD TxCLK IN to TxCLK OUT Delay @ 25°C,VCC=3.3V (Figure 8) 3 3.7 5.5 ns

TPLLS Transmitter Phase Lock Loop Set (Figure 10) 10 ms

TPDD Transmitter Powerdown Delay (Figure 14) 100 ns

Receiver Switching Characteristics

Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

CLHT CMOS/TTL Low-to-High Transition Time (Figure 3) 2.2 5.0 ns

CHLT CMOS/TTL High-to-Low Transition Time (Figure 3) 2.2 5.0 ns

RSPos0 Receiver Input Strobe Position for Bit 0 (Note 7)(Figure 17) f = 40 MHz 1.0 1.4 2.15 ns

RSPos1 Receiver Input Strobe Position for Bit 1 4.5 5.0 5.8 ns

RSPos2 Receiver Input Strobe Position for Bit 2 8.1 8.5 9.15 ns

RSPos3 Receiver Input Strobe Position for Bit 3 11.6 11.9 12.6 ns

RSPos4 Receiver Input Strobe Position for Bit 4 15.1 15.6 16.3 ns

RSPos5 Receiver Input Strobe Position for Bit 5 18.8 19.2 19.9 ns

RSPos6 Receiver Input Strobe Position for Bit 6 22.5 22.9 23.6 ns

RSPos0 Receiver Input Strobe Position for Bit 0 (Note 6)(Figure 17) f = 66 MHz 0.7 1.1 1.4 ns

RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns

RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns

RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns

RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns

RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns

RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns

RSKM RxIN Skew Margin (Note 5) (Figure 18) f = 40 MHz 490 ps

f = 66 MHz 400 ps

RCOP RxCLK OUT Period (Figure 7) 15 T 50 ns

RCOH RxCLK OUT High Time (Figure 7) f = 40 MHz 6.0 10.0 ns

f = 66 MHz 4.0 6.1 ns

RCOL RxCLK OUT Low Time (Figure 7) f = 40 MHz 10.0 13.0 ns

f = 66 MHz 6.0 7.8 ns

RSRC RxOUT Setup to RxCLK OUT (Figure 7) f = 40 MHz 6.5 14.0 ns

f = 66 MHz 2.5 8.0 ns

RHRC RxOUT Hold to RxCLK OUT (Figure 7) f = 40 MHz 6.0 8.0 ns

f = 66 MHz 2.5 4.0 ns

RCCD RxCLK IN to RxCLK OUT Delay (Figure 9) f = 40 MHz 4.0 6.7 8.0 ns

f = 66 MHz 5.0 6.6 9.0 ns

RPLLS Receiver Phase Lock Loop Set (Figure 11) 10 ms

RPDD Receiver Powerdown Delay (Figure 15) 1 μs

Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter pulse positions

(min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference

(both dependent on type/length of cable), and clock jitter less than 250 ps.

Note 6: The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.

Note 7: The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.

5 www.national.com

DS90CR215/DS90CR216

AC Timing Diagrams

1290902

FIGURE 1. “Worst Case” Test Pattern

1290903

1290904

FIGURE 2. DS90CR215 (Transmitter) LVDS Output Load and Transition Times

1290905

1290906

FIGURE 3. DS90CR216 (Receiver) CMOS/TTL Output Load and Transition Times

1290907

FIGURE 4. D590CR215 (Transmitter) Input Clock Transition Time

www.national.com 6

DS90CR215/DS90CR216

1290908

Note 8: Measurements at VDIFF = 0V

Note 9: TCCS measured between earliest and latest LVDS edges

Note 10: TxCLK Differential Low→High Edge

FIGURE 5. D590CR215 (Transmitter) Channel-to-Channel Skew

1290909

FIGURE 6. D590CR215 (Transmitter) Setup/Hold and High/Low Times

1290910

FIGURE 7. D590CR216 (Receiver) Setup/Hold and High/Low Times

7 www.national.com

DS90CR215/DS90CR216

1290929

FIGURE 8. DS90CR215 (Transmitter) Clock In to Clock Out Delay

1290912

FIGURE 9. D590CR216 (Receiver) Clock In to Clock Out Delay

1290913

FIGURE 10. DS90CR215 (Transmitter) Phase Lock Loop Set Time

www.national.com 8

DS90CR215/DS90CR216

1290914

FIGURE 11. DS9OCR216 (Receiver) Phase Lock Loop Set Time

1290915

FIGURE 12. Seven Bits of LVDS in Once Clock Cycle

1290916

FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR215)

9 www.national.com

DS90CR215/DS90CR216

1290917

FIGURE 14. Transmitter Powerdown Delay

1290918

FIGURE 15. Receiver Powerdown Delay

1290919

FIGURE 16. Transmitter LVDS Output Pulse Position Measurement

www.national.com 10

DS90CR215/DS90CR216

1290928

FIGURE 17. Receiver LVDS Input Strobe Position

11 www.national.com

DS90CR215/DS90CR216

1290920

C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max

Tppos—Transmitter output pulse position (min and max)

RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note Cycle-to-cycle jitter is less than 250 ps ) + ISI (Inter-symbol interference) (Note

ISI is dependent on interconnect length; may be zero )

Cable Skew—typicaIIy 10 ps–40 ps per foot, media dependent

Note 11: Cycle-to-cycle jitter is less than 250 ps

Note 12: ISI is dependent on interconnect length; may be zero

FIGURE 18. Receiver LVDS Input Skew Margin

Applications Information

The DS90CR215 and DS90CR216 are backward compatible

with the existing 5V Channel Link transmitter/receiver pair

(DS90CR213, DS90CR214). To upgrade from a 5V to a 3.3V

system the following must be addressed:

1. Change 5V power supply to 3.3V. Provide this supply to

the VCC, LVDS VCC and PLL V CC.

2. Transmitter input and control inputs except 3.3V TTL/

CMOS levels. They are not 5V tolerant.

3. The receiver powerdown feature when enabled wilI lock

receiver output to a logic low. However, the 5V/66 MHz

receiver maintain the outputs in the previous state when

powerdown occurred.

DS90CR215 Pin Descriptions — Channel Link Transmitter

Pin Name I/O No. Description

TxIN I 21 TTL level input.

TxOUT+ O 3 Positive LVDS differential data output.

TxOUT− O 3 Negative LVDS differential data output.

TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN.

TxCLK OUT+ O 1 Positive LVDS differential clock output.

TxCLK OUT− O 1 Negative LVDS differential clock output.

PWR DWN I 1 TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at power down.

V CC I 4 Power supply pins for TTL inputs.

GND I 5 Ground pins for TTL inputs.

PLL V CC I 1 Power supply pins for PLL.

PLL GND I 2 Ground pins for PLL.

LVDS V CC I 1 Power supply pin for LVDS outputs.

LVDS GND I 3 Ground pins for LVDS outputs.

DS90CR216 Pin Descriptions — Channel Link Receiver

Pin Name I/O No. Description

RxIN+ I 3 Positive LVDS differential data inputs.

RxIN− I 3 Negative LVDS differential data inputs.

RxOUT O 21 TTL level data outputs.

RxCLK IN+ I 1 Positive LVDS differential clock input.

RxCLK IN− I 1 Negative LVDS differential clock input.

RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.

PWR DWN I 1 TTL level input. When asserted (low input) the receiver outputs are low.

www.national.com 12

DS90CR215/DS90CR216

Pin Name I/O No. Description

V CC I 4 Power supply pins for TTL outputs.

GND I 5 Ground pins for TTL outputs.

PLL V CC I 1 Power supply for PLL.

PLL GND 1 2 Ground pin for PLL.

LVDS V CC I 1 Power supply pin for LVDS inputs.

LVDS GND I 3 Ground pins for LVDS inputs.

The Channel Link devices are intended to be used in a wide

variety of data transmission applications. Depending upon the

application the interconnecting media may vary. For example,

for lower data rate (clock rate) and shorter cable lengths (<

2m), the media electrical performance is less critical. For

higher speed/long distance applications the media's perfor-

mance becomes more critical. Certain cable constructions

provide tighter skew (matched electrical length between the

conductors and pairs). Twin-coax for example, has been

demonstrated at distances as great as 5 meters and with the

maximum data transfer of 1.38 Gbit/s. Additional applications

information can be found in the following National Interface

Application Notes:

AN = #### Topic

AN-1041 Introduction to Channel Link

AN-1035 PCB Design Guidelines for LVDS and

Link Devices

AN-806 Transmission Line Theory

AN-905 Transmission Line Calculations and

Differential Impedance

AN-916 Cable Information

CABLES

A cable interface between the transmitter and receiver needs

to support the differential LVDS pairs. The 21-bit CHANNEL

LINK chipset (DS90CR215/216) requires four pairs of signal

wires and the 28-bit CHANNEL LINK chipset

(DS90CR285/286) requires five pairs of signal wires. The ide-

al cable/connector interface would have a constant 100Ω

differential impedance throughout the path. It is also recom-

mended that cable skew remain below 150 ps (@ 66 MHz

clock rate) to maintain a sufficient data sampling window at

the receiver.

In addition to the four or five cable pairs that carry data and

clock, it is recommended to provide at least one additional

conductor (or pair) which connects ground between the trans-

mitter and receiver. This low impedance ground provides a

common mode return path for the two devices. Some of the

more commonly used cable types for point-to-point applica-

tions include flat ribbon, flex, twisted pair and Twin-Coax. All

are available in a variety of configurations and options. Flat

ribbon cable, flex and twisted pair generally perform well in

short point-to-point applications while Twin-Coax is good for

short and long applications. When using ribbon cable, it is

recommended to place a ground line between each differen-

tial pair to act as a barrier to noise coupling between adjacent

pairs. For Twin-Coax cable applications, it is recommended

to utilize a shield on each cable pair. All extended point-to-

point applications should also employ an overall shield sur-

rounding all cable pairs regardless of the cable type. This

overall shield results in improved transmission parameters

such as faster attainable speeds, longer distances between

transmitter and receiver and reduced problems associated

with EMS or EMI.

The high-speed transport of LVDS signals has been demon-

strated on several types of cables with excellent results.

However, the best overall performance has been seen when

using Twin-Coax cable. Twin-Coax has very low cable skew

and EMI due to its construction and double shielding. All of

the design considerations discussed here and listed in the

supplemental application notes provide the subsystem com-

munications designer with many useful guidelines. It is rec-

ommended that the designer assess the tradeoffs of each

application thoroughly to arrive at a reliable and economical

cable solution.

BOARD LAYOUT

To obtain the maximum benefit from the noise and EMI re-

ductions of LVDS, attention should be paid to the layout of

differential lines. Lines of a differential pair should always be

adjacent to eliminate noise interference from other signals

and take full advantage of the noise canceling of the differ-

ential signals. The board designer should also try to maintain

equal length on signal traces for a given differential pair. As

with any high speed design, the impedance discontinuities

should be limited (reduce the numbers of vias and no 90 de-

gree angles on traces). Any discontinuities which do occur on

one signal line should be mirrored in the other line of the dif-

ferential pair. Care should be taken to ensure that the differ-

ential trace impedance match the differential impedance of

the selected physical media (this impedance should also

match the value of the termination resistor that is connected

across the differential pair at the receiver's input). Finally, the

location of the CHANNEL LINK TxOUT/RxIN pins should be

as close as possible to the board edge so as to eliminate ex-

cessive pcb runs. All of these considerations will limit reflec-

tions and crosstalk which adversely effect high frequency

performance and EMI.

UNUSED INPUTS

All unused inputs at the TxIN inputs of the transmitter must

be tied to ground. All unused outputs at the RxOUT outputs

of the receiver must then be left floating.

TERMINATION

Use of current mode drivers requires a terminating resistor

across the receiver inputs. The CHANNEL LINK chipset will

normally require a single 100Ω resistor between the true and

complement lines on each differential pair of the receiver in-

put. The actual value of the termination resistor should be

selected to match the differential mode characteristic

impedance (90Ω to 120Ω typical) of the cable. Figure 19

shows an example. No additional pull-up or pull-down resis-

tors are necessary as with some other differential technolo-

gies such as PECL. Surface mount resistors are recommend-

ed to avoid the additional inductance that accompanies

leaded resistors. These resistors should be placed as close

as possible to the receiver input pins to reduce stubs and ef-

fectively terminate the differential lines.

13 www.national.com

DS90CR215/DS90CR216

1290924

FIGURE 19. LVDS Serialized Link Termination

DECOUPLING CAPACITORS

Bypassing capacitors are needed to reduce the impact of

switching noise which could limit performance. For a conser-

vative approach three parallel-connected decoupling capaci-

tors (Multi-Layered Ceramic type in surface mount form

factor) between each VCC and the ground plane(s) are rec-

ommended. The three capacitor values are 0.1 μF, 0.01μF

and 0.001 μF. An example is shown in Figure 20. The de-

signer should employ wide traces for power and ground and

ensure each capacitor has its own via to the ground plane. If

board space is limiting the number of bypass capacitors, the

PLL VCC should receive the most filtering/bypassing. Next

would be the LVDS VCC pins and finally the logic VCC pins.

1290925

FIGURE 20. CHANNEL LINK

Decoupling Configuration

CLOCK JITTER

The CHANNEL LINK devices employ a PLL to generate and

recover the clock transmitted across the LVDS interface. The

width of each bit in the serialized LVDS data stream is one-

seventh the clock period. For example, a 66 MHz clock has a

period of 15 ns which results in a data bit width of 2.16 ns.

Differential skew (Δt within one differential pair), interconnect

skew (Δt of one differential pair to another) and clock jitter will

all reduce the available window for sampling the LVDS serial

data streams. Care must be taken to ensure that the clock

input to the transmitter be a clean low noise signal. Individual

bypassing of each VCC to ground will minimize the noise

passed on to the PLL, thus creating a low jitter LVDS clock.

These measures provide more margin for channel-to-channel

skew and interconnect skew as a part of the overall jitter/skew

budget.

COMMON MODE vs. DIFFERENTIAL MODE NOISE

MARGIN

The typical signal swing for LVDS is 300 mV centered at

+1.2V. The CHANNEL LINK receiver supports a 100 mV

threshold therefore providing approximately 200 mV of differ-

ential noise margin. Common mode protection is of more

importance to the system's operation due to the differential

data transmission. LVDS supports an input voltage range of

Ground to +2.4V. This allows for a ±1.0V shifting of the center

point due to ground potential differences and common mode

noise.

POWER SEQUENCING AND POWERDOWN MODE

Outputs of the CNANNEL LINK transmitter remain in TRI-

STATE until the power supply reaches 2V. Clock and data

outputs will begin to toggle 10 ms after VCC has reached 3V

and the Powerdown pin is above 1.5V. Either device may be

placed into a powerdown mode at any time by asserting the

Powerdown pin (active low). Total power dissipation for each

device will decrease to 5 μW (typical).

The CHANNEL LINK chipset is designed to protect itself from

accidental loss of power to either the transmitter or receiver.

If power to the transmit board is lost, the receiver clocks (input

and output) stop. The data outputs (RxOUT) retain the states

they were in when the clocks stopped. When the receiver

board loses power, the receiver inputs are shorted to V CC

through an internal diode. Current is limited (5 mA per input)

by the fixed current mode drivers, thus avoiding the potential

for latchup when powering the device.

www.national.com 14

DS90CR215/DS90CR216

1290926

FIGURE 21. Single-Ended and Differential Waveforms

15 www.national.com

DS90CR215/DS90CR216

Physical Dimensions inches (millimeters) unless otherwise noted

Order Number DS90CR215MTD or DS90CR216MTD

NS Package Number MTD48

www.national.com 16

DS90CR215/DS90CR216

Notes

17 www.national.com

DS90CR215/DS90CR216

Notes

DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products Design Support

Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench

Audio www.national.com/audio App Notes www.national.com/appnotes

Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns

Data Converters www.national.com/adc Samples www.national.com/samples

Interface www.national.com/interface Eval Boards www.national.com/evalboards

LVDS www.national.com/lvds Packaging www.national.com/packaging

Power Management www.national.com/power Green Compliance www.national.com/quality/green

Switching Regulators www.national.com/switchers Distributors www.national.com/contacts

LDOs www.national.com/ldo Quality and Reliability www.national.com/quality

LED Lighting www.national.com/led Feedback/Support www.national.com/feedback

Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy

PowerWise® Solutions www.national.com/powerwise Solutions www.national.com/solutions

Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero

Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic

Wireless (PLL/VCO) www.national.com/wireless PowerWise® Design

University

www.national.com/training

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY

OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,

IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR

APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND

APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE

NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE

AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR

PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY

RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other

brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com

National Semiconductor

Americas Technical

Support Center

Email: support@nsc.com

Tel: 1-800-272-9959

National Semiconductor Europe

Technical Support Center

Email: europe.support@nsc.com

National Semiconductor Asia

Pacific Technical Support Center

Email: ap.support@nsc.com

National Semiconductor Japan

Technical Support Center

Email: jpn.feedback@nsc.com

www.national.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Communications and Telecom www.ti.com/communications

Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers

Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps

DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy

DSP dsp.ti.com Industrial www.ti.com/industrial

Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical

Interface interface.ti.com Security www.ti.com/security

Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265