© 1999, 2001
MOS FIELD EFFECT TRANSISTOR
2SK3224
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DATA SHEET
Document No. D13797EJ2V0DS00 (2nd edition)
Date Published April 2001 NS CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark ★ shows major revised points.
DESCRIPTION
The 2SK3224 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
•Low on-state resistance
RDS(on)1 = 40 mΩ MAX. (VGS = 10 V, ID = 10 A)
RDS(on)2 = 60 mΩ MAX. (VGS = 4.0 V, ID = 10 A)
•Low Ciss : Ciss = 790 pF TYP.
•Built-in gate protection diode
•TO-251/TO-252 package
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V) VDSS 60 V
Gate to Source Voltage (VDS = 0 V) VGSS(AC) ±20 V
Gate to Source Voltage (VDS = 0 V) VGSS(DC) +20, −10 V
Drain Current (DC) (TC = 25°C) ID(DC) ±20 A
Drain Current (pulse) Note1 ID(pulse) ±70 A
Total Power Dissipation (TC = 25°C) PT25 W
Total Power Dissipation (TA = 25°C) PT1.0 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg –55 to +150 °C
Single Avalanche Current Note2 IAS 10 A
Single Avalanche Energy Note2 EAS 10 mJ
Notes 1. PW ≤ 10
µ
s, Duty cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 30 V, RG = 25 Ω, VGS = 20 → 0 V
ORDERING INFORMATION
PART NUMBER PACKAGE
2SK3224 TO-251
2SK3224-Z TO-252
(TO-251)
(TO-252)
★
★
★
Data Sheet D13797EJ2V0DS
2
2SK3224
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTE RISTI CS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Zero Gate Volt age Drai n Current IDSS VDS = 60 V, VGS = 0 V 10
µ
A
Gate Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±10
µ
A
Gate Cut-off Voltage VGS(off) VDS = 10 V, ID = 1 mA 1.0 1.5 2.0 V
Forward Transfer Adm i t tance | yfs |V
DS = 10 V, ID = 10 A 8.0 15 S
Drain to Sourc e On-state Res i stance RDS(on)1 VGS = 10 V, I D = 10 A 24 40 mΩ
RDS(on)2 VGS = 4.0 V, ID = 10 A 33 60 mΩ
Input Capac i t ance Ciss VDS = 10 V 790 pF
Output Capaci tance Coss VGS = 0 V 240 pF
Reverse Transf er Capacitanc e Crss f = 1 MHz 100 pF
Turn-on Delay Time td(on) VDD = 30 V, I D = 10 A 19 ns
Rise Time trVGS = 10 V 165 ns
Turn-off Del a y T i me td(off) RG = 10 Ω62 ns
Fall Time tf71 ns
Total Gate Charge QGVDD = 48 V 20 nC
Gate to Source Charge QGS VGS = 10 V 3 nC
Gate to Drain Charge QGD ID = 20 A 6.5 nC
Body Diode Forward Voltage VF(S-D) IF = 20 A , VGS = 0 V 0.93 V
Reverse Recovery T i me trr If = 20 A , VGS = 0 V 40 ns
Reverse Recovery Charge Qrr di/dt = 100 A /
µ
s45nC
TEST CIRCUIT 3 GATE CHARGE
V
GS
= 20
→
0
V
PG.
R
G
= 25 Ω
50 Ω
D.U.T. L
V
DD
TEST CIRCUIT 1 AVALANCHE CAPABILITY
PG. R
G
= 10 Ω
D.U.T. R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
R
G
PG.
I
G
= 2 mA
50 Ω
D.U.T. R
L
V
DD
I
D
V
DD
I
AS
V
DS
BV
DSS
Starting T
ch
V
GS
0
τ = 1 µs
Duty Cycle ≤ 1%
τ
V
GS
Wave Form
I
D
Wave Form
V
GS
I
D
10%
0
0
90%
90%
90%
ID
ton toff
td(on) t
r
td(off) tf
10% 10%
★
Data Sheet D13797EJ2V0DS 3
2SK3224
TYPICAL CHARACTERISTICS (TA = 25°C)
★
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
T
C
- Case Temperature - °C
dT - Percentage of Rated Power - %
0020 40 60 80 100 120 140 160
20
40
60
80
100
120
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
T
C
- Case Temperature - °C
P
T
- Total Power Dissipation - W
0
020 40 60 80 100 120 140 160
35
30
25
20
15
10
5
FORWARD BIAS SAFE OPERATING AREA
V
DS
- Drain to Source Voltage - V
I
D
- Drain Current - A
1
0.1
0.1
10
100
1000
1 10 100
T
C
= 25
˚C
Single Pulse
PW
=
10
µs
100
µs
1
ms
10
ms
DC
ID(DC)
ID(pulse)
R
DS(on)
Limited
(at V
GS
= 10 V)
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
PW - Pulse Width - s
r
th(t)
- Transient Thermal Resistance - ˚C/W
10
0.001
0.01
0.1
1
100
1000
1
m10
m 100
m 1 10 100 1000 10
µµ
100
Single Pulse
R
th(ch-C)
= 5.0˚C/W
R
th(ch-A)
= 125˚C/W
Data Sheet D13797EJ2V0DS
4
2SK3224
FORWARD TRANSFER CHARACTERISTICS
VGS - Gate to Source Voltage - V
ID - Drain Current - A
1
0.1
10
100
Pulsed
20468
VDS = 10 V
TA = −50˚C
25˚C
75˚C
150˚C
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
VDS - Drain to Source Voltage - V
ID - Drain Current - A
00 234
80
100
1
Pulsed
VGS
=
10 V
VGS
=
4.0
V
60
40
20
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
VGS - Gate to Source Voltage - V
RDS(on) - Drain to Source On-State Resistance - mΩ
05
20
10
0
60
10
Pulsed
50
40
30 ID = 10 A
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
I
D
- Drain Current - A
R
DS(on)
- Drain to Source On-State Resistance - mΩ
20
10
0.1 101
50
40
30
80
70
60
100
Pulsed
0
V
GS
= 4.0 V
V
GS
= 10 V
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
V
GS(off)
- Gate to Source Cut-off Voltage - V
0.5
V
DS
= 10 V
I
D
= 1 mA
1.0
1.5
2.0
−50 0 50 100 150
0
T
ch
- Channel Temperature - ˚C
Data Sheet D13797EJ2V0DS 5
2SK3224
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
1.0
ISD - Diode Forward Current - A
01.5
V
SD
- Source to Drain Voltage - V
0.5
Pulsed
0.1
1
10
100
1000
VGS = 0 V
VGS = 10 V
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
V
DS
- Drain to Source Voltage - V
C
iss
, C
oss
, C
rss
- Capacitance - pF
10
0.1
100
1000
10000
1 10 100
V
GS
= 0 V
f = 1 MHz
C
oss
C
rss
C
iss
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
IF - Drain Current - A
trr - Reverse Recovery Time - ns
di/dt = 100 A/µs
VGS = 0 V
1
0.1
10
1 10 100
1000
100
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
T
ch
- Channel Temperature - ˚C
R
DS(on)
- Drain to Source On-state Resistance - mΩ
0−50
10
0 50 100 150
I
D
= 10
A
20
40
50
60
70
80
90
30
V
GS
= 4.0
V
V
GS
= 10
V
V
GS
- Gate to Source Voltage - V
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
Q
G
- Gate Charge - nC
V
DS
- Drain to Source Voltage - V
00 10203040
20
40
60
80
4
2
0
8
6
V
DD
= 48 V
30 V
12 V
12
10
16
14
V
GS
I
D
= 20 A
V
DS
SWITCHING CHARACTERISTICS
I
D
- Drain Current - A
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
1
0.1
10
100
1000
10
1100
V
DD
= 30 V
V
GS
= 10 V
R
G
= 10 Ωt
r
t
f
t
d(off)
t
d(on)
Data Sheet D13797EJ2V0DS
6
2SK3224
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
L - Inductive Load - H
| IAS | - Single Avalanche Current - A
VDD = 30 V
RG = 25 Ω
10 100
10
100
1 m 10 m
0.1
1
IAS = 10 A
E
AS
= 10 mJ
VGS = 20 → 0 V
Starting Tch = 25˚C
µ
µ
SINGLE AVALANCHE ENERGY
DERATING FACTOR
Starting T
ch
- Starting Channel Temperature - ˚C
Energy Derating Factor - %
25 50 75 100
60
40
20
0
160
140
125 150 175
120
100
80
V
DD
= 30 V
R
G
= 25 Ω
V
GS
= 20 → 0 V
I
AS
≤ 10 A
Data Sheet D13797EJ2V0DS 7
2SK3224
PACKAGE DRAWINGS (Unit: mm)
1) TO-251 (MP-3)
1.Gate
2.Drain
3.Source
4.Fin (Drain)
213
6.5±0.2
5.0±0.2
4
1.5-
0.1
+0.2
5.5±0.27.0 MAX.
13.7 MIN.
2.32.3
0.75
0.5±0.1
2.3±0.2
1.6±0.2
1.1±0.2
0.5-
0.1
+0.2
0.5-
0.1
+0.2
2) TO-252 (MP-3Z)
1. Gate
2. Drain
3. Source
4. Fin (Drain)
123
4
6.5±0.2
5.0±0.2
4.3 MAX.0.8
2.3 2.3 0.9
MAX.
5.5±0.2
10.0 MAX.
2.0
MIN.
1.5-
0.1
+0.2
2.3±0.2
0.5±0.1
0.8
MAX.
0.8
1.0 MIN.
1.8 TYP.
0.7
1.1±0.2
EQUIVALENT CIRCUIT
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Source
Body
Diode
Gate
Protection
Diode
Gate
Drain
2SK3224
M8E 00. 4
The information in this document is current as of April, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
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