CY25403SXC - Cypress Semiconductor Corp.

CY25403/CY25423/CY25483

Three PLL Programmable Clock Generator with

Spread Spectrum

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-12564 Rev. *E Revised June 02, 2010

Features

■Three fully integrated phase locked loops (PLLs)

■Input frequency range

❐External crystal: 8 to 48 MHz

❐External reference: 8 to 166 MHz clock

■Reference Clock input voltage range

❐2.5 V, 3.0 V, and 3.3 V for CY25483

❐1.8 V for CY25403 and CY25423

■Wide operating output frequency range

❐3 to 166 MHz

■Programmable Spread Spectrum with Center and Down

Spread option and Lexmark and Linear modulation profiles

■VDD supply voltage options:

❐2.5 V, 3.0 V, and 3.3 V for CY25403 and CY25483

❐1.8 V for CY25423

■Selectable output clock voltages independent of VDD supply:

❐2.5 V, 3.0 V, and 3.3 V for CY25403 and CY25483

❐1.8 V for CY25423

■Frequency Select feature with option to select four different

frequencies

■Power Down, Output Enable, and SS ON/OFF controls

■Low jitter, high accuracy outputs

■Ability to synthesize nonstandard frequencies with Fractional-N

capability

■Three clock outputs with Programmable drive strength

■Glitch-free outputs while frequency switching

■8-pin SOIC package

■Commercial and Industrial temperature ranges

Benefits

■Multiple high performance PLLs allow synthesis of unre lated

frequencies

■Nonvolatile programming for personalization of PLL

frequencies, spread spectrum characteristics, drive strength,

crystal load capacitance, and output frequencies

■Application specific Programmable EMI reduction using

Spread Spectrum for clocks

■Programmable PLLs for system frequency margin tests

■Meets critical timing requirements in complex system designs

■Suitability for PC, consumer, portable, and networking

applications

■Capable of Zero PPM frequency synthesis error

■Uninterrupted system operation during clock frequency switch

■Application compatibility in standard and low power systems

Block Diagram

OSC PLL1

PLL3

(SS)

CLK3

(SS)

CLK2

(No SS

)

CLK1

(SS)

Crossbar

Switch

FS1

SSON

XOUT

XIN/

EXCLKIN

PD#/OE

PLL 2

(SS)

FS0

MUX

and

Control

Logic

Output

Dividers

and

Drive

Strength

Control

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 2 of 12

Table 1. Device Selector Guide

Figure 1. Pin Diagram - CY25403 8-Pin SOIC

Table 2. Pin Definition - CY25403 (2.5 V, 3.0 V, or 3.3 V Supply)

Device Crystal Input EXCKLKIN Input VDD

CY25403 Yes 1.8V LVCMOS 2.5V, 3.0V, 3.3V

CY25483 No 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V

CY25423 Yes 1.8 V LVCMOS 1.8 V

Pin Number Name IO Description

1 XIN/EXCLKIN Input Crystal Input or 1.8 V External Clock Input

DD Power Power Supply: 2.5 V, 3.0 V, or 3.3 V

3 CLK1 Output Programmable Clock Output with Spread Spe ctrum

4 CLK2/FS0 Output/Input Multifunction Programmab le pin: Programmable Clock Output with no Spread

Spectrum or Frequency Select pin

5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin

6 CLK3/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with S pread S pectrum

or Spread Spectrum ON/OFF control pin

7 GND Power Power Supply Ground

8 XOUT Output Crystal Output

VDD CY25403

XOUT

GND

CLK3/SSON

PD#/OE/FS1

XIN/

EXCLKIN

CLK1

CLK2/FS0

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 3 of 12

Figure 2. Pin Diagram - CY25483 8-Pin SOIC

Table 3. Pin Definition - CY25483 (2.5 V, 3.0 V, or 3.3 V Supply)

Figure 3. Pin Diagram - CY25423 8-Pin SOIC

Table 4. Pin Definition - CY25423 (1.8 V Supply)

Pin Number Name IO Description

1 EXCLKIN Input 2.5 V, 3.0 V, or 3.3 V External Clock Inpu t

DD Power Power Supply: 2.5 V, 3.0 V, or 3.3 V

3 CLK1 Output Programmable Clock Output with Spread Spectrum

4 CLK2/FS0 Output/Input Multifunction Progra mma ble pin: Progra mmable Clock Output with no Spread

Spectrum or Frequency Select pin

5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin

6 CLK3/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with S pread Spectrum

or Spread Spectrum ON/OFF control pin

7 GND Power Power Supply Ground

8 DNU Output Do not use this pin

Pin Number Name IO Description

1 XIN/EXCLKIN Input Crystal Input or 1.8 V External Clock Input

DD Power Power Supply: 1.8 V

3 CLK1 Output Programmable Clock Output with Spread Spectrum

4 CLK2/FS0 Output/Input Multifunction Programmable pin: Programmable Clock Output with no Spread

Spectrum or Frequency Select pin

5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency

Select pin

6 CLK3/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with Spread

Spectrum or Spread Spectrum ON/OFF control pin

7 GND Power Power Supply Ground

8 XOUT Output Crystal Output

VDD CY25483

DNU

GND

PD#/OE/FS1

EXCLKIN

CLK1

CLK2/FS0

CLK3/SSON

CY25423

XOUT

GND

PD#/OE/FS1

XIN/

EXCLKIN

VDD

CLK1

CLK2/FS0

CLK3/SSON

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 4 of 12

General Description

3 Configurable PLLs

The CY25403, CY25423, and CY25483 have three

programmable PLLs that can be used to generate output

frequencies ranging from 3 to 166 MHz. The advantage of having

three PLLs is that a single device generates up to three

independent frequencies from a single crystal.

Input Reference Clocks

The input reference clock can be either a crystal or a clock signal,

for CY25403 and CY25423 while just a clock signal for CY25483.

The input frequency range for crystal (XIN) is 8 MHz to 48 MHz

and that for external reference clock (EXCLKIN) is 8 MHz to 166

MHz. The voltage range of the reference clock input for CY25483

is 2.5 V/3.0 V/3.3 V while that for CY25403 and CY25423 is

1.8 V. This gives user an option for this device to be compatible

for different input clock voltage levels in the system.

VDD Power Supply Options

These devices have programmable power supply options. The

CY25403/CY25483 is a high voltage part that can be

programmed to operate at any voltage 2.5 V , 3.0 V, or 3.3 V while

CY25423 is a low voltage part that can operate at 1.8 V.

Output Source Selection

These devices have programmable input sources for each of its

clock outputs. There are four available clock sou rces an d these

clock sources are: XIN/EXCLKIN, PLL1, PLL2, and PLL3.

Output clock source selection is done by using four out of four

crossbar switch. Thus, any one of these four available clock

sources can be arbitrarily selected for the clock outputs. This

gives user a flexibility to have up to three independent clock

outputs.

Spread Spectrum Control

Two of the three PLLs (PLL2 and PLL3) have spread spectru m

capability for EMI reduction in the system. The device uses a

Cypress proprietary PLL and Spread Spectrum Clock (SSC)

technology to synthesize and modulate the frequency of the PLL.

The spread spectrum feature can be turned on or off using a

multifunction control pin (CLK3/SSON). It can be programmed to

either center spread range from ±0.125% to ±2.50% or down

spread range from –0.25% to –5.0% with Lexmark or Linear

profile.

Frequency Select

Each PLL can be programmed for up to four different

frequencies. There are two multifunction programmable pins,

CLK2/FS0 and PD#/OE/FS1 which if programmed as frequency

select inputs, can be used to select among these arbitrarily

programmed frequency settings. Each output has

programmable output divider options.

Glitch-Free Frequen cy Switch

When the frequency select pin, FS(1:0) is used to switch

frequency, the outputs are glitch-free provided frequency is

switched using output dividers. This feature enables

uninterrupted system operation while clock frequency is being

switched.

PD#/OE Mode

Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to

operate as either frequency se lect (FS1), power down (PD#) or

output enable (OE) mode. PD# is a low-true input. If a ctivated it

shuts off the entire chip, resulting in minimum power

consumption for the device. Setting this signal high brings the

device in the operational mode with default register settings.

When this pin is programmed as Output Enable (OE), clock

outputs can be enabled or disabled using OE (pin 5). Indivi dual

clock outputs can be programmed to be sensitive to this OE pin.

Output Drive Strength

The DC drive strength of the individual clock output can be

programmed for different values. Table 5 shows the typical rise

and fall times for different drive strength settings.

Generic Configuration and Custom Frequency

There is a generic set of output frequencies available from the

factory that can be used for the device evaluation purposes. The

device, CY25403, CY25423, and CY25483 can be custom

programmed to any desired frequencies and listed features. For

customer specific programming, please contact local Cypress

Field Application Engineer (FAE) or sales representative.

Table 5. Output Drive Strength

Output Drive Strength Rise/Fall Time (ns)

(Typical Value)

Low 6.8

Mid Low 3.4

Mid High 2.0

High 1.0

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 5 of 12

Absolute Maximum Conditions

Parameter Description Condition Min Max Unit

VDD Supply Voltage for CY25403/CY25483 –0.5 4.5 V

VDD Supply Voltage for CY25423 –0.5 2.6 V

VIN Input Voltage for CY25403/CY2 5483 Relative to VSS –0.5 VDD+0.5 V

VIN Input Voltage for CY25423 Re lative to VSS –0.5 2.2 V

TSTemperature, Storage Non Functional –65 +150 °C

ESDHBM ESD Protection (Human Body Model) JEDEC EIA/JESD22-A114-E 2000 Volts

UL-94 Flammability Rating V-0 at 1/8 in. 10 ppm

MSL Moisture Sensitivity Level SOIC package 3

Recommended Operating Conditions

Parameter Description Min Typ Max Unit

VDD VDD Operating Voltage for CY25403 2.25 – 3.60 V

VDD VDD Operating Voltage for CY25423 1.65 1.8 1.95 V

TAC Commercial Ambient Temperature 0 – +70 °C

TAI Industrial Ambient Temperature –40 -- +85 °C

CLOAD Maximum Load Capa citance – – 15 pF

tPU Power up time for all VDD to reach minimum specified voltage

(power ramps must be monotonic) 0.05 – 500 ms

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 6 of 12

DC Electrical Specifications

Parameter Description Conditions Min Typ Max Unit

VOL Output Low Voltage IOL = 2 mA, drive strength = [00] – – 0.4 V

IOL = 3 mA, drive stren gt h = [0 1]

IOL = 7 mA, drive stren gt h = [1 0]

IOL = 12 mA, drive strength = [11]

VOH Output High Voltage IOH = –2 mA, drive strength = [00] VDD - 0.4 – – V

IOH = –3 mA, drive strength = [01]

IOH = –7 mA, drive strength = [10]

IOH = –12 mA, drive strength = [11]

VIL1 Input Low Voltage of PD#/OE, FS0,

FS1 and SSON – – 0.2*VDD V

VIL2 Input Low Voltage of EXCLKIN – – 0.18 V

VIH1 Input High Voltage of PD#/OE, FS0,

FS1 and SSON 0.8*VDD ––V

VIH2 Input High Voltage of EXCLKIN for

CY25403/CY25423 1.62 – 2.2 V

VIH3 Input High Voltage of EXCLKIN for

CY25483 0.8*VDD ––V

IIL Input Low Current, PD#/OE/FS1 VIN = 0V – – 10 µA

IIH Input High Current, PD#/OE/FS1 VIN = VDD ––10µA

IILDN Input Low Current, SSON and FS0 pins VIN = 0V (Internal pull down resistor

= 160k typ.) ––10µA

IIHDN Input High Current, SSON and FS0

pins VIN = VDD (Internal pull down

resistor = 160k typ.) 14 – 36 µA

RDN Pull Down Resistor of CLK1, CLK2/FS0

and CLK3/SSON pins Output clocks in off state by setting

PD# = Low 100 160 250 kΩ

IDD[1, 2]Supply Current for CY25423 PD# = High, No load –20–mA

Supply Current for CY25403/CY25483 PD# = High, No load –22–mA

IDDS[1] Standby Current PD# = Low –3–µA

CIN[1] Input Capacitance SSON, PD#/OE/FS1 and FS0 pins ––7pF

1. Guaranteed by desi gn but not 100% tested.

2. Configuration dependent.

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 7 of 12

AC Electrical Specifications

Parameter Description Conditions Min Typ Max Unit

FIN (crystal) Crystal Frequency, XIN 8 –48 MHz

FIN (clock) Input Clock Frequency (EXCLKIN) 8 –166 MHz

FCLK Output Clock Frequency 3 –166 MHz

DC Output Duty Cycle, All Clocks except

Ref Out Duty Cycle is defined in F igure 5 on page 8; t1/t2,

measured at 50% of VDD 45 50 55 %

DC Ref Out Duty Cycle Ref In Min 45%, Max 55% 40 – 60 %

TRF1[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as sh own in

Figure 6 on page 8, CL = 15 pF, drive strength [00] –6.8–ns

TRF2[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as show n in

Figure 6 on page 8, CL = 15 pF, drive strength [01] –3.4–ns

TRF3[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as show n in

Figure 6 on page 8, CL = 15 pF, drive strength [10] –2.0–ns

TRF4[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as show n in

Figure 6 on page 8, CL = 15 pF, drive strength [11] –1.0–ns

TCCJ[1,2] Cycle-to-cycle Jitter (peak) Configuration dependent. See Table 6 – 100 – ps

TLOCK[1] PLL Lock Time Measured from 90% of the applied power supply

level –13ms

1. Guaranteed by design but not 100% test ed.

2. Configuration dependent.

Table 6. Configuration Example for C-C Jitter

Ref. Frequency

(MHz)

CLK1 Output CLK2 Output CLK3 Output

Freq. (MHz) C-C Jitter Typ

(ps) Freq. (MHz) C-C Jitter Typ

(ps)

14.3181 8.0 134 166 103 48 92

19.2 74.25 99 166 94 8 91

27 48 67 27 109 166 103

48 48 93 27 123 166 137

Recommended Crystal Specification for SMD Package

Parameter Description Range 1 Range 2 Range 3 Unit

Fmin Minimum Frequency 8 14 28 MHz

Fmax Maximum Frequency 14 28 48 MH z

R1 Motional Resistance (ESR) 135 50 30 Ω

C0 Shunt Capacitance 4 4 2 pF

CL Parallel Load Capacitance 18 14 12 pF

DL(max) Maximum Crystal Drive Level 300 300 300 µW

Recommended Crystal Specification for Thru-Hole Package

Parameter Description Range 1 Range 2 Range 3 Unit

Fmin Minimum Frequency 8 14 24 MHz

Fmax Maximum Frequency 14 24 32 MHz

R1 Motional Resistance (ESR) 90 50 30 Ω

C0 Shunt Capacitance 7 7 7 pF

CL Parallel Load Capacitance 18 12 12 pF

DL(max) Maximum Crystal Drive Level 1000 1000 1000 µW

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 8 of 12

Test and Measurement Setup

Figure 4. Test and Measurement Setup

Voltage and Timing Definitions

Figure 5. Duty Cycle Definition

Figure 6. Rise Time = TRF, Fall Time = TRF

0.1 μF

VDD Outputs

CLOAD

GND

DUT

Clock

Output

50% of V

Clock

Output

RF T

V DD

80% of V

20% of V

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 9 of 12

Ordering Information

Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible

Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales

Representative for more information

Possible Configurations

Part Number Type Package Supply Voltage Production Flow

Pb-free

CY25403SXC Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0°C to 70° C

CY25403SXCT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0°C to 70°C

CY25423SXC Field Programmable 8-pin SOIC 1.8 V Commercial, 0°C to 70°C

CY25423SXCT Field Programmable 8-pin SOIC -Tape and Reel 1.8 V Commercial, 0°C to 70°C

CY25483SXC Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0°C to 70 ° C

CY25483SXCT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0°C to 70°C

CY25403SXI Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, -40°C to +85°C

CY25403SXIT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40°C to +85°C

CY25423SXI Field Programmable 8-pin SOIC 1.8 V Industrial, -40°C to +85°C

CY25423SXIT Field Programmable 8-pin SOIC -Tape and Reel 1.8 V Industrial, -40°C to +85°C

CY25483SXI Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, -40°C to +85°C

CY25483SXIT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40°C to +85°C

Programmer

CY3675-CLKMAKER1 Programming Kit

CY3675-SOIC8A Socket Adapter Board, for programming CY25402, CY25403, CY25422,

CY25423, CY25482, and CY25483

Part Number[1]Type VDD(V) Production Flow

Pb-free

CY25403SXC-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0°C to 70°C

CY25403SXC-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0°C to 70°C

CY25403SXI-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, -40°C to +85°C

CY25403SXI-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, -40°C to +85°C

CY25423SXC-xxx 8-pin SOIC Supply Voltage: 1.8 V Commercial, 0°C to 70°C

CY25423SXC-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 1.8 V Commercial, 0°C to 70°C

CY25423SXI-xxx 8-pin SOIC Supply Voltage: 1.8 V Industrial, -40°C to +85°C

CY25423SXI-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 1.8 V Industrial, -40°C to +85°C

CY25483SXC-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0°C to 70°C

CY25483SXC-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0°C to 70°C

CY25483SXI-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, -40°C to +85°C

CY25483SXI-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, -40°C to +85°C

1. xxx indicates factory programmed parts based on customer specific configuration . For more details, cont act your local Cypress FAE or Sales Representative.

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 10 of 12

Ordering Code Definitions

Package Drawing and Dimensions

Figure 7. 8-Pin (150-Mil ) SOIC S8

Package Type: (T = Tape and Reel)

Customer specific identification code

Temperature code (C=Co m mercial or I=Industrial)

8-Pin SOIC package

Marketing Code: CY25403/23/83 = Device Number

SX C/I - xxx T

CY254x3

51-85066 *D

[+] Feedback

CY25403/CY25423/CY25483

Document #: 001-12564 Rev. *E Page 11 of 12

Acronyms

Acronym Description

DL drive level

DNU do not use

DUT device under test

EMI electromagnetic in terference

ESD electrostatic discharge

FAE field application engineer

FS frequency select

JEDEC EIA joint electron devices

engineering council electronic

industries alliance

LVCMOS low voltage complemetary

metal oxide semiconductor

OE output enabl e

OSC oscillator

PD power down

PLL phase locked loop

PPM parts per million

SS spread spectrum

SSC spread spectrum clock

SSON spread spectrum on

[+] Feedback

Document #: 001-12564 Rev. *E Revised June 02, 2010 Page 12 of 12

All products and company names mentioned in this document may be the trademarks of their respective holders.

CY25403/CY25423/CY25483

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r

medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n express written ag re em en t with Cypress. Furthermor e, Cyp ress doe s not author iz e its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, cr eate der ivative works of ,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypress

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without

the express written perm ission of Cypres s.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials describ ed herein. Cyp ress does not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document History Page

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Automotive cypress.com/go/automotive

Clocks & Buffers cypress.com/go/clocks

Interface cypress.com/go/interface

Lighting & Power Control cypress.com/go/powerpsoc

cypress.com/go/plc

Memory cypress.com/go/memory

Optical & Image Sensing cypress.com/go/image

PSoC cypress.com/go/psoc

Touch Sensing cypress.com/go/touch

USB Controllers cypress.com/go/USB

Wireless/RF cypress.com/go/wireless

PSoC® Solutions

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Document Title: CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum

Document Number: 001-12564

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 690296 See ECN RGL New Data Sheet

*A 815788 See ECN RGL Minor Change: To post on web

*B 1428744 See ECN RGL/AESA Changed data sheet format to match generic part, CY2544/46

Added new device and specification for high ref. input voltage part, CY25483

Removed Preliminary from Title page

Replaced CLK2 with REFOUT

*C 2748211 08/10/09 TSAI Posting to external web.

*D 2899300 03/25/10 CXQ Updated Ordering Information . Added note regarding Possible Configura-

tions in Ordering Information section.

Added Possible Configurations table for “xxx’ parts.

Updated Package Drawing and Dimensions

*E 2898568 06/02/10 CXQ Updated Ordering Information and template.

[+] Feedback