SN54HC00, SN74HC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS181D – DECEMBER 1982 – REVISED DECEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 20-µA Max ICC
D
Typical tpd = 8 ns
D
±4-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
SN54HC00 ...J OR W PACKAGE
SN74HC00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B
1A
NC
3Y
3A V
4B
2Y
GND
NC
SN54HC00 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
description/ordering information
The ’HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function
Y = A • B or Y = A + B in positive logic.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74HC00N SN74HC00N
SOIC D
Tube SN74HC00D
HC00
SOIC
–
D
Tape and reel SN74HC00DR
HC00
–40°C to 85°CSOP – NS Tape and reel SN74HC00NSR HC00
SSOP – DB Tape and reel SN74HC00DBR HC00
TSSOP PW
Tube SN74HC00PW
HC00
TSSOP
–
PW
Tape and reel SN74HC00PWR
HC00
CDIP – J Tube SNJ54HC00J SNJ54HC00J
–55°C to 125°CCFP – W Tube SNJ54HC00W SNJ54HC00W
LCCC – FK Tube SNJ54HC00FK SNJ54HC00FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B Y
H H L
LXH
X L H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC00, SN74HC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS181D – DECEMBER 1982 – REVISED DECEMBER 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
A
BY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC00 SN74HC00
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
∆t/∆vInput transition rise/fall time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54HC00, SN74HC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS181D – DECEMBER 1982 – REVISED DECEMBER 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC00 SN74HC00
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 V
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 2 40 20 µA
Ci2 V to 6 V 3 10 10 10 pF
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HC00 SN74HC00
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 45 90 135 115
tpd A or B Y4.5 V 9 18 27 23 ns
6 V 8 15 23 20
2 V 38 75 110 95
ttY4.5 V 8 15 22 19 ns
6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per gate No load 20 pF
SN54HC00, SN74HC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS181D – DECEMBER 1982 – REVISED DECEMBER 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
50%50% 10%10% 90% 90% VCC
0 V
trtf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MCER002C – JANUARY 1995 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
J (R-GDIP-T**) CERAMIC DUAL-IN-LINE
1
20
0.290
(7,87)
0.310
0.975
(24,77)
(23,62)
0.930
(7,37)
0.245
(6,22)
(7,62)
0.300
1614
PINS **
0.290
(7,87)
0.310
0.785
(19,94)
(19,18)
0.755
(7,37)
0.310
(7,87)
(7,37)
0.290
0.755
(19,18)
(19,94)
0.785
0.245
(6,22)
(7,62)
0.300
A
0.300
(7,62)
(6,22)
0.245
A MIN
A MAX
B MAX
B MIN
C MIN
C MAX
DIM
0°–15°
Seating Plane
0.014 (0,36)
0.008 (0,20)
4040083/E 03/99
C
8
7
0.020 (0,51) MIN
B
0.070 (1,78)
0.100 (2,54)
0.065 (1,65)
0.045 (1,14)
14 LEADS SHOWN
14
0.015 (0,38)
0.023 (0,58)
0.100 (2,54)
0.200 (5,08) MAX
0.130 (3,30) MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, and GDIP1-T20
MECHANICAL DATA
MCFP002A – JANUARY 1995 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F14) CERAMIC DUAL FLATPACK
0.360 (9,14)
0.250 (6,35)
87
141
0.235 (5,97)
0.004 (0,10)
0.026 (0,66)
4 Places
0.015 (0,38)
0.045 (1,14)
0.335 (8,51)
0.008 (0,20)
0.045 (1,14)
Base and Seating Plane
0.005 (0,13) MIN
0.019 (0,48)
0.390 (9,91)
0.260 (6,60)
0.080 (2,03)
4040180-2/C 02/02
0.360 (9,14)
0.250 (6,35)
0.280 (7,11) MAX
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
MECHANICAL DATA
MLCC006B – OCTOBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
BB AC AD
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
1.060
(26,92)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY
20 pin vendor option 4040049/E 12/2002
9
8
0.070 (1,78)
A
0.045 (1,14) 0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
MS-100
VARIATION AA
C
D
D
D
0.030 (0,76)
0.045 (1,14)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
Product Folder: SN74HC00, Quad 2-Input Positive-NAND Gates
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SN74HC00, Quad 2-Input Positive-NAND Gates
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54HC00 SN74HC00
Voltage Nodes (V) 6, 5, 2 6, 5, 2
Vcc range (V) 2.0 to 6.0 2.0 to 6.0
Input Level CMOS CMOS
Output Level CMOS CMOS
Output Drive (mA) -4/4
No. of Gates 4 4
Static Current 0.02
tpd max (ns) 20
FEATURES Back to Top
● Wide Operating Voltage Range of 2 V to 6 V
● Outputs Can Drive Up To 10 LSTTL Loads
● Low Power Consumption, 20-uA Max ICC
● Typical tpd = 8 ns
● ±4-mA Output Drive at 5 V
● Low Input Current of 1 uA Max
DESCRIPTION Back to Top
The ’HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic.
TECHNICAL DOCUMENTS Back to Top
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DATASHEET Back to Top
Full datasheet in Acrobat PDF: sn74hc00.pdf (279 KB,Rev.D) (Updated: 12/03/2002)
APPLICATION NOTES Back to Top
View Application Notes for Digital Logic
● CMOS Power Consumption and CPD Calculation (Rev. B) (SCAA035B - Updated: 06/01/1997)
● Designing With Logic (Rev. C) (SDYA009C - Updated: 06/01/1997)
● Evaluation of Nickel/Palladium/Gold-Finished Surface-Mount Integrated Circuits (SZZA026 - Updated: 06/20/2001)
● Implications of Slow or Floating CMOS Inputs (Rev. C) (SCBA004C - Updated: 02/01/1998)
● Input and Output Characteristics of Digital Integrated Circuits (SDYA010 - Updated: 10/01/1996)
● Live Insertion (SDYA012 - Updated: 10/01/1996)
● SN54/74HCT CMOS Logic Family Applications and Restrictions (SCLA011 - Updated: 05/01/1996)
● Selecting the Right Texas Instruments Signal Switch (SZZA030 - Updated: 09/07/2001)
file:///E|/042120003_HTML/sn74hc00.html (1 of 4) [25-Apr-03 6:28:02 PM]
Product Folder: SN74HC00, Quad 2-Input Positive-NAND Gates
● TI IBIS File Creation, Validation, and Distribution Processes (SZZA034 - Updated: 08/29/2002)
● Understanding and Interpreting Texas Instruments Standard-Logic Products Data Sh (Rev. A) (SZZA036A - Updated: 02/27/2003)
● Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (SCLA008 - Updated: 04/01/1996)
MORE LITERATURE Back to Top
● Enhanced Plastic Portfolio Brochure (SGZB004, 387 KB - Updated: 08/19/2002)
● Logic Reference Guide (SCYB004, 1032 KB - Updated: 10/23/2001)
● MicroStar Junior BGA Design Summary (SCET004, 167 KB - Updated: 07/28/2000)
● Military Brief (SGYN138, 803 KB - Updated: 10/10/2000)
● Overview of IEEE Std 91-1984, Explanation of Logic Symbols Training Booklet (Rev. A) (SDYZ001A, 138 KB - Updated: 07/01/1996)
● Palladium Lead Finish User's Manual (SDYV001, 2041 KB - Updated: 11/01/1996)
● QML Class V Space Products Military Brief (Rev. A) (SGZN001A, 257 KB - Updated: 10/07/2002)
USER GUIDES Back to Top
● LOGIC Pocket Data Book (SCYD013, 4837 KB - Updated: 12/05/2002)
● Signal Switch Data Book (SCDD003, 10259 KB - Updated: 03/19/2001)
SAMPLES Back to Top
ORDERABLE DEVICE PACKAGE
INDUSTRY (TI) PINS TEMP (ºC) STATUS PRODUCT CONTENT SAMPLES
SN74HC00D SOIC
(D) 14 -40 TO 85 ACTIVE View Product Content Request Samples
SN74HC00DR SOIC
(D) 14 -40 TO 85 ACTIVE View Product Content Request Samples
SN74HC00N PDIP
(N) 14 -40 TO 85 ACTIVE View Product Content Request Samples
SN74HC00NSR SOP
(NS) 14 -40 TO 85 ACTIVE View Product Content Request Samples
SN74HC00PWR TSSOP
(PW) 14 -40 TO 85 ACTIVE View Product Content Request Samples
PRICING/AVAILABILITY/PKG Back to Top
DEVICE INFORMATION
Updated Daily
ORDERABLE
DEVICE STATUS PACKAGE
TYPE | PINS TEMP (ºC) PRODUCT
CONTENT
BUDGETARY
PRICING
QTY | $US
STD
PACK
QTY
SN74HC00ADBLE OBSOLETE SSOP
(DB) | 14 -40 TO 85 View Contents 1KU |
SN74HC00D ACTIVE SOIC
(D) | 14 -40 TO 85 View Contents 1KU | 0.11 50
TI INVENTORY STATUS
As Of 09:00 AM GMT, 17 Apr 2003
IN STOCK IN PROGRESS
QTY | DATE LEAD TIME
0* Call**
0*1953 | 30 Apr 4 WKS
>10k | 12 May
REPORTED DISTRIBUTOR INVENTORY
As Of 09:00 AM GMT, 17 Apr 2003
DISTRIBUTOR
COMPANY | REGION IN STOCK PURCHASE
None Reported
View Distributors
Avnet | Americas >1k
Arrow | Americas >1k
EBV
Electronik | Europe >1k
DigiKey | Americas >1k
Newark
Electronics | Americas >1k
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Product Folder: SN74HC00, Quad 2-Input Positive-NAND Gates
SN74HC00DR ACTIVE SOIC
(D) | 14 -40 TO 85 View Contents 1KU | 0.11 2500
SN74HC00N ACTIVE PDIP
(N) | 14 -40 TO 85 View Contents 1KU | 0.11 25
SN74HC00N3 OBSOLETE PDIP
(N) | 14 -40 TO 85 View Contents 1KU |
SN74HC00NS ACTIVE SOP
(NS) | 14 View Contents 1KU |
SN74HC00NSLE OBSOLETE SOP
(NS) | 14 -40 TO 85 View Contents 1KU |
SN74HC00NSR ACTIVE SOP
(NS) | 14 -40 TO 85 View Contents 1KU | 0.55 2000
SN74HC00PW ACTIVE TSSOP
(PW) | 14 -40 TO 85 View Contents 1KU | 0.18 90
SN74HC00PWLE OBSOLETE TSSOP
(PW) | 14 -40 TO 85 View Contents 1KU |
SN74HC00PWR ACTIVE TSSOP
(PW) | 14 -40 TO 85 View Contents 1KU | 0.11 2000
0*>10k | 28 Apr 2 WKS
0*3 | 21 Apr 7 WKS
1100 | 28 Apr
500 | 29 Apr
1000 | 22 May
8100 | 27 May
0* Call**
0* Call**
0* Call**
0*>10k | 28 Apr 2 WKS
0*450 | 16 Apr 4 WKS
>10k | 08 May
0* Call**
0*2400 | 25 Apr 2 WKS
>10k | 28 Apr
Avnet | Americas >1k
Arrow | Americas >1k
EBV
Electronik | Europe >1k
Abacus Polar | Europe >1k
DigiKey | Americas >1k
Avnet-SILICA | Europe >1k
Avnet-SILICA | Europe >1k
Avnet | Americas >1k
Arrow | Americas >1k
EBV
Electronik | Europe >1k
DigiKey | Americas >1k
Newark
Electronics | Americas >1k
None Reported
View Distributors
None Reported
View Distributors
None Reported
View Distributors
DigiKey | Americas >1k
Arrow | Americas 356
None Reported
View Distributors
Arrow | Americas >1k
Avnet | Americas >1k
DigiKey | Americas 316
Table Data Updated on: 4/17/2003
Products | Applications | Support | my.TI
© Copyright 1995-2002 Texas Instruments Incorporated. All rights reserved.
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