SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181D - DECEMBER 1982 - REVISED DECEMBER 2002 D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-A Max ICC Typical tpd = 8 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max SN54HC00 . . . FK PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1A 1B 1Y 2A 2B 2Y GND 1B 1A NC VCC 4B SN54HC00 . . . J OR W PACKAGE SN74HC00 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) NC - No internal connection description/ordering information The 'HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A * B or Y = A + B in positive logic. ORDERING INFORMATION PDIP - N SN74HC00N Tube SN74HC00D Tape and reel SN74HC00DR SOP - NS Tape and reel SN74HC00NSR HC00 SSOP - DB Tape and reel SN74HC00DBR HC00 Tube SN74HC00PW Tape and reel SN74HC00PWR CDIP - J Tube SNJ54HC00J SNJ54HC00J CFP - W Tube SNJ54HC00W SNJ54HC00W TSSOP - PW -55C to 125C TOP-SIDE MARKING Tube SOIC - D -40C to 85C ORDERABLE PART NUMBER PACKAGE TA SN74HC00N HC00 HC00 LCCC - FK Tube SNJ54HC00FK SNJ54HC00FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS OUTPUT Y A B H H L L X H X L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181D - DECEMBER 1982 - REVISED DECEMBER 2002 logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC00 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage t/v NOM MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 VCC = 4.5 V VCC = 6 V 0 VCC = 2 V VCC = 4.5 V UNIT V V 4.2 0.5 0.5 1.35 1.35 1.8 0 Output voltage Input transition rise/fall time SN74HC00 MIN VCC VCC V 1.8 0 0 VCC VCC 1000 1000 500 500 V V ns VCC = 6 V 400 400 TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181D - DECEMBER 1982 - REVISED DECEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -20 A VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 MIN TA = 25C TYP MAX SN74HC00 MIN MIN MAX 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 2 40 20 A 3 10 10 10 pF 6V Ci SN54HC00 2 V to 6 V V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25C TYP MAX SN54HC00 SN74HC00 MIN MIN PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 45 90 135 115 tpd A or B Y 4.5 V 9 18 27 23 6V 8 15 23 20 tt Y MIN MAX MAX 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 UNIT ns ns operating characteristics, TA = 25C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate POST OFFICE BOX 655303 No load * DALLAS, TEXAS 75265 TYP 20 UNIT pF 3 SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181D - DECEMBER 1982 - REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MCER002C - JANUARY 1995 - REVISED JUNE 1999 J (R-GDIP-T**) CERAMIC DUAL-IN-LINE 14 LEADS SHOWN PINS ** 14 16 20 A MAX 0.310 (7,87) 0.310 (7,87) 0.310 (7,87) A MIN 0.290 (7,37) 0.290 (7,37) 0.290 (7,37) B MAX 0.785 (19,94) 0.785 (19,94) 0.975 (24,77) B MIN 0.755 (19,18) 0.755 (19,18) 0.930 (23,62) C MAX 0.300 (7,62) 0.300 (7,62) 0.300 (7,62) C MIN 0.245 (6,22) 0.245 (6,22) 0.245 (6,22) DIM B 14 8 C 1 7 0.065 (1,65) 0.045 (1,14) 0.100 (2,54) 0.070 (1,78) 0.020 (0,51) MIN A 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040083/E 03/99 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package is hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, and GDIP1-T20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MCFP002A - JANUARY 1995 - REVISED FEBRUARY 2002 W (R-GDFP-F14) CERAMIC DUAL FLATPACK Base and Seating Plane 0.260 (6,60) 0.235 (5,97) 0.045 (1,14) 0.026 (0,66) 0.008 (0,20) 0.004 (0,10) 0.080 (2,03) 0.045 (1,14) 0.280 (7,11) MAX 1 0.019 (0,48) 0.015 (0,38) 14 0.050 (1,27) 0.390 (9,91) 0.335 (8,51) 0.005 (0,13) MIN 4 Places 7 8 0.360 (9,14) 0.250 (6,35) 0.360 (9,14) 0.250 (6,35) 4040180-2 / C 02/02 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL MPDI002C - JANUARY 1995 - REVISED DECEMBER 20002 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0- 8 A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated Product Folder: SN74HC00, Quad 2-Input Positive-NAND Gates Contact Us Buy About TI TI Worldwide my.TI Advanced Search Keyword Part Number PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY/PKG | SAMPLES | APPLICATION NOTES | USER GUIDES | MORE LITERATURE PRODUCT SUPPORT: TRAINING SN74HC00, Quad 2-Input Positive-NAND Gates DEVICE STATUS: ACTIVE PARAMETER NAME SN54HC00 SN74HC00 Voltage Nodes (V) 6, 5, 2 6, 5, 2 Vcc range (V) 2.0 to 6.0 2.0 to 6.0 Input Level CMOS CMOS Output Level CMOS No. of Gates CMOS -4/4 Output Drive (mA) 4 4 Static Current 0.02 tpd max (ns) 20 FEATURES Back to Top Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-uA Max ICC Typical tpd = 8 ns 4-mA Output Drive at 5 V Low Input Current of 1 uA Max DESCRIPTION Back to Top The 'HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function Y = (A * B)\ or Y = A\ + B\ in positive logic. TECHNICAL DOCUMENTS Back to Top To view the following documents, Acrobat Reader 4.0 is required. To download a document to your hard drive, right-click on the link and choose 'Save'. DATASHEET Back to Top Full datasheet in Acrobat PDF: sn74hc00.pdf (279 KB,Rev.D) (Updated: 12/03/2002) APPLICATION NOTES Back to Top View Application Notes for Digital Logic CMOS Power Consumption and CPD Calculation (Rev. B) (SCAA035B - Updated: 06/01/1997) Designing With Logic (Rev. C) (SDYA009C - Updated: 06/01/1997) Evaluation of Nickel/Palladium/Gold-Finished Surface-Mount Integrated Circuits (SZZA026 - Updated: 06/20/2001) Implications of Slow or Floating CMOS Inputs (Rev. C) (SCBA004C - Updated: 02/01/1998) Input and Output Characteristics of Digital Integrated Circuits (SDYA010 - Updated: 10/01/1996) Live Insertion (SDYA012 - Updated: 10/01/1996) SN54/74HCT CMOS Logic Family Applications and Restrictions (SCLA011 - Updated: 05/01/1996) Selecting the Right Texas Instruments Signal Switch (SZZA030 - Updated: 09/07/2001) file:///E|/042120003_HTML/sn74hc00.html (1 of 4) [25-Apr-03 6:28:02 PM] Product Folder: SN74HC00, Quad 2-Input Positive-NAND Gates TI IBIS File Creation, Validation, and Distribution Processes (SZZA034 - Updated: 08/29/2002) Understanding and Interpreting Texas Instruments Standard-Logic Products Data Sh (Rev. A) (SZZA036A - Updated: 02/27/2003) Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (SCLA008 - Updated: 04/01/1996) Back to Top MORE LITERATURE Enhanced Plastic Portfolio Brochure (SGZB004, 387 KB - Updated: 08/19/2002) Logic Reference Guide (SCYB004, 1032 KB - Updated: 10/23/2001) MicroStar Junior BGA Design Summary (SCET004, 167 KB - Updated: 07/28/2000) Military Brief (SGYN138, 803 KB - Updated: 10/10/2000) Overview of IEEE Std 91-1984, Explanation of Logic Symbols Training Booklet (Rev. A) (SDYZ001A, 138 KB - Updated: 07/01/1996) Palladium Lead Finish User's Manual (SDYV001, 2041 KB - Updated: 11/01/1996) QML Class V Space Products Military Brief (Rev. A) (SGZN001A, 257 KB - Updated: 10/07/2002) Back to Top USER GUIDES LOGIC Pocket Data Book (SCYD013, 4837 KB - Updated: 12/05/2002) Signal Switch Data Book (SCDD003, 10259 KB - Updated: 03/19/2001) Back to Top SAMPLES ORDERABLE DEVICE PACKAGE INDUSTRY (TI) PINS TEMP (C) STATUS PRODUCT CONTENT SAMPLES SN74HC00D SOIC (D) 14 -40 TO 85 ACTIVE View Product Content Request Samples SN74HC00DR SOIC (D) 14 -40 TO 85 ACTIVE View Product Content Request Samples SN74HC00N PDIP (N) 14 -40 TO 85 ACTIVE View Product Content Request Samples SN74HC00NSR SOP (NS) 14 -40 TO 85 ACTIVE View Product Content Request Samples SN74HC00PWR TSSOP (PW) 14 -40 TO 85 ACTIVE View Product Content Request Samples Back to Top PRICING/AVAILABILITY/PKG DEVICE INFORMATION Updated Daily TI INVENTORY STATUS As Of 09:00 AM GMT, 17 Apr 2003 ORDERABLE DEVICE STATUS PACKAGE TYPE | PINS SN74HC00ADBLE OBSOLETE SSOP (DB) | SN74HC00D ACTIVE SOIC (D) | BUDGETARY PRICING QTY | $US TEMP (C) PRODUCT CONTENT 14 -40 TO 85 View Contents 1KU | 14 -40 TO 85 View Contents 1KU | 0.11 STD PACK QTY IN STOCK IN PROGRESS QTY | DATE 0* 50 0* 1953 | 30 Apr >10k | 12 May REPORTED DISTRIBUTOR INVENTORY As Of 09:00 AM GMT, 17 Apr 2003 LEAD TIME DISTRIBUTOR COMPANY | REGION Call** None Reported View Distributors 4 WKS Avnet | Americas >1k Arrow | Americas >1k EBV | Europe Electronik file:///E|/042120003_HTML/sn74hc00.html (2 of 4) [25-Apr-03 6:28:02 PM] IN STOCK >1k DigiKey | Americas >1k Newark | Americas Electronics >1k PURCHASE Product Folder: SN74HC00, Quad 2-Input Positive-NAND Gates SN74HC00DR ACTIVE SOIC (D) | 14 -40 TO 85 View Contents 1KU | 0.11 2500 0* >10k | 28 Apr 2 WKS Avnet | Americas >1k Arrow | Americas >1k EBV | Europe Electronik >1k Abacus Polar | Europe >1k DigiKey | Americas SN74HC00N ACTIVE PDIP (N) | 14 -40 TO 85 View Contents 1KU | 0.11 25 0* 3 | 21 Apr 7 WKS 1100 | 28 Apr 500 | 29 Apr 1000 | 22 May OBSOLETE PDIP (N) ACTIVE SOP (NS) OBSOLETE SOP (NS) SN74HC00NSR ACTIVE SOP (NS) | 14 -40 TO 85 View Contents 1KU | 0.55 2000 0* >10k | 28 Apr 2 WKS SN74HC00PW ACTIVE TSSOP (PW) | 14 -40 TO 85 View Contents 1KU | 0.18 90 0* 450 | 16 Apr 4 WKS SN74HC00N3 SN74HC00NS SN74HC00NSLE | 14 -40 TO 85 View Contents 1KU 0* | Call** SN74HC00PWR OBSOLETE TSSOP (PW) ACTIVE TSSOP (PW) >1k Avnet-SILICA | Europe >1k Avnet | Americas >1k Arrow | Americas >1k >1k DigiKey | Americas >1k Newark | Americas Electronics >1k None Reported View Distributors | View Contents 14 1KU 0* | Call** None Reported View Distributors | 14 -40 TO 85 View Contents 1KU 0* | Call** None Reported View Distributors >10k | 08 May SN74HC00PWLE Avnet-SILICA | Europe EBV | Europe Electronik 8100 | 27 May >1k | 14 -40 TO 85 View Contents 1KU 0* | DigiKey | Americas >1k Arrow | Americas 356 Call** None Reported View Distributors | 14 -40 TO 85 View Contents 1KU | 0.11 2000 0* 2400 | 25 Apr >10k | 28 Apr Table Data Updated on: 4/17/2003 Products | Applications | Support | my.TI (c) Copyright 1995-2002 Texas Instruments Incorporated. All rights reserved. file:///E|/042120003_HTML/sn74hc00.html (3 of 4) [25-Apr-03 6:28:02 PM] 2 WKS Arrow | Americas >1k Avnet | Americas >1k DigiKey | Americas 316 Product Folder: SN74HC00, Quad 2-Input Positive-NAND Gates Trademarks | Privacy Policy | Terms of Use file:///E|/042120003_HTML/sn74hc00.html (4 of 4) [25-Apr-03 6:28:02 PM]