HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 1 - 1999 Hyundai System IC Division
PRELIMINARY
DESCRIPTION
HV7131B is a highly integrated single chip CMOS color image sensor using Hyundai 0.5um CMOS process
developed for image application to realize high efficiency R/G/B photo sensor. The sensor has 648X488 pixel
array, and in general color interpolation method using 3x3 spatial mask with window size 642X482 pixels may
be used for VGA(640X480) display mode. Each compact active pixel element has high photo-sensitivity and
converts photon energy to analog voltage signal. The sensor has three on-chip 8 bit Digital to Analog Convert
(DAC) and 648 comparators to digitize the pixel output. The three on-chip 8 bit DAC can be used for
independent R/G/B gain control. Hyundai proprietary on-chip Correlated Double Sampling (CDS) circuit can
reduce Fixed Pattern Noise (FPN) dramatically. The whole 8 bit digital color raw data is directly available on
the package pins and just a few control signals are needed for whole chip control so that it is very easy to
configure CMOS imaging system.
FEATURES
l 648 x 488 pixels resolution l Full function control through standard I2C bus
l Active pixel size: 8um x 8um l Built-in Automatic Gain Control AGC
l High efficiency R/G/B color photo sensors l 48Pin CLCC / 20Pin CDIP
l Integrated 8-bit ADC for direct digital output l Bayer RGB color pattern
l Low power 3.3V operation (5V tolerant I/O) l Anti-blooming circuit
l Integrated pan control and window sizing l Flexible exposure time control
l Clock speed up to 15MHz l Integrated on-chip timing and drive control
l Programmable frame rate and synchronous format l 1/3" optical format
TECHNICAL SPECIFICATION FUNCTIONAL BLOCK DIAGRAM
Pixel resolution 648x488
Pixel size 8x8um2
Fill factor 30%
Format VGA
Sensitivity 2.2V/lux·sec
Supply voltage for analog 3.3V
Supply voltage for digital 3.3V
Supply voltage for 5V tolerant input 5.0V
Power Consumption @15MHz
Operating temperature 0~40 Centigrade
Technology 0.5um 3metal CMOS
Pixel Array
ADC Block
Line Buffer
Decoder/Pixel Driver
I2C
Control Register & Logic
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 2 - 1999 Hyundai System IC Division
PRELIMINARY
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
l Supply voltage(Analog, Digital) :3.0 V ~3.6 V
l Voltage on any input pins :0 V ~5.0 V
l Operating Temperature(Centigrade) :0~40
l Storage Temperature(Centigrade) :-30 ~80
Note : Input pins are 5V tolerant. Stresses exceeding the absolute maximum ratings may induce failure.
DC Operating Conditions
Symbol Parameter Units Min. Max. Load[pF] Notes
Vdd Internal operation supply voltage Volt 3.0 3.6
Vih Input voltage logic "1" Volt 2.0 56.5
Vil Input voltage logic "0" Volt 00.8 6.5
Voh Output voltage logic "1" Volt 2.15 3.6 60
Vol Output voltage logic "0" Volt 0.4 0.4 60
TaAmbient operating temperature Celsius 0 40
AC Operating Conditions
Symbol Parameter Max Operation Frequency Units Notes
MCLK Main clock frequency 15 MHz 1
SCK I2C clock frequency 400 KHz 2
1. MCLK can be divided according to Clock Divide Register for internal clock.
2. SCK is driven by host processor. For the detail serial bus timing, refer to I2C Spec.
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 3 - 1999 Hyundai System IC Division
PRELIMINARY
ELECTRO-OPTICAL CHARACTERISTICS
color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mmt) is used.
Parameter Units Min. Typical Max. Note
Sensitivity mV / luxžsec 1600 2200 -1)
Dark Signal mV/sec - - 50 2)
Output Saturation Signal mV 1200 - - 3)
Dynamic Range dB - - 48 4)
Output Signal Shading %-8 13 5)
Dark Signal Shading mV/sec - - 10 6)
Frame Rate fps - - 45 7)
Note:
1) Measured at 28lux illumination for exposure time 10 ms.
2) Measured at zero illumination for exposure time 50 ms. (Ttemp = 40 Centigrade)
3) Measured at Vdd =3.3V and 100lux illumination for exposure time 50msec.
4) 48dB is limited by 8-bit ADC.
5) Variance of average value of 4x4 pixels response of each block over all equal blacks at 50%
saturation level illumination for exposure time 10msec.
6) Range between Vmax and Vmin at zero illumination for exposure time 50msec, where Vmax and Vmin
are the maximum and minimum values of each block’s response, respectively.
7) Measured at MCLK 15MHz.
Integration time must be set in order for effective window height not to exceed window height.
It’s because effective window height is directly proportional to integration time.
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 4 - 1999 Hyundai System IC Division
PRELIMINARY
INPUT / OUTPUT AC CHARACTERISTICS
l All output timing delays are measured with output load 60[pF].
l Output delay include the internal clock path delay[6ns] and output driving delay that changes in
respect to the output load, the operating environment, and a board design.
l Due to the variable valid time delay of the output, output signals may be latched in the negative
edge of MCLK for the stable data transfer between the image sensor and a host for less than
15MHz operation.
MCLK to HSYNC/VSYNC Timing
T1 : MCLK rising to HSYNC/VSYNC valid maximum Time : 18ns [output load: 60pF]
T2 : HSYNC/VSYNC valid Time : minimum 1clock(subject to T1, T2 timing rule)
MCLK to DATA Timing
T3 : MCLK rising to DATA Valid maximum Time : 18ns [output load: 60pF]
Note) HSYNC signal is high when valid data is on the DATA bus.
MCLK
HSYNC/VSYNC T2
T1
T1
T3
DATA[7:0] Valid DATA
MCLK
T3
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 5 - 1999 Hyundai System IC Division
PRELIMINARY
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
ENB Timing
T4 : ENB Setup Time : 5[ns]
T5 : ENB Hold Time : 5[ns]
T6 : ENB Valid Time : minimum 2 Clock
RESET Timing
Must in Valid(active low) state at least 8 MCLK periods
MCLK
T5
T4
ENB
T
T6
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 6 - 1999 Hyundai System IC Division
PRELIMINARY
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
I2C Bus (Programming Serial Bus) Timing
I2C Bus Interface Timing
Parameter Symbol Min. Max. Unit
SCK clock frequency fsck 0 400 KHz
Time that I2C bus must be free before a new
transmission can start tbuf 1.2 -us
Hold time for a START thd;sta 1.0 -us
LOW period of SCK tlow 1.2 -us
HIGH period of SCK thigh 1.0 -us
Setup time for START tsu;sta 1.2 -us
Data hold time thd;dat 1.3 -us
Data setup time tsu;dat 250 -ns
Rise time of both SDA and SCK tr-250 ns
Fall time of both SDA and SCK tf-300 ns
Setup time for STOP tsu;sto 1.2 -us
Capacitive load of each bus lines(SDA,SCK) Cb- - pf
SDA
SCK
stop start
tbuftlow
tr
thd;stathd;dat thightsu;dattsu;sta tsu;sto
stopstart
tf thd;sta
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 7 - 1999 Hyundai System IC Division
PRELIMINARY
PIN CONFIGURATION (48 pin CLCC)
Pin9~16, Pin19~20, Pin33~41 : No Connection
COLOR PATTERN
PIN NO. NAME PIN NO. NAME
1SCK 26 DGND
2DGND 27 DATA3
3ENB 28 DATA2
4DGND 29 DATA1
5MCLK 30 DATA0
6VDD5 31 DVDD
7AVDD 32 DGND
8AGND 42 DVDD
17 AGND 43 RESET
18 AVDD 44 VSYNC
21 DGND 45 HSYNC
22 DATA7 46 DGND
23 DATA6 47 SDA
24 DATA5 48 DGND
25 DATA4
origin (0,0)
(647, 487)
DIE pixel array
1 0
646
487
486
Read out
start point
647
RG
GB
RG
GB
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 8 - 1999 Hyundai System IC Division
PRELIMINARY
PIN CONFIGURATION (20 pin CDIP)
COLOR PATTERN
PIN NO. NAME PIN NO. NAME
1AGND 11 DVDD
2DATA 7 12 RESET
3DATA 6 13 VSYNC
4DATA 5 14 HSYNC/DVALID
5DATA 4 15 SDA
6DATA 3 16 SCK
7DATA 2 17 ENB
8DATA 1 18 MCLK
9DATA 0 19 +5V Tolerant
Bias
10 DGND 20 AVDD
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
(647, 487)
DIE
origin (0,0)
active sensing area
487
486
647 646 1 0
RG
GB
RG
GB
Read out
Start Point
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 9 - 1999 Hyundai System IC Division
PRELIMINARY
PIN DESCRIPTION (48 Pin CLCC)
PIN NAME I/O DESCRIPTION
1SCK I I2C clock ; I2C clock control from I2C master
2DGND I Digital Ground
3ENB I Sensor Enable Signal ; 'H' enable normal operation
'L' disable
4DGND I Digital Ground
5MCLK I Master Clock (up to 15MHz)
; Global master clock for image sensor internal timing control
6VDD5 I I/O bias voltage for 5V tolerant *1)
7AVDD I Analog Supply Voltage 3.3V
8AGND I Analog Ground
9 ~ 16 N.C No Connection
17 AGND I Analog Ground
18 AVDD I Analog Supply Voltage 3.3V
19, 20 Reserved Reserved
21 DGND I Digital Ground
22 DATA7 O Image Data bit 7
23 DATA6 O Image Data bit 6
24 DATA5 O Image Data bit 5
25 DATA4 O Image Data bit 4
26 DGND I Digital Ground
27 DATA3 O Image Data bit 3
28 DATA2 O Image Data bit 2
29 DATA1 O Image Data bit 1
30 DATA0 O Image Data bit 0
31 DVDD I Digital Supply Voltage 3.3V
32 DGND I Digital Ground
33 ~ 41 N.C No Connection
42 DVDD I Digital Supply Voltage 3.3V
43 RESET I Hardware Reset Signal, Active Low
44 VSYNC O Vertical synchronization signal / Frame start output
; Signal pulse at start of image data frame with programmable
blanking duration
45 HSYNC
/DVALID O Horizontal synchronization signal / Data valid output
; Data valid when 'H' with programmable blanking duration
46 DGND I Digital Ground
47 SDA I/O I2C Data ; I2C standard data I/O port
48 DGND I Digital Ground
*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 10 - 1999 Hyundai System IC Division
PRELIMINARY
PIN DESCRIPTION (20 Pin CDIP)
PIN NAME I/O DESCRIPTION
1AGND IAnalog Ground
2DATA 7 OImage data bit 7 ( MSB )
3DATA 6 OImage data bit 6
4DATA 5 OImage data bit 5
5DATA 4 OImage data bit 4
6DATA 3 OImage data bit 3
7DATA 2 OImage data bit 2
8DATA 1 OImage data bit 1
9DATA 0 OImage data bit 0 ( LSB )
10 DGND IDigital Ground
11 DVDD IDigital Supply Voltage, 3.3V
12 RESET IHardware Reset Signal, Active Low
13 VSYNC OVertical synchronization signal / Frame start output
; Signal pulse at start of image data frame with programmable
blanking duration
14 HSYNC / DVALID OHorizontal synchronization signal / Data valid output
; Data valid when 'H' with programmable blanking duration
15 SDA I/O I2C Data ; I2C standard data I/O port
16 SCK I I2C Clock ; I2C clock control from I2C master
17 ENB ISensor enable signal ; 'H' enable normal operation
'L' disable sensor by stalling internal clock
18 MCLK IMaster Clock(up to 15MHz)
; Global master clock for image sensor internal timing control
19 + 5 V II/O bias voltage for 5V tolerant *1)
20 AVDD IAnalog Supply Voltage 3.3V
*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 11 - 1999 Hyundai System IC Division
PRELIMINARY
REGISTER DESCRIPTION
MODE_A[8’h00]
Represent device identity. High nibble: Sensor Array Size, Low Nibble: Revision Number
For HV7131B, identity value is 8’h00, [VGA: 0, Revision 0]
MODE_B[8’h01]
This is operating mode select register. Each bit's description is as below.
Bit Function Description
0Integration time unit
Selects integration time unit between line unit and pixel unit. Commonly
line unit is used for its large step control, but under high luminance or when
precise control is needed in the case such as anti-flicker, pixel unit control
is used.
Default is line unit mode[0].
1Single Frame mode
Selects continuous frame output and single frame output. When single shot
mode is selected, only one frame data is produced and the sensor goes to
idle mode.
Default is continuous frame output mode[0].
2Window Mode Selects imaging array size between programmable window size and full
size [648x488]. Default is window size mode[1] and current window default
size is 641x482. [Window size is determined by RowStartAddress, Column
StartAddress, WindowWidth, WindowHeight Registers.]
3HSYNC output mode Selects HSYNC output mode between “data valid mode” and “data valid
with clock mode”.
Default is data valid mode[0].
4,5 Output data type
Selects output data type among (data – reference), data only or reference
only. Internally the sensor produces reference data and image data
respectively, and image data is deducted by reference data in order to
reduce Fixed Pattern Noise. Generally the technique is called Correlated
Double Sampling(CDS).
Default is data - reference (CDS) [00].
6,7 Operation Mode Selects sensor operation mode among normal sensing mode and chip test
related modes. In normal use, the mode should be set to normal mode[00].
Default is normal operation mode[00].
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 12 - 1999 Hyundai System IC Division
PRELIMINARY
MODE_C[8’h02]
This is operating mode select register. Each bit's description is as below
Bit Function Description
1Display Mode Selects Color mode or Black/White Mode
In Black/White mode, gain control is controlled by G Gain Register Value
FRAME SIZE CONTROL REGISTERS
HV7131B may image any user specified window area within image sensor array(648x488). This is called
panning function, and for this function, FRS(Frame Row Start), FCS(Frame Column Start), FWH(Frame
Window Height), and FWW(Frame Window Width) are used. Panning window can be programmed as
below.
Note1) Metal shielded pixel element produce black level data, and effective image array size 646 x 486.
In general, color interpolation algorithm using 3x3 spatial mask for mosaic CFA single sensor require that
pixels around the edge of a programmed image window are used for just color interpolation of neighbor
pixels. Accounting for this fact, image array window should be programmed to larger value than the size
that is to be displayed. For example, in order to make 640X480 24bit color image data, 642X482 pixel
array is necessary.
Note2) You have to change the frame register value as below to get the full 640X480 window size.
{FRSU, FRSL}3{FWHU, FWHL}482
{FCSU, FCSL}3{FWWU, FWWL}642
(647,0)
}
(0,487)
{FWWU, FWWL} {FCSU, FCSL}
{FRSU, FRSL}
Metal Shielding
(1,1)
(0,0)
(646,486)
(647,487)
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 13 - 1999 Hyundai System IC Division
PRELIMINARY
TIMING CONTROL REGISTERS
l HSYNC blank register[8’h20-8’h21]
The HSYNC Blank register defines data blank time between current line and next line by pixel clock unit.
The value programmed to HSYNC blank register defines HSYNC Low Time with (Sensor Array Width –
Window Width) clocks added. For example, if Window Width = 500, HSYNC Blank = 10, then HSYNC
Low Time is HSYNC Blank + (Sensor Array Width – Window Width), 10 + (648 – 500) = 158 clocks.
For more timing details, refer to Frame Timing Diagram section.
l VSYNC blank register[8’h22-8’h23]
The VSYNC blank register defines the active high duration of VSYNC output by pixel clock unit.
The active high VSYNC indicates frame boundary between continuous frames. For VSYNC-HSYNC
timing relation in the frame transition, please refer to Frame Timing Diagram section.
l Integration time value register[8’h25-8’h27]
Integration time value register defines the time during which active pixel element evaluates photon
energy that is converted to digital data output by internal ADC processing. Integration time is equivalent
to exposure time in general camera so that integration time need to be increased in dark environment
and decreased in light environment. Integration time unit is selected between pixel unit and line unit by
MODE_B[0] bit. When line unit mode is selected, only two lower bytes of Integration time value
register[8’h26-8’h27] are accounted in the internal sensor logic because representable maximum
integration time, Maximum Value(216-1) * Sensor Array Width(648) * Clock Period(100ns for 10Mhz) =
4.246 sec, is quite big enough to adapt to any very dark environment. For pixel unit mode, whole three
bytes value are used for integration time, Integration Time Value(8’h25-8’h27) * Clock Period, and
representable maximum value is Maximum Value(224-1) * Clock Period(100ns for 10Mhz) = 1.677sec.
Sensor Array Width(648)
Window Width(500)
Sensor Array Width(648)
Window Width(500)
HSYNC Low Time(158)
HSYNC Blank(10)
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 14 - 1999 Hyundai System IC Division
PRELIMINARY
l Master clock divider register
This four bits register is used to divide external pixel clock for internal use. The actual pixel operating
frequency used in the sensor is the same as external pixel frequency divided by divisor as below.
Register value Divisor Register value Divisor Register value Divisor
0 1 4 16 8 256
1 2 5 32 9 512
2 4 6 64 10 1024
3 8 7 128 11 2048
CHARATERISTICS ADJUSTMENT REGISTERS
Each sensor has a little different photo-diode characteristics so that the sensor provides internal
adjustment registers that calibrate internal sensing circuit in order to get optimal performance. There are
three kinds of registers as below.
l Reset level register[8’h30]
The register controls the voltage level that is initially compared to pixel analog voltage, and the initial
voltage level is called as “reference voltage level”. Internal DAC analog voltage decrements from
reference voltage level until the pixel analog voltage output is lager than DAC analog voltage.
Appropriate reference voltage level varies from various factors, such as process variation, luminance,
etc. If the register value is set to too large or too small value, vertical fixed pattern noise may be
produced. Therefore this register value must be programmed to appropriate value in order to avoid FPN.
For the automatic reset level control, please refer to Reset Level Statistics Register Section. High
register value means high reference voltage and large digital output. Program value range is 0~63,
l RGB gain registers[8’h31-8’h33]
There are three color gain registers for R, G, B pixels, respectively. These registers are used to amplify
digital pixel output . If the gain register value is decreased, digital pixel output is increased. That is,
under dark light condition the pixel output is not enough to get right image so that we must amplify the
output value by decreasing gain value to get good image. These registers may be used for white
balance and color effect with independent R,G,B color control. Program value range is 0~63.
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 15 - 1999 Hyundai System IC Division
PRELIMINARY
l Pixel bias voltage register[8’h34]
The register controls pixel analog voltage decrement degree by controlling bias current of pixel output
sensing load transistor. With the reset level register(8’h30) it is used to adjust ADC circuit output
characteristics. The larger register value causes the higher bias current to increase pixel output
decrement degree, and commonly the register default value is used. Program value range is 0~7.
RSET LEVEL STATISTICS REGISTER
l Low Reset Level Count[8’h57-8’h58]
This two-byte register has a value representing a eighth (1/8) of pixels that have reset value less than 3
during one frame time and is updated when VSYNC gets active. With high reset level counter register it
can be used as a parameter for external automatic reset level control logic that update the appropriate
value in the reset level register to automatically compensate die to die overall reset level variation.
l High Reset Level Count[8’h59-8’h5a]
This two byte register has a value representing a eighth (1/8) of pixels that have reset value larger than
123 during one frame time and is updated when VSYNC gets active. With low reset level counter register
it can be used as a parameter for external automatic reset level control logic that update the appropriate
value in the reset level (30H) register to automatically compensate die to die overall reset level variation.
RGB OFFSET REGISTERS[8’h50-8’h52]
These registers control offset value of RGB digital output to make color effect. Normally these register
values are set to default zero.
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 16 - 1999 Hyundai System IC Division
PRELIMINARY
REGISTER ADDRESS AND DEFAULT VALUE
Group Symbol Address Description
MODE_A 00H Device Identity (Read only : 00H )
Operating Mode Selection ( Default : 04H )
b0 0 Line Unit Integration
1Pixel Unit Integration
b1 0 Continuous Frame
1Single Shot Frame
b2 0 Full Image (648X488)
1Windowed Image
b3 0 HSYNC only
1HSYNC & Internal Clock
b5 b4 Output Data Type
0 0 Data_Level - Reference_Level
0 1 Reference_Level
1 0 Data_Level
1 1 reserved
b7 b6 Operating Mode
0 0 Normal Mode
0 1 Reserved
1 0 Reserved
1 1 Reserved
MODE_B
01H
b1 0 Color Output
1Black & White Output
Mode-
Registers
MODE_C 02H
Internal
Test
Register
53H, 55H, 56H,
60H, 61H
[ Reserved]
Test Registers for Image Sensor Future Enhancement
[These register should not be used in normal operation]
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 17 - 1999 Hyundai System IC Division
PRELIMINARY
REGISTER ADDRESS AND DEFAULT VALUE ( continue )
Group Symbol Address Description
FRSU 10H Row Start Address (Upper byte ) Default : 00H
FRSL 11H Row Start Address ( Lower byte ) 03H[3]
FCSU 12H Column start Address ( Upper byte ) 00H
FCSL 13H Column start Address ( Lower byte ) 03H[3]
FWHU 14H Window Height ( Upper byte ) 01H
FWHL 15H Window Height ( Lower byte ) E2H[482]
FWWU 16H Window Width ( Upper byte ) 02H
Frame-
Registers
FWWL 17H Window Width ( Lower byte ) 81H[641]
THBU 20H HSYNC Blanking Duration value ( Upper byte ) Default :00H
THBL 21H HSYNC Blanking Duration value ( Lower byte ) 03H
TVBU 22H VSYNC Blanking Duration value ( Upper byte ) 00H
TVBL 23H VSYNC Blanking Duration value ( Lower byte ) 03H
TITU 25H Integration Time value ( Upper byte ) 00H
TITM 26H Integration Time value ( Middle byte ) 01H
TITL 27H Integration Time value ( Lower byte ) F4H
Timing-
Register
TMCD 28H Master Clock Divider 00H
ARLV 30H Reset Level Value 38H
ARCG 31H Red Color Gain 1EH
AGCG 32H Green Color Gain 1EH
ABCG 33H Blue Color Gain 1EH
Adjust-
Register
APBV 34H Pixel Bias Voltage Control 02H
OFSR 50H R Offset Register 00H
OFSG 51H G offset Register 00H
Offset
Register
OFSB 52H B offset Register 00H
LoREfNOH 57H Low Reset Level Counter [<3] (Upper byte) (Read Only)
LoREfNOL 58H Low Reset Level Counter [<3] (Lower byte) (Read Only)
HiRefNOH 59H High Reset Level Counter [>123] (Upper byte) (Read Only)
Reset
Level
Statistics
Register
HiRefNOL 59HHigh Reset Level Counter [>123] (Lower byte) (Read Only)
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 18 - 1999 Hyundai System IC Division
PRELIMINARY
PROGRAMMING SEQUENCE FOR CMOS IMAGE SENSOR
l Single Register Byte Programming
S22H A01H Amode inform A P
*1 *2 *3 *4 *5 *6 *7 *8
ð Set "Operating Mode" register into Window mode
*1. Drive: I2C start condition
*2. Drive: 22H(001_0001 + 0) [device address + R/W bit]
*3. Read: acknowledge from sensor
*4. Drive: 01H [sub-address]
*5. Read: acknowledge from sensor
*6. Drive:
*7. Read: acknowledge from sensor
*8. Drive:
l Multiple Register Byte Programming using Auto increment Mode
S22H A01H A02H A65H A P
*1 *2 *3 *4 *5 *6 *7 *8 *9 *10
ð You can program multiple configuration registers with single I2C bus cycle.
ð Set "Row Start Address" register as 265H
*1. Drive: I2C start condition
*2. Drive: 22H(001_0001 + 0) [device address + R/W bit]
*3. Read: acknowledge from sensor
*4. Drive: 10H [sub-address]
*5. Read: acknowledge from sensor
*6. Drive: 02H [row start address upper byte]
*7. Read: acknowledge from sensor
*8. Drive: 65H [row start address lower byte]
*9. Read: acknowledge from sensor
*10. Drive
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 19 - 1999 Hyundai System IC Division
PRELIMINARY
PROGRAMMING SEQUENCE FOR CMOS IMAGE SENSOR ( continue )
l Reading Register Value
S22H A01H A S 23H ARead Data A P
*1 *2 *3 *4 *5 *6 *7 *8 *9 *10
ð Single Read or Auto-Increment Read
ð Set "Reset Level Value" register
*1. Drive: I2C start condition
*2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)]
*3. Read: acknowledge from sensor
*4. Drive: 10H [sub-address]
*5. Read: acknowledge from sensor
*6. Drive: I2C start condition
*7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)]
*8. Read: acknowledge from sensor
*9. Read: Read Data from sensor
*10. Drive: acknowledge to sensor(if there is no more read data Ack=1, else Ack=0)
*11. Drive
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 20 - 1999 Hyundai System IC Division
PRELIMINARY
FRAME TIMING DIAGRAMS
There are two frame timing cases,
l Integration Time < EffectiveWindowHeight * Scale
l Integration Time > EffectiveWindowHeight * Scale
EffectiveWindowHeight is equal to the number of data lines generated in a frame and is defined to be selected
by
if((RowStartAddress + WindowHeight + 1) <= SensorArrayHeight)
EffectiveWindowHeight = WindowHeight;
else EffectiveWidnowHeight = (SensorArrayHeight - RowStartAddress - 1);
The above selection logic is somewhat confusing in respect of general counting measure. It’s partly due to the
mixed use of indexing start points, i.e. ‘0’ and ‘1’ in the chip design. Therefore in order to avoid the confusion
it is desirable to just follows the equation when you estimate the frame rate.
For example, RowStartAddress = 200 and WindowHeight = 400, EffectiveWindowHeight is 287 and 287 data
lines per a frame are generated.
Scale is selected according to Integration Time Mode by
If(PixelMode) Scale = SensorArrayWidth; // For H7131B[648x488], SensorArrayWidth is 648
else Scale = 1;
When Integration Time > (EffectiveWindowHeight * Scale), next frame VSYNC does not follow
immediately after current frame’s last line has been produced. Instead, one of the following two idle time
slots is inserted according to Integration Time Mode before next frame VSYNC gets active.
SensorArrayHeight
[488]
SensorArrayWidth
[648]
RowStartAddress
[200]
WindowHeight
[400]
EffectiveWindowHeight
[287]
(0,0)
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 21 - 1999 Hyundai System IC Division
PRELIMINARY
< Idle Slots >
l Line Mode: (Integration Time - EffectiveWindowHeight) * 1024 clks
l Pixel Mode: (Integration Time - EffectiveWindowHeight *Scale)
= (Integration Time - EffectiveWindowHeight *SensorArrayWidth) clks
Each Frame Timing of the above cases may be decomposed into four timing segments
l Initial Data Setup Time after ENB gets active
l Even Line
l Odd Line
l Frame Transition
The subsections will describe frame timing diagram for said frame time cases, (Integration Time <
Effective Window Height * Scale) and (Integration Time > Effective Window Height * Scale).
1. Frame Timing Diagram for Integration Time < (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress = 3; WindowHeight = 482;
ColumnStartAddress = 3; WindowWidth = 642;
IntegrationTime = 400 [Line Mode];
EffectiveWindowHeight is “482” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e.
488 > (3 + 482 + 1), is met, and Scale is “1” for integration time is line mode. Therefore, (Integration Time
< EffectiveWindowHeight * Scale), i.e. 400 < 482 * 1, is met.
Overall Frames Sequence
Initial Data Setup Time
Line 0
Line 1
, Line 2
Line 480
....
Line 481
VSYNC
Line 0
Line 1
, Line 2
Line 480
....
Line 481
VSYNC
Line 0
Line 1
, Line 2
Line 480
....
Line 481
VSYNC
....
Frame 1 Frame 2Frame 0
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 22 - 1999 Hyundai System IC Division
PRELIMINARY
MCLK
ENB
VSYNC
Delay
Slots Fig. 1 Initial Data Setup Time after ENB gets active
MCLK
HSYNC
DATA
Time
Slot
Clock
Ruler
Fig.2 Even Line Data Timing
IMAGE RAW DATA
Window Width
642 clks
R
R
ENB
Deglitch
2 clocks
Sensor Reset
SensorArrayHeight clocks
[488 clocks]
One Line Time Delay
(SensorArrayWidth +
HBLANK) clocks
[651 clocks]
VSYNC
3 clocks
Integration Time *
Scale clocks
[400 * 648 clocks]
Line Head
Blank
3 clks
HBLANK
3 clks
R
G
G
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
R
G
R
G
R
G
⋅
Line Tail
Blank
3 clks
SensorArrayWidth (648)
HBLANK(3)
G
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 23 - 1999 Hyundai System IC Division
PRELIMINARY
MCLK
HSYNC
DATA
Time
Slot
Clock
Ruler
Fig.3 Odd Line Data Timing
MCLK
HSYNC
VSYNC
DATA
Time
Slot
Integration Time < EffectiveWindowHeight * Scale
Fig.4 Frame Transition Timing
R
G
R
.
.
.
R
.
G
G
B
.
B
.
Line Head
Blank
3 clks
Line Tail
Blank
3 clks
IMAGE RAW DATA
Window Width
642 clks
IMAGE RAW DATA
Window Width
642 clks
HBLANK
3 clks
G
B
G
B
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
G
B
G
B
G
B
⋅
Line Tail
Blank
3 clks
Line Head
Blank
3 clks
SensorArrayWidth (648)
HBLANK(3)
G
G
B
.
G
IMAGE RAW DATA
Window Width
642 clks
VSYNC
3 clks
≈
≈
HBLANK
3 clks
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 24 - 1999 Hyundai System IC Division
PRELIMINARY
2. Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress = 3; WindowHeight = 482;
ColumnStartAddress = 3; WindowWidth = 642;
IntegrationTime = 600 [Line Mode];
EffectiveWindowHeight is “482” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e.
488 > (3 + 482 + 1), is met, and Scale is “1” for integration time is line mode. Therefore, (Integration Time
< EffectiveWindowHeight * Scale), i.e. 600 > 482 * 1, is met, and Idle Slot of Line Mode, i.e. (600 - 482) *
1024 clocks idle slot, is inserted before the next frame initiation.
Overall Frames Sequence
MCLK
ENB
VSYNC
Delay
Slots
Fig. 5 Initial Data Setup Time after ENB gets active
Line 481
ENB
Deglitch
2 clocks
Sensor Reset
SensorArrayHeight clocks
[488 clocks]
One Line Time Delay
(SensorArrayWidth +
HBLANK) clocks
[651 clocks]
VSYNC
3 clocks
Integration Time *
Scale clocks
[600 * 648 clocks]
Initial Data Setup Time
Line 1
, Line 2
Line 480
....
Line 481
Line 0
Line 1
, Line 2
Line 480
....
VSYNC
Line 0
Line 1
, Line 2
Line 480
....
Line 481
VSYNC
Idle Time
Line 0
VSYNC
Idle Time
Idle Time
Frame 1 Frame 2Frame 0
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 25 - 1999 Hyundai System IC Division
PRELIMINARY
MCLK
HSYNC
DATA
Time
Slot
Clock
Ruler
Fig.6 Even Line Data Timing
MCLK
HSYNC
DATA
Time
Slot
Clock
Ruler
Fig.7 Odd Line Data Timing
IMAGE RAW DATA
Window Width
642 clks
R
R
Line Head
Blank
3 clks
Line Head
Blank
3 clks
IMAGE RAW DATA
Window Width
642 clks
HBLANK
3 clks
HBLANK
3 clks
R
G
G
B
G
G
B
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
R
G
G
B
R
G
G
B
R
G
G
B
⋅
⋅
Line Tail
Blank
3 clks
Line Tail
Blank
3 clks
SensorArrayWidth (648)
SensorArrayWidth (648)
HBLANK(3)
HBLANK(3)
G
B
G
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 26 - 1999 Hyundai System IC Division
PRELIMINARY
MCLK
HSYNC
VSYNC
DATA
Time
Slot
Integration Time > EffectiveWindowHeight * Scale
Fig.8 Frame Transition Timing
R
.
.
.
R
G
G
B
G
B
.
Line Tail
Blank
IMAGE RAW DATA
Window Width
Line Head
Blank
.
G
IMAGE RAW DATA
Window Width
VSYNC
3 clks
≈≈
Idle Slot
(Integration Time -
HBLANK
3 clks
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 27 - 1999 Hyundai System IC Division
PRELIMINARY
PACKAGE DISMENSION (48 PIN CLCC) UNIT: mm
* C : Center of Image Area
0.53
±
0.15
0.98
±
0.15
C
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 28 - 1999 Hyundai System IC Division
PRELIMINARY
PACKAGE DIMENSION (20 PIN CDIP) UNIT: mm
0.53±0.15
0.98±0.15
1.27 +- 0.05 0.30 +- 0.10
2.60 +- 0.30
0.25
16.00 +- 0.12
12.00 +- 0.10
14.94 +- 0.11 15.24 +- 0.30
1.27 +- 0.25
5.00
0.46 +- 0.10
C
HV7131B
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
System IC Division
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 29 - 1999 Hyundai System IC Division
PRELIMINARY
MEMO
Hyundai Electronics Industries Co., Ltd
System IC Division
Headquarter & Factory
San 136-1,Ami-Ri,Bubal-Eub,Ichon-Si,Kyoungki-Do,Korea 467-860
Tel : 82-336-630-2042/2484, Fax : 82-336-639-1412, E-mail : wkkim@hei.co.kr