DSP56F805/D Rev. 6.0, 8/2001 Semiconductor Products Sector DSP56F805 Preliminary Technical Data DSP56F805 16-bit Digital Signal Processor * Up to 40 MIPS at 80 MHz core frequency * * DSP and MCU functionality in a unified, C-efficient architecture Up to 64K x 16-bit words each of external program and data memory * Two 6-channel PWM Modules * Hardware DO and REP loops * Two 4-channel, 12-bit ADCs * MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes * Two Quadrature Decoders * CAN 2.0 B Module * Two Serial Communication Interfaces (SCIs) * Serial Peripheral Interface (SPI) * 31.5K x 16-bit words Program Flash * 512 x 16-bit words Program RAM * 4K x 16-bit words Data Flash * Up to four General Purpose Quad Timers * 2K x 16-bit words Data RAM * JTAG/OnCETM port for debugging * 2K x 16-bit words Boot Flash * 14 Dedicated and 18 Shared GPIO lines * 144-pin LQFP Package 6 3 4 PWM Outputs Current Sense Inputs 4 4 4 PWM Outputs IRQB A/D1 A/D2 VREF VPP VCAPC VDD 6 2 8 VSS VDDA VSSA 8 PWMB JTAG/ OnCE Port Fault Inputs Digital Reg Analog Reg Low Voltage Supervisor ADC 4 4 Quadrature Decoder 1 / Quad B Timer Interrupt Controller Program Memory 32252 x 16 Flash 512 x 16 SRAM Quad Timer C 2 Quad Timer D / Alt Func CAN 2.0A/B 2 2 SCI0 or GPIO 2 SCI1 or GPIO 4 SPI or GPIO 14 EXTBOOT IRQA Quadrature Decoder 0 / Quad A Timer 4 RSTO RESET Fault Inputs 6 Current Sense Inputs 3 PWMA Dedicated GPIO Program Controller and Hardware Looping Unit * PDB * 16-Bit DSP56800 Core XDB2 * CGDB XAB1 XAB2 * * INTERRUPT CONTROLS 16 COP/ Watchdog ApplicationSpecific Memory & Peripherals XTAL Clock Gen EXTAL * IPBB CONTROLS 16 COP RESET MODULE CONTROLS ADDRESS BUS [8:0] CLKO PLL * IPBus Bridge (IPBB) External Bus Interface Unit DATA BUS [15:0] Figure 1. DSP56F805 Block Diagram (c) Motorola, Inc., 2001. All rights reserved. Bit Manipulation Unit PAB * Boot Flash 2048 x 16 Flash Data Memory 4096 x 16 Flash 2048 x 16 SRAM Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Address Generation Unit External Address Bus Switch External Data Bus Switch Bus Control A[00:05] 6 10 A[06:15] or GPIO-E2:E3 & GPIO-A0:A7 D[00:15] 16 PS Select DS Select WR Enable RD Enable Part 1 Overview 1.1 DSP56F805 Features 1.1.1 Digital Signal Processing Core * Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture * As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency * Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) * Two 36-bit accumulators, including extension bits * 16-bit bidirectional barrel shifter * Parallel instruction set with unique DSP addressing modes * Hardware DO and REP loops * Three internal address buses and one external address bus * Four internal data buses and one external data bus * Instruction set supports both DSP and controller functions * Controller style addressing modes and instructions for compact code * Efficient C compiler and local variable support * Software subroutine and interrupt stack with depth limited only by memory * JTAG/OnCE debug programming interface 1.1.2 Memory * Harvard architecture permits as many as three simultaneous accesses to program and data memory * On-chip memory including a low cost, high volume flash solution -- 31.5K x 16 bit words of Program Flash -- 512 x 16-bit words of Program RAM -- 4Kx 16-bit words of Data Flash -- 2K x 16-bit words of Data RAM -- 2K x 16-bit words of Boot Flash * Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states -- As much as 64K x 16 bits of data memory -- As much as 64K x 16 bits of program memory 1.1.3 2 Peripheral Circuits for DSP56F805 * Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four Fault inputs, fault tolerant design with dead-time insertion; supports both center- and edgealigned modes * Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions; ADC and PWM modules can be synchronized * Two Quadrature Decoders each with four inputs or two additional Quad Timers DSP56F805 Preliminary Technical Data DSP56F805 Description * Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins * CAN 2.0 B Module with 2-pin port for transmit and receive * Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines) * Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines) * 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins * Computer Operating Properly (COP) watchdog timer * Two dedicated external interrupt pins * External reset input pin for hardware reset * External reset output pin for system reset * JTAG/On-Chip Emulation (OnCETM) module for unobtrusive, processor speed-independent debugging * Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock 1.1.4 Energy Information * Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs * Uses a single 3.3V power supply * On-chip regulators for digital and analog circuitry to lower cost and reduce noise * Wait and Stop modes available 1.2 DSP56F805 Description The DSP56F805 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the DSP56F805 is well-suited for many applications. The DSP56F805 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation. The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both MCU and DSP applications. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The DSP56F805 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The DSP56F805 also provides two external dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The DSP56F805 DSP controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data flash (each programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It also supports program execution from external memory (64K). DSP56F805 Preliminary Technical Data 3 The DSP56F805 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of fieldprogrammable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased. Key application-specific features of the DSP56F805 include the two Pulse Width Modulator (PWM) modules. These modules each incorporate three complementary, individually programmable PWM signal outputs (each module is also capable of supporting six independent PWM functions for a total of 12 PWM outputs) to enhance motor control functionality. Complementary operation permits programmable deadtime insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. A "smoke-inhibit", writeonce protection feature for key parameters and a patented PWM waveform distortion correction circuit are also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to synchronize the ADCs. The DSP56F805 incorporates two separate Quadrature Decoders capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer in the Quadrature Decoder can be programmed with a timeout value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This DSP controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller and 14 dedicated GPIO are also included on the DSP56F805. 1.3 "Best in Class" Development Environment The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique C application code independent of component architecture. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of Evaluation Modules (EVMs) and development system cards support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 4 DSP56F805 Preliminary Technical Data Product Documentation 1.4 Product Documentation The four documents listed in Table 1 are required for a complete description and proper design with the DSP56F805. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/dsp. Table 1. DSP56F805 Chip Documentation Topic Description Order Number DSP56800 Family Manual Detailed description of the DSP56800 family architecture, and 16-bit DSP core processor and the instruction set DSP56800FM/D DSP56F801/803/805/807 User's Manual Detailed description of memory, peripherals, and interfaces of the DSP56F801, DSP56F803, DSP56F805, and DSP56F807 DSP56F801-7UM/D DSP56F805 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56F805/D DSP56F805 Product Brief Summary description and block diagram of the DSP56F805 core, memory, peripherals and interfaces DSP56F805PB/D 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. "asserted" A high true (active high) signal is high or a low true (active low) signal is low. "deasserted" A high true (active high) signal is low or a low true (active low) signal is high. Examples: 1. Signal/Symbol Logic State Signal State Voltage1 PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. DSP56F805 Preliminary Technical Data 5 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the DSP56F805 are organized into functional groups, as shown in Table 2 and as illustrated in Figure 2. In Table 3 through Table 19, each table row describes the signal or signals present on a pin. Table 2. Functional Group Pin Allocations Functional Group Number of Pins Detailed Description Power (VDD or VDDA) 9 Table 3 Ground (VSS or VSSA) 9 Table 4 Supply Capacitors and VPP 3 Table 5 PLL and Clock 3 Table 2.3 Address Bus1 16 Table 7 Data Bus 16 Table 8 Bus Control 4 Table 9 Interrupt and Program Control 5 Table 10 Dedicated General Purpose Input/Output 14 Table 11 Pulse Width Modulator (PWM) Port 26 Table 12 Serial Peripheral Interface (SPI) Port1 4 Table 13 Quadrature Decoder Port2 8 Table 14 Serial Communications Interface (SCI) Port1 4 Table 15 CAN Port 2 Table 16 Analog to Digital Converter (ADC) Port 9 Table 17 Quad Timer Module Ports 6 Table 18 JTAG/On-Chip Emulation (OnCE) 6 Table 19 1. 2. 6 Alternately, GPIO pins Alternately, Quad Timer pins DSP56F805 Preliminary Technical Data Introduction Power Port Ground Port VDD 8 VSS Power Port VDDA Ground Port VSSA 8 8 6 GPIOB0-7 GPIOD0-5 Dedicated GPIO 1 1 Other Supply Ports VCAPC PLL and Clock EXTAL VPP 6 3 2 4 PWMA0-5 ISA0-2 FAULTA0-3 PWMA Port 1 6 1 XTAL 1 CLKO 3 DSP56F805 4 PWMB0-5 ISB0-2 FAULTB0-3 PWMB Port 1 1 A0-A5 External Address Bus or GPIO 6 A6-7 (GPIOE2-E3) 2 A8-15 (GPIOA0-A7) 8 External Data Bus 1 1 1 D0-D15 16 1 1 PS SCLK (GPIOE4) MOSI (GPIOE5) MISO (GPIOE6) SPI Port or GPIO SS (GPIOE7) TXD0 (GPIOE0) RXD0 (GPIOE1) SCI0 Port or GPIO 1 External Bus Control DS RD WR PHASEA0 (TA0) Quadrature Decoder0 or Quad Timer A PHASEB0 (TA1) INDEX0 (TA2) HOME0 (TA3) PHASEA1 (TB0) Quadrature Decoder1 or Quad Timer B PHASEB1 (TB1) INDEX1 (TB2) HOME1 (TB3) TCK JTAG/OnCE Port 1 1 1 1 TXD1 (GPIOD6) RXD1 (GPIOD7) SCI1 Port or GPI0 1 8 1 1 ANA0-7 (GPIOC6) VREF ADCA Port 1 1 1 1 1 1 MSCAN_RX MSCAN_TX CAN 1 1 1 2 4 TC0-1 TD0-3 Quad Timers C&D 1 TMS 1 TDI 1 TDO 1 TRST 1 1 DE 1 1 1 1 1 IRQA IRQB RESET RSTO Interrupt/ Program Control EXTBOOT Figure 2. DSP56F805 Signals Identified by Functional Group1 1. Alternate pin functionality is shown in parenthesis. DSP56F805 Preliminary Technical Data 7 2.2 Power and Ground Signals Table 3. Power Inputs No. of Pins Signal Name 8 VDD Power--These pins provide power to the internal structures of the chip, and should all be attached to VDD. 1 VDDA Analog Power--These pins supply an analog power source. Signal Description Table 4. Grounds No. of Pins Signal Name 7 VSS GND--These pins provide grounding for the internal structures of the chip, and should all be attached to VSS. 1 VSSA Analog Ground--This pin supplies an analog ground. 1 TCS TCS--This pin is reserved for factory use and must be tied to VSS for normal use. In block diagrams, this pin is considered an additional VSS. Signal Description Table 5. Supply Capacitors and VPP State During Reset No. of Pins Signal Name Signal Type 2 VCAPC Supply Supply VCAPC - Connect each pin to a 2.2F bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. For more information, please refer to Section 5.2. 1 VPP Input Input VPP - This pin should be left unconnected as an open circuit for normal functionality. Signal Description 2.3 Clock and Phase Lock Loop Signals Table 6. PLL and Clock No. of Pins Signal Name Signal Type State During Reset 1 EXTAL Input Input Signal Description External Crystal Oscillator Input--This input can be connected to an 8 MHz external crystal. If an 8MHz or less external clock source is used, EXTAL can be used as the input and XTAL must not be connected. For more information, please refer to Section 3.5.2. This input can also be connected to an external 8 MHz clock. For more information, please refer to Section 3.5. The input clock can be selected to provide the clock directly to the DSP core. This input clock can also be selected as input clock for the on-chip PLL. 8 DSP56F805 Preliminary Technical Data Address, Data, and Bus Control Signals Table 6. PLL and Clock (Continued) State During Reset No. of Pins Signal Name Signal Type 1 XTAL Output Chipdriven Crystal Oscillator Output--This output connects the internal crystal oscillator output to an external crystal. If an external clock source over 8MHz is used, XTAL must be used as the input and EXTAL connected to GND. For more information, please refer to Section 3.5.2. 1 CLKO Output Chipdriven Clock Output--This pin outputs a buffered clock signal. By programming the CS[1:0] bits in the PLL Control Register (PCR1), the user can select between outputting a version of the signal applied to XTAL and a version of the DSP master clock at the output of the PLL. The clock frequency on this pin can also be disabled by programming the CS[1:0] bits in PCR1. Signal Description 2.4 Address, Data, and Bus Control Signals Table 7. Address Bus Signals No. of Pins Signal Name Signal Type State During Reset 6 A0-A5 Output Tri-stated Address Bus--A0-A5 specify the address for external program or data memory accesses. 2 A6-A7 Output Tri-stated Address Bus--A6-A7 specify the address for external program or data memory accesses. GPIOE2- GPIOE3 Input/ Output Signal Description Input Port E GPIO--These two General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. 8 A8-A15 Output GPIOA0- GPIOA7 Input/ Output Tri-stated Address Bus--A8-A15 specify the address for external program or data memory accesses. Input Port A GPIO--These eight General Purpose I/O (GPIO) pins can be individually be programmed as input or output pins. After reset, the default state is Address Bus. Table 8. Data Bus Signals No. of Pins Signal Name Signal Type 16 D0-D15 Input/ Output State During Reset Tri-stated Signal Description Data Bus-- D0-D15 specify the data for external program or data memory accesses. D0-D15 are tri-stated when the external bus is inactive. DSP56F805 Preliminary Technical Data 9 Table 9. Bus Control Signals State During Reset Signal Description Output Tristated Program Memory Select--PS is asserted low for external program memory access. DS Output Tristated Data Memory Select--DS is asserted low for external data memory access. 1 WR Output Tristated Write Enable--WR is asserted during external memory write cycles. When WR is asserted low, pins D0-D15 become outputs and the DSP puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0-A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM. 1 RD Output Tristated Read Enable--RD is asserted during external memory read cycles. When RD is asserted low, pins D0-D15 become inputs and an external device is enabled onto the DSP data bus. When RD is deasserted high, the external data is latched inside the DSP. When RD is asserted, it qualifies the A0-A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Internal pullups may be active. No. of Pins Signal Name Signal Type 1 PS 1 2.5 Interrupt and Program Control Signals Table 10. Interrupt and Program Control Signals No. of Pins Signal Name Signal Type State During Reset 1 IRQA Input Input External Interrupt Request A--The IRQA input is a synchronized external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. 1 IRQB Input Input External Interrupt Request B--The IRQB input is an external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. 1 RESET Input Input Reset--This input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. Signal Description To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the OnCE/ JTAG module. In this case, assert RESET, but do not assert TRST. 10 1 RSTO Output Output 1 EXTBOOT Input Input Reset Output--This output reflects the internal reset state of the chip. External Boot--This input is tied to VDD to force device to boot from offchip memory. Otherwise, it is tied to VSS. DSP56F805 Preliminary Technical Data GPIO Signals 2.6 GPIO Signals Table 11. Dedicated General Purpose Input/Output (GPIO) Signals No. of Pins Signal Name Signal Type 8 GPIOB0- GPIOB7 Input or Output State During Reset Input Signal Description Port B GPIO--These eight dedicated General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is GPIO input. 6 GPIOD0- GPIOD5 Input or Output Input Port D GPIO--These six dedicated GPIO pins can be individually programmed as an input or output pins. After reset, the default state is GPIO input. 2.7 Pulse Width Modulator (PWM) Signals Table 12. Pulse Width Modulator (PWMA and PWMB) Signals State During Reset No. of Pins Signal Name Signal Type 6 PWMA0-5 Output Tristated PWMA0-5--These are six PWMA output pins. 3 ISA0-2 Input Input ISA0-2--These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA. 4 FAULTA0-3 Input Input FAULTA0-3--These four Fault input pins are used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. 6 PWMB0-5 Output Output 3 ISB0-2 Input Input ISB0-2-- These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMB. 4 FAULTB0-3 Input Input FAULTB0-3--These four Fault input pins are used for disabling selected PWMB outputs in cases where fault conditions originate off-chip. Signal Description PWMB0-5--These are six PWMB output pins. DSP56F805 Preliminary Technical Data 11 2.8 Serial Peripheral Interface (SPI) Signals Table 13. Serial Peripheral Interface (SPI) Signals State During Reset No. of Pins Signal Name Signal Type 1 MISO Input/ Output Input GPIOE6 Input/ Output Input Signal Description SPI Master In/Slave Out (MISO)--This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is MISO. 1 MOSI Input/ Output Input SPI Master Out/Slave In (MOSI)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. GPIOE5 Input/ Output Input Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin. After reset, the default state is MOSI. 1 SCLK Input/ Output Input SPI Serial Clock--In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. GPIOE4 Input/ Output Input Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin. After reset, the default state is SCLK. 1 SS Input Input SPI Slave Select--In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. GPIOE7 Input/ Output Input Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as input or output pin. After reset, the default state is SS. 12 DSP56F805 Preliminary Technical Data Quadrature Decoder Signals 2.9 Quadrature Decoder Signals Table 14. Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals No. of Pins Signal Name Signal Type State During Reset 1 PHASEA0 Input Input Phase A--Quadrature Decoder #0 PHASEA input TA0 Input/Output Input TA0--Timer A Channel 0 PHASEB0 Input Input Phase B--Quadrature Decoder #0 PHASEB input TA1 Input/Output Input TA1--Timer A Channel 1 INDEX0 Input Input Index--Quadrature Decoder #0 INDEX input TA2 Input/Output Input TA2--Timer A Channel 2 HOME0 Input Input Home--Quadrature Decoder #0 HOME input TA3 Input/Output Input TA3--Timer A Channel 3 PHASEA1 Input Input Phase A--Quadrature Decoder #1 PHASEA input TB0 Input/Output Input TB0--Timer B Channel 0 PHASEB1 Input Input Phase B--Quadrature Decoder #1 PHASEB input TB1 Input/Output Input TB1--Timer B Channel 1 INDEX1 Input Input Index--Quadrature Decoder #1 INDEX input TB2 Input/Output Input TB2--Timer B Channel 2 HOME1 Input Input Home--Quadrature Decoder #1 HOME input TB3 Input/Output Input TB3--Timer B Channel 3 1 1 1 1 1 1 1 Signal Description DSP56F805 Preliminary Technical Data 13 2.10 Serial Communications Interface (SCI) Signals Table 15. Serial Communications Interface (SCI0 and SCI1) Signals No. of Pins Signal Name Signal Type State During Reset 1 TXD0 Output Input Transmit Data (TXD0)--transmit data output GPIOE0 Input/ Output Input Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Signal Description After reset, the default state is SCI output. 1 RXD0 Input Input Receive Data (RXD0)-- receive data input GPIOE1 Input/ Output Input Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI input. 1 TXD1 Output Input Transmit Data (TXD1)--transmit data output GPIOD6 Input/ Output Input Port D GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI output. 1 RXD1 Input Input Receive Data (RXD1)--receive data input GPIOD7 Input/ Output Input Port D GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI input. 2.11 CAN Signals Table 16. CAN Module Signals No. of Pins Signal Name Signal Type State During Reset 1 MSCAN_ RX Input Input 1 MSCAN_ TX Output Output 14 Signal Description MSCAN Receive Data--MSCAN input. This pin has an internal pull-up resistor. MSCAN Transmit Data--MSCAN output. CAN output is open-drain output and pull-up resistor is needed. DSP56F805 Preliminary Technical Data Analog-to-Digital Converter (ADC) Signals 2.12 Analog-to-Digital Converter (ADC) Signals Table 17. Analog to Digital Converter Signals No. of Pins Signal Name Signal Type State During Reset 4 ANA0-3 Input Input ANA0-3--Analog inputs to ADC channel 1 4 ANA4-7 Input Input ANA4-7--Analog inputs to ADC channel 2 1 VREF Input Input VREF--Analog reference voltage Signal Description 2.13 Quad Timer Module Signals Table 18. Quad Timer Module Signals No. of Pins Signal Name Signal Type State During Reset 2 TC0-1 Input/Output Input TC0-1--Timer C Channels 0 and 1 4 TD0-3 Input/Output Input TD0-3--Timer D Channels 0, 1, 2, and 3 Signal Description 2.14 JTAG/OnCE Table 19. JTAG/On-Chip Emulation (OnCE) Signals No. of Pins Signal Name Signal Type State During Reset 1 TCK Input Input, pulled low internally Test Clock Input--This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor. 1 TMS Input Input, pulled high internally Test Mode Select Input--This input pin is used to sequence the JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. 1 TDI Input Input, pulled high internally Test Data Input--This input pin provides a serial input data stream to the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an onchip pull-up resistor. 1 TDO Output Tri-stated 1 TRST Input Input, pulled high internally 1 DE Output Output Signal Description Test Data Output--This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. Test Reset--As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. Debug Event--DE provides a low pulse on recognized debug events. DSP56F805 Preliminary Technical Data 15 Part 3 Specifications 3.1 General Characteristics The DSP56F805 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5Vcompatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 20 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The DSP56F805 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 20. Absolute Maximum Ratings Characteristic Symbol Min Max Unit Supply voltage VDD VSS - 0.3 VSS + 4.0 V All other input voltages, excluding Analog inputs VIN VSS - 0.3 VSS + 5.5V V Analog inputs, ANA0-7 and VREF VIN VSSA VDDA V Current drain per pin excluding VDD, VSS, PWM outputs, TCS, VPP, VDDA, VSSA I -- 10 mA Current drain per pin for PWM outputs I -- 20 mA Junction temperature TJ -- 150 C TSTG -55 150 C Storage temperature range 16 DSP56F805 Preliminary Technical Data DC Electrical Characteristics Table 21. Recommended Operating Conditions Characteristic Symbol Min Max Unit VDD,VDDA 3.0 3.6 V Ambient operating temperature TA -40 85 C Flash program/erase temperature TF 0 85 C Supply voltage Table 22. Thermal Characteristics1 144-pin LQFP Characteristic Symbol Value Unit Thermal resistance junction-to-ambient (estimated) JA 42.7 C/W I/O pin power dissipation PI/O User Determined W Power dissipation PD PD = (IDD x VDD) + PI/O W PDMAX (TJ - TA) / JA C Maximum allowed PD 1. See Section 5.1 for more detail. 3.2 DC Electrical Characteristics Table 23. DC Electrical Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fop = 80 MHz Characteristic Symbol Min Typ Max Unit Input high voltage (XTAL/EXTAL) VIHC 2.25 2.5 2.75 V Input low voltage (XTAL/EXTAL) VILC -0.3 -- 0.5 V Input high voltage VIH 2.0 -- 5.5 V Input low voltage VIL -0.3 -- 0.8 V Input current low (pullups disabled) IIL -1 -- 1 A Input current high (pullups disabled) IIH -1 -- 1 A Output tri-state current low IOZL -10 -- 10 A Output tri-state current high IOZH -10 -- 10 A Output High Voltage with IOH load VOH VDD - 0.7 -- -- V Output Low Voltage with IOL load VOL -- -- 0.4 V Output High Current IOH -300 -- -- A DSP56F805 Preliminary Technical Data 17 Table 23. DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fop = 80 MHz Characteristic Symbol Min Typ Max Unit Output Low Current IOL -- -- 2 mA Input capacitance CIN -- 8 -- pF Output capacitance COUT -- 12 -- pF PWM pin output source current1 IOHP -- -- -10 mA PWM pin output sink current2 IOLP -- -- 16 mA Total supply current IDDT3 PLL set to 5 MHz out -- 120 145 mA Run,4 PLL set to 20 MHz out -- 141 166 mA Run,4 PLL set to 40 MHz out -- 143 168 mA Run,4 PLL set to 80 MHz out -- 150 175 mA Wait5 -- 90 120 mA Stop -- 65 105 mA VEI -- 2.5 TBD V Low Voltage Interrupt Recovery Hysteresis VEIH -- 50 -- mV Power on Reset7 POR -- 1.5 2.0 V Run ,4 Low Voltage Interrupt6 1. PWM pin output source current measured with 50% duty cycle. 2. PWM pin output sink current measured with 50% duty cycle. 3. IDDT = IDD + IDDA (Total supply current for VDD + VDDA) 4. Run (operating) IDD measured using external square wave clock source (fosc = 8 MHz) into XTAL. All inputs 0.2 V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 5. Wait IDD measured using external square wave clock source (fosc = 8 MHz) into XTAL; all inputs 0.2 V from rail; no DC loads; less than 50 pF on all outputs. C L = 20 pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured with PLL. 6. When VDD drops below VEI max value, an interrupt is generated. 7. Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates. 18 DSP56F805 Preliminary Technical Data AC Electrical Characteristics 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins except XTAL, which is tested using the input levels in Section 3.2. In Figure 3 the levels of VIH and VIL for an input signal are shown. Low VIH Input Signal High 90% 50% 10% Midpoint1 VIL Fall Time Rise Time Note: The midpoint is VIL + (VIH - VIL)/2. Figure 3. Input Signal Measurement References Figure 4 shows the definitions of the following signal states: * Active state, when a bus or signal is driven, and enters a low impedance state. * Tri-stated, when a bus or signal is placed in a high impedance state. * Data Valid state, when a signal level has reached V OL or VOH. * Data Invalid state, when a signal level is in transition between VOL and VOH. Data2 Valid Data1 Valid Data3 Valid Data2 Data1 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 4. Signal States DSP56F805 Preliminary Technical Data 19 3.4 Flash Memory Characteristics Table 24. Flash Memory Truth Table Mode XE1 YE2 SE3 OE4 PROG5 ERASE6 MAS17 NVSTR8 Standby L L L L L L L L Read H H H H L L L L Word Program H H L L H L L H Page Erase H L L L L H L H Mass Erase H L L L L H H H 1. 2. 3. 4. 5. 6. 7. 8. X address enable, all rows are disabled when XE = 0 Y address enable, YMUX is disabled when YE = 0 Sense amplifier enable Output enable, tri-state flash data out bus when OE = 0 Defines program cycle Defines erase cycle Defines mass erase cycle, erase whole block Defines non-volatile store cycle Table 25. IFREN Truth Table 20 Mode IFREN = 1 IFREN = 0 Read Read information block Read main memory block Word program Program information block Program main memory block Page erase Erase information block Erase main memory block Mass erase Erase both block Erase main memory block DSP56F805 Preliminary Technical Data Flash Memory Characteristics Table 26. Timing Symbols Characteristic Symbol See Figure(s) X address access time Txa - Y address access time Tya - OE access time Toa - PROG/ERASE to NVSTR set up time Tnvs* Figure 5, Figure 6, Figure 7 NVSTR hold time Tnvh* Figure 5, Figure 6 NVSTR hold time(mass erase) Tnvh1* Figure 7 NVSTR to program set up time Tpgs* Figure 5 Program hold time Tpgh Figure 5 Address/data set up time Tads Figure 5 Address/data hold time Tadh Figure 5 Recovery time Trcv* Figure 5, Figure 6, Figure 7 Cumulative program HV period Thv Figure 5 Program time Tprog* Figure 5 Erase time Terase* Figure 6 Mass erase time Tme* Figure 7 *The flash interface unit provides registers for the control of these parameters. DSP56F805 Preliminary Technical Data 21 Table 27. Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF Characteristic Symbol Min Typ Max Unit Program time1 Tprog 20 - - us Erase time2 Terase 20 - - ms Mass erase time3 Tme 100 - - ms Endurance4 ECYC 10,000 - - cycles Data Retention DRET 10 - - years The following parameters should only be used in the Manual Word Programming mode. PROG/ERASE to NVSTR set up time Tnvs - 5 - us NVSTR hold time Tnvh - 5 - us NVSTR hold time(mass erase) Tnvh1 - 100 - us NVSTR to program set up time Tpgs - 10 - us Recovery time Trcv - 1 - us Cumulative program HV period5 Thv - 3 - ms 1. Program specification guaranteed from TA = 0 C to 85 C. 2. Erase specification guaranteed from TA = 0 C to 85 C. 3. Mass erase specification guaranteed from TA = 0 C to 85 C. 4. One cycle is equal to an erase, program, and read. 5. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 22 DSP56F805 Preliminary Technical Data Flash Memory Characteristics IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs Tprog Tpgh NVSTR Tpgs Tnvh Trcv Thv Figure 5. Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 6. Flash Erase Cycle DSP56F805 Preliminary Technical Data 23 IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 7. Flash Mass Erase Cycle 3.5 External Clock Operation The DSP56F805 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 3.5.1 Crystal Oscillator The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 29. In Figure 8 a typical crystal oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 4-8 MHz (optimized for 8 MHz) EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 10 M Figure 8. Crystal Oscillator 24 DSP56F805 Preliminary Technical Data External Clock Operation 3.5.2 External Clock Source The recommended method of connecting an external clock is given in Figure 9. The external clock source is connected to XTAL and the EXTAL pin is grounded. DSP56F805 XTAL EXTAL External Clock VSS Figure 9. Connecting an External Clock Signal using XTAL It is possible to instead drive EXTAL with an external clock, though this is not the recommended method. If you elect to drive EXTAL with an external clock source the following conditions must be met: 1. XTAL must be completely un-loaded, 2. the maximum frequency of the applied clock must be less than 8 MHz. Figure 10 illustrates how to connect an external clock circuit with a external clock source using EXTAL as the input. DSP56F805 XTAL EXTAL External No Connection Clock ( < 8MHz) Figure 10. Connecting an External Clock Signal using EXTAL Table 28. External Clock Operation Timing Requirements5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)1 fosc 0 -- 80 MHz Clock Pulse Width2, 5 tPW 6.25 -- -- ns External clock input rise time3, 5 trise -- -- 3 ns External clock input fall time4, 5 tfall -- -- 3 ns 1. 2. 3. 4. 5. See Figure 9 for details on using the recommended connection of an external clock driver. The high or low pulse width must be no smaller than 6.25 ns or the chip will not function. External clock input rise time is measured from 10% to 90%. External clock input fall time is measured from 90% to 10%. Parameters listed are guaranteed by design. DSP56F805 Preliminary Technical Data 25 VIH External Clock 90% 50% 10% tPW 90% 50% 10% tPW trise tfall VIL Note: The midpoint is VIL + (VIH - VIL)/2. Figure 11. External Clock Timing Table 29. PLL Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 8 MHz PLL output frequency fop 40 -- 80 MHz PLL stabilization time 2 tplls -- 1 10 ms 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8 MHz input crystal. 2. This is the minimum time required after the PLL setup is changed to ensure reliable operation. 3.6 External Bus Asynchronous Timing Table 30. External Bus Asynchronous Timing 1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fop = 80 MHz Symbol Typical Min Typical Max Unit Address Valid to WR Asserted tAWR 6.5 -- ns WR Width Asserted Wait states = 0 Wait states > 0 tWR 7.5 (T*WS)+7.5 -- -- ns ns WR Asserted to D0-D15 Out Valid tWRD -- T + 4.2 ns Data Out Hold Time from WR Deasserted tDOH 4.8 -- ns Data Out Set Up Time to WR Deasserted Wait states = 0 Wait states > 0 tDOS 6.4 (T*WS)+6.4 -- -- ns ns RD Deasserted to Address Not Valid tRDA 0 -- ns Characteristic 26 DSP56F805 Preliminary Technical Data External Bus Asynchronous Timing Table 30. External Bus Asynchronous Timing (Continued)1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fop = 80 MHz Characteristic Symbol Address Valid to RD Deasserted Wait states = 0 Wait states > 0 tARDD Input Data Hold to RD Deasserted tDRD RD Assertion Width Wait states = 0 Wait states > 0 tRD Address Valid to Input Data Valid Wait states = 0 Wait states > 0 tAD Typical Min Typical Max -- 18.7 (T*WS) + 18.7 Address Valid to RD Asserted tARDA RD Asserted to Input Data Valid Wait states = 0 Wait states > 0 tRDD Unit ns ns 0 -- ns 19 (T*WS)+19 -- -- ns ns -- -- 1 (T*WS)+1 ns ns -4.4 -- ns -- -- 2.4 (T*WS) + 2.4 ns ns WR Deasserted to RD Asserted tWRRD 6.8 -- ns RD Deasserted to RD Asserted tRDRD 0 -- ns WR Deasserted to WR Asserted tWRWR 14.1 -- ns RD Deasserted to WR Asserted tRDWR 12.8 -- ns 1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and T = Clock Period. For 80 MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. To calculate the required access time for an external memory for any frequency < 80 Mhz, use this formula: Top = Clock period @ desired operating frequency WS = Number of wait states Memory Access Time = (Top*WS) + (Top- 11.5) DSP56F805 Preliminary Technical Data 27 A0-A15, PS, DS (See Note) tARDD tRDA tARDA RD tRDRD tRD tAWR tWRWR tWR tWRRD tRDWR WR tRDD tAD tWRD tDRD tDOS D0-D15 tDOH Data Out Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 12. External Bus Asynchronous Timing 28 DSP56F805 Preliminary Technical Data Reset, Stop, Wait, Mode Select, and Interrupt Timing 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 31. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 6 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF Characteristic Symbol Typical Min Typical Max Unit See Figure RESET Assertion to Address, Data and Control Signals High Impedance tRAZ -- 21 ns Figure 13 Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 tRA 275,000T 128T -- -- ns ns RESET De-assertion to First External Address Output tRDA 33T 34T ns Figure 13 Edge-sensitive Interrupt Request Width tIRW 1.5T -- ns Figure 14 IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine tIDM -- 15T ns Figure 15 IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine tIG -- 16T ns Figure 15 IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State3 tIRI -- 13T ns Figure 16 IRQA Width Assertion to Recover from Stop State4 tIW -- 2T ns Figure 17 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 tIF Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 tIRQ Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 RSTO pulse width5 normal operation internal reset mode 1. 2. Figure 13 Figure 17 -- -- 275,000T 12T ns ns Figure 18 -- -- 275,000T 12T ns ns Figure 18 tII -- -- 275,000T 12T ns ns tRSTO Figure 19 63ET 2,097,151ET ns ns In the formulas, T = clock cycle. For an operating frequency of 80 MHz, T = 12.5 ns. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: * After power-on reset * When recovering from Stop state DSP56F805 Preliminary Technical Data 29 3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. ET = External Clock period, For an external crystal frequency of 8 MHz, ET=125 ns. 6. Parameters listed are guaranteed by design. RESET tRA tRAZ tRDA A0-A15, D0-D15 First Fetch PS, DS, RD, WR First Fetch Figure 13. Asynchronous Reset Timing IRQA IRQB tIRW Figure 14. External Interrupt Timing (Negative-Edge-Sensitive) A0-A15, PS, DS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 15. External Level-Sensitive Interrupt Timing 30 DSP56F805 Preliminary Technical Data Reset, Stop, Wait, Mode Select, and Interrupt Timing IRQA, IRQB tIRI A0-A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 16. Interrupt from Wait State Timing tIW IRQA tIF A0-A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 17. Recovery from Stop State Using Asynchronous Interrupt Timing tIRQ IRQA tII A0-A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 18. Recovery from Stop State Using IRQA Interrupt Service RSTO tRSTO Figure 19. Reset Output Timing DSP56F805 Preliminary Technical Data 31 3.8 Serial Peripheral Interface (SPI) Timing Table 32. SPI Timing1 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Symbol Cycle time Master Slave tELD Enable lag time Master Slave tELG Clock (SCLK) high time Master Slave tCH Clock (SCLK) low time Master Slave tCL Data setup time required for inputs Master Slave tDS Data hold time required for inputs Master Slave tDH Access time (time to data active from high-impedance state) Slave tA Disable time (hold time to high-impedance state) Slave tD Data Valid for outputs Master Slave (after enable edge) tDV Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF 32 Max Unit 50 50 -- -- ns ns -- 25 -- -- ns ns -- 100 -- -- ns ns 17.6 25 -- -- ns ns 24.1 25 -- -- ns ns 20 0 -- -- ns ns 0 2 -- -- ns ns 4.8 15 ns 3.7 15.2 ns -- -- 4.5 20.4 ns ns 0 0 -- -- ns ns -- -- 11.5 10.0 ns ns -- -- 9.7 9.0 ns ns tC Enable lead time Master Slave 1. Parameters Min See Figure Figures 20, 21, 22, 23 Figure 23 Figure 23 Figures 20, 21, 22, 23 Figure 23 Figures 20, 21, 22, 23 Figures 20, 21, 22, 23 Figure 23 Figure 23 Figures 20, 21, 22, 23 Figures 20, 21, 22, 23 Figures 20, 21, 22, 23 Figures 20, 21, 22, 23 listed are guaranteed by design. DSP56F805 Preliminary Technical Data Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tDS tCH MISO (Input) tCH MSB in Bits 14-1 tDI(ref) tDV tDI MOSI (Output) LSB in Master MSB out Bits 14-1 Master LSB out tR tF Figure 20. SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH MISO (Input) MSB in tDV(ref) MOSI (Output) tDI Master MSB out tDS tR tDH Bits 14-1 LSB in tDV Bits 14- 1 tF Master LSB out tR Figure 21. SPI Master Timing (CPHA = 1) DSP56F805 Preliminary Technical Data 33 SS (Input) tC tF tR tCL SCLK (CPOL = 0) (Input) tELG tCH tELD tCL SCLK (CPOL = 1) (Input) tA MISO (Output) Slave MSB out tDS tDH MOSI (Input) MSB in tF tR tCH tD Bits 14-1 Slave LSB out tDV tDI Bits 14-1 tDI LSB in Figure 22. SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD SCLK (CPOL = 1) (Input) tCL tDV tA MISO (Output) tF tCH Slave MSB out Bits 14-1 tDV tDS tR tD Slave LSB out tDI tDH MOSI (Input) MSB in Bits 14-1 LSB in Figure 23. SPI Slave Timing (CPHA = 1) 34 DSP56F805 Preliminary Technical Data Quad Timer Timing 3.9 Quad Timer Timing Table 33. Timer Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Symbol Min Max Unit PIN 4T+6 -- ns Timer input high/low period PINHL 2T+3 -- ns Timer output period POUT 2T-3 -- ns POUTHL 1T-3 -- ns Timer input period Timer output high/low period 1. 2. In the formulas listed, T = clock cycle. For 80 MHz operation, T = 12.5 ns. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL POUT POUTHL POUTHL Timer Outputs Figure 24. Timer Timing DSP56F805 Preliminary Technical Data 35 3.10 Quadrature Decoder Timing Table 34. Quadrature Decoder Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Symbol Min Max Unit Quadrature input period PIN 8T+12 -- ns Quadrature input high/low period PHL 4T+6 -- ns Quadrature phase period PPH 2T+3 -- ns 1. In the formulas listed, T = clock cycle. For 80 MHz operation, T = 12.5 ns. VSS = 0 V, VDD = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF. 2. Parameters listed are guaranteed by design. PPH PPH PPH PPH Phase A (Input) PIN PHL PHL Phase B (Input) PIN PHL PHL Figure 25. Quadrature Decoder Timing 36 DSP56F805 Preliminary Technical Data Serial Communication Interface (SCI) Timing 3.11 Serial Communication Interface (SCI) Timing Table 35. SCI Timing4 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Symbol Min Max Unit BR -- (fMAX*2.5)/(80) Mbps RXD2 Pulse Width RXDPW 0.965/BR 1.04/BR ns TXD3 Pulse Width TXDPW 0.965/BR 1.04/BR ns Baud Rate1 1. 2. 3. 4. fMAX is the frequency of operation of the system clock in MHz. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) RXDPW Figure 26. RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 27. TXD Pulse Width DSP56F805 Preliminary Technical Data 37 3.12 Analog-to-Digital Converter (ADC) Characteristics Table 36. ADC Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Symbol Min Typ Max Unit VADIN 0 -- VDDA1 V Resolution RES 12 -- 12 Bits Integral Non-Linearity INL -- +/- 3 TBD LSB2 Differential Non-Linearity DNL -- +/- .8 TBD LSB2 Input voltages Monotonicity GUARANTEED ADC internal clock fADIC 0.5 -- 5 MHz Conversion range RAD VSSA -- VDDA V Power-up time tADPU -- 16 -- tAIC cycles3 Conversion time tADC -- 6 -- tAIC cycles3 Sample time tADS -- 1 -- tAIC cycles3 Input capacitance CADI -- 5 -- pF4 VREF current IVREF -- -- 14.5 mA Gain Error (transfer gain) EGAIN -- .99725 -- -- Offset Voltage VOFFSET -- 25 TBD mV SINAD SINAD -- 59 -- -- ENOB ENOB -- 9.5 -- bit SFDR SFDR -- 64 -- db BW -- 100 -- KHz Bandwidth 1. 2. 3. 4. VDDA should be tied to the same potential as VDD via separate traces. LSB = Least Significant Bit. tAIC = 1/fADIC. See Figure 28 NOTE: IADC quiescent current (both ADCs) is 39.3 mA IVREF quiescent current (both ADCs) is 11.85 mA Typical values measured at VDD = 3.3, VREF = 3.0 VREF must be equal to or less than VDD VREF can go as low as 2.7V. 38 DSP56F805 Preliminary Technical Data Controller Area Network (CAN) Timing ADC analog input 1 3 2 4 Figure 28. Equivalent Analog Input Circuit 1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. 2.04pf 3. Equivalent resistance for the ESD isolation resistor and the channel select mux. 500 ohms 4. Sampling capacitor at the sample and hold circuit. 1pf 3.13 Controller Area Network (CAN) Timing Table 37. CAN Timing2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, MSCAN Clock = 30 MHz Characteristic Baud Rate Bus Wakeup detection 1 Symbol Min Max Unit BRCAN -- 1 Mbps T WAKEUP 5 -- us 1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into Sleep mode then, any bus event (on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1 Mbps. 2. Parameters listed are guaranteed by design. MSCAN_RX CAN receive data pin (Input) T WAKEUP Figure 29. Bus Wakeup Detection DSP56F805 Preliminary Technical Data 39 3.14 JTAG Timing Table 38. JTAG Timing1, 3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Symbol Min Max Unit TCK frequency of operation2 fOP DC 10 MHz TCK cycle time tCY 100 -- ns TCK clock pulse width tPW 50 -- ns TMS, TDI data setup time tDS 0.4 -- ns TMS, TDI data hold time tDH 1.2 -- ns TCK low to TDO data valid tDV -- 26.6 ns TCK low to TDO tri-state tTS -- 23.5 ns tTRST 50 -- ns tDE 4T -- ns TRST assertion time DE assertion time 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80 MHz operation, T = 12.5 ns. 2. TCK frequency of operation must be less than 1/8 the processor rate. 3. Parameters listed are guaranteed by design. tCY tPW tPW VIH VM TCK (Input) VM = VIL + (VIH - VIL)/2 VM VIL Figure 30. Test Clock Input Timing Diagram 40 DSP56F805 Preliminary Technical Data JTAG Timing TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 31. Test Access Port Timing Diagram TRST (Input) tTRST Figure 32. TRST Timing Diagram DE tDE Figure 33. OnCE--Debug Event DSP56F805 Preliminary Technical Data 41 Part 4 Packaging 4.1 Package and Pin-Out Information DSP56F805 RXD0 TXD0 PWMA5 PWMA4 GPIOD2 PWMA3 GPIOD1 PWMA2 GPIOD0 PWMA1 GPIOB7 PWMA0 GPIOB6 HOME0 GPIOB5 INDEX0 GPIOB4 VSS GPIOB3 VDD GPIOB2 PHASEB0 GPIOB1 PHASEA0 GPIOB0 VSS VDD VDD VDDA VSSA EXTAL XTAL ANA7 ANA6 ANA5 ANA4 This section contains package and pin-out information for the 144-pin LQFP configuration of the DSP56F805. 109 73 Motorola DSP56F805 Orientation Mark 144 37 1 ANA3 ANA2 ANA1 ANA0 VREF FAULTA3 FAULTA2 MSCAN_RX FAULTA1 MSCAN_TX FAULTA0 RXD1 ISA2 VSS ISA1 VDD ISA0 VCAPC TRST TDO TXD1 TDI TC1 TMS TC0 TCK FAULTB3 TCS FAULTB2 IRQB IRQA RD WR VSS A15 A14 D10 D11 D12 D13 D14 D15 A0 VDD PWMB0 VSS PWMB1 A1 PWMB2 A2 PWMB3 A3 A4 A5 PWMB4 A6 PWMB5 A7 ISB0 A8 ISB1 A9 ISB2 A10 FAULTB0 A11 FAULTB1 A12 A13 VDD PS DS EXTBOOT RESET DE CLKO TD0 TD1 VDD TD2 VSS TD3 RSTO SS GPIOD3 MISO GPIOD4 MOSI SCLK VCAPC GPIOD5 D0 VPP D1 D2 INDEX1 VDD PHASEB1 VSS PHASEA1 D3 HOME1 D4 D5 D6 D7 D8 D9 Figure 34. Top View, DSP56F805 144-pin LQFP Package 42 DSP56F805 Preliminary Technical Data Package and Pin-Out Information DSP56F805 Table 39. DSP56F805 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1 D10 37 A14 73 ANA4 109 EXTBOOT 2 D11 38 A15 74 ANA5 110 RESET 3 D12 39 VSS 75 ANA6 111 DE 4 D13 40 WR 76 ANA7 112 CLKO 5 D14 41 RD 77 XTAL 113 TD0 6 D15 42 IRQA 78 EXTAL 114 TD1 7 A0 43 IRQB 79 VSSA 115 VDD 8 VDD 44 FAULTB2 80 VDDA 116 TD2 9 PWMB0 45 TCS 81 VDD 117 VSS 10 VSS 46 FAULTB3 82 VDD 118 TD3 11 PWMB1 47 TCK 83 VSS 119 RSTO 12 A1 48 TC0 84 GPIOB0 120 SS 13 PWMB2 49 TMS 85 PHASEA0 121 GPIOD3 14 A2 50 TC1 86 GPIOB1 122 MISO 15 PWMB3 51 TDI 87 PHASEB0 123 GPIOD4 16 A3 52 TXD1 88 GPIOB2 124 MOSI 17 A4 53 TDO 89 VDD 125 SCLK 18 A5 54 TRST 90 GPIOB3 126 VCAPC 19 PWMB4 55 VCAPC 91 VSS 127 GPIOD5 20 A6 56 ISA0 92 GPIOB4 128 D0 21 PWMB5 57 VDD 93 INDEX0 129 VPP 22 A7 58 ISA1 94 GPIOB5 130 D1 23 ISB0 59 VSS 95 HOME0 131 D2 24 A8 60 ISA2 96 GPIOB6 132 INDEX1 25 ISB1 61 RXD1 97 PWMA0 133 VDD 26 A9 62 FAULTA0 98 GPIOB7 134 PHASEB1 27 ISB2 63 MSCAN_TX 99 PWMA1 135 VSS DSP56F805 Preliminary Technical Data 43 Table 39. DSP56F805 Pin Identification by Pin Number (Continued) 44 Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 28 A10 64 FAULTA1 100 GPIOD0 136 PHASEA1 29 FAULTB0 65 MSCAN_RX 101 PWMA2 137 D3 30 A11 66 FAULTA2 102 GPIOD1 138 HOME1 31 FAULTB1 67 FAULTA3 103 PWMA3 139 D4 32 A12 68 VREF 104 GPIOD2 140 D5 33 A13 69 ANA0 105 PWMA4 141 D6 34 VDD 70 ANA1 106 PWMA5 142 D7 35 PS 71 ANA2 107 TXD0 143 D8 36 DS 72 ANA3 108 RXD0 144 D9 DSP56F805 Preliminary Technical Data Package and Pin-Out Information DSP56F805 Figure 35. 144-pin LQFP Mechanical Information DSP56F805 Preliminary Technical Data 45 Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: TJ = T A + ( P D x R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: RJA = RJC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: 46 * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. * Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. DSP56F805 Preliminary Technical Data * Use the value obtained by the equation (TJ - TT)/PD where TT is the temperature of the package case determined by a thermocouple. The junction-to-case thermal resistances quoted in this data sheet are determined using the first definition on page 45. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 5.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct DSP operation: 47 * Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from the board ground to each VSS pin. * The minimum bypass requirement is to place six 0.01-0.1 F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the nine VDD/VSS pairs, including VDDA/VSSA. The VCAP capacitors must be 150 milliohm or less ESR capacitors. * Ensure that capacitor leads and associated printed circuit traces that connect to the chip V DD and VSS pins are less than 0.5 inch per capacitor lead. * Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS. * Bypass the VDD and VSS layers of the PCB with approximately 100 F, preferably with a highgrade capacitor such as a tantalum capacitor. * Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. DSP56F805 Preliminary Technical Data * Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. * Take special care to minimize noise levels on the VREF, VDDA and VSSA pins. * Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. * Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. Part 6 Ordering Information Table 40 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 40. DSP56F805 Ordering Information Part Supply Voltage DSP56F805 3.0-3.6 V Package Type Low Profile Plastic Quad Flat Pack (LQFP) Pin Count Frequency (MHz) Order Number 144 80 DSP56F805FV80 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. 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