General Description
The MAX9381 differential data, differential clock D flip-
flop is pin compatible with the ON Semiconductor
MC100EP52, with the added benefit of a wider supply-
voltage range from 2.25V to 5.5V and 25% lower supply
current. Data enters the master part of the flip-flop
when the clock is low and is transferred to the outputs
upon a positive transition of the clock. Interchanging
the clock inputs allows the part to be used as a nega-
tive edge-triggered device. The MAX9381 utilizes input
clamping circuits that ensure the stability of the outputs
when the inputs are left open or at VEE.
The MAX9381 is offered in an 8-pin SO package and
the smaller 8-pin µMAX package.
Applications
Precision Clock and Data Distribution
Central Office
DSLAM
DLC
Base Station
ATE
Features
♦3.0GHz Guaranteed Operating Clock Frequency
♦0.2psRMS Added Random Jitter
♦328ps Typical Propagation Delay
♦PECL Operation from VCC = 2.25V to 5.5V with
VEE = 0V
♦ECL Operation from VEE = -2.25V to -5.5V with
VCC = 0V
♦Input Safety Clamps Ensure Output Stability when
Inputs are Open or at VEE
♦±2kV ESD Protection (Human Body Model)
MAX9381
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
________________________________________________________________ Maxim Integrated Products 1
Q
VEE
CLK
1
2
8
7
VCC
QD
CLK
D
SO/µMAX
TOP VIEW
3
4
6
5
MAX9381
Pin Configuration
Ordering Information
75kΩDQ
Q
1
45
6
72
3
8
MAX9381
D
D
CLK
CLK VEE
VCC
Q
Q
75kΩ
75kΩ
75kΩ
Functional Diagram
19-2397; Rev 0; 4/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX9381ESA -40°C to +85°C 8 SO
MAX9381EUA* -40°C to +85°C 8 µMAX
*Future product—contact factory for availability.
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC - VEE...............................................................-0.3V to +6.0V
Input Voltage (D, D, CLK, CLK) .......(VEE - 0.3V) to (VCC + 0.3V)
Differential Input Voltage ...............Smaller of |VCC - VEE| or 3.0V
Output Current (Q, Q)
Continuous .......................................................................50mA
Surge..............................................................................100mA
Junction-to-Ambient Thermal Resistance in Still Air
8-Pin µMAX ..............................................................+221°C/W
8-Pin SO ...................................................................+170°C/W
Maximum Continuous Power Dissipation
8-Pin µMAX (derate 4.5mW/°C above +70°C) ..............362mW
8-Pin SO (derate 5.9mW/°C above +70°C)...................471mW
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
8-Pin µMAX ..............................................................+155°C/W
8-Pin SO .....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin µMAX ................................................................+39°C/W
8-Pin SO .....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model ..........................................................±2kV
Soldering Temperature (10s) ...........................................+300°C
MAX9381
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.25V to 5.5V (TA= +25°C to +85°C), VCC - VEE = 2.375V to 5.5V (TA= -40°C to +25°C), outputs terminated with 50Ω
±1% to VCC - 2.0V, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless oth-
erwise noted.) (Notes 1, 2, and 3)
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
INPUTS (D, D, CLK, CLK)
Differential Input
High Voltage
VIHD
Figure 1 VEE +
1.2 VCC
VEE +
1.2 VCC
VEE +
1.2 VCC
V
Differential Input
Low Voltage VILD Figure 1
VEE
VCC -
0.15 VEE
VCC -
0.15 VEE
VCC -
0.15
V
V
C C
- V
E E
< 3.0V
0.15
VCC -
VEE 0.15
VCC -
VEE 0.15
VCC -
VEE
Differential Input
Voltage VID
Figure 1
V
C C
- V
E E
≥ 3.0V
0.15 3.0 0.15 3.0 0.15 3.0
V
Single-Ended
Input Current
IIH, IIL
D, D, CLK, or CLK
= VIHD or VILD
-10 +200 -10 +200 -10 +200
µA
Output High
Voltage VOH Figure 1 VCC -
1.145
VCC -
0.895
VCC -
1.145
VCC -
0.895
VCC -
1.145
VCC -
0.895
V
Output Low
Voltage VOL Figure 1 VCC -
1.945
VCC -
1.695
VCC -
1.945
VCC -
1.695
VCC -
1.945
VCC -
1.695
V
Differential
Output Voltage VOD VOH - VOL,
Figure 1
550 550 550
mV
Power-Supply
Current (Note 4) IEE
17
35
20
35
22 35
mA
MAX9381
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.25V to 5.5V (TA= +25°C to +85°C), VCC - VEE = 2.375V to 5.5V (TA= -40°C to +25°C), outputs terminated with 50Ω
±1% to VCC - 2.0V, fCLK ≤3.0GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V,
VIHD - VILD = 0.15V to smaller of |VCC - VEE| or 3V, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1.0V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 5)
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4: All pins floating except VCC and VEE.
Note 5: Guaranteed by design and characterization, and are not production tested. Limits are set to ±6 sigma.
Note 6: Device jitter added to the input clock.
-40°C +25°C +85°C
PARAMETER
SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
Propagation Delay
CLK, CLK to Q, Q
tPHL
tPLH Figure 2
370 328 405 490
ps
Maximum Clock
Frequency
fCLKMAX VOD ≥ 300mV 3.0 3.0 3.0
GHz
Setup Time tSFigure 2
100 100 100
ps
Hold Time tHFigure 2
50 50 50
ps
Added Random
Jitter (Note 6) tRJ
0.2 0.8 0.2 0.8 0.2 0.8
ps
(RMS)
Differential Output
Rise/Fall Time tR/tF20% to 80%,
Figure 2
70 120 170 80 120 180 90 120 200
ps
MAX9381
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC - VEE = 3.3V, outputs loaded with 50Ω±1% to VCC - 2V, VIH = VCC - 1V, VIL = VCC - 1.5V, fCLK = 3GHz, fD= fCLK/2 input tran-
sition time = 125ps (20% to 80%), unless otherwise noted.)
SUPPLY CURRENT (IEE)
vs. TEMPERATURE
MAX9381 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
18
20
22
24
16
-40 85
INPUTS AND
OUTPUTS OPEN
OUTPUT AMPLITUDE (VOH - VOL)
vs. CLK FREQUENCY
MAX9381 toc02
CLK FREQUENCY (GHz)
OUTPUT AMPLITUDE (mV)
2.52.01.51.00.503.0
400
500
600
700
800
300
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9381 toc03
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME (ps)
603510-15-40 85
fCLK = 1.5GHz
FALL TIME
RISE TIME
117
119
121
123
125
115
MAX9381 toc04
TEMPERATURE (°C)
IN-TO-OUT PROPAGATION DELAY (ps)
330
340
350
360
320
CLK-TO-Q PROPAGATION DELAY
vs. TEMPERATURE
603510-15-40 85
tPHL
tPLH
Detailed Description
The MAX9381 D flip-flop transfers the logic level at the
D input to the Q output on a rising edge transition of the
clock, provided the minimum setup and hold times are
met. By interchanging the CLK and CLK inputs, the flip-
flop functions as a falling-edge triggered flip-flop.
The input signals (D, Dand CLK, CLK) are differential
and have a maximum differential input voltage of 3.0V
or VCC - VEE, whichever is less. To ensure that the out-
puts remain stable when the inputs are left open, each
of the inputs is driven low by a 75kΩbias resistor con-
nected to VEE. If the D and Dinputs are left open or at
VEE, the output is guaranteed to be a differential low on
the next low-to-high transition of the clock. If the CLK
and CLK inputs are left open or at VEE, the outputs
remain unchanged (Table 1). Terminate the outputs (Q,
Q) through 50Ωto VCC - 2V or an equivalent Thevenin
termination (see the Output Termination section).
ECL/PECL Operation
Output levels are referenced to VCC and are consid-
ered PECL or ECL, depending on the level of the VCC
supply. With VCC connected to a positive supply and
VEE connected to GND, the outputs are PECL. The out-
puts are ECL when VCC is connected to GND and VEE
is connected to a negative supply.
Applications Information
T Flip-Flop
The MAX9381 can be configured as a T flip-flop by
connecting Q to Dand Qto D. This configuration pro-
vides an output at half the frequency of the clock. The
maximum operating frequency is determined by the
sum of the setup time, the propagation delay of the
MAX9381
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1 D Noninverting D Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to VEE.
2DInverting D Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to VEE.
3 CLK Noninverting Clock Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to VEE.
4CLK Inverting Clock Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to VEE.
5V
EE Negative Supply
6QInverting Q Output from the Flip-Flop. Terminate with a 50Ω resistor to VCC - 2V or equivalent.
7 Q Noninverting Q Output from the Flip-Flop. Terminate with a 50Ω resistor to VCC - 2V or equivalent.
8V
CC Positive Supply. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
D, DCLK, CLK Q, Q
L↑L
H↑H
Open or VEE ↑L
X Open or VEE No change
Table 1. Truth Table*
*Where logic states are differential, ↑is a low-to-high transition
and X signifies a don’t care state.
VCC
VEE
VIHD (MAX)
(MIN)
(MIN)
VILD (MAX)
INPUT VOLTAGE DEFINITION OUTPUT VOLTAGE DEFINITION
VIHD
VILD
VID = 0
VID = 0
VID
VID
VOH - VOL
VCC
VOH
VOL
VEE
Figure 1. Input and Output Voltage Definitions
MAX9381
device and any added delay by circuit board traces.
The minimum supply voltage is 2.375V and is deter-
mined by input and output voltage range.
Output Termination
Terminate the outputs through 50Ωto VCC - 2V or use
equivalent Thevenin terminations. Terminate each Q and
Qoutputs with identical termination on each for the lowest
output distortion. When a single-ended signal is taken
from the differential output, terminate both Q and Q.
Ensure that output currents do not exceed the current
limits as specified in the Absolute Maximum Ratings
table. Under all operating conditions, the device’s total
thermal limits should be observed.
Power-Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors. Place the capac-
itors as close to the device as possible with the 0.01µF
capacitor closest to the device pins.
Use multiple vias when connecting the bypass capaci-
tors to ground. This reduces trace inductance, which
lowers power-supply bounce when drawing high tran-
sient currents.
Circuit Board Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50Ωcharacteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners, or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 375
PROCESS: Bipolar
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
6 _______________________________________________________________________________________
D
D
CLK
CLK
Q
Q
tStH
tPLH
Q - Q
tR
20%
80%
0V (DIFFERENTIAL)
tPHL
DIFFERENTIAL
OUTPUT
WAVEFORM
20%
80%
0V (DIFFERENTIAL)
tF
Figure 2. CLK-to-Q Propagation Delay and Transition Timing Diagram
MAX9381
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
PACKAGE OUTLINE, 8L uMAX/uSOP
1
1
21-0036 J
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
MAX
0.043
0.006
0.014
0.120
0.120
0.198
0.026
0.007
0.037
0.0207 BSC
0.0256 BSC
A2 A1
c
eb
A
L
FRONT VIEW SIDE VIEW
E H
0.6±0.1
0.6±0.1
ÿ 0.50±0.1
1
TOP VIEW
D
8
A2 0.030
BOTTOM VIEW
16∞
S
b
L
H
E
D
e
c
0∞
0.010
0.116
0.116
0.188
0.016
0.005
8
4X S
INCHES
-
A1
A
MIN
0.002
0.950.75
0.5250 BSC
0.25 0.36
2.95 3.05
2.95 3.05
4.78
0.41
0.65 BSC
5.03
0.66
6∞0∞
0.13 0.18
MAX
MIN
MILLIMETERS
- 1.10
0.05 0.15
α
α
DIM
9LUCSP, 3x3.EPS