DATA SHEET
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
1 ©2012 Integrated Devi ce Technology, Inc.
Quad-Frequency Programmable XO IDT8N3Q001 REV G
General Description
The IDT8N3Q001 is a Quad-Frequency Programmable Clock
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x
7mm x 1.55mm package.
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, th e ID T8 N 3 Q0 0 1 ca n be pr o g rammed via the I2C
interface to output clock frequencies between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷ N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL M and N divider registers (P, MINT, MFRAC and N),
reprogramming those registers to other frequencies under control of
FSEL0 and FSEL1 is su pp o r te d . Th e ext e nd ed temperature ran ge
supports wireless infrastructure, telecommunication and networking
end equipment requir e m en ts.
Features
•Fourth generation FemtoClock® NG technology
•Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
•Four power-up default frequencies (see part number order
codes), re-programmable by I2C
• I2C programming interface for the output clock frequency and
internal PLL control registers
•Frequency programming resolution is 435.9Hz ÷N
•One 2.5V, 3.3V LVPECL clock output
•Two control inputs for the power-up default frequency
•LVCMOS/LVTTL compatible control inputs
•RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.244ps
(typical), integer PLL feedback configuration
•RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.265ps
(typical), integer PLL feedback configuration
•Full 2.5V or 3.3V supply modes
•-40°C to 85°C ambient operating temperature
•Available in Lead-free (RoHS 6) package
IDT8N3Q001
10-lead Cer amic 5mm x 7mm x 1. 55mm
package body
CD Package
Top View
8 VCC
7 nQ
6 Q
FSEL0 4
FSEL1 5
10 SCLK
9 SDATA
DNU 1
OE 2
VEE 3
Pin Assignment
Block Diagram
Q
nQ
OSC
fXTAL
÷MINT, MFRAC
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz ÷N
I2C Control
Configuration Register (ROM)
(Frequency, APR, Polarity)
25 7
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
÷P
2
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
2 ©2012 Integrated Devi ce Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal in put resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3A. OE Configuration
NOTE: OE is an asynchronous control.
Table 3B. Output Frequency Range
NOTE: Supported output frequency range. The output frequen cy
can be programmed to any frequency in this range and to a precision
of 218Hz or better.
Number Name Type Description
1 DNU Unused Do not use.
2 OE Input Pullup Output enable pin. See Tabl e 3 for function. LVCMOS/LVT TL interface
levels.
3V
EE Power Negative power supply.
5, 4 FSEL1, FSEL0 Input Pulldown Default frequency sele ct pins. See the Default Frequency Order Codes
section. LVCMOS/LVTTL interface levels.
6, 7 Q, nQ Output Differential clock output. LVPECL interface levels.
8VCC Power Power supply pin.
9SDATA Input/Output Pullup I2C Data Input/Output. Input: LVCMOS/LVTTL compatible interface levels.
Output: Open drain.
10 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL compatible interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 5.5 pF
RPULLUP Input Pullup Resistor 50 k
RPULLDOWN Input Pulldown Resistor 50 k
Input
Output EnableOE
0 Outputs Q, nQ are in high-impedance state.
1 (default) Outputs are enabled.
15.476MHz to 866.67MHz
975MHz to 1,300MMHz
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
3 ©2012 Integrated Devi ce Technology, Inc.
Block Diagram with Programming Registers
Q
nQ
OSC
fXTAL
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz ÷ N
I2C Control
SCLK
SDATA
FSEL[1:0]
OE
Pullup
Pullup
Pulldown
Pullup
Feedback Divider M (25 Bit)
MINT
(7 bits) MFRAC
(18 bits)
Programming Registers
P0 MINT0 MFRAC0 N0
I2C: 2 bits 7 bits 18 bits 7 bits
Def: 2 bits 7 bits 18 bits 7 bits
P1 MINT1 MFRAC1 N1
I2C: 2 bits 7 bits 18 bits 7 bits
Def: 2 bits 7 bits 18 bits 7 bits
P2 MINT2 MFRAC2 N2
I2C: 2 bits 7 bits 18 bits 7 bits
Def: 2 bits 7 bits 18 bits 7 bits
P3 MINT3 MFRAC3 N3
I2C: 2 bits 7 bits 18 bits 7 bits
Def: 2 bits 7 bits 18 bits 7 bits
Def (default): Power-up default register setting for I2C registers
00
01
10
11
34
34
34
34
34
7
27
7
30
30
30
30
18
Output Divider N
Pn, MINTn, MFRACn and Nn
34
÷P
2
2
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
4 ©2012 Integrated Devi ce Technology, Inc.
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the refe rence clock fXTAL of either 114.285
MHz or 100MHz. The PLL includes the FemtoClock NG VCO al ong
with the Pre-divider (P), the feedback divider (M) and the post divider
(N). The P, M, and N dividers determine the output frequency based
on the fXTAL reference and must be configured correctly for proper
operation. The feedback divid er is fractional supporting a huge
number of output frequencies. The configuration of the feedback
divider to integer-only values results in an improved output phase
noise characteristics at the expense of the rang e of output
frequencies. In addition, internal registers are used to hold up to four
different factory pre-set P, M, and N configur a ti o n settings. These
default pre-sets are stored in the I2C registers at power-up. Each
configuration is selected via the the FSEL[1:0] pins and can be read
back using the SCLK and SDATA pins.
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I2C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
If the user does choose to write a different P, M, and N configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I2C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The P, M, and N frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
The devices use the fractional feedback divi der with a delta-sigma
modulator for noise shaping and robust frequency synth esis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divid er (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion ( MFRAC) and provides the means for
high-resolution frequen cy generation. The output frequency fOUT is
calculated by:
The four configuration registers for the P, M (MINT & MFRAC) and N
dividers which are named Pn, MINTn, MFRACn and Nn with n=0 to
3. “n” denominates one of the four possi ble configurations.
As identified previously , the configurations of P, M (MINT & MFRAC)
and N divider settings are stored the I2C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default freq uencies and order codes,
please see the Ordering Information Section in this document. For
available order codes, see the FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Informa tion document.
For more information and guidelines on programming of the device
for custom frequency configurations, the register description, the
selection of fractional and integer-feedback configurations and the
serial interface description, see the FemtoClock NG Cerami c 5x7
Module Programming Guide.
fOUT fXTAL 1
PN
------------MINT MFRAC 0.5+
218
-----------------------------------
+=(1)
Table 4. Frequency Selection
Input
Selects RegisterFSEL1 FSEL0
0 (def.) 0 (def.) Frequency 0 P0, MINT0, MFRAC0, N0
0 1 Frequency 1 P1, MINT1, MFRAC1, N1
1 0 Frequency 2 P2, MINT2, MFRAC2, N2
1 1 Frequency 3 P3, MINT3, MFRAC3, N3
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
5 ©2012 Integrated Devi ce Technology, Inc.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating cond itions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics,VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 5B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 5C. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Item Rating
Supply Voltage, VCC 3.63V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO (SDATA)
Outputs, IO (LVPECL)
Continuous Current
Surge Current
10mA
50mA
100mA
Package Thermal Impedan ce, JA 49.4C/W (0 mps)
Storage Temperature, TSTG -65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Power Supply Voltage 3.135 3.3 3.465 V
IEE Power Supply Current 140 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Supply Voltage 2.375 2.5 2.625 V
IEE Power Supply Current 136 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High
Voltage FSEL[1:0], OE VCC =3.3V +5% 1.7 VCC +0.3 V
FSEL[1:0], OE VCC =2.5V +5% 1.7 VCC +0.3 V
VIL Input Low
Voltage
FSEL[1:0] VCC =3.3V +5% -0.3 0.5 V
OE VCC =3.3V +5% -0.3 0.8 V
FSEL[1:0] VCC =2.5V +5% -0.3 0.5 V
OE VCC =2.5V +5% -0.3 0.8 V
IIH Input
High Current
OE VCC = VIN = 3.465V or 2.625V 10 µA
SDATA, SCLK VCC = VIN = 3.465V or 2.625V 5 µA
FSEL0, FSEL1 VCC = VIN = 3.465V or 2.625V 150 µA
IIL Input
Low Current
OE VCC = 3.465V or 2.625V, VIN = 0V -500 µA
SDATA, SCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA
FSEL0, FSEL1 VCC = 3.465V or 2.625V, VIN = 0V -5 µA
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
6 ©2012 Integrated Devi ce Technology, Inc.
Table 5D. LVPECL DC Characteristics, VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs terminated with 50 to VCC – 2V.
AC Electrical Characteristics
Table 6. AC Characteristic s, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCC – 1.4 V CC – 0.8 V
VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.5 V
VSWING Peak-to-Peak Output Voltage Swing 0.55 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency Q, nQ Output Divider, N = 3 to126 15.476 866.67 MHz
Output Divider, N = 2 975 1,300 MHz
fIInitial Accuracy Measured at 25°C ±10 ppm
fSTemperature Stability Option code = A or B ±100 ppm
Option code = E or F ±50 ppm
Option code = K or L ±20 ppm
fAAging Frequency drift over 10 year life ±3 ppm
Frequency drift over 15 year life ±5 ppm
fTTotal Stability Option code A or B (10 year life) ±113 ppm
Option code E or F (10 year life) ±63 ppm
Option code K or L (10 year life) ±33 ppm
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 20 ps
tjit(per) RMS Period Jitter; NOTE 1 2.85 4 ps
tjit(Ø)
RMS Phase Jitter (Random);
Fractional PLL feedback and
fXTAL=100.000MHz (2xxx order
codes)
17 MHz fOUT 1300MHz,
NOTE 2,3,4 0.440 0.995 ps
RMS Phase Jitter (Random);
Integer PLL feedback and
fXTAL=100.00MHz (1xxx order codes)
500 MHz fOUT 1300MHz,
NOTE 2,3,4 0.240 0.390 ps
125 MHz fOUT 500MHz,
NOTE 2,3,4 0.245 0.425 ps
17 MHz fOUT 125MHz,
NOTE 2,3,4 0.350 0.555 ps
fOUT 156.25MHz, NOTE 2, 3, 4 0.244 ps
fOUT 156.25MHz, NOTE 2, 3, 5 0.265 ps
RMS Phase Jitter (Random)
Fractional PLL feedback and
fXTAL=114.285MHz (0xxx order codes)
17 MHz fOUT 1300 MHz,
NOTE 2, 3, 4 0.475 0.990 ps
N(100) Single-side band phase noise,
100Hz from Carrier 156.25MHz -94.7 dBc/Hz
N(1k) Single-side band phase noise,
1kHz from Carrier 156.25MHz -121.3 dBc/Hz
N(10k) Single-side band phase noise,
10kHz from Carrier 156.25MHz -131.1 dBc/Hz
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
7 ©2012 Integrated Devi ce Technology, Inc.
NOTE: Electrical parameters are guaranteed over the specified ambient op erating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Please refer to the phase noise plots.
NOTE 3: Please see the FemtoClockNG Ceramic 5x7 Modules Programming guide for more information on PLL feedb ack modes and the
optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes and configures
DSM_ENA = 0 and ADC_EN = 0.
NOTE 4: Integration range: 12kHz-2 0MHz.
NOTE 5: Integration range: 1kHz-40 MHz.
N(100k) Single-side band phase noise,
100kHz from Carrier 156.25MHz -137.3 dBc/Hz
N(1M) Single-side band phase noise,
1MHz from Carrier 156.25MHz -139.0 dBc/Hz
N(10M) Single-side band phase noise,
10MHz from Carrier 156.25MHz -154.9 dBc/Hz
PSNR Power Supply Noise Rejection 50mV Sinusoidal Noise
1kHz - 50kHz -54 dB
tR / tFOutput Rise/Fall Time 20% to 80% 100 425 ps
odc Outpu t D ut y Cycle 45 55 %
tSTARTUP Oscillator Start-Up Time 20 ms
tSET Output frequency settling time after
FSEL0 and FSEL1 values are changed 470 µs
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
8 ©2012 Integrated Devi ce Technology, Inc.
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)
Noise Power dBc
Hz
Offset Frequency (Hz)
NOTE: RMS Phase Noise (Random) for Integer PLL Feedback and fXTAL=100.000MHz.
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
9 ©2012 Integrated Devi ce Technology, Inc.
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
Output Rise/Fall Time
2.5V LVPECL Output Load AC Test Circuit
Period Jitt er
Cycle-to-Cycle Jitter
SCOPE
Qx
nQx
VEE
VCC
-1.3V±0.165V
2V
Offset Frequency
f1f2
Phase Noise Plot
R
MS Jitter = Area Under Curve Defined by the Offset Frequency Marke
rs
Noise Power
20%
80% 80%
20%
tRtF
VSWING
nQ
Q
SCOPE
Qx
nQx
VEE
VCC
-0.5V± 0.125V
2V
VOH
VRE
F
VOL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
nQ
Q
➤
➤
➤
➤
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
10 ©2012 Integrated Dev i ce Technology, Inc.
Parameter Measurement Information, continued
Output Duty Cycle/Pulse Width/Period
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Select Pins
The FSEL[1:0] pins have internal pulldowns and OE control pins
have internal pullups; additional resistance is not required but can be
added for additional protection. A 1k resistor can be used. SCLK
and SDATA should be left floating if not used.
tPW tPERIOD
tPW
tPERIOD
odc = x 100%
nQ
Q
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
11 ©2012 Integrated Dev i ce Technology, Inc.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typ ical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 1A and 1B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 1A. 3.3V LVPECL Output Termination Figure 1B. 3.3V LVPECL Output Termination
3.3V
VCC - 2V
R1
50Ω
R2
50Ω
RTT
Zo = 50Ω
Zo = 50Ω
+
_
RTT = * Zo
1
((VOH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL Input
R1
84Ω
R2
84Ω
3.3V
R3
125Ω
R4
125Ω
Zo = 50Ω
Zo = 50Ω
LVPECL Inp
ut
3.3V
3
.3V
+
_
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
12 ©2012 Integrated Dev i ce Technology, Inc.
Termination for 2.5V LVPECL Outputs
Figure 2A and Figure 2B show examples of termination for 2.5V
L VPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 2B can be eliminated and the termination is
shown in Figure 2C.
Figure 2A. 2.5V LVPECL Driver Termination Example
Figure 2C. 2.5V LVPECL Driver Termination Example
Figure 2B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
VCC = 2.5V 2.5V
2.5V
50Ω
50Ω
R1
250Ω
R3
250Ω
R2
62.5Ω
R4
62.5Ω
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50Ω
R2
50Ω
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50Ω
R2
50Ω
R3
18Ω
+
–
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
13 ©2012 Integrated Dev i ce Technology, Inc.
Schematic Layout
Figure 3 shows an example of IDT8N3Q00 1 application schematic.
In this example, the device is operated at VCC = 3.3V. As with any
high speed analog circuitry, the power supply pins are vulnerable to
noise. To achieve optimum jitter performance, power supply isolation
is required. The IDT8N3Q001 pro vi des separate power supplies to
isolate from coupling into the internal PLL.
In order to achi eve the best possible fi ltering, it is recom mended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally ,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Figure 3. IDT8N3Q001 Applicat ion Schematic
Zo = 5 0 Oh m
nQ
R7
50
RU2
Not Install
SCLK
R3
133
SDATA
Logi c Control Input Examples
FSEL1
R1
SP
VCC
+
-
BLM18BB221SN1
Ferrite Bead
1 2
RU1
1K
RD1
Not Install
Q
VCC
3.3V
R2
SP
R6
82.5
C3
0.1uF
VCC
OE
3.3V
To Logic
Input
pins
Set Logic
Input to
'0'
FSEL0
R4
133
VCC
Zo = 5 0 Oh m
R9
50
R5
82.5
C1
0.1uF
Optional
Y-Termination
R8
50
To Logic
Input
pins
C2
10uF
S et Logic
Input to
'1'
Zo = 5 0 Oh m
U1
1
2
3 6
7
8
4
5 9
10
DNU
OE
VEE Q
nQ
VCC
FSEL0
FSEL1 SDATA
SCLK
VCC=3.3V
+
-
RD2
1K
Zo = 5 0 Oh m
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
14 ©2012 Integrated Dev i ce Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N3Q001.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8N3Q001 is the sum of the core power plus the powe r dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW
• Power (outputs)MAX = 34.2mW/Loaded Ou tpu t pair
Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 34.2mW = 519.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculatio n is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C /W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.519W * 49.4°C/W = 110.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 10 Lead Cera mic 5mm x 7mm Package, Forced Convection
JA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 41°C/W
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
15 ©2012 Integrated Dev i ce Technology, Inc.
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 4.
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V
(VCC_MAX – VOH_MAX) = 0.8V
• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V
(VCC_MAX – VOL_MAX) = 1.5V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.5V)/50] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 34.2mW
VOUT
VCC
VCC
- 2V
Q1
RL
50Ω
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
16 ©2012 Integrated Dev i ce Technology, Inc.
Reliability Information
Table 8. JA vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package
NOTE: For proper thermal dissipation, the PCB layout for the pin pad should at minimum equal the package pin dimensions.
Transistor Count
The transistor count for IDT8N3Q001 Rev G is: 47,372
JA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 41°C/W
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
17 ©2012 Integrated Dev i ce Technology, Inc.
Package Outline and Package Dimensions
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
18 ©2012 Integrated Dev i ce Technology, Inc.
Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products
The programmable VCXO and XO devices support a va riety of
devices options such as the output type, number of default frequen-
cies, internal crystal frequency, power supply voltage, ambient
temperature range and the frequency accuracy. The device options,
default frequenci es and default VCXO pull range must be specified
at the time of order and are programmed by IDT before the shipment.
Shown below are the availabl e or der codes, including the device
options and default frequency configurations. Example part number:
the order code 8N3QV01FG-0001CDI specifies a programmab le,
quad default-frequency VCXO with a voltage supply of 2.5V, a
LVPECL output, a 50 ppm crystal frequency accuracy, contains a
114.285MHz internal crystal as frequency source, industrial
temperature range, a lead-free (6/6 RoHS) 10-lea d Ceramic 5mm x
7mm x 1.55mm p ack ag e and is fa ctory-programmed to the default
frequencies of 100MHz, 122.88MHz, 125MHz and 156.25MHz and
to the VCXO pull range of minimum 100 ppm.
Other default frequencies and order codes are available from IDT on
request. For more information on available default frequencies, see
the FemtoClock NG Ceramic-Package XO and VCXO Ordering
Product Information document.
Shipping Package
8: Tape & Reel
(no letter): Tr ay
Ambient Temperature Range
“I”: Industrial: (TA = -40°C to 85°C)
(no letter) : (TA = 0°C to 70°C)
Package Code
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm
Die Revision
G
Option Code (Supply Voltage and Frequency-Stability)
A: VCC = 3.3V±5%, ±100ppm
B: VCC = 2.5V±5%, ±100ppm
E: VCC = 3.3V±5%, ±50ppm
F: VCC = 2.5V±5%, ±50ppm
K: VCC = 3.3V±5%, ±20ppm
L: VCC = 2.5V±5%, ±20ppm
Default-Frequenc y and VCXO Pull Range
See document FemtoClock NG Ceramic-Package XO and VCXO
Ordering Product Information.
Last digit = L: configuration pre-programmed and not changable
dddd fXTAL (MHz) PLL feedback Use for
0000 to 0999 114.285 Fractional VCXO, XO
1000 to 1999 100.000 Integer XO
2000 to 2999 Fractional XO
FemtoClock NG
I/O Identifier
0: LVCMOS
3: LVPE CL
4: LVDS
Number of Default Freq ue nc ie s
S: 1: Single
D: 2: Dual
Q: 4: Quad
Part Number
Function #pins OE fct. at
pin
001 XO 10 OE@2
003 XO 10 OE@1
V01 VCXO 10 OE@2
V03 VCXO 10 OE@1
V75 VCXO 6 OE@2
V76 VCXO 6 nOE@2
V85 VCXO 6 —
085 XO 6 OE@1
270 XO 6 OE@1
271 XO 6 OE@2
272 XO 6 nOE@2
273 XO 6 nOE@1
8N X X XXX X X - dddd XX X X
Part Order/Nu mb er
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
19 ©2012 Integrated Dev i ce Technology, Inc.
Table 9. Device Marking
Marking
Industrial Temperature Range (TA = -40°C to 85°C) Commercial Temperature Range (TA = 0°C to 70°C)
IDT8N3x001yG-
ddddCDI IDT8N3x001yG-
ddddCD
x = Number of Default Frequencies, y = Option Code, dddd=Default-Frequency and VCXO Pull Range
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any p atent s or other right s of third par ties, which woul d result from its use. No oth er circu it s, p atent s, or l icenses ar e implied. This product is intende d for use in normal
commercial and industrial applicat ions. Any other app lications, such as those requi ring high reliabi lity or other extrao rdinary environment al requirement s are not recommended wit hout
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
20 ©2012 Integrated Dev i ce Technology, Inc.
Revision History Sheet
Rev Table Page Description of Change Date
A 9 19 Table 9 Device Marking, corrected marking. 3/6/12
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications describe d herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way whe n installed in customer products. The information contained herein is provided without representation or warranty of any kind, whethe r express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not c onvey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or simi lar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registere d trademarks of ID T. Other tr ademar ks and ser vice mark s used herein, including protected names, logos and designs, are the property of IDT or the ir respe ctive third
party owners.
Copyright 2012. All rights reserved.
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