1
FEATURES
THS4151
D, DGN, DGK PACKAGES
(TOP VIEW)
1
2
3
4
8
7
6
5
VIN-
VOCM
VCC+
VOUT+
VIN+
NC
VCC-
VOUT-
THS4150
D, DGN, DGK PACKAGES
(TOP VIEW)
SHUTDOWN
NUMBER OF
CHANNELS
DEVICE
THS4150
THS4151 1
1X
-
HIGH-SPEED DIFFERENTIAL I/O FAMILY
1
2
3
4
8
7
6
5
VIN-
VOCM
VCC+
VOUT+
VIN+
PD
VCC-
VOUT-
Typical A/D Application Circuit
KEY APPLICATIONS
DIGITAL
OUTPUT
VIN
−
+−
+
DVDD
VOCM
AVSS
AVDD
AIN
AIN
VDD
Vref
5 V
−5 V
DESCRIPTION
−100
−90
−80
−70
−60
−50
−40
100 k 1 M
THD − Total Harmonic Distortion − dB
f − Frequency − Hz
THS4151
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
10 M 100 M
Single Input to
Differential Output
Differential Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = 5 V to ±15 V
THS4150
THS4151
www.ti.com
........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
HIGH-SPEED DIFFERENTIAL I/O AMPLIFIERS
23
•High Performance
– 150 MHz – 3 dB Bandwidth (V
CC
= ± 5 V)– 650 V/ µs Slew Rate (V
CC
= ± 15 V)– – 89 dB Third Harmonic Distortion at 1 MHz– – 83 dB Total Harmonic Distortion at 1 MHz– 7.6 nV/ √Hz Input-Referred Noise•Differential Input/Differential Output– Balanced Outputs Reject Common-ModeNoise
– Differential Reduced Second HarmonicDistortion
•Wide Power-Supply Range– V
CC
= 5 V Single-Supply to ± 15 V DualSupply
•I
CC(SD)
= 1 mA (V
CC
= ± 5) in Shutdown Mode(THS4150)
•Single-Ended to Differential Conversion•Differential ADC Driver•Differential Antialiasing•Differential Transmitter and Receiver•Output Level Shifter
The THS415x is one in a family of fully differentialinput/differential output devices fabricated usingTexas Instruments ' state-of-the-art BiComIcomplementary bipolar process.
The THS415x is made of a true fully-differential signalpath from input to output. This design leads to anexcellent common-mode noise rejection andimproved total harmonic distortion.
RELATED DEVICES
DEVICE DESCRIPTION
THS412x 100 MHz, 43 V/ µs, 3.7 nV/ √HzTHS413x 150 MHz, 51 V/ µs, 1.3 nV/ √HzTHS414x 160 MHz, 450 V/ µs, 6.5 nV/ √Hz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
(1)
PACKAGED DEVICES
EVALUATIONT
A
MSOP PowerPAD™ MSOP
MODULESSMALL OUTLINE(D)
(DGN) SYMBOL (DGK) SYMBOL
THS4150CD THS4150CDGN AQB THS4150CDGK ATT THS4150EVM0 ° C to 70 ° C
THS4151CD THS4151CDGN AQD THS4151CDGK ATU THS4151EVMTHS4150ID THS4150IDGN AQC THS4150IDGK AST –– 40 ° C to 85 ° C
THS4151ID THS4151IDGN AQE THS4151IDGK ASU –
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
Over operating free-air temperature range (unless otherwise noted).
UNIT
V
CC-
to
Supply voltage ± 16.5 VV
CC+
V
I
Input voltage ± V
CC
I
O
Output current
(2)
150 mAV
ID
Differential input voltage ± 6 VContinuous total power dissipation See Dissipation Rating TableMaximum junction temperature
(3)
150 ° CT
J
Maximum junction temperature, continuous operation, long term reliability
(4)
125 ° CC suffix 0 ° C to 70 ° CT
A
Operating free-air temperature
I suffix – 40 ° C to 85 ° CT
stg
Storage temperature – 65 ° C to 150 ° CLead temperature
(5)
HBM 2500 VESD ratings CDM 1500 VMM 200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The THS415x may incorporate a PowerPad™ on the underside of the chip. This acts as a heatsink and must be connected to athermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperaturewhich could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing thePowerPad™ thermally enhanced package.(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature mayresult in reduced reliability and/or lifetime of the device.(5) See the MSL/Reflow Rating information provided with the material, or see TI ' s web site at www.ti.com for the latest information.
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DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
THS4150
THS4151
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........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
POWER RATING
(2)θ
JA
(1)
θ
JCPACKAGE
( ° C/W) ( ° C/W)
T
A
= 25 ° C T
A
= 85 ° C
D 97.5 38.3 1.02 W 410 mWDGN 58.4 4.7 1.71 W 685 mWDGK 260 54.2 385 mW 154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.(2) Power rating is determined with a junction temperature of 125 ° C. This is the point where distortionstarts to substantially increase. Thermal management of the final PCB should strive to keep thejunction temperature at or below 125 ° C for best performance and long term reliability.
MIN TYP MAX UNIT
Dual supply ± 2.5 ± 15V
CC+
to
Supply voltage VV
CC –
Single supply 5 30C suffix 0 70T
A
Operating free-air temperature ° CI suffix – 40 85
At V
CC
= 15 V, R
L
= 800 Ω, T
A
= 25 ° C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
V
CC
= 5 150Gain = 1,BW Small-signal bandwidth ( – 3 dB) V
CC
= ± 5 150 MHzR
f
= 390 ΩV
CC
= ± 15 150V
CC
= 5 80Gain = 2,BW Small-signal bandwidth ( – 3 dB) V
CC
= ± 5 81 MHzR
f
= 750 ΩV
CC
= ± 15 81SR Slew rate
(1)
V
CC
= ± 15, Gain = 1 650 V/ µsSettling time to 0.1% 53Differential step voltage = 2 V
PP
,t
s
nsGain = 1Settling time to 0.01% 247
DISTORTION PERFORMANCE
f = 1 MHz – 85V
CC
= 5
f = 8 MHz – 66Total harmonic distortion
f = 1 MHz – 83THD Differential input, differential output Gain = 1, V
CC
= ± 5 dBf = 8 MHz – 65R
f
= 390 Ω, R
L
= 800 Ω, V
O
= 2 V
PP
f = 1 MHz – 84V
CC
= ± 15
f = 8 MHz – 65Spurious free dynamic range (SFDR) V
O
= 2 V
PP
, f = 1 MHz – 87 dBV
O
= 0.14 V
RMS
, Gain = 1,Third intermodulation distortion – 95 dBcf = 20 MHz
NOISE PERFORMANCE
V
n
Input voltage noise f > 10 kHz 7.6 nV/ √HzI
n
Input current noise f > 10 kHz 1.78 pA/ √Hz
(1) Slew rate is measured from an output level range of 25% to 75%.
Copyright © 2000 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
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THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)At V
CC
= 15 V, R
L
= 800 Ω, T
A
= 25 ° C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC PERFORMANCE
T
A
= 25 ° C 63 67Open loop gain dBT
A
= full range
(2)
60T
A
= 25 ° C 1.1 7Input offset voltage
T
A
= full range 8.5 mVV
OS
Input offset voltage, referred to V
OCM
T
A
= 25 ° C 0.6 8Offset drift T
A
= full range 7 µV/ ° CI
IB
Input bias current 4.3 15 µAT
A
= full rangeI
OS
Input offset current 250 1200 nAOffset drift T
A
= full range 0.7 nA/ ° CShutdown delay to output T
A
= full range 1.1 µs
INPUT CHARACTERISTICS
CMRR Common-mode rejection ratio T
A
= full range – 75 – 83 dBV
S –
+1.5VV
ICR
Common-mode input voltage range to VV
S+
– 1.5Vr
I
Input resistance Measured into each input terminal 14.4 M Ω
C
I
Input capacitance, closed loop 3.9 pFr
o
Output resistance Open loop/single ended 0.4 Ω
r
o(SD)
Output resistance Shutdown 636 Ω
OUTPUT CHARACTERISTICS
T
A
= 25 ° C 1.2 to 3.8 0.9 to 4.1V
CC
= 5 V
T
A
= full range 1.2 to 3.8T
A
= 25 ° C ± 3.7 ± 3.9Output voltage swing V
CC
= ± 5 V VT
A
= full range ± 3.6T
A
= 25 ° C ± 11.6 ± 12.7V
CC
= ± 15 V
T
A
= full range ± 11T
A
= 25 ° C 30 45V
CC
= 5 V
T
A
= full range 25T
A
= 25 ° C 45 60I
O
Output current, R
L
= 7 ΩV
CC
= ± 5 V mAT
A
= full range 35T
A
= 25 ° C 65 85V
CC
= ± 15 V
T
A
= full range 50
POWER-SUPPLY
Single supply 4 30 33V
CC
Supply voltage range VSplit supply ± 2 ± 15 ± 16.5T
A
= 25 ° C 15.8 18.5V
CC
= ± 5 V
T
A
= full range 21I
CC
Quiescent current (per amplifier) mAT
A
= 25 ° C 17.5 21V
CC
= ± 15 V
T
A
= full range 23T
A
= 25 ° C 1 1.3I
CC(SD)
Quiescent current (shutdown) (THS4150)
(3)
mAT
A
= full range 1.5T
A
= 25 ° C 70 90PSRR Power-supply rejection ratio (dc) dBT
A
= full range 65
(2) The full range temperature is 0 ° C to 70 ° C for the C suffix, and – 40 ° C to 85 ° C for the I suffix.(3) For detailed information on the behavior of the power-down circuit, see the Power-down mode description in the Principles of Operationsection of this data sheet.
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TYPICAL CHARACTERISTICS
Table of Graphs
TYPICAL CHARACTERISTICS
−20
−10
0
10
20
30
40
50
100 k 1 M 10 M
G − Gain − dB
f − Frequency − Hz 100 M 1 G
G = 10
G = 5
G = 2
G = 1
VCC = ±5 V
VI = 22.5 mVRMS
G = 100
−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
100k 1M 10M 100M 1G
GGain dB- -
f Frequency Hz- -
V =5
CC
V = 15
CC ±
V = 5
CC ±
Gain=1
R =390
R =800
V =22.5mV
f
L
I RMS
W
W
THS4150
THS4151
www.ti.com
........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
FIGURE
Small-signal frequency response 1, 2Large-signal frequency response 3Settling time 4SR Slew rate vs Temperature 5vs Frequency 6Total harmonic distortion
vs Output voltage 7vs Frequency 8 – 13Harmonic distortion
vs Output voltage 14 – 17Third intermodulation distortion vs Output voltage 18V
n
Voltage noise vs Frequency 19I
n
Current noise vs Frequency 20V
O
Output voltage vs Single-ended load resistance 21Power supply current shutdown vs Supply voltage 22Output current range vs Supply voltage 23V
OS
Single-ended output offset voltage vs Common-mode output voltage 24CMRR Common-mode rejection ratio vs Frequency 25z Impedance of the V
OCM
terminal vs Frequency 26z
o
Output impedance (powered up) vs Frequency 27z
o
Output impedance (shutdown) vs Frequency 28PSRR Power-supply rejection ratio vs Frequency 29
SMALL-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL FREQUENCY RESPONSE
Figure 1. Figure 2.
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1.9
1.7
1.6
1.5 0 50 100 150
− Output Voltage − V
2
2.1
2.3
200 250 300
1.8
2.2
ts − Settling T ime − ns
VO
Rf = 390 Ω,
CF = 1 pF,
VCC = ±5 V,
VO = 4 Vpp,
Gain = 1
Settling to 1% = 17.2 ns
Settling to 0.1% = 53.3 ns
Settling to 0.01% = 247.5 ns
−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
100 k 1 M 10 M
G − Gain − dB
f − Frequency − Hz 100 M 1 G
VCC = 5 VCC = ±5
VCC = ±15
Gain = 1
Rf = 390 Ω,
RL = 800 Ω,
VI = 0.2 VRMS
400
450
500
550
600
650
700
−40 −20 0 20 60 80 100
VCC = ±15 V, VO = 2 VPP
VCC = ±15 V, VO = 4 VPP
VCC = ±5 V, VO = 2 VPP
VCC = ±5 V, VO = 4 VPP
CL= 0,
CF = 1 pF
T − Temperature −°C
40
SR − Slew Rate − V/ sµ
−100
−90
−80
−70
−60
−50
−40
100 k 1 M
THD − Total Harmonic Distortion − dB
f − Frequency − Hz
10 M 100 M
Single Input to
Differential Output
Differential Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±5 V to ±15 V
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
LARGE-SIGNAL FREQUENCY RESPONSE SETTLING TIME
Figure 3. Figure 4.
SLEW RATE TOTAL HARMONIC DISTORTIONvs vsTEMPERATURE FREQUENCY
Figure 5. Figure 6.
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−100
−90
−80
−70
0.2 1.2 2.2 3.2 4.2
Single Input to
Differential Output
Differential Input to
Differential Output
VCC = ±5 to ±15
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
f = 1 MHz
THD − Total Harmonic Distortion − dB
VO − Output Voltage − V
−120
−110
−100
−90
−80
−70
−60
−50
−40
Harmonic Distortion − dB
100 k 1 M
f − Frequency − Hz
10 M 100 M
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±2.5 V
2nd HD
3rd HD
5th HD
4th HD
Single Input to
Differential Output
−120
−110
−100
−90
−80
−70
−60
−50
−40
Harmonic Distortion − dB
100 k 1 M
f − Frequency − Hz
10 M 100 M
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±5 V
2nd HD
3rd HD
5th HD
4th HD
Single Input to
Differential Output
THS4150
THS4151
www.ti.com
........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vsOUTPUT VOLTAGE
Figure 7.
HARMONIC DISTORTION HARMONIC DISTORTIONvs vsFREQUENCY FREQUENCY
Figure 8. Figure 9.
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−120
−110
−100
−90
−80
−70
−60
−50
−40
Harmonic Distortion − dB
10 k 100 k
f − Frequency − Hz
1 M 10 M
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±2.5 V
2nd HD
3rd HD
5th HD
4th HD
Differential Input to
Differential Output
−120
−110
−100
−90
−80
−70
−60
−50
−40
Harmonic Distortion − dB
100 k 1 M
f − Frequency − Hz
10 M 100 M
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±5 V
2nd HD
3rd HD
5th HD
4th HD
Differential Input to
Differential Output
−120
−110
−100
−90
−80
−70
−60
−50
−40
Harmonic Distortion − dB
10 k 100 k
f − Frequency − Hz
1 M 10 M
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±15 V
2nd HD
3rd HD
5th HD
4th HD
Differential Input to
Differential Output
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION HARMONIC DISTORTIONvs vsFREQUENCY FREQUENCY
Figure 10. Figure 11.
HARMONIC DISTORTION HARMONIC DISTORTIONvs vsFREQUENCY FREQUENCY
Figure 12. Figure 13.
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−120
−110
−100
−90
−80
−70
0 1 2 3 4 5
3rd HD
2nd HD
5th HD
4th HD
Single Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±5 V
f = 1 MHz
Harmonic Distortion − dB
VO − Output Voltage − V
−120
−110
−100
−90
−80
−70
0 1 2 3 4 5
3rd HD
2nd HD
5th HD
4th HD
Single Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±15 V
f = 1 MHz
Harmonic Distortion − dB
VO − Output Voltage − V
−120
−110
−100
−90
−80
−70
0 1 2 3 4 5
3rd HD
2nd HD
5th HD
4th HD
Differential Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±5 V
f = 1 MHz
Harmonic Distortion − dB
VO − Output Voltage − V
−120
−110
−100
−90
−80
−70
0 1 2 3 4 5
3rd HD
2nd HD
5th HD
4th HD
Differential Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±15 V
f = 1 MHz
Harmonic Distortion − dB
VO − Output Voltage − V
THS4150
THS4151
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........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION HARMONIC DISTORTIONvs vsOUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 14. Figure 15.
HARMONIC DISTORTION HARMONIC DISTORTIONvs vsOUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 16. Figure 17.
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−110
−100
−90
−80
−70
−12 −7 −2 3 8
Single Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±5 V,
f = 1 MHz
Third Intermodulation Distortion − dB
VO − Output Voltage − V
10
110 100 1 k
− Voltage Noise −
f − Frequency − Hz
100
10 k 100 k
VnnV/ Hz
VCC = 5 V to ±15 V
−15
−10
−5
0
5
10
15
10 100 1 k 10 k 100 k
VCC = ±15 V
VCC = − ±15 V
VCC = ±5 V
VCC = − ±5 V
− Output Voltage − V
VO
RL − Single-Ended Load Resistance − Ω
VOUT+
VOUT−
VOUT−
VOUT+
1
10
100
10 100 1 k 100 k10 k
− Current Noise −
f − Frequency − Hz
InpA/ Hz
VCC = 5 V to ±15 V
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
THIRD INTERMODULATION DISTORTION VOLTAGE NOISEvs vsOUTPUT VOLTAGE FREQUENCY
Figure 18. Figure 19.
CURRENT NOISE OUTPUT VOLTAGEvs vsFREQUENCY SINGLE-ENDED LOAD RESISTANCE
Figure 20. Figure 21.
10 Submit Documentation Feedback Copyright © 2000 – 2009, Texas Instruments Incorporated
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0
0.5
1
1.5
2
2.5
0 2 4 6 8 10 12 14 16
VCC − Supply Voltage − ±V
− Power Supply Current Shutdown − ICC mA
TA = 25°C
0
10
20
30
40
50
60
70
80
90
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TA = 40°C
TA = 25°C
TA = 125°C
TA = 85°C
VCC − Supply Voltage − V
− Output Current Range − mA
IO
−100
−60
−20
20
60
100
−12 −7 −2 3 8
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
− Single-Ended Output Offset Voltage − mV
VOCM − Common-Mode Output Voltage − V
VOS
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
CMRR − Common Mode Rejection Ratio − dB
f − Frequency − Hz
1 M 10 M 100 M 1 G
VCC = 5 V to ±15 V,
VI = 0.25 VRMS
THS4150
THS4151
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........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)
POWER-SUPPLY CURRENT SHUTDOWN OUTPUT CURRENT RANGEvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 22. Figure 23.
SINGLE-ENDED OUTPUT OFFSET VOLTAGE COMMON-MODE REJECTION RATIOvs vsCOMMON-MODE OUTPUT VOLTAGE FREQUENCY
Figure 24. Figure 25.
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0
2000
4000
6000
8000
10000
12000
14000
16000 VCC = 5 V to ±15 V
f − Frequency − Hz
z − Impedance of the V
100 k 1 M 10 M 100 M 1 G
Ω
OCM Terminal −
0.1
1
10
100
100 k 1 M 10 M
Output Impedance −
f − Frequency − Hz 100 M 1 G
Ω
VCC = ±5 V
−70
−60
−50
−40
−30
−20
−10
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
100 k 1 M 10 M 100 M 1 G
VCC− = 225 mVRMS + (-2.5 V) dc
= 225 mVRMS + (-5 V) dc
= 225 mVRMS + (-15 V) dc
VCC+ = 2.5 V, 5 V, 15 V
10
100
1000
100 k 1 M 10 M
Output Impedance (Shutdown) −
100 M 1 G
Ω
VCC = ±5 V
Rf = R(g) = 500 Ω
f − Frequency − Hz
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
IMPEDANCE OF THE V
OCM
TERMINAL OUTPUT IMPEDANCE (POWERED UP)vs vsFREQUENCY FREQUENCY
Figure 26. Figure 27.
OUTPUT IMPEDANCE (SHUTDOWN) POWER-SUPPLY REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 28. Figure 29.
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Product Folder Link(s): THS4150 THS4151
APPLICATION INFORMATION
RESISTOR MATCHING
ǒVCC)Ǔ)ǒVCC–Ǔ
2
_
+
x1
Output Buffer
Vcm Error
Amplifier
C R
CR
x1
Output Buffer
VOUT+
VOUT-
VCC+
VCC-
VIN-
VIN+
30 kΩ30 kΩVCC+
VCC- VOCM
THS4150
THS4151
www.ti.com
........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltagedepends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortionwill diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better tokeep the performance optimized.
V
OCM
sets the dc level of the output signals. If no voltage is applied to the V
OCM
pin, it will be set to the midrailvoltage internally defined as:
In the differential mode, the V
OCM
on the two outputs cancel each other. Therefore, the output in the differentialmode is the same as the input when gain is 1. V
OCM
has a high bandwidth capability up to the typical operatingrange of the amplifier. For the prevention of noise going through the device, use a 0.1- µF capacitor on the V
OCMpin as a bypass capacitor. Figure 30 shows the simplified diagram of the THS415x.
Figure 30. THS415x Simplified Diagram
Copyright © 2000 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
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DATA CONVERTERS
VIN
-
+-
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 µF
-5 V
VCC-
VIN
-
+-
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 µF
VIN
-
+-
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 µF
VCC
RPU
VCC
RPU
THS1206
R(g)
R(g)
VP
Rf
Rf
VOUT
VOUT
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
www.ti.com
Data converters are one of the most popular applications for the fully differential amplifiers. The followingschematic shows a typical configuration of a fully differential amplifier attached to a differential ADC.
Figure 31. Fully Differential Amplifier Attached to a Differential ADC
Fully differential amplifiers can operate with a single supply. V
OCM
defaults to the midrail voltage, V
CC
/2. Thedifferential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit.If the ADC has a reference voltage output (V
ref
), then it is recommended to connect it directly to the V
OCM
of theamplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the inputterminal of the amplifier should not exceed the common-mode input voltage range.
Figure 32. Fully Differential Amplifier Using a Single-Supply
Some single-supply applications may require the input voltage to exceed the common-mode input voltage range.In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within thespecifications of the amplifier.
Figure 33. Circuit With Improved Common-Mode Input Voltage
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Product Folder Link(s): THS4150 THS4151
RPU +VP– VCC
ǒVIN – VPǓ1
RG )ǒVOUT – VPǓ1
RF
DRIVING A CAPACITIVE LOAD
THS415x
Output
Output
20 Ω
20 Ω
390 Ω
390 Ω
390 Ω
390 Ω
ACTIVE ANTIALIAS FILTERING
VIN-
VIN++
-+
-
VOCM
VOCM
VIN-
VIN+
VCC-
THS1050
THS415x
C3
C3
R4
R(t)
R2
R4
+
C1
+
VCC
C1
R2
R3
R3
C2
R1
R1
Vs
VIC
THS4150
THS4151
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........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
The following equation is used to calculate R
PU
:
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions aretaken. The first is to realize that the THS415x has been internally compensated to maximize its bandwidth andslew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on theoutput will decrease the device's phase margin leading to high-frequency ringing or oscillations. Therefore, forcapacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output ofthe amplifier, as shown in Figure 34 . A minimum value of 20 Ωshould work well for most applications. Forexample, in 50- Ωtransmission systems, setting the series resistor value to 20 Ωboth isolates any capacitanceloading and provides the proper line impedance matching at the source end.
Figure 34. Driving a Capacitive Load
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-passfilters can prevent the aliasing of the high frequency noise with the frequency of operation. Figure 35 presents amethod by which the noise may be filtered in the THS415x.
Figure 35. Antialias Filtering
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Hd(f) +ȧ
ȧ
ȡ
Ȣ
K
–ǒf
FSF x fcǓ2)1
Qjf
FSF x fc )1ȧ
ȧ
ȣ
Ȥ
xȧ
ȡ
Ȣ
Rt
2R4 )Rt
1)j2πfR4RtC3
2R4 )Rt ȧ
ȣ
ȤWhere K +R2
R1
FSF x fc +1
2π2 x R2R3C1C2
Ǹand Q +2 x R2R3C1C2
Ǹ
R3C1 )R2C1 )KR3C1
FSF +Re2)|Im|2
Ǹand Q +Re2)|Im|2
Ǹ2Re
FSF x fc +1
2πRC 2 x mn
Ǹand Q +2 x mn
Ǹ
1)m(1)K)
THEORY OF OPERATION
Rf
R(g)
R(g) Rf
_
+
Differential Amplifier
VOCM
_
+_
+
VCC+
VIN-
VIN+
VO+
VO-
THS415x
Fully differential Amplifier
VCC-
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
www.ti.com
The transfer function for this filter circuit is:
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency-scaling factor, and Q is thequality factor.
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 =C, and C2 = nC results in:
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then selectC and calculate R for the desired fc.
PRINCIPLES OF OPERATION
The THS415x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereasfully differential amplifiers are differential in/differential out.
Figure 36. Differential Amplifier Versus a Fully Differential Amplifier
To understand the THS415x fully differential amplifiers, the definition for the pinouts of the amplifier are provided.
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Input voltage definition VID +ǒVI)Ǔ–ǒVI–ǓVIC +ǒVI)Ǔ)ǒVI–Ǔ
2
Output voltage definition VOD +ǒVO)Ǔ–ǒVO–ǓVOC +ǒVO)Ǔ)ǒVO–Ǔ
2
Transfer function VOD +VID x AǒfǓ
Output common mode voltage VOC +VOCM
VOCM
_
+_
+
VCC+
VIN-
VIN+
VO+
VO-
Differential Structure Rejects
Coupled Noise at the Output
Differential Structure Rejects
Coupled Noise at the Input
Differential Structure Rejects
Coupled Noise at the Power Supply VCC-
−
Rf
R(g)
+
+
−
VCC−
VCC+
R(g)
Rf
Vs
VIN−
VIN+
VO+
VO−
VOCM
Note: For proper operation, maintain symmetry by setting
Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g) ⇒ A = Rf/R(g)
-
Rf
R(g)
+
+
-
VCC-
VCC+
R(g)
Rf
Vs
VIN-
VIN+
VO+
VO-
VOCM
GAIN R(g) ΩRf Ω
1
2
5
10
390
374
402
402
390
750
2010
4020
RECOMMENDED RESISTOR VALUES
THS4150
THS4151
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........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
Figure 37. Definition of the Fully Differential Amplifier
The following schematics depict the differences between the operation of the THS415x, a fully differentialamplifier, in two different modes. Fully differential amplifiers can work with differential input or can beimplemented as single in/differential out.
Figure 38. Amplifying Differential Signals
Figure 39. Single In With Differential Out
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VO)+VI)
2)VOCM
VO– +–VI)
2)VOCM
VOCM
_
+_
+
VCC+
VIN-
VIN+
VO+
VO-
VOD= 1-0 = 1
VOD = 0-1 = -1
a
b
+1
0
+1
0
VCC-
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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If each output is measured independently, each output is one-half of the input signal when the gain is 1. Thefollowing equations express the transfer function for each output:
The second output is equal and opposite in sign:
V
OCM
will be set to midrails if it is not derived by any external power source.
Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an invertingamplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice asmuch dynamic range compared to single-ended amplifiers. For example, a 1-V
PP
ADC can only support an inputsignal of 1 V
PP
. If the output of the amplifier is 2 V
PP
, then it will not be practical to feed a 2-V
PP
signal into thetargeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-V
PP
signalswith opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has beenable to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differential amplifier. Thefinal result indicates twice as much dynamic range.
Figure 40 illustrates the increase in dynamic range. The gain factor should be considered in this scenario. TheTHS415x fully differential amplifier offers an improved CMRR and PSRR due to its symmetrical input and output.Furthermore, second harmonic distortion is improved. Second harmonics tend to cancel because of thesymmetrical output.
Figure 40. Fully Differential Amplifier With Two 1-V
PP
Signals
Similar to the standard inverting amplifier configuration, input impedance of a fully differential amplifier is selectedby the input resistor, R
(g)
. If input impedance is a constraint in design, the designer may choose to implement thedifferential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the fullydifferential amplifier. The following schematic depicts the general format of instrumentation amplifiers.
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VOD
VIN1 – VIN2 +Rf
R(g) ǒ1)2R2
R1 Ǔ
_
+
_
+
_
+
THS4012
THS4012
VIN1
VIN2
R2
R1
R2
R(g)
R(g)
Rf
Rf
THS415x
CIRCUIT LAYOUT CONSIDERATIONS
THS4150
THS4151
www.ti.com
........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
The general transfer function for this circuit is:
Figure 41. Fully Differential Instrumentation Amplifier
To achieve the levels of high frequency performance of the THS415x, follow proper printed-circuit board highfrequency design techniques. A general set of guidelines is given below. In addition, a THS415x evaluation boardis available to use as a guide for layout or for evaluating the device performance.•Ground planes — It is highly recommended that a ground plane be used on the board to provide allcomponents with a low inductive ground connection. However, in the areas of the amplifier inputs and output,the ground plane can be removed to minimize the stray capacitance.•Proper power supply decoupling — Use a 6.8- µF tantalum capacitor in parallel with a 0.1- µF ceramic capacitoron each supply terminal. It may be possible to share the tantalum among several amplifiers depending on theapplication, but a 0.1- µF ceramic capacitor should always be used on the supply terminal of every amplifier.In addition, the 0.1- µF capacitor should be placed as close as possible to the supply terminal. As this distanceincreases, the inductance in the connecting trace makes the capacitor less effective. The designer shouldstrive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.•Sockets — Sockets are not recommended for high-speed operational amplifiers. The additional leadinductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directlyto the printed-circuit board is the best implementation.•Short trace runs/compact part placements — Optimum high frequency performance is achieved when strayseries inductance has been minimized. To realize this, the circuit layout should be made as compact aspossible, thereby minimizing the length of all trace runs. Particular attention should be paid to the invertinginput of the amplifier. Its length should be kept as short as possible. This will help to minimize straycapacitance at the input of the amplifier.•Surface-mount passive components — Using surface-mount passive components is recommended for highfrequency amplifier circuits for several reasons. First, because of the extremely low lead inductance ofsurface-mount components, the problem with stray series inductance is greatly reduced. Second, the smallsize of surface-mount components naturally leads to a more compact layout, thereby minimizing both strayinductance and capacitance. If leaded components are used, it is recommended that the lead lengths be keptas short as possible.
Copyright © 2000 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
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POWER-DOWN MODE
VCC
PD
VCC-
To Internal Bias
Circuitry Control
50 kΩ
10
100
1000
100 k 1 M 10 M
f Frequency - Hz
OUTPUT IMPEDANCE (SHUTDOWN)
vs
FREQUENCY
100 M 1 G
VCC = ±5 V
Output Impedance (Shutdown) - Ω
Rf = R(g) = 500 Ω
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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The power-down mode is used when power saving is required. The power-down terminal ( PD) found on theTHS415x is an active low terminal. If it is left as a no-connect terminal, the device will always stay on due to aninternal 50 k Ωresistor to V
CC
. The threshold voltage for this terminal is approximately 1.4 V above V
CC –
. Thismeans that if the PD terminal is 1.4 V above V
CC –
, the device is active. If the PD terminal is less than 1.4 Vabove V
CC –
, the device is off. For example, if V
CC –
= – 5 V, then the device is on when PD reaches 3.6 V, ( – 5 V +1.4 V = – 3.6 V). By the same calculation, the device is off below – 3.6 V. It is recommended to pull the terminal toV
CC –
in order to turn the device off. Figure 42 shows the simplified version of the power-down circuit. While in thepower-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is typicallygreater than 1 M Ωin the power-down state.
Figure 42. Simplified Power-Down Circuit
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be verylow while in the power-down state. This is because the feedback resistor (R
f
) and the gain resistor (R
(g)
) are stillconnected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output ofthe amplifier. An example of the closed-loop output impedance is shown in Figure 43 .
Figure 43.
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GENERAL PowerPAD DESIGN
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
THS4150
THS4151
www.ti.com
........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
The THS415x is available packaged in a thermally-enhanced DGN package, which is a member of thePowerPAD family of packages. This package is constructed using a downset leadframe upon which the die ismounted [see Figure 44 (a) and Figure 44 (b)]. This arrangement results in the lead frame being exposed as athermal pad on the underside of the package [see Figure 44 (c)]. Because this thermal pad has direct thermalcontact with the die, excellent thermal performance can be achieved by providing a good thermal path away fromthe thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also besoldered to a copper area underneath the package. Through the use of thermal paths within this copper area,heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of thesurface mount with the, heretofore, awkward mechanical methods of heatsinking.
More complete details of the PowerPAD™ installation process and thermal management techniques can befound in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002 ). Thisdocument can be found at the TI web site (www.ti.com ) by searching on the key word PowerPAD. Thedocument can also be ordered through your local TI sales office. Refer to literature number SLMA002 whenordering.
A. The thermal pad is electrically isolated from all terminals in the package.
Figure 44. Views of Thermally Enhanced DGN Package
Copyright © 2000 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
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THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009 ...........................................................................................................................................................
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Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November, 2006) to Revision G .......................................................................................... Page
•Corrected x-axis values in Figure 2 ....................................................................................................................................... 5
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4150CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150IDGKR ACTIVE VSSOP DGK 8 TBD Call TI Call TI
THS4150IDGKRG4 ACTIVE VSSOP DGK 8 TBD Call TI Call TI
THS4150IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4150IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4151CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4151IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4150CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4150CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4150IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4151IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4150CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4150CDR SOIC D 8 2500 367.0 367.0 35.0
THS4150IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4151IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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