FUJITSU MICROELECTRONICS DATA SHEET DS07-13714-2E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90460/465 Series MB90462/467/F462/F462A/F463A/V460 DESCRIPTION The MB90460/465 series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC* family, the instruction set for the F2MC-16LX CPU core of the MB90460/465 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90460/465 has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90460/465 series include : an 8/10-bit A/D converter, UARTs (SCI) 0 to 1, 16-bit PPG timer, a multi-functional timer (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 to 5, 16-bit PPG timer, a waveform generator) , a multi-pulse generator (16-bit PPG timer, 16-bit reload timer, waveform sequencer) , PWC 0 to 1, 16-bit reload timer and DTP/external interrupt. * : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU MICROELECTRONICS LIMITED. FEATURES * Minimum execution time : 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4 * Maximum memory space 16 Mbyte Linear/bank access * Instruction set optimized for controller applications Supported data types : bit, byte, word, and long-word types Standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division and extended RETI instructions The information for microcontroller supports is shown in the following homepage. Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. http://edevice.fujitsu.com/micom/en-support/ Copyright(c)2001-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2008.8 MB90460/465 Series (Continued) * Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed : 4 byte instruction queue * Enhanced interrupt function Up to eight programmable priority levels External interrupt inputs : 8 lines * Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs : 8 lines * Internal ROM FLASH : 64Kbyte with flash security (MB90F462/F462A), 128Kbyte with flash security (MB90F463A) MASKROM : 64 Kbyte (MB90462/467) * Internal RAM EVA : 8 Kbyte FLASH : 2 Kbyte MASKROM : 2 Kbyte * General-purpose ports Up to 51 channels (Input pull-up resistor settable for : 16 channels) * A/D Converter (RC) : 8 ch 8/10-bit resolution selectable Conversion time : 6.13 s (Min) , 16 MHz operation * UART : 2 channels * 16 bit PPG : 3 channels (MB90460 series), 2 channels (MB90465 series) Mode switching function provided (PWM mode or one-shot mode) Can be worked with a multi-functional timer, a multi-pulse generator (MB90460 series only) or individually * 16 bit reload timer : 2 channels Can be worked with multi-pulse generator (MB90460 series only) or individually * 16-bit PWC timer : 2 channels (MB90460 series), 1 channel (MB90465 series) * Multi-functional timer Input capture : 4 channels Output compare with selectable buffer : 6 channels Free-run timer with up or up/down mode selection and selectable buffer : 1 channel 16-bit PPG : 1 channel Waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time) * Multi-pulse generator 16-bit PPG : 1 channel (MB90460 series only) 16-bit reload timer : 1 channel Waveform sequencer : (16-bit timer with buffer and compare clear function) (MB90460 series only) * Time-base counter/watchdog timer : 18-bit * Low-power consumption mode : Sleep mode Stop mode CPU intermittent operation mode (Continued) 2 DS07-13714-2E MB90460/465 Series (Continued) * Package : LQFP-64 (FPT-64P-M23 : 0.65 mm pitch) QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch) * CMOS technology DS07-13714-2E 3 MB90460/465 Series PRODUCT LINEUP Part number Item Series Classification ROM size RAM size CPU function I/O port MB90V460 MB90F462 MB90F462A MB90F463A MB90460 series Development/ Mass-produced products evaluation (Flash ROM) product 64 KBytes 128 KBytes 8 KBytes 2 KBytes Number of Instruction : 351 Minimum execution time : 62.5 ns / 4 MHz (PLL x 4) Addressing mode : 23 Data bit length : 1, 8, 16 bits Maximum memory space : 16 MBytes I/O port (CMOS) : 51 Pulse width counter timer : 2 channels PWC UART 16-bit reload timer 16-bit PPG timer Multi-functional timer (for AC/DC motor control) Multi-pulse generator (for DC motor control) 8/10-bit A/D converter MB90462 MB90467 MB90465 series Mass-produced products (Mask ROM) 64 KBytes Pulse width counter timer : 1ch Timer function (select the counter timer from three internal clocks) Various Pulse width measuring function (H pulse width, L pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period) UART : 2 channels With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used Transmission can be one-to-one (bi-directional communication) or one-to-n (MasterSlave communication) Reload timer : 2 channels Reload mode, single-shot mode or event count mode selectable Can be worked with a multi-pulse generator or individually (MB90460 series only) PPG timer : PPG timer : 3 channels 2ch PWM mode or single-shot mode selectable Can be worked with multi-functional timer / multi-pulse generator (MB90460 series only) or individually 16-bit free-running timer with up or up/down mode selection and buffer : 1 channel 16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit PPG timer : 1 channel Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time) 16-bit PPG timer : 1 channel Waveform sequencer (includes 16-bit timer with buffer and compare Not present clear function) 16-bit reload timer operation (toggle output, one shot output selectable) Event counter function : 1 channel built-in 8/10-bit resolution (8 channels) Conversion time : Min. 6.13 s (16 MHz internal clock) (Continued) 4 DS07-13714-2E MB90460/465 Series (Continued) Part number Item MB90V460 MB90F462 MB90F462A MB90F463A MB90462 DTP/External interrupt 8 independent channels Selectable causes : Rising edge, falling edge, "L" level or "H" level Lower power consumption Stop mode / Sleep mode / CPU intermittent operation mode Package MB90467 LQFP-64 (FPT-64P-M23 : 0.65 mm pitch) QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch) PGA256 Power supply voltage for operation* 4.5 V to 5.5 V * Process CMOS * : Varies with conditions such as the operating frequency (See section " ELECTRICAL CHARACTERISTICS") . Assurance for the MB90V460 is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25 C, and an operating frequency of 1 MHz to 16 MHz. PACKAGE AND CORRESPONDING PRODUCTS Package MB90V460 MB90F462 x PGA256 FPT-64P-M23 x FTP-64P-M06 x DIP-64P-M01 x MB90F462A MB90F463A x x MB90462 MB90467 x x : Available, x : Not available Note : For more information about each package, see section " PACKAGE DIMENSIONS". DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V460 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V460, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are mapped to bank FF only. (This setting can be changed by configuring the development tool.) * In the MB90462/F462/F462A/F463A/467, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only. Difference between MB90460 series and MB90465 series * Waveform sequencer, 16-bit PPG timer 1, and PWC 0 are not present in MB90465 series. Difference between MB90F462, MB90F462A and MB90F463A * 64Kbytes flash ROM is avaliable in MB90F462 and MB90F462A while 128Kbytes flash ROM is avaliable in MB90F463A. DS07-13714-2E 5 MB90460/465 Series PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30*1/RTO0 (U) VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0 P07/PWO0*2 RST MD1 MD2 X0 X1 VSS P00*1/OPT0*2 P01*1/OPT1*2 P02*1/OPT2*2 P03*1/OPT3*2 P04*1/OPT4*2 P05*1/OPT5*2 P06/PWI0*2 P44/SNI1*2 P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7 MD0 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 P43/SNI0*2 P42/SCK0 P41/SOT0 P40/SIN0 P37/PPG0 P36/PPG1*2 C VCC P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X) (TOP VIEW) (FPT-64P-M06) *1 : Heavy current pins *2 : Resource function for these pins are not applicable to MB90465 series (Continued) 6 DS07-13714-2E MB90460/465 Series 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P44/SNI1*2 P43/SNI0*2 P42/SCK0 P41/SOT0 P40/SIN0 P37/PPG0 P36/PPG1*2 C VCC P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X) P30*1/RTO0 (U) VSS (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0 P63/INT7 MD0 RST MD1 MD2 X0 X1 VSS P00*1/OPT0*2 P01*1/OPT1*2 P02*1/OPT2*2 P03*1/OPT3*2 P04*1/OPT4*2 P05*1/OPT5*2 P06/PWI0 P07/PWO0 P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 (FPT-64P-M23) *1 : Heavy current pins *2 : Resource function for these pins are not applicable to MB90465 series (Continued) DS07-13714-2E 7 MB90460/465 Series (Continued) (TOP VIEW) C P36/PPG1*2 P37/PPG0 P40/SIN0 P41/SOT0 P42/SCK0 P43/SNI0*2 P44/SNI1*2 P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7 MD0 RST MD1 MD2 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X) P30*1/RTO0 (U) VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0 P07/PWO0*2 P06/PWI0*2 P05*1/OPT5*2 P04*1/OPT4*2 P03*1/OPT3*2 P02*1/OPT2*2 P01*1/OPT1*2 P00*1/OPT0*2 (DIP-64P-M01) *1 : Heavy current pins *2 : Resource function for these pins are not applicable to MB90465 series 8 DS07-13714-2E MB90460/465 Series PIN DESCRIPTION Pin No. QFP*2 LQFP*1 SDIP*3 Pin name I/O circuit 23, 24 22, 23 30, 31 X0, X1 A Oscillation input pins. 20 19 27 RST B External reset input pin. P00 to P05 26 to 31 25 to 30 33 to 38 32 31 39 33 32 40 OPT0 to OPT5*4 P06 4 PWI0* P07 PWO0*4 General-purpose I/O ports. D E E P10 34 33 41 INT0 C 42 INT1 35 43 INT2 C 36 to 37 44 to 45 P13 to P14 INT3 to INT4 C 38 46 INT5 TIN0 PWC 0 signal output pin.*4 Can be used as interrupt request input channels 0. Input is enabled when 1 is set in EN0 in standby mode. Can be used as interrupt request input channels 1. Input is enabled when 1 is set in EN1 in standby mode. Can be used as interrupt request input channels 2. Input is enabled when 1 is set in EN2 in standby mode. OPT0 to 5 pins for fixed-level input. This function is enabled when the waveform sequencer enables its input bit.*4 General-purpose I/O ports. C P15 39 General-purpose I/O ports. General-purpose I/O ports. DTTI1*4 37 to 38 PWC 0 signal input pin.*4 General-purpose I/O ports. P12 36 General-purpose I/O ports. RTO0 to 5 pins for fixed-level input. This function is enabled when the waveform generator enables its input bits. P11 34 Output terminals OPT0 to 5 of the waveform sequencer. These pins output the waveforms specified at the output data registers of the waveform sequencer circuit. Output is generated when OPE0 to 5 of OPCR is enabled.*4 General-purpose I/O ports. DTTI0 35 Function Can be used as interrupt request input channels 3 to 4. Input is enabled when 1 is set in EN3 to EN4 in standby mode. General-purpose I/O ports. C Can be used as interrupt request input channel 5. Input is enabled when 1 is set in EN5 in standby mode. External clock input pin for reload timer 0. (Continued) DS07-13714-2E 9 MB90460/465 Series Pin No. 2 QFP* LQFP* 1 SDIP* 3 Pin name I/O circuit P16 40 39 47 INT6 General-purpose I/O ports. C TO0 41 40 48 42 41 49 43 42 50 44 43 51 45 44 52 P17 FRCK P20 TIN1 P21 TO1 P22 PWI1 P23 PWO1 45 to 48 53 to 56 IN0 to IN3 C F F F F 50 to 55 58 to 63 59 58 2 60 59 3 RTO0 (U) to RTO5 (Z) F G 60 4 62 61 5 SIN0 General-purpose I/O ports. Event output pin for reload timer 1. General-purpose I/O ports. PWC 1 signal input pin. General-purpose I/O ports. PWC 1 signal output pin. Trigger input pins for input capture channels 0 to 3. When input capture channels 0 to 3 are used for input operation, these pins are enabled as required and must not be used for any other I/P. Waveform generator output pins. These pins output the waveforms specified at the waveform generator. Output is generated when waveform generator output is enabled. (U) to (Z) show the coils that control 3-phase motor. Output pins for PPG channels 1. This function is enabled when PPG channels 1 enable output.*4 Output pins for PPG channels 0. This function is enabled when PPG channels 0 enable output. General-purpose I/O ports. F P41 SOT0 External clock input pin for reload timer 1. General-purpose I/O ports. H P40 61 General-purpose I/O ports. General-purpose I/O ports. H P37 PPG0 External clock input pin for free-running timer. General-purpose I/O ports. P36 PPG1*4 General-purpose I/O ports. General-purpose I/O ports. P30 to P35 51 to 56 Can be used as interrupt request input channels 6. Input is enabled when 1 is set in EN6 in standby mode. Event output pin for reload timer 0. P24 to P27 46 to 49 Function Serial data input pin for UART channel 0. While UART channel 0 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O ports. F Serial data output pin for UART channel 0. This function is enabled when UART channel 0 enables data output. (Continued) 10 DS07-13714-2E MB90460/465 Series Pin No. QFP* 2 LQFP*1 SDIP*3 Pin name I/O circuit P42 63 62 6 SCK0 General-purpose I/O ports. F P43 64 63 7 SNI0*4 64 8 SNI1*4 F 1 9 SNI2*4 F 2 4 to 11 3 to 10 10 11 to 18 PPG2 P50 to P57 AN0 to AN7 Trigger input pins for position detection of the Multi-pulse generator. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.*4 General-purpose I/O ports. F P46 3 Trigger input pins for position detection of the waveform sequencer. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.*4 General-purpose I/O ports. P45 2 Serial clock I/O pin for UART channel 0. This function is enabled when UART channel 0 enables clock output. General-purpose I/O ports. P44 1 Function Trigger input pins for position detection of the Multi-pulse generator. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.*4 General-purpose I/O ports. F Output pins for PPG channel 2. This function is enabled when PPG channel 2 enables output. General-purpose I/O ports. I A/D converter analog input pins. This function is enabled when the analog input specification is enabled. (ADER) . 12 11 19 AVCC VCC power input pin for analog circuits. 13 12 20 AVR Reference voltage (+) input pin for the A/D converter. This voltage must not exceed VCC and AVCC. Reference voltage (-) is fixed to AVSS. 14 13 21 AVSS VSS power input pin for analog circuits. P60 15 14 22 16 15 23 SIN1 General-purpose I/O ports. F P61 SOT1 Serial data input pin for UART channel 1. While UART channel 1 is operating for input, the input of this pin is used as required and must not be used for any other in-put. General-purpose I/O ports. F Serial data output pin for UART channel 1. This function is enabled when UART channel 1 enables data output. (Continued) DS07-13714-2E 11 MB90460/465 Series (Continued) Pin No. QFP*2 LQFP*1 SDIP*3 Pin name I/O circuit P62 17 16 24 SCK1 Function General-purpose I/O port. F P63 Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1 enables clock output. General-purpose I/O port. 18 17 25 19 18 26 MD0 J Input pin for operation mode specification. Connect this pin directly to VCC or VSS. 21, 22 20, 21 28, 29 MD1, MD2 J Input pin for operation mode specification. Connect this pin directly to VCC or VSS. 25, 50 24, 49 32, 57 VSS Power (0 V) input pin. 57 56 64 VCC Power (5 V) input pin. 58 57 1 C Capacity pin for power stabilization. Please connect to an approximately 0.1 F ceramic capacitor. INT7 F Usable as interrupt request input channel 7. Input is enabled when 1 is set in EN7 in standby mode. *1 : FPT-64P-M23 *2 : FPT-64P-M06 *3 : DIP-64P-M01 *4 : Pin names not applicable to MB90465 series 12 DS07-13714-2E MB90460/465 Series I/O CIRCUIT TYPE Classification Type Remarks X1 Xout N-ch P-ch X0 P-ch A N-ch Main clock (main clock crystal oscillator) * At an oscillation feedback resistor of approximately 1 M Standby mode control B R Hysteresis input R P-ch Pull up control P-ch C N-ch Pout * Hysteresis input * Pull-up resistor approximately 50 k * CMOS output * Hysteresis input * Selectable pull-up resistor approximately 50 k * IOL = 4 mA * Standby control available Nout Hysteresis input Standby mode control R P-ch Pull up control P-ch D N-ch Pout * CMOS output * CMOS input * Selectable pull-up resistor approximately 50 k * Standby control available * IOL = 12 mA Nout CMOS input Standby mode control (Continued) DS07-13714-2E 13 MB90460/465 Series Classification Type R P-ch Pull up control P-ch E N-ch Pout Remarks * CMOS output * CMOS input * Selectable pull-up resistor approximately 50 k * Standby control available * IOL = 4 mA Nout CMOS input Standby mode control P-ch N-ch F Pout * * * * CMOS output Hysteresis input Standby control available IOL = 4 mA * * * * CMOS output CMOS input Standby control available IOL = 12 mA * * * * CMOS output CMOS input Standby control available IOL = 4 mA Nout Hysteresis input Standby mode control P-ch N-ch G Pout Nout CMOS input Standby mode control P-ch N-ch H Pout Nout CMOS input Standby mode control (Continued) 14 DS07-13714-2E MB90460/465 Series (Continued) Classification Type P-ch N-ch Pout Remarks * * * * CMOS output CMOS input Analog input IOL = 4 mA Nout I CMOS input Analog input control Analog input * Hysteresis input J DS07-13714-2E Hysteresis input 15 MB90460/465 Series HANDLING DEVICES 1. Preventing Latchup CMOS ICs may cause latchup in the following situations : * When a voltage higher than VCC or lower than VSS is applied to input or output pins. * When a voltage exceeding the rating is applied between VCC and VSS. * When AVCC power is supplied prior to the VCC voltage. If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage. 2. Handling unused input pins Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 k resistance. Unused input/output pins may be left open in the output state, but if such pins are in the input state they should be handled in the same way as input pins. 3. Use of the external clock When the device uses an external clock, drive only the X0 pin while leaving the X1 pin open (See the illustration below) . MB90460/465 series X0 Open X1 4. Power Supply Pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pins near the device. 5. Crystal Oscillator Circuit Noise around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with the ground area for stabilizing the operation. 6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVR) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage of AVR dose not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 16 DS07-13714-2E MB90460/465 Series 7. Connection of Unused Pins of A/D Converter Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVR = VSS. 8. N.C. Pin The N.C. (internally connected) pin must be opened for use. 9. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more. 10. Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. 11. Return from standby state If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state. DS07-13714-2E 17 MB90460/465 Series BLOCK DIAGRAM X0 X1 Timebase timer Reset circuit (Watch-dog timer) RST Other pins VSS x 2, VCC x 1, MD0-2, C CPU F2MC-16LX series core Clock control circuit Delayed interrupt generator Interrupt controller Multi-functional Timer P13/INT3, P14/INT4 P37/PPG0 16-bit PPG (Ch0) P11/INT1 2 8 DTP/External interrupt 16-bit input capture (Ch0/1/2/3) P40/SIN0 P41/SOT0 P42/SCK0 4 4 UART (Ch0) 16-bit free-run timer Multi-pulse Generator 16-bit PPG (Ch1) 16-bit reload timer (Ch0) 3 3 Waveform sequencer P17/FRCK P30/RTO0 (U) P31/RTO1 (X) P32/RTO2 (V) P33/RTO3 (Y) P34/RTO4 (W) P35/RTO5 (Z) 16-bit output compare (Ch0 to 5) F2MC-16LX Bus P15/INT5/TIN0 P16/INT6/TO0 Waveform generator P10/INT0/DTTI0 P20/TIN1 P21/TO1 16-bit reload timer (Ch1) P22/PWI1 P23/PWO1 PWC (Ch1) PWC (Ch0) P46/PPG2 P24/IN0 to P27/IN3 16-bit PPG (Ch2) CMOS I/O port 0, 1, 3, 4 P60/SIN1 P61/SOT1 P62/SCK1 UART (Ch1) P63/INT7 CMOS I/O port 1, 2, 3, 6 CMOS I/O port 5 RAM ROM A/D converter (8/10 bit) 8 ROM correction P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 ROM mirroring AVCC AVR AVSS Note : P00 to P07 (8 channels) : With registers that can be used as input pull-up resistors P10 to P17 (8 channels) : With registers that can be used as input pull-up resistors *1: Not present in MB90465 series *2: Resource function for these pins are not applicable to MB90465 series 18 DS07-13714-2E MB90460/465 Series MEMORY MAP FFFFFFH ROM area Address #1 FC0000H 010000H ROM area (FF bank image) Address #2 : Internal access memory : Access not allowed 004000H 003FE0H Peripheral area Address #3 RAM area Register 000100H 0000C0H 000000H Peripheral area In Single chip mode the mirror function is supported Parts No. Address#1 Address#2 Address#3 MB90462/467 FF0000H 004000H 000900H MB90F462 FF0000H 004000H 000900H MB90F462A FF0000H 004000H 000900H MB90F463A FE0000H 004000H 000900H MB90V460 (FF0000H) 004000H 002100H Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. DS07-13714-2E 19 MB90460/465 Series I/O MAP Address Abbreviation Resource name Initial value 000000H PDR0 Port 0 data register R/W R/W Port 0 XXXXXXXXB 000001H PDR1 Port 1 data register R/W R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 data register R/W R/W Port 2 XXXXXXXXB 000003H PDR3 Port 3 data register R/W R/W Port 3 XXXXXXXXB 000004H PDR4 Port 4 data register R/W R/W Port 4 -XXXXXXXB 000005H PDR5 Port 5 data register R/W R/W Port 5 XXXXXXXXB 000006H PDR6 Port 6 data register R/W R/W Port 6 ----XXXXB 000007H Prohibited area 000008H PWCSL0 000009H PWCSH0 00000AH 00000BH 00000CH Byte Word access access Register PWC0 DIV0 PWC control status register CH0 PWC data buffer register CH0 Divide ratio control register CH0 00000DH to 0FH R/W R/W R/W R/W R/W R/W R/W 00000000B 00000000B PWC timer* (CH0) XXXXXXXXB XXXXXXXXB ------00B Prohibited area 000010H DDR0 Port 0 direction register R/W R/W Port 0 00000000B 000011H DDR1 Port 1 direction register R/W R/W Port 1 00000000B 000012H DDR2 Port 2 direction register R/W R/W Port 2 00000000B 000013H DDR3 Port 3 direction register R/W R/W Port 3 00000000B 000014H DDR4 Port 4 direction register R/W R/W Port 4 -0000000B 000015H DDR5 Port 5 direction register R/W R/W Port 5 00000000B 000016H DDR6 Port 6 direction register R/W R/W Port 6 ----0000B 000017H ADER Analog input enable register R/W R/W Port 5, A/D 11111111B R/W Communication prescaler 0 0---0000B 000018H 000019H Prohibited area CDCR0 00001AH R/W Prohibited area Clock division control register 1 R/W R/W Communication prescaler 1 0---0000B RDR0 Port 0 pull-up resistor setting register R/W R/W Port 0 00000000B RDR1 Port 1 pull-up resistor setting register R/W R/W Port 1 00000000B 00001BH CDCR1 00001CH 00001DH 00001EH to 1FH Clock division control register 0 Prohibited area (Continued) 20 DS07-13714-2E MB90460/465 Series Address Abbreviation 000020H SMR0 Serial mode register 0 R/W R/W 00000000B 000021H SCR0 Serial control register 0 R/W R/W 00000100B 000022H SIDR0 / SODR0 Input data register 0 / output data register 0 R/W R/W 000023H SSR0 Serial status register 0 R/W R/W 00001000B 000024H SMR1 Serial mode register 1 R/W R/W 00000000B 000025H SCR1 Serial control register 1 R/W R/W 00000100B 000026H SIDR1 / SODR1 Input data register 1 / output data register 1 R/W R/W 000027H SSR1 Status register 1 R/W R/W 00001000B 000028H PWCSL1 R/W R/W 00000000B 000029H PWCSH1 R/W R/W 00002AH 00002BH 00002CH PWC1 DIV1 Byte Word access access Register PWC control status register CH1 PWC data buffer register CH1 Divide ratio control register CH1 00002DH to 2FH Resource name UART0 UART1 Initial value XXXXXXXXB XXXXXXXXB 00000000B PWC timer (CH1) XXXXXXXXB R/W R/W R/W ------00B 00000000B XXXXXXXXB Prohibited area 000030H ENIR Interrupt / DTP enable register R/W R/W 000031H EIRR Interrupt / DTP cause register R/W R/W XXXXXXXXB DTP/external interrupt 000032H ELVRL Request level setting register (Lower Byte) R/W R/W 000033H ELVRH Request level setting register (Higher Byte) R/W R/W 00000000B 000034H ADCS0 A/D control status register 0 R/W R/W 00000000B 000035H ADCS1 A/D control status register 1 R/W R/W 000036H ADCR0 A/D data register 0 R R 000037H ADCR1 A/D data register 1 R/W R/W PDCR0 PPG0 down counter register R PCSR0 PPG0 period setting register W PDUT0 PPG0 duty setting register W R/W R/W --000000B R/W R/W 00000000B 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH PCNTL0 00003FH PCNTH0 PPG0 control status register 8/10-bit A/D converter 00000000B 00000000B XXXXXXXXB 00000-XXB 11111111B 11111111B XXXXXXXXB 16-bit PPG timer (CH0) XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) DS07-13714-2E 21 MB90460/465 Series Address 000040H 000041H 000042H 000043H 000044H 000045H Abbreviation 00004CH 00004DH PCSR1 PPG1 period setting register W PDUT1 PPG1 duty setting register W R/W R/W --000000B R/W R/W 00000000B PPG1 control status register 11111111B XXXXXXXXB 16-bit PPG timer (CH1) * XXXXXXXXB XXXXXXXXB XXXXXXXXB 11111111B PDCR2 PPG2 down counter register R PCSR2 PPG2 period setting register W PDUT2 PPG2 duty setting register W R/W R/W --000000B R/W R/W 00000000B 00004EH PCNTL2 00004FH PCNTH2 000050H 11111111B R PCNTH1 00004BH Initial value 000047H 00004AH Resource name PPG1 down counter register PCNTL1 000049H Byte Word access access PDCR1 000046H 000048H Register PPG2 control status register 11111111B XXXXXXXXB 16-bit PPG timer (CH2) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB TMRR0 16-bit timer register 0 R/W TMRR1 16-bit timer register 1 R/W TMRR2 16-bit timer register 2 R/W 000056H DTCR0 16-bit timer control register 0 R/W R/W 000057H DTCR1 16-bit timer control register 1 R/W R/W 00000000B 000058H DTCR2 16-bit timer control register 2 R/W R/W 00000000B 000059H SIGCR Waveform control register R/W R/W 00000000B R/W 000051H 000052H 000053H 000054H 000055H 00005AH 00005BH 00005CH 00005DH CPCLRB / Compare clear buffer register / CPCLR Compare clear register (lower) TCDT Timer data register (lower) R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB Multi Function XXXXXXXXB Timer (Waveform generator) XXXXXXXXB 00000000B 11111111B 11111111B 16-bit free-running timer 00000000B 00000000B 00005EH TCCSL Timer control status register (lower) R/W R/W 00000000B 00005FH TCCSH Timer control status register (upper) R/W R/W -0000000B (Continued) 22 DS07-13714-2E MB90460/465 Series Address 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H Abbreviation Byte Word access access Register IPCP0 Input capture data register CH0 R IPCP1 Input capture data register CH1 R IPCP2 Input capture data register CH2 R IPCP3 Input capture data register CH3 R Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit input capture (CH0 to CH3) XXXXXXXXB XXXXXXXXB 000068H PICSL01 PPG output control / Input capture control status register 01 (lower) R/W R/W 00000000B 000069H PICSH01 PPG output control / Input capture control status register 01 (upper) R/W R/W 00000000B 00006AH ICSL23 Input capture control status register 23 (lower) R/W R/W 00000000B 00006BH ICSH23 Input capture control status register 23 (upper) R R ------00B 00006CH to 6EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH Prohibited area ROM mirroring function selection register W W OCCPB0/ Output compare buffer register 0/ OCCP0 output compare register 0 R/W OCCPB1/ Output compare buffer register 1/ OCCP1 output compare register 1 R/W OCCPB2/ Output compare buffer register 2/ OCCP2 output compare register 2 R/W OCCPB3/ Output compare buffer register 3/ OCCP3 output compare register 3 R/W OCCPB4/ Output compare buffer register 4/ OCCP4 output compare register 4 R/W OCCPB5/ Output compare buffer register 5/ OCCP5 output compare register 5 R/W ROMM ROM mirroring function -------1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Output compare XXXXXXXXB (CH0 to CH5) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) DS07-13714-2E 23 MB90460/465 Series Address Abbreviation Byte Word access access 00007CH OCS0 Compare control register 0 R/W R/W 00000000B 00007DH OCS1 Compare control register 1 R/W R/W -0000000B 00007EH OCS2 Compare control register 2 R/W R/W 00007FH OCS3 Compare control register 3 R/W R/W 000080H OCS4 Compare control register 4 R/W R/W 00000000B 000081H OCS5 Compare control register 5 R/W R/W -0000000B 000082H TMCSRL0 Timer control status register CH0 (lower) R/W R/W 00000000B 000083H TMCSRH0 Timer control status register CH0 (upper) R/W R/W 000084H 000085H TMR0 / TMRD0 R/W 000086H TMCSRL1 Timer control status register CH1 (lower) R/W R/W 000087H TMCSRH1 Timer control status register CH1 (upper) R/W R/W 000088H 000089H TMR1 / TMRD1 16 bit timer register CH1 / 16-bit reload register CH1 R/W 00008AH OPCLR Output control lower register R/W R/W 00000000B 00008BH OPCUR Output control upper register R/W R/W 00000000B 00008CH IPCLR Input control lower register R/W R/W 00008DH IPCUR Input control upper register R/W R/W 00008EH TCSR Timer control status register R/W R/W 00000000B 00008FH NCCR Noise cancellation control register R/W R/W 00000000B Register 16 bit timer register CH0 / 16-bit reload register CH0 000090H to 9DH Resource name Initial value 00000000B Output compare (CH0 to CH5) -0000000B 16-bit reload timer (CH0) ----0000B XXXXXXXXB XXXXXXXXB 00000000B 16-bit reload timer (CH1) ----0000B XXXXXXXXB XXXXXXXXB 00000000B Waveform* sequencer 00000000B Prohibited area Program address detect control status register R/W R/W Rom correction 00000000B Delayed interrupt cause / clear register R/W R/W Delayed interrupt -------0B LPMCR Low-power consumption mode register R/W R/W CKSCR Clock selection register R/W 00009EH PACSR 00009FH DIRR 0000A0H 0000A1H 0000A2H to A7H 00011000B R/W Low-power consumption control register 11111100B Prohibited area 0000A8H WDTC Watchdog control register R/W R/W Watchdog timer X-XXX111B 0000A9H TBTC Timebase timer control register R/W R/W Timebase timer 1--00100B (Continued) 24 DS07-13714-2E MB90460/465 Series Address Abbreviation Register 0000AAH to ADH 0000AEH Byte Word access access Resource name Initial value Flash memory interface circuit 00010000B Prohibited area FMCS Flash memory control status register 0000AFH R/W R/W Prohibited area 0000B0H ICR00 Interrupt control register 00 R/W R/W 00000111B 0000B1H ICR01 Interrupt control register 01 R/W R/W 00000111B 0000B2H ICR02 Interrupt control register 02 R/W R/W 00000111B 0000B3H ICR03 Interrupt control register 03 R/W R/W 00000111B 0000B4H ICR04 Interrupt control register 04 R/W R/W 00000111B 0000B5H ICR05 Interrupt control register 05 R/W R/W 00000111B 0000B6H ICR06 Interrupt control register 06 R/W R/W 00000111B 0000B7H ICR07 Interrupt control register 07 R/W R/W 0000B8H ICR08 Interrupt control register 08 R/W R/W 0000B9H ICR09 Interrupt control register 09 R/W R/W 00000111B 0000BAH ICR10 Interrupt control register 10 R/W R/W 00000111B 0000BBH ICR11 Interrupt control register 11 R/W R/W 00000111B 0000BCH ICR12 Interrupt control register 12 R/W R/W 00000111B 0000BDH ICR13 Interrupt control register 13 R/W R/W 00000111B 0000BEH ICR14 Interrupt control register 14 R/W R/W 00000111B 0000BFH ICR15 Interrupt control register 15 R/W R/W 00000111B 0000C0H to FFH Interrupt controller 00000111B 00000111B External area 001FF0H PADR0L Program address detection register 0 (Lower Byte) R/W R/W XXXXXXXXB 001FF1H PADR0M Program address detection register 0 (Middle Byte) R/W R/W XXXXXXXXB 001FF2H PADR0H Program address detection register 0 (Higher Byte) R/W R/W XXXXXXXXB 001FF3H PADR1L Program address detection register 1 (Lower Byte) R/W R/W XXXXXXXXB 001FF4H PADR1M Program address detection register 1 (Middle Byte) R/W R/W XXXXXXXXB 001FF5H PADR1H Program address detection register 1 (Higher Byte) R/W R/W XXXXXXXXB Rom correction (Continued) DS07-13714-2E 25 MB90460/465 Series (Continued) Address 003FE0H 003FE1H 003FE2H 003FE3H 003FE4H 003FE5H 003FE6H 003FE7H 003F78H 003FE9H 003FEAH 003FEBH 003FECH 003FEDH 003FEEH 003FEFH 003FF0H 003FF1H 003FF2H 003FF3H 003FF4H 003FF5H 003FF6H 003FF7H 003FF8H 003FF9H 003FFAH 003FFBH 003FFCH 003FFDH 003FFEH to 003FFFH 26 Abbreviation Register Byte Word access access OPDBR0 Output data buffer register 0 R/W OPDBR1 Output data buffer register 1 R/W OPDBR2 Output data buffer register 2 R/W OPDBR3 Output data buffer register 3 R/W OPDBR4 Output data buffer register 4 R/W OPDBR5 Output data buffer register 5 R/W OPEBR6 Output data buffer register 6 R/W OPEBR7 Output data buffer register 7 R/W OPEBR8 Output data buffer register 8 R/W OPEBR9 Output data buffer register 9 R/W OPEBRA Output data buffer register A R/W OPEBRB Output data buffer register B R/W OPDR Output data register R CPCR Compare clear register R/W TMBR Timer buffer register R Resource name Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B Waveform* sequencer 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B XXXXXXXXB 0000XXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B Prohibited area DS07-13714-2E MB90460/465 Series * Meaning of abbreviations used for reading and writing R/W : Read and write enabled R : Read only W : Write only * Explanation of initial values 0 : The bit is initialized to 0. 1 : The bit is initialized to 1. X : The initial value of the bit is undefined. : The bit is not used. Its initial value is undefined. The Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FE0H to 003FFFH. Note : For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However, initial value for resets that initializes the value is listed. *: These registers are not present in MB90465 series DS07-13714-2E 27 MB90460/465 Series INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER EI2OS support Interrupt cause Interrupt vector Interrupt control register *2 Number Address ICR Address Reset x #08 08H FFFFDCH INT9 instruction x #09 09H FFFFD8H Exception processing x #10 0AH FFFFD4H A/D converter conversion termination #11 0BH FFFFD0H Output compare channel 0 match #12 0CH FFFFCCH End of measurement by PWC0 timer / PWC0 timer overflow*3 #13 0DH FFFFC8H 16-bit PPG timer 0 #14 0EH FFFFC4H #15 0FH FFFFC0H 16-bit PPG timer 1*3 #16 10H FFFFBCH Output compare channel 2 match #17 11H FFFFB8H 16-bit reload timer 1 underflow #18 12H FFFFB4H Output compare channel 3 match #19 13H FFFFB0H #20 14H FFFFACH #21 15H FFFFA8H #22 16H FFFFA4H Output compare channel 5 match #23 17H FFFFA0H End of measurement by PWC1 timer / PWC1 timer overflow #24 18H FFFF9CH DTP/ext. interrupt channels 4/5 detection #25 19H FFFF98H Waveform sequencer timer compare match / write timing*3 #26 1AH FFFF94H DTP/ext. interrupt channels 6/7 detection #27 1BH FFFF90H Waveform sequencer position detect / compare interrupt*3 #28 1CH FFFF8CH #29 1DH FFFF88H #30 1EH FFFF84H #31 1FH FFFF80H 16-bit PPG timer 2 #32 20H FFFF7CH Input capture channels 0/1 #33 21H FFFF78H #34 22H FFFF74H Output compare channel 1 match 3 DTP/ext. interrupt channels 0/1 detection DTTI0 Output compare channel 4 match DTP/ext. interrupt channels 2/3 detection DTTI1*3 Waveform generator 16-bit timer 0/1/2 underflow 16-bit reload timer 0 underflow 16-bit free-running timer zero detect 16-bit free-running timer compare clear Priority High ICR00 0000B0H*1 ICR01 0000B1H*1 ICR02 0000B2H*1 ICR03 0000B3H*1 ICR04 0000B4H*1 ICR05 0000B5H*2 ICR06 0000B6H*1 ICR07 0000B7H*1 ICR08 0000B8H*1 ICR09 0000B9H*1 ICR10 0000BAH*1 ICR11 0000BBH*1 (Continued) 28 DS07-13714-2E MB90460/465 Series (Continued) Interrupt cause EI2OS support Input capture channels 2/3 Timebase timer UART1 receive UART1 send UART0 receive Interrupt vector Interrupt control register Priority *2 Number Address #35 23H FFFF70H #36 24H FFFF6CH #37 25H FFFF68H #38 26H FFFF64H #39 27H FFFF60H UART0 send #40 28H FFFF5CH Flash memory status #41 29H FFFF58H Delayed interrupt generator module #42 2AH FFFF54H ICR Address ICR12 0000BCH*1 ICR13 0000BDH*1 ICR14 0000BEH*1 ICR15 0000BFH*1 Low : Can be used and support the EI2OS stop request. : Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. x : Cannot be used. : Usable when an interrupt cause that shares the ICR is not used. *1: - For peripheral functions that share the ICR register, the interrupt level will be the same. - If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with another peripheral function, the service can be started by either of the function. And if EI2OS clear is supported, both interrupt request flags for the two interrupt causes are cleared by EI2OS interrupt clear signal. It is recommended to mask either of the interrupt request during the use of EI2OS. - EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt is masked during EI2OS operation. It is recommended to mask either of the interrupt requests during the use of EI2OS. *2: This priority is applied when interrupts of the same level occur simultaneously. *3: In MB90465 series, these resources are not present, and therefore the interrupts are not available. DS07-13714-2E 29 MB90460/465 Series PERIPHERAL RESOURCES 1. Low-Power Consumption Control Circuit The MB90460/465 series has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode : A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and peripheral functions. Main clock mode : The main clock, with a frequency one-half that of the oscillation clock (HCLK) , is used to operate the CPU and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive. * CPU intermittent operation mode CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses are supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode, intermittent clock pulses are only applied to the CPU when it is accessing a register, internal memory, a peripheral function, or an external unit. * Standby mode In standby mode, the low power consumption control circuit stops supplying the clock to the CPU (sleep mode) or the CPU and peripheral functions (timebase timer mode) , or stops the oscillation clock itself (stop mode) , reducing power consumption. * PLL sleep mode PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock mode; other components continue to operate on the PLL clock. * Main sleep mode Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock mode; other components continue to operate on the main clock. * PLL timebase timer mode PLL timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, PLL clock and timebase timer, to stop. All functions other than the timebase timer are deactivated. * Main timebase timer mode Main timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, main clock and the timebase timer, to stop. All functions other than the timebase timer are deactivated. * Stop mode Stop mode causes the source oscillation to stop. All functions are deactivated. 30 DS07-13714-2E MB90460/465 Series Block Diagram Low power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RESV RST Pin Pin high impedance control circuit Pin Hi-z control Internal reset generation circuit Internal reset CPU intermittent operation selecter Select intermittent cycles CPU clock control circuit RST Release reset 3 Standby control circuit CPU clock Stop and sleep signals Stop signal Cancel interrupt Peripheral clock control circuit Machine clock Peripheral clock Oscillation stabilization wait is passed Clock generator Clock selector 2 Oscillation stabilization wait interval selector 2 x1 x2 x3 x4 PLL multipiler circuit RESV MCM WS1 WS0 RESV MCS CS1 CS0 Clock selection register (CKSCR) X0 Pin X1 Pin DS07-13714-2E Divideby-2 Divideby-512 Divideby-2 Divideby-4 Divideby-4 Divideby-4 Main clock System clock generation circuit Timebase timer 31 MB90460/465 Series 2. I/O Ports (1) Outline of I/O ports When a data register serving for control output is read, the data output from it as a control output is read regardless of the value in the direction register. Note that, if a read-modify-write instruction (such as a bit set instruction) is used to preset output data in the data register when changing its setting from input to output, the data read is not the data register latched value but the input data from the pin. Ports 0 to 4 and 6 are input/output ports which serve as inputs when the direction register value is "0" or as outputs when the value is "1". Port 5 are input/output ports as other port when ADER is 00H. Block Diagram * Block diagram of Port 0 pins RDR Port data register (PDR) Resource output Direct resource input Resource output enable Pull-up resistor About 50 K Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read (Continued) 32 DS07-13714-2E MB90460/465 Series * Block diagram of Port 1 pins RDR Port data register (PDR) Resource output Resource input Resource output enable Pull-up resistor About 50 K Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read * Block diagram of Port 2 pins Port data register (PDR) Resource output Resource input Resource output enable Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) (Continued) DS07-13714-2E 33 MB90460/465 Series * Block diagram of Port 3 pins Port data register (PDR) Resource output Resource output enable Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) * Block diagram of Port 4 pins Port data register (PDR) Resource output Resource input Resource output enable Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) (Continued) 34 DS07-13714-2E MB90460/465 Series (Continued) * Block diagram of Port 5 pins ADER Port data register (PDR) Analog input Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read * Block diagram of Port 6 pins Port data register (PDR) Resource output Resource input Resource output enable Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) External interrupt enable DS07-13714-2E 35 MB90460/465 Series 3. Timebase Timer The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization to the internal count clock (main oscillator clock divided by 2) . Features of timebase timer : * Interrupt generated when counter overflow * EI2OS supported * Interval timer function : An interrupt generated at four different time intervals * Clock supply function : Four different clocks can be selected as a watchdog timer's count clock Supply clock for oscillation stabilization Block Diagram To watchdog timer Timebase timer counter Divide-by -two HCLK x 21 x 22 x 23 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF Counter clear OF OF To the oscillation setting time selector in the clock control section Power-on reset Counter clear circuit Stop mode start CKSCR : MCS = 1 to 0 *1 Interval timer selector TBOF clear TBOF set Timebase timer interrupt signal #36 (24H)*2 Timebase timer interrpt register (TBTC) TBIE TBOF TBR TBC1 TBC0 OF : Overflow HCLK : Oscillation clock *1 : Switching of the machine clock from the oscillation clock to the PLL clock *2 : Interrupt number 36 DS07-13714-2E MB90460/465 Series 4. Watchdog Timer The watchdog timer is a 2-bit counter that uses the timebase timer's supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given period, the CPU will be reset. * Features of Watchdog Timer : Reset CPU at four different time intervals Status bits to indicate the reset causes Block Diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE Watchdog timer WT1 WT0 2 Activation with CLR Start of sleep mode Start of hold status mode Start of stop mode Counter clear control circuit Count clock selector 2-bit counter CLR Overflow Watchdog reset generator To the internal reset generator CLR Clear 4 (Timebase timer counter) One-half of HCLK x 21 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK : Oscillation clock DS07-13714-2E 37 MB90460/465 Series 5. 16-bit reload timer ( x 2) The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot mode) . Output pins TO1 - TO0 are able to output different waveform accroding to the counter operating mode. TO1 TO0 toggles when counter underflow if counter is operated as reload mode. TO1 - TO0 output specified level (H or L) when counter is counting if the counter is in one-shot mode. Features of the 16 bit reload timer : * Interrupt generated when timer underflow * EI2OS supported * Internal clock operating mode : Three internal count clocks can be selected Counter can be activated by software or exteranl trigger (singal at TIN1 - TIN0 pin) Counter can be reloaded or stopped when underflow after activated * Event count operating mode : Counter counts down by one when specified edge at TIN1 - TIN0 pin Counter can be reloaded or stopped when underflow 38 DS07-13714-2E MB90460/465 Series Block Diagram F2MC-16LX Bus TMRD0*1 <TMRD1> 16-bit reload register Reload signal TMR0*1 <TMR1> Reload control circuit 16-bit timer register Count clock generation circuit Machine clock CLK 3 Prescaler Gate input Valid clock judgment circuit Clear Input control circuit P15/TIN0*1 <P20/TIN1> Output control circuit Clock selector Output signal generation circuit Invert External clock 2 Select signal Function selection Pin EN 3 To UART0 and UART1 *1 <To the A/D converter> CLK Internal clock Pin Wait signal CSL1 CSL0 MOD2 MOD1MOD0OUTE OUTL RELD INTE Timer control status register (TMCSR0)*1 <TMCSR1> P16/TO0*1 <P21/TO1> Operation control circuit UF CNTE TRG Interrupt request signal #30 (1EH)*2 <#32 (20H)> *1 : This register includes channel 0 and channel 1. The register enclosed in < and > indicates the channel 1 register. *2 : Interrupt number DS07-13714-2E 39 MB90460/465 Series 6. 16-bit PPG Timer ( x 3, PPG1 is not present in MB90465 series) The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting buffer register, 16-bit duty setting buffer register, 16-bit control register and a PPG output pin. This module can be used to output pulses synchronized by software trigger or GATE signal from Multi-functional timer, refer to "Multi-functional Timer" Features of 16-bit PPG Timer : * Two operating mode : PWM and One-shot * 8 types of counter operation clock (, /2, /4, /8, /16, /32, /64, /128) can be selected * Interrupt generated when trigger signal arrived, or counter borrow, or change of PPG output * EI2OS supported Block Diagram Period Setting Buffer Register 0/1/2 Duty Setting Buffer Register 0/1/2 Prescaler Duty Setting Register 0/1/2 CLK LOAD 16-bit down counter STOP START BORROW MDSE PGMS OSEL POEN Machine clock P37/PPG0 or P36/PPG1 or P46/PPG2 Pin S Down Counter Register 0/1/2 F2MC-16LX Bus 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 Period Setting Register 0/1/2 Comparator CKS2 CKS1 CKS0 Q PPG0 (multi-functional timer) or PPG1 (multi-pulse generator) or PPG2 R Interrupt selection GATE-from multi-functional timer (for PPG ch. 0 only) Edge detection Interrupt #14/#16/#32 IRS1 IRS0 IRQF IREN (for PPG ch. 1 & 2) STGR CNTE RTRG 40 DS07-13714-2E MB90460/465 Series 7. Multi-functional Timer The 16-bit multi-functional timer module consists of one 16-bit free-running timer, four input capture circuits, six output comparators and one channel of 16-bit PPG timer. This module allows six independent waveforms generated by PPG timer or waveform generator to be outputted. With the 16-bit free-run timer and the input capture circuit, a input pulse width measurement and external clock cycle measurement can be done. (1) 16-bit free-running timer (1 channel) * The 16-bit free-running timer consists of a 16-bit up/up-down counter, control register, 16-bit compare clear register (with buffer register) and a prescaler. * 8 types of counter operation clock (, /2, /4, /8, /16, /32, /64, /128) can be selected. ( is the machine clock) * Two types of interrupt causes : - Compare clear interrupt is generated when there is a comparing match with compare clear register and 16bit free-run timer. - Zero detection interrupt is generated while 16-bit free-running timer is detected as zero in count value. * EI2OS supported * The compare clear register has a selectable buffer register, into which data is written for transfer to the compare clear register. When the timer is stopped, transfer occurs immediately when the data is written to the buffer. When the timer is operation, data transfer from the buffer occurs when the timer value is detected to be zero. * Reset, software clear, compare match with compare clear register in up-count mode will reset the counter value to "0000H". * Supply clock to output compare module : The prescaler ouptut is acted as the count clock of the output compare. (2) Output compare module (6 channels) * The output compare module consists of six 16-bit compare registers (with selectable buffer register) , compare output latch and compare control registers. An interrupt is generated and output level is inverted when the value of 16-bit free-running timer and compare register are matched. * 6 compare registers can be operated independently. * Output pins and interrupt flag are corresponding to each compare register. * Inverts output pins by using 2 compare registers together. 2 compare registers can be paired to control the output pins. * Setting the initial value for each output pin is possible. * Interrupt generated when there is a comparing match with output compare register and 16 bit free-run timer * EI2OS supported (3) Input capture module (4 channels) Input capture consists of 4 independent external input pins, the corresponding capture register and capture control register. By detecting any edge of the input signal from the external pin, the value of the 16-bit freerunning timer can be stored in the capture register and an interrupt is generated simultaneously. * Operation synchronized with the 16-bit free-run timer's count clock. * 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected and there is indication bit to show the trigger edge is rising or falling. * 4 input captures can be operated independently. * Two independent interrupts are generated when detecting a valid edge from external input. * EI2OS supported (4) 16-bit PPG timer ( x 1) The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator. DS07-13714-2E 41 MB90460/465 Series (5) Waveform Generator module The waveform generator consists of three 16-bit timer registers, three timer control registers and 16-bit waveform control register. With waveform generator, it is possible to generate real time output, 16-bit PPG waveform output, non-overlap 3-phase waveform output for inverter control and DC chopper waveform output. * It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (Dead-time timer function) * It is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode. (Dead-time timer function) * By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated to start or stop PPG timer operation. (GATE function) * When a match is detected by realtime output compare, the 16-bit timer is activated. The PPG timer can be started or stopped easily by generating a GATE signal for PPG operation until the 16-bit timer stops. (GATE function) * Forced to stop output waveform using DTTI0 pin input * Interrupt generated when DTTI0 active or 16-bit tmer underflow * EI2OS supported * MCU to 3-phase Motor Interface Circuit VCC RTO0(U) RTO2(V) RTO4(W) (V) (U) RTO1(X) RTO3(Y) (W) RTO5(Z) RTO0 (U) , RTO2 (V) , RTO4 (W) are called "UPPER ARM". RTO1 (X) , RTO3 (Y) , RTO5 (Z) are called "LOWER ARM". RTO0 (U) and RTO1 (X) are called "non-overlapping output pair". RTO2 (V) and RTO3 (Y) are called "non-overlapping output pair". RTO4 (W) and RTO5 (Z) are called "non-overlapping output pair". (U) , (V) , (W) are the 3-phase coil connection. 42 DS07-13714-2E MB90460/465 Series * 3-phase Motor Coil Connection Circuit (U) Star Connection Circuit (V) (W) (U) Delta Connection Circuit (W) DS07-13714-2E (V) 43 MB90460/465 Series Block Diagram * Block Diagram of Multi-functional Timer Real time I/O Interrupt#12 Interrupt#15 Interrupt#17 Interrupt#19 Interrupt#21 Interrupt#23 16-bit Output Compare RT0 to 5 output compare 0 output compare 1 output compare 2 output compare 3 output compare 4 output compare 5 Pin P30/RTO0 (U) RTO1 Pin P31/RTO1 (X) RTO2 Pin P32/RTO2 (V) RTO3 Pin P33/RTO3 (Y) RTO4 Pin P34/RTO4 (W) RTO5 Pin P35/RTO5 (Z) RT0 to 5 Waveform generator buffer transfer RTO0 counter value DTTI F2MC-16LX Bus Interrupt#31 Interrupt#34 16-bit free- A/D trigger running timer Zero detect Compare clear A/D trigger EXCK counter Interrupt #33 value Interrupt #35 16-bit Input Capture Pin P10/INT0/DTTI0 Interrupt#29 16-bit timer 0/1/2 underflow Interrupt#20 DTTI0 falling edge detect PPG0 PPG0 GATE GATE Pin P17/FRCK Input capture 0/1 Input capture 2/3 IN0 Pin P24/IN0 IN1 Pin P25/IN1 IN2 Pin P26/IN2 IN3 Pin P27/IN3 (Continued) 44 DS07-13714-2E MB90460/465 Series * Block diagram of 16-bit free-running timer STOP MODE SCLR CLK2 CLK1 CLK0 STOP UP/ CLR UP-DOWN Prescaler Zero detect circuit 16-bit free-running timer CK Zero detect (to output compare) F2MC-16LX BUS To Input Capture & Output Compare transfer 16-bit compare clear register Compare circuit Compare clear match (to output compare) 16-bit compare clear buffer register Selector I1 O I0 Mask Circuit I0 O I1 Selector Interrupt #31 (1FH) I0 O I1 Selector Interrupt #34 (22H) A/D trigger MSI2 MSI1 MSI0 ICLR ICRE IRQZF IRQZE I0 O I1 Selector (Continued) DS07-13714-2E 45 MB90460/465 Series * Block diagram of 16-bit output compare Count value from Free-running timer BUF0 Compare buffer register 0/2/4 Zero detect from free-running timer Compare clear match from free-running timer I0 O I1 Selector transfer Compare register 0/2/4 F2MC-16LX BUS BTS0 BUF1 BTS1 Compare circuit I0 O I1 Selector Compare buffer register 1/3/5 transfer Compare register 1/3/5 CMOD Compare circuit IOP1 IOP0 IOE1 T Q RT0/2/4 (Waveform generator) T Q RT1/3/5 (Waveform generator) IOE0 Interrupt #12, #17, #21 #15, #19, #23 * Block diagram of 16-bit input capture Count value from Free-running timer Edge detect F2MC-16LX BUS Capture register 0/2 EG11 EG10 EG01 EG00 Edge detect Capture register 1/3 ICP0 ICP1 ICE0 IN0/2 IEI1 IEI0 IN1/3 ICE1 Interrupt #33, #35 #33, #35 (Continued) 46 DS07-13714-2E MB90460/465 Series (Continued) * Block diagram of waveform generator DCK2 DCK1 DCK0 NRSL DTIF DTIE DTTI0 control circuit Divider NWS1 NWS0 SIGCR Noise Cancellation DTTI0 PICSH01 PGEN1 PGEN0 GATE 0/1 DTCR0 TMD2 TMD1 TMD0 GTEN1 GTEN0 GATE (to PPG0) TO0 Compare circuit Selector Output Control Selector 16-bit timer 0 RTO0 (U) Output Control TO1 RT1 RTO2 (V) Output Control Waveform control RT0 RTO4 (W) U 16-bit timer register 0 RTO1 (X) Dead time generator X GATE 2/3 F2MC-16LX BUS DTCR1 TMD2 TMD1 TMD0 GTEN1 GTEN0 PICSH01 PGEN3 PGEN2 TO2 Waveform control RT2 TO3 RT3 Selector 16-bit timer 1 Compare circuit Selector V 16-bit timer register 1 RTO3 (Y) Dead time generator Y GATE 4/5 DTCR2 TMD2 TMD1 TMD0 GTEN1 GTEN0 PICSH01 PGEN5 PGEN4 TO4 Waveform control RT4 TO5 RT5 Selector 16-bit timer 2 Compare circuit Selector W Z PPG0 16-bit timer register 2 RTO5 (Z) Dead time generator DS07-13714-2E 47 MB90460/465 Series 8. Multi-Pulse Generator (Not present in MB90465 series, but the 16-bit reload timer 0 can be used individually) The Multi-pulse Generator consists of a 16-bit PPG timer, a 16-bit reload timer and a waveform sequencer. By using the waveform sequencer, 16-bit PPG timer output signal can be directed to Multi-pulse Generator output (OPT5 to 0) according to the input signal of Multi-pulse Generator (SNI2 to 0) . Meanwhile, the OPT5 to 0 output signal can be hardware terminated by DTTI input (DTTI1) in case of emergency. The OPT5 to 0 output signals are synchronized with the PPG signal in order to eliminate the unwanted glitch. The Multi-pulse generator has the following features : * Output Signal Control - 12 output data buffer registers are provided - Output data register can be updated by any one of output data buffer registers when : 1. an effective edge detected at SNI2 - SNI0 pin 2. 16-bit reload timer underflow 3. output data buffer register OPDBR0 is written * Output data register (OPDR) determines which OPT terminals (OPT5 - 0) output the 16-bit PPG waveform - Waveform sequencer is provided with a 16-bit timer to measure the speed of motor - The 16-bit timer can be used to disable the OPT output when the position detection is missing * Input Position Detect Control - SNI2 - SNI0 input can be used to detect the rotor position - A controllable noise filter is provided to the SNI2 - SNI0 input * PPG Synchronization for Output signal - OPT output is able to synchronize the edge of PPG waveform to avoid a short pulse (or glitch) appearance * Vaious interrupt generation causes * EI2OS supported (1) 16-bit PPG timer (x 1, not present in MB90465 series) The 16-bit PPG timer 1 is used to provide a PPG signal for waveform sequencer. (2) 16-bit reload timer (x 1) The 16-bit reload timer 0 is used to provide signal to waveform sequencer. (3) Waveform sequencer (not present in MB90465 series) By using the waveform sequencer, 16-bit PPG timer output signal can be directed to Multi-pulse generator output (OPT5 ~ OPT0) according to the input signal of Multi-pulse generator (SNI2 ~ SNI0). Meanwhile, the OPT5 ~ OPT0 outputsignal can be hardware terminated by DTTI input (DTTI1) in case of emergency. The OPT5 ~ OPT0 output signalsare synchronized with the PPG signal in order to eliminate the unwanted glitch. 48 DS07-13714-2E MB90460/465 Series F2MC-16LX Bus Block Diagram * Block diagram of Multi-pulse generator P12/INT2/DTTI1 Pin DTTI OPT5 Pin P05/OPT5 P45/SNI2 Pin SNI2 OPT4 Pin P04/OPT4 P44/SNI1 Pin SNI1 OPT3 Pin P03/OPT3 P43/SNI0 Pin SNI0 OPT2 Pin P02/OPT2 P15/INT5/TIN0 Pin TIN0 OPT1 Pin P01/OPT1 OPT0 Pin P00/OPT0 WAVEFORM SEQUENCER 16-BIT PPG TIMER 1 16-BIT RELOAD TIMER 0 PPG1 PPG1 TOUT TIN * : The dash line is the TIN0 path for MB90465 series. The 16-bit reload timer 0 can be used individually in MB90465 series. Interrupt #22 INTERRUPT #22 Interrupt #26 INTERRUPT #26 Interrupt #28 INTERRUPT #28 WIN0 TIN0O Pin P15/INT5/TIN0 Pin P16/INT6/TO0 * (Continued) DS07-13714-2E 49 MB90460/465 Series (Continued) * Block diagram of waveform sequencer Interrupt #26 WRITE TIMING INTERRUPT Interrupt #22 POSITION DETECTION INTERRUPT OPCR Register PDIRT DTIE DTIF NRSL OPS2 OPS1 OPS0 WTIF WTIE PDIF PDIE OPE5 OPE4 OPE3 OPE2 OPE1 OPE0 From PPG1 WTS1 WTS0 OP x 1/OP x 0 OPDR Register DTTI1 Control Circuit Noise Filter RDA2 to 0 3 P00/OPT0 Pin P01/OPT1 Pin P02/OPT2 Pin P03/OPT3 Pin P04/OPT4 Pin P05/OPT5 P12/INT2/DTTI1 Pin 3 COMPARE CLEAR INTERRUPT BNKF 16-BIT TIMER Pin WTO CCIRT WTIN1 P15/INT5/TIN0 P43/SNI0 Pin POSITION DETECT CIRCUIT WTO DATA WRITE CONTROL UNIT OPS2 OPS1 OPS0 OUTPUT CONTROL CIRCUIT Pin D1 D0 DECODER F2MC-16LX Bus OUTPUT DATA BUFFER REGISTER x 12 OPDBRB to 0 Registers SYN Circuit P44/SNI1 Pin 3 SELECTOR TIN0O WTIN0 TIN0O WTIN0 P45/SNI2 Pin WTIN1 WTIN1 COMPARISON CIRCUIT WTS1 WTS0 CPIF CPIE CPD2 CPD1 CPD0 CMPE CPE1 CPE0 SNC2 SNC1 SNC0 SEE2 SEE1 SEE0 COMPARE MATCH INTERRUPT IPCR Register S21 S20 S11 NCCR Register 50 S10 S01 S00 D1 D0 PDIRT Interrupt #28 DS07-13714-2E MB90460/465 Series 9. PWC Timer (x 2, PWC0 is not present in MB90465 series) The PWC (pulse width count) timer is a 16-bit multi-function up-counter with reload timer functions and inputsignal pulse-width count functions as well. The PWC timer consists of a 16-bit counter, on input pulse divider, a divide ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. The PWC timer has the following features : * Interrupt generated when timer overflow or end of PWC measurement. * EI2OS supported * Timer functions : - Generates an interrupt request at set time intervals. - Outputs pulse signals synchronized with the timer cycle. - Selects the counter clock from among three internal clocks. * Pulse-width count functions - Counts the time between external pulse input events. - Selects the counter clock from among three internal clocks. - Count mode * H pulse width (rising edge to falling edge) /L pulse width (falling edge to rising edge) * Rising-edge cycle (rising edge to falling edge) /Falling-edge cycle (falling edge to rising edge) * Count between edges (rising or falling edge to falling or rising edge) Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider. Generates an interrupt request upon the completion of count operation. Selects single or consecutive count operation. DS07-13714-2E 51 MB90460/465 Series Block Diagram PWC read Error detection ERR 16 PWC 16 16 Overflow Write enabled Reload Data transfer 16 Clock Overflow 23 Count enabled Count bit output Control circuit Flag setting 22 16-bit up count timer Timer clear F2MC-16LX bus P07/PWO0 P23/PWO1 F.F. Start edge selection Count end edge End edge selection Clock divider CKS1, CKS0, Divider clear Internal clock (machine clock / 4) Divider ON/OFF P06/PWI0 P22/PWI1 Edge detection Count start edge 8-bit divider Count end interrupt request Overflow interrupt request CKS0 ERR CKS1 Division rate selection 15 PWCS 2 52 DIVR DS07-13714-2E MB90460/465 Series 10. UART (x 2) The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features : * Full-duplex double buffering * Capable of asynchronous (start-stop bit) and CLK-synchronous communications * Support for the multiprocessor mode * Various method of baud rate generation : - External clock input possible - Internal clock (a clock supplied from 16-bit reload timer can be used.) - Embedded dedicated baud rate generator Operation Baud rate Asynchronous 31250/9615/4808/2404/1202 bps CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5 Kbps * : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz * Error detection functions (parity, framing, overrun) * NRZ (Non Return to Zero) Signal format * Interrupt request : - Receive interrupt (receive complete, receive error detection) - Transmit interrupt (transmission complete) - Transmit / receive conforms to extended intelligent I/O service (EI2OS) * Flexible data length : - 7 bit to 9 bit selective (without a parity bit) - 6 bit to 8 bit selective (with a parity bit) DS07-13714-2E 53 MB90460/465 Series Block Diagram Control bus Reception interrupt request output Dedicated baud rate generator 16-bit reload timer Send interrupt request output Clock selector Send clock Reception clock Pin send control circuit Reception control circuit SCK0, 1 Start bit detection circuit Send start circuit Reception bit counter Send bit counter Reception parity counter Send parity counter Pin Reception shift register Pin SIN0, 1 Serial input data register (0, 1) Reception status determination circuit Send shift register Serial output data register (0, 1) Start of transmission End of reception SOT0, 1 EI2OS receive error generation signal (to CPU) Internal data bus Communication prescaler control register MD DIV2 DIV1 DIV0 54 Serial mode register 0, 1 MD1 MD0 CS2 CS1 CS0 RST SCKE SOE Serial control register 0, 1 PEN P SBL CL A/D REC RXE TXE Serial status register 0, 1 PE ORE FRE RDRF TDRE BDS RIE TIE DS07-13714-2E MB90460/465 Series 11. DTP/External Interrupts The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent I/O service (EI2OS) . Features of DTP/External Interrupt : * Total 8 external interrupt channels * Two request levels ("H" and "L") are provided for the intelligent I/O service. * Four request levels (rising edge, falling edge, "H" level and "L" level) are provided for external interrupt requests. Block Diagram Request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 2 Pin 2 2 2 2 2 2 2 Selector Selector P63/INT7 Pin P10/INT0/DTTI0 Selector Pin Selector P16/INT6/TO0 Pin P11/INT1 Selector Pin Selector Internal data bus P15/INT5/TIN0 Pin P12/INT2/DTTI1 Selector Selector Pin Pin P14/INT4 P13/INT3 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request number #20(14H) #22(16H) #25(19H) #27(1BH) EN7 DS07-13714-2E EN6 EN5 EN4 EN3 EN2 EN1 EN0 55 MB90460/465 Series 12. Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. F2MC- 16LX bus Block Diagram 56 Delayed interrupt cause issuance/cancellation decoder Interrupt cause latch DS07-13714-2E MB90460/465 Series 13. A/D Converter The converter converts the analog voltage input to an analog input pin (input voltage) to a digital value. The converter has the following features : * The minimum conversion time is 6.13 s (for a machine clock of 16 MHz; includes the sampling time) . * The minimum sampling time is 2.0 s (for a machine clock of 16 MHz) . * The converter uses the RC-type successive approximation conversion method with a sample hold circuit. * A resolution of 10 bits or 8 bits can be selected. * Up to eight channels for analog input pins can be selected by a program. * Various conversion mode : - Single conversion mode : Selectively convert one channel. - Scan conversion mode : Continuously convert multiple channels. Maximum of 8 program selectable channels. - Continuous conversion mode : Repeatedly convert specified channels. - Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) * At the end of A/D conversion, an interrupt request can be generated and EI2OS can be activated. * In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. * The conversion can be activated by software, 16-bit reload timer 1 (rising edge) and 16-bit free-running timer zero detection edge. DS07-13714-2E 57 MB90460/465 Series Block Diagram AVCC AVR AVSS MPX F2MC-16LX bus Input circuit D/A converter AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Sequential compare register Comparator Sample and hold circuit Decoder Data register ADCR0/1 A/D control register 0 A/D control register 1 ADCS0/1 16-bit reload timer 1 16-bit free-running timer zero detection Operation clock Prescaler : Machine clock 58 DS07-13714-2E MB90460/465 Series 14. ROM Correction Function In the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register, the program forces the next instruction to be processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be conducted using INT9 interrupts, programs can be repaired using batch processing. *Overview of the Rom correction Function * The address of the instruction after the one that a program is currently processing is always stored in an address latch via the internal data bus. Address match detection constantly compares the address stored in the address latch with the one configured in the detection address configuration register. If the two compared addresses match, the CPU forcibly changes this instruction into an INT9 instruction, and executes an interrupt processing program. * There are two detection address configuration registers : PADR0 and PADR1. Each register provides an interrupt enable bit. This allows you to individually configure each register to enable/prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register. Block Diagram PADR0 (24 bit) Detection address configuration register 0 PADR1 (24 bit) INT9 instruction (INT9 interrupt generation) Comparator Internal data bus Address latch Detection address configuration register 1 PACSR ReReReReserved served served served AD1E Reserved AD0E Reserved Address detection control register (PACSR) Reserved : Make sure this is always set to "01" * Address latch Stores value of address output to internal data bus. * Address detection control register (PACSR) Set this register to enable/prohibit interrupt output when an address match is detected. * Detection address configuration register (PADR0, PADR1) Configure an address with which to compare the address latch value. DS07-13714-2E 59 MB90460/465 Series 15. ROM Mirroring Function Selection Module The ROM mirroring function selection module can select what the FF bank allocated the ROM and see through the 00 bank according to register settings. Block Diagram F2MC-16LX bus ROM mirroring register Address area FF bank 00 bank ROM 60 DS07-13714-2E MB90460/465 Series 16. 512/1024 Kbit Flash Memory The 512 Kbit (MB90F462 and MB90F462A) or 1024 Kbit (MB90F463A) flash memory is allocated in the FEH toFFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and programaccessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as "enable sector protect" cannot be used. Features of 512/1024 Kbit flash memory * 64K words x 8 bits/32K words x 16 bits (16K+8K+8K+32K) sector configuration for MB90F462/F462A * 128K words x 8 bits/64K words x 16 bits (64K+16K+8K+8K+32K) sector configuration for MB90F463A * 64 kwords x 8 bits/32 kwords x 16 bits (16 k + 8 k + 8 k + 32 k) sector configuration * Automatic program algorithm (same as the Embedded Algorithm : MBM29F400TA) * Installation of the deletion temporary stop/delete restart function * Write/delete completion detected by the data polling or toggle bit * Write/delete completion detected by the CPU interrupt * Compatibility with the JEDEC standard-type command * Each sector deletion can be executed (Sectors can be freely combined) . * Flash security feature * Number of write/delete operations 10,000 times guaranteed. * Flash reading cycle time (Min) 2 machine cycles DS07-13714-2E 61 MB90460/465 Series (1) Sector configuration of 512Kbit flash memory The flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When 512 Kbit flash memory is accessed from the CPU, SA0 to SA3 are allocated in the FF bank registers, respectively. Flash memory CPU address *Writer address FFFFFFH 7FFFFH FFC000H 7C000H FFBFFFH 7BFFFH FFA000H 7A000H FF9FFFH 79FFFH FF8000H 78000H FF7FFFH 77FFFH FF0000H 70000H SA3 (16 Kbytes) SA2 (8 Kbytes) SA1 (8 Kbytes) SA0 (32 Kbytes) When 1024 Kbit flash memory is accessed from the CPU, SA0 and SA1 to SA4 are allocated in the FE and FFbank registers, respectively. Flash memory CPU address *Writer address FFFFFFH 7FFFFH FFC000H 7C000H FFBFFFH 7BFFFH FFA000H 7A000H FF9FFFH 79FFFH FF8000H 78000H FF7FFFH 77FFFH FF0000H 70000H FEFFFFH 6FFFFH FE0000H 60000H SA4 (16 Kbytes) SA3 (8 Kbytes) SA2 (8 Kbytes) SA1 (32 Kbytes) SA0 (64 Kbytes) 62 DS07-13714-2E MB90460/465 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Symbol VCC Power supply voltage AVCC AVR Input voltage VI Output voltage VO Maximum clamp current ICLAMP Total maximum clamp current | ICLAMP | "L" level maximum output IOL current Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 Unit V V V V V mA mA VCC AVCC* 1 AVCC AVR, AVR AVSS *2 *2 *4 *4 mA *3 All pins except P00 ~ P05, P30 ~ P35 Average output current = operating current x operating efficiency P00 ~ P05, P30 ~ P35 onlyAverage output current = operating current x operating efficiency IOLAV1 4 mA IOLAV2 12 mA IOL 100 mA IOLAV 50 mA Average output current = operating current x operating efficiency IOH - 15 mA *3 IOHAV -4 mA Average output current = operating current x operating efficiency IOH - 100 mA IOHAV - 50 mA PD TA Tstg -40 -55 300 +85 +150 mW C C "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature Remarks Average output current = operating current x operating efficiency *1 : AVCC shall never exceed VCC when power on. *2 : VI and VO shall never exceed VCC + 0.3 V. *3 : The maximum output current is a peak value for a corresponding pin. *4 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P46, P60 to P63 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. (Continued) DS07-13714-2E 63 MB90460/465 Series (Continued) * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits: * Input/Output Equivalent circuits Protective diode VCC +B input (0 V to 16 V) P-ch Limiting resistance N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 64 DS07-13714-2E MB90460/465 Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage Symbol VCC VCC Value Unit Remarks 5.5 V Normal operation (MB90462, MB90467, MB90V460) 4.5 5.5 V Normal operation (MB90F462, MB90F462A, MB90F463A) 3.0 5.5 V Retains status at the time of operation stop Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. Min Max 3.0 Smoothing capacitor CS 0.1 1.0 F Operating temperature TA -40 +85 C * C pin connection circuit C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-13714-2E 65 MB90460/465 Series 3. DC Characteristics (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name "H" level output voltage VOH All output pins VOL All pins except VCC = 4.5 V, P00 to P05 and IOL = 4.0 mA P30 to P35 "L" level output voltage "H" level input voltage "L" level input voltage Input leakage current P00 to P05, P30 to P35 VIH P00 to P07 P30 to P37 P50 to P57 VIHS P10 to P17 P20 to P27 P40 to P46 P60 to P63, RST VIHM MD0 to MD2 VIL P00 to P07 P30 to P37 P50 to P57 VILS P10 to P17 P20 to P27 P40 to P46 P60 to P63, RST VILM MD0 to MD2 IIL All input pins Condition VCC = 4.5 V, IOH = - 4.0 mA VCC = 4.5 V, IOL = 12.0 mA VCC = 3.0 V to 5.5 V (MB90462, MB90467) VCC = 4.5 V to 5.5 V (MB90F463, MB90F462A, MB90F463A) VCC = 5.5 V, VSS < VI < VCC Value Unit Remarks Min Typ Max VCC - 0.5 V 0.4 V 0.4 V 0.7 VCC VCC + 0.3 V CMOS input pin 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin VCC - 0.3 VCC + 0.3 V MD pin input VSS - 0.3 0.3 VCC V CMOS input pin VSS - 0.3 0.2 VCC V CMOS hysteresis input pin VSS - 0.3 VSS + 0.3 V MD pin input -5 5 A (Continued) 66 DS07-13714-2E MB90460/465 Series (Continued) Parameter (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Condition VCC = 5.0 V, Internal operation at 16 MHz, Normal operation VCC = 5.0 V, Internal operation at 16 MHz, When data written in flash mode programming of erasing ICC Power supply current* ICCS VCC = 5.0 V, Internal operation at 16 MHz, In sleep mode ICTS VCC = 5.0 V, Internal operation at 16 MHz, In Timer mode, TA = 25 C VCC In stop mode, TA = 25 C ICCH Value Unit Typ Max 40 50 mA 30 50 MB90F462, mA MB90F462A, MB90F463A 45 60 MB90F462, mA MB90F462A, MB90F463A 20 MB90462, MB90467, mA MB90F462, MB90F462A, MB90F463A 5.0 MB90462, MB90467, mA MB90F462, MB90F462A, MB90F463A MB90462, MB90467, MB90F462, MB90F462A, MB90F463A 15 2.5 5 20 A Input capacitance CIN Except AVCC, AVSS, C, VCC and VSS 10 80 pF Pull-up resistance RUP P00 to P07 P10 to P17 RST 25 50 100 k 25 50 100 k Pull-down resistance RDOWN MD2 Remarks Min MB90462, MB90467 * : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock. DS07-13714-2E 67 MB90460/465 Series 4. AC Characteristics (1) Clock Timings (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Clock frequency fC X0, X1 Clock cycle time tHCYL X0, X1 Frequency fluctuation rate locked*1 f Input clock pulse width Parameter Value Unit Remarks Min Typ Max 3 16 3 32 62.5 333 ns Crystal oscillator 31.25 333 ns External clock 5 % PWH PWL X0 10 ns Recommened duty ratio of 30% to 70% Input clock rise/fall time tCR tCF X0 5 ns External clock operation Internal operating clock fCP 1.5 16 Internal operating clock cycle time tCP 62.5 666 MHz Crystal oscillator External clock *2 MHz Main clock operation ns Main clock operation *1 : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. *2 : Internal operating clock frequency must not be over 16 MHz. f = fo Center frequency x 100 (%) + fo - tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF 68 tCR DS07-13714-2E MB90460/465 Series Relationship between internal operating clock frequency and power supply voltage Operation guarantee range of MB90F462 MB90F462A, MB90F463A Power supply voltage VCC (V) 5.5 4.5 3.3 3.0 Operation guarantee range of MB90462, MB90467, MB90V460 1 8 3 Operation guarantee range of PLL 12 16 Internal clock fCP (MHz) Relationship between oscillating frequency and internal operating clock frequency Internal clock fCP (MHz) 16 Multiplied- Multiplied- Multipliedby-4 by-3 by-2 Multipliedby-1 12 9 8 Not multiplied 4 3 4 8 Oscillation clock fC (MHz) 16 The AC ratings are measured for the following measurement reference voltages * Input signal waveform * Output signal waveform Hysteresis Input Pin Output Pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pin other than hysteresis input/MD input 0.7 VCC 0.3 VCC DS07-13714-2E 69 MB90460/465 Series (2) Reset Input Timing (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Reset input time Symbol tRSTL Pin RST Value Condition Units Remarks ns Under normal operation ms In stop mode Min Max 4 tCP Oscillation time of oscillator + 4 tCP* * : Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is between handreds s to several ms. In the external clock, the oscillation time is 0 ms. * In stop mode tRSTL RST 0.2 VCC X0 0.2 VCC 90% of amplitude Internal operation clock 4 tCP Oscillation time of oscillator Internal reset 70 Oscillation setting time Instruction execution DS07-13714-2E MB90460/465 Series (3) Power-on Reset (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Power supply rising time tR VCC Power supply cut-off time tOFF VCC Condition Value Unit Min Max 0.05 30 ms 4 ms Remarks Due to repeated operations Note : VCC must be kept lower than 0.2 V before power-on. The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply using the above values. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock. VCC 3.0 V VSS DS07-13714-2E RAM data Hold It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. 71 MB90460/465 Series (4) UART0 to UART1 (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SOT delay time tSLOV Valid SIN SCK tIVSH SCK valid SIN hold time tSHIX Serial clock "H" pulse width Condition Value Unit Remarks Min Max SCK0 to SCK1 8 tCP ns SCK0 to SCK1 SOT0 to SOT1 CL = 80 pF + 1 TTL for an output pin of SCK0 to SCK1 internal shift clock SIN0 to SIN1 mode SCK0 to SCK1, SIN0 to SIN1 -80 80 ns 100 ns 60 ns tSHSL SCK0 to SCK1 4 tCP ns Serial clock "L" pulse width tSLSH SCK0 to SCK1 4 tCP ns SCK SOT delay time tSLOV 150 ns Valid SIN SCK tIVSH 60 ns SCK valid SIN hold time tSHIX 60 ns SCK0 to SCK1, CL = 80 pF + 1 TTL SOT0 to SOT1 for an output pin of external shift clock SCK0 to SCK1, mode SIN0 to SIN1 SCK0 to SCK1, SIN0 to SIN1 Note : * These are AC ratings in the CLK synchronous mode. * CL is the load capacitance value connected to pins while testing. * tCP is machine cycle time (unit : ns) . 72 DS07-13714-2E MB90460/465 Series * Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC * External shift clock mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN DS07-13714-2E tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 73 MB90460/465 Series (5) Resources Input Timing (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Input pulse width Symbol Pin name Condition tTIWH tTIWL IN0 to IN3, SNI0 to SNI2 TIN0 to TIN1 PWI0 to PWI1 DTTI0, DTTI1 0.8 VCC*1 Value Min Max 4 tCP Unit Remarks ns 0.8 VCC 0.2 VCC*2 tTIWH 0.2 VCC*2 tTIWL *1 : 0.7 VCC for PWI0 input pin *2 : 0.3 VCC for PWI0 Input pin (6) Resources Output Timing (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Condition CLK TOUT transition time tTo PWO0 to PWOI1 PPG0 to PPG2 TO0 to TO1 CLK Value Min Max 30 Unit Remarks ns 2.4 V tTO 2.4 V TOUT 0.8 V 74 DS07-13714-2E MB90460/465 Series (7) Trigger Input Timimg (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Input pulse width Symbol Pin name Condition tTRGH tTRGL INT0 to INT7 0.8 VCC Min Max 5 tCP Unit Remarks ns 0.8 VCC 0.2 VCC tTRGH DS07-13714-2E Value 0.2 VCC tTRGL 75 MB90460/465 Series 5. A/D Converter Electrical Characteristics Parameter Resolution Total error (3.0 V AVR - AVSS, VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value SymPin Unit Remarks bol name Min Typ Max 10 bit 3.0 LSB For MB90F462, MB90462, MB90F462A, MB90F463A, MB90467 5.0 LSB For MB90V460 Non-linear error 2.5 LSB Differential linearity error 1.9 LSB AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB V VOT AN0 to AN7 For MB90F462, MB90462, MB90F462A, MB90F463A, MB90467 AVSS - 3.5 LSB AVSS + 0.5 LSB AVSS + 4.5 LSB V For MB90V460 AVR - 3.5 LSB AVR - 1.5 LSB AVR + 0.5 LSB V For MB90F462, MB90462, MB90F462A, MB90F463A,MB90467 AVR - 6.5 LSB AVR - 1.5 LSB AVR + 1.5 LSB V For MB90V460 Zero transition voltage Full-scale transition voltage VFST AN0 to AN7 Conversion time 6.125 1000 s Actual value is specified as a sum of values specified in ADCR0 : CT1, CT0 and ADCR0 : ST1, ST0. Be sure that the setting value is greater than the min value Sampling period 2 s Actual value is specified in ADCR0 : ST1, ST0 bits. Be sure that the setting value is greater than the min value Analog port input current IAIN AN0 to AN7 10 A Analog input voltage VAIN AN0 to AN7 AVSS AVR V Reference voltage AVR AVSS + 2.7 AVCC V Power supply current IA 2.3 6 mA 2 5 mA For MB90V460 5 A * 140 260 A For MB90F462, MB90462, MB90467 600 900 A For MB90F462A, MB90F463A 0.9 1.3 mA For MB90V460 5 A 4 LSB I Reference voltage supply current AVCC AH* IR AVR IRH* Offset between channels AN0 to AN7 For MB90F462, MB90F462A, MB90F463A, MB90462, MB90467 * * : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 5.0 V) 76 DS07-13714-2E MB90460/465 Series 6. A/D Converter Glossary Resolution : Linearity error : Analog changes that are identifiable with the A/D converter The deviation of the straight line connecting the zero transition point ("00 0000 0000" "000000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF Digital output 3FE Actual conversion value 1.5 LSB 3FD {1 LSB x (N - 1) + 0.5 LSB} 004 VNT (Measured value) 003 Actual conversion value Theoretical characteristics 002 001 0.5 LSB AVR AVss Analog input Total error for digital output N = 1 LSB = (Theoretical value) VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVR - AVSS 1024 [LSB] [V] VOT (Theoretical value) = AVSS + 0.5 LSB [V] VFST (Theoretical value) = AVR - 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) to N (Continued) DS07-13714-2E 77 MB90460/465 Series (Continued) Linearity error Actual conversion value {1 LSB x (N - 1) + VOT } 3FE 3FD Digital output Theoretical characteristics N+1 Actual conversion value VFST (Measured value) Digital output 3FF Differential linearity error VNT (measured value) 004 Actual conversion value 003 002 Theoretical characteristics 001 N V (N + 1) T (Measured value) N-1 VNT (Measured value) Actual conversion value N-2 VOT (Measured value) AVss AVR AVss AVR Analog input Linearity error of = digital output N Differential linearity error = of digital output N 1 LSB = Analog input VNT - {1 LSB x (N - 1) + VOT} 1 LSB [LSB] V (N + 1) T - VNT -1 [LSB] 1 LSB VFST - VOT 1022 [V] VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH" 78 DS07-13714-2E MB90460/465 Series 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit recommends about 5 k or lower (sampling period = 2.0 s @machine clock of 16 MHz) . When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient. * Analog input circuit model Analog input R Comparator C R 2.6 K, C 28 pF R 1.95K C 17 pF R 3.2 K, C 30 pF MB90462, MB90F462, MB90467 MB90F462A,MB90F463A MB90V460 Note : Listed values must be considered as standards. * Error The smaller the absolute value of | AVR - AVSS |, the greater the error would become relatively. 8. Flash Memory Program and Erase Performances Parameter Condition Sector erase time Chip erase time TA = + 25 C VCC = 3.0 V Word (16 bit width) programming time Erase/Program cycle DS07-13714-2E Value Unit Remarks 15 s Excludes 00H programming prior erasure 5 s Excludes 00 H programming prior erasure 16 3,600 s Excludes system-level overhead 10,000 cycle Min Typ Max 1 79 MB90460/465 Series EXAMPLE CHARACTERISTICS * Power Suppy Current of MB90462, MB90467 ICCH vs. VCC TA = 25 C, external clock input 40 ICCS vs. VCC TA = 25 C, external clock input FC = 16 [MHz] 20 35 16 25 FC = 10 [MHz] 20 FC = 8 [MHz] ICCS (mA) FC = 12 [MHz] 30 ICCH (mA) FC = 16 [MHz] 18 15 FC = 4 [MHz] 10 FC = 12 [MHz] 12 FC = 10 [MHz] 10 FC = 8 [MHz] 8 6 FC = 4 [MHz] 4 FC = 2 [MHz] 2 FC = 2 [MHz] 5 14 0 2 3 4 5 6 0 2 3 4 5 6 VCC (V) VCC (V) 1000 1000 900 900 800 800 700 700 600 600 500 400 500 400 300 300 200 200 100 100 0 0 0 -2 -4 -6 -8 IOH (mA) 80 VOL vs. IOL TA = 25 C, VCC = 4.5 V VOL (V) VCC -VOH (mV) VCC - VOH vs. IOH TA = 25 C, VCC = 4.5 V - 10 - 12 0 2 4 6 8 10 12 IOL (mA) DS07-13714-2E MB90460/465 Series * Power Suppy Current of MB90F462 ICCS vs. VCC TA = 25 C, external clock input ICCH vs. VCC TA = 25 C, external clock input 40 35 20 FC = 16 [MHz] 18 30 20 14 FC = 10 [MHz] 12 FC = 12 [MHz] 10 FC = 10 [MHz] 8 FC = 8 [MHz] ICCS (mA) 25 ICCH (mA) FC = 16 [MHz] 16 FC = 12 [MHz] FC = 8 [MHz] 15 6 FC = 4 [MHz] 10 FC = 2 [MHz] 2 FC = 2 [MHz] 5 FC = 4 [MHz] 4 0 2 3 4 0 2 3 4 5 5 6 VCC (V) 6 VCC (V) VOL vs. IOL TA = 25 C, VCC = 4.5 V 1000 1000 900 900 800 800 700 700 600 600 VOL (V) VCC - VOH (mV) VCC - VOH vs. IOH TA = 25 C, VCC = 4.5 V 500 400 500 400 300 300 200 200 100 100 0 0 0 2 4 6 IOH (mA) DS07-13714-2E 8 10 12 0 2 4 6 8 10 12 IOL (mA) 81 MB90460/465 Series * Power Suppy Current of MB90F462A/F463A Ta=25[ ICC [mA] 40.0 ] ] Ta=25[ ICCS [mA] 20.0 18.0 35.0 FCH =16.0[MHz] 16.0 30.0 14.0 FCH =12.0[MHz] 25.0 12.0 FCH =10.0[MHz] 20.0 FCH =8.0[MHz] 15.0 FCH =16.0[MHz] 10.0 FCH =12.0[MHz] 8.0 FCH =10.0[MHz] 6.0 10.0 FCH =4.0[MHz] 4.0 FCH =2.0[MHz] 2.0 FCH =8.0[MHz] FCH =4.0[MHz] 5.0 FCH =2.0[MHz] 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 1.0 7.0 Vcc[V] 2.0 3.0 4.0 5.0 6.0 7.0 Vcc[V] * Output Voltage of MB90F462A/F463A VCC-VOH [V] ] Ta=25[ Ta=25[ VOL1 [V] 0.8 1.0 Vcc=3.0[V] Vcc=3.0[V] 0.8 Vcc=3.5[V] ] Vcc=3.5[V] Vcc=4.0[V] c Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] Vcc=6.0[V] 0.6 Vcc=4.0[V] Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] 0.6 Vcc=6.0[V] 0.4 0.4 0.2 0.2 0.0 0.0 0 -2 -4 Ta=25[ VOL2 [V] 0.30 -6 -8 -10 IOH [mA] 0 2 4 6 8 10 IOL [mA] ] Vcc=3.0[V] Vcc=3.5[V] Vcc=4.0[V] Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] Vcc=6.0[V] 0.25 0.20 0.15 0.10 0.05 0.00 0 82 2 4 6 8 10 IOL [mA] DS07-13714-2E MB90460/465 Series ORDERING INFORMATION Part number Package MB90F462PMC MB90F462APMC MB90F463APMC MB90462PMC MB90467PMC 64-pin Plastic LQFP (FPT-64P-M23) MB90F462PF MB90F462APF MB90F463APF MB90462PF MB90467PF 64-pin Plastic QFP (FPT-64P-M06) MB90F462P-SH MB90F462AP-SH MB90F463AP-SH MB90462P-SH MB90467P-SH DS07-13714-2E Remarks 64-pin Plastic SH-DIP (DIP-64P-M01) 83 MB90460/465 Series PACKAGE DIMENSIONS 64-pin plastic QFP Lead pitch 1.00 mm Package width x package length 14 x 20 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP64-14x20-1.00 (FPT-64P-M06) 64-pin plastic QFP (FPT-64P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 24.700.40(.972.016) * 20.000.20(.787.008) 51 0.170.06 (.007.002) 33 32 52 18.700.40 (.736.016) *14.000.20 (.551.008) INDEX Details of "A" part +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 20 64 0~8 1 19 1.00(.039) 0.420.08 (.017.003) 0.20(.008) +0.15 M 0.25 -0.20 1.200.20 (.047.008) +.006 .010 -.008 (Stand off) "A" 0.10(.004) C 2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 84 DS07-13714-2E MB90460/465 Series 64-pin plastic LQFP Lead pitch 0.65 mm Package width x package length 12.0 x 12.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LFQFP64-12x12-0.65 (FPT-64P-M23) 64-pin plastic LQFP (FPT-64P-M23) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.000.20(.551.008)SQ *12.000.10(.472.004)SQ 48 0.1450.055 (.0057.0022) 33 32 49 0.10(.004) Details of "A" part +0.20 1.50 -0.10 +.008 (Mounting height) .059 -.004 0.25(.010) INDEX 0~8 17 64 1 "A" 16 0.65(.026) 0.320.05 (.013.002) 0.13(.005) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (Stand off) M (c)2003-2008 FUJITSU LIMITED F64034S-c-1-2 C 2003 FUJITSU LIMITEDMICROELECTRONICS F64034S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07-13714-2E 85 MB90460/465 Series (Continued) 64-pin plastic SH-DIP Lead pitch 1.778mm(70mil) Package width x package length 17 x 58 mm Sealing method Plastic mold Mounting height 5.65 mm MAX (DIP-64P-M01) 64-pin plastic SH-DIP (DIP-64P-M01) Note: Pins width and pins thickness include plating thickness. +0.22 +.009 58.00 -0.55 2.283 -.022 INDEX-1 17.000.25 (.669.010) INDEX-2 +0.70 4.95 -0.20 +.028 .195 -.008 +0.50 0.70 -0.19 +.020 .028 -.007 0.270.10 (.011.004) +0.20 3.30 -0.30 .130 +.008 -.012 1.378 .0543 C +0.40 -0.20 +.016 -.008 1.778(.0700) 0.470.10 (.019.004) 19.05(.750) +0.50 0.25(.010) M 2001-2008 FUJITSU MICROELECTRONICS LIMITED D64001S-c-4-6 1.00 -0 .039 +.020 -.0 0~15 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 86 DS07-13714-2E MB90460/465 Series MAIN CHANGES IN THIS EDITION Page Section Changed the series name; MB90460 seriesMB90460/465 series Added the part number; MB90F462A, MB90F463A Changed the package. (FPT-64P-M09 FPT-64P-M23) 61, 62 PERIPHERAL RESOURCES 16. 512/1024 Kbit Flash Memory Change Results Added the 1024 Kbit flash memory. 74 ELECTRICAL CHARACTERISTICS Added the "(6) Resources Output Timing" 4. AC Characteristics 76 ELECTRICAL CHARACTERISTICS Changed the unit of "Zero transition voltage" and "Full-scale 5. A/D Converter Electrical transition voltage"; Characteristics mV V ORDERING INFORMATION Changed the part number; MB90462PFM MB90462PMC MB90467PFM MB90467PMC MB90F462PFM MB90F462PMC PACKAGE DIMENSIONS Changed the figure of package. FPT-64P-M09 FPT-64P-M23 83 85 The vertical lines marked in the left side of the page show the changes. DS07-13714-2E 87 MB90460/465 Series FUJITSU MICROELECTRONICS LIMITED 7-1, Nishishinjuku 2-chome, Shinjuku Dai-Ichi Seimei Bldg., Shinjuku-ku, Tokyo 163-0722, JAPAN Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. 151 Lorong Chuan, #05-08 New Tech Park, Singapore 556741, SINGAPORE Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, F. R. GERMANY Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. No.222 Yan An Road(E), Rm.3102, Bund Center, Shanghai 200002, P. R. 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