UT54ACS164E/UT54ACTS164E Radiation-Hardened 8-Bit Shift Registers FUNCTION TABLE FEATURES * * * * * * * * * AND-gated (enable/disable) serial inputs Fully buffered clock and serial inputs Direct clear 0.6m CRH CMOS Process - Latchup immune High speed Low power consumption Wide operating power supply from 3.0V to 5.5V Available QML Q or V processes Flexible package - 14-lead flatpack DESCRIPTION The UT54ACS164E and the UT54ACTS164E are 8-bit shift registers which feature AND-gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data. A low at either input inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high-level at both serial inputs sets the first flip-flop to the high level at the next clock pulse. Data at the serial inputs may be changed while the clock is high or low, providing the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock input. The devices are characterized over full military temperature range of -55C to +125C. PINOUT INPUTS CLR CLK A B QA L X X X L L L H L X X QA0 QB0 QH0 H H H H QAn QGn H L X L QAn QGn H X L L QAn QGn LOGIC SYMBOL (9) CLR (8) CLK B A 1 14 VDD B 2 13 QH QA 3 12 QG QB QC 4 11 5 10 QF QE QD 6 9 CLR VSS 7 8 CLK QB ... QH Notes: 1. QA0, QB0, QH0 = the level of QA, QB or QH, respectively, before the indicated steady-state input conditions were established. 2. QAn and QGn = the level of QA or QG before the most recent transition of the clock; indicates a one-bit shift. A 14-Lead Flatpack Top View OUTPUTS (1) (2) SRG8 R C1/ & 1D (3) QA (4) QB (5) Q (6) C QD (10) Q (11) E Q (12) F QG (13) QH Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM CLR CLK SERIAL (9) (8) (1) A B (2) C R K S C R K S C R K S (4) (3) QA C R K S QB (5) QC C R K S C R K S (6) QD (10) QE C R K S C R K S (11) (12) QF QG (13) QH RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD + .3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 3.0 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C 2 DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS164E7 ( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C) SYMBOL VIL VIH IIN VOL VOH IOS IOL IOH Description CONDITION Low-level input voltage 1 High-level input voltage 1 VDD MAX UNIT 3.0V 0.9 V 5.5V 1.65 3.0V 2.1 5.5V 3.85 -1 A 3.0V 0.25 V 4.5V 0.25 VIN = VDD or VSS 5.5V Low-level output voltage 3 IOL = 100A Short-circuit output current 2 ,4 Low level output current9 High level output current9 IOH = -100A V 1 Input leakage current High-level output voltage 3 MIN 3.0V 2.75 4.5V 4.25 3.0V -100 100 5.5V -200 200 VIN = VDD or VSS 3.0V 6 VOL = 0.4V 5.5V 8 VIN = VDD or VSS 3.0V -6 VOH = VDD-0.4V 5.5V -8 VO = VDD and VSS V mA mA mA Ptotal Power dissipation 2, 8 CL = 50pF 5.5V 1.9 mW/ MHz IDDQ Quiescent Supply Current VIN = VDD or VSS 5.5V 10 A CIN Input capacitance 5 = 1MHz 0V 15 pF Output capacitance 5 = 1MHz 0V 15 pF COUT Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B. 8. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 3 AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS164E2 (VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C) SYMBOL tPHL1 PARAMETER CLK to Qn VDD CL = 30pF CL = 50pF tPLH1 CLK to Qn CL = 30pF CL = 50pF tPLH2 CLR to Qn CL = 30pF CL = 50pF MINIMUM MAXIMUM UNIT ns 3.0V & 3.6V 4 21 4.5V & 5.5V 4 17 3.0V & 3.6V 4 25 4.5V & 5.5V 4 21 3.0V & 3.6V 2 18 4.5V & 5.5V 2 14 3.0V & 3.6V 2 22 4.5V & 5.5V 2 18 3.0V & 3.6V 5 21 4.5V & 5.5V 5 17 3.0V & 3.6V 5 25 4.5V & 5.5V 5 21 83 ns ns ns ns ns fMAX Maximum clock frequency CL = 50pF 3.0V, 4.5V, and 5.5V tSU1 Data setup time before CLK CL = 50pF 3.0V, 4.5V, and 5.5V 4 ns tSU2 CLR inactive Setup time before CLK CL = 50pF 3.0V, 4.5V, and 5.5V 4 ns tH3 Data hold time after CLK CL = 50pF 3.0V, 4.5V, and 5.5V 2 ns tW Minimum pulse width CLR low CLK high CLK low CL = 50pF 3.0V, 4.5V, and 5.5V 6 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B. 3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested. 4 MHz DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS164E7 ( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C) SYMBOL VIL VIH IIN VOL VOH IOS IOL IOH Description CONDITION Low-level input voltage 1 High-level input voltage 1 VDD MAX UNIT 3.0V 0.8 V 5.5V 0.8 3.0V 2.0 5.5V 2.75 -1 A 3.0V 0.4 V IOL = 8mA 4.5V 0.4 V IOL = -6mA 3.0V 2.4 V IOL = -8mA 4.5V 3.15 V VO = VDD and VSS 3.0V -100 100 5.5V -200 200 VIN = VDD or VSS 3.0V 6 VOL = 0.4V 5.5V 8 VIN = VDD or VSS 3.0V -6 VOH = VDD-0.4V 5.5V -8 VIN = VDD or VSS 5.5V Low-level output voltage 3 IOL = 6mA Short-circuit output current 2 ,4 Low level output current10 High level output current10 V 1 Input leakage current High-level output voltage 3 MIN mA mA mA Ptotal Power dissipation 2, 8, ,9 CL = 50pF 5.5V 1.9 mW/ MHz IDDQ Quiescent Supply Current VIN = VDD or VSS 5.5V 10 A Quiescent Supply Current Delta For input under test 5.5V 1.6 mA IDDQ VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS CIN COUT Input capacitance 5 = 1MHz 0V 15 pF Output capacitance 5 = 1MHz 0V 15 pF Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B. 8. Power does not include power contribution of any TTL output sink current 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 5 AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS164E2 (VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C) SYMBOL tPHL1 PARAMETER CLK to Qn VDD CL = 30pF CL = 50pF tPLH1 CLK to Qn CL = 30pF CL = 50pF tPLH2 CLR to Qn CL = 30pF CL = 50pF MINIMUM MAXIMUM UNIT ns 3.0V & 3.6V 4 21 4.5V & 5.5V 4 17 3.0V & 3.6V 4 25 4.5V & 5.5V 4 21 3.0V & 3.6V 2 18 4.5V & 5.5V 2 14 3.0V & 3.6V 2 22 4.5V & 5.5V 2 18 3.0V & 3.6V 5 21 4.5V & 5.5V 5 17 3.0V & 3.6V 5 25 4.5V & 5.5V 5 21 83 ns ns ns ns ns fMAX Maximum clock frequency CL = 50pF 3.0V, 4.5V, and 5.5V tSU1 Data setup time before CLK CL = 50pF 3.0V, 4.5V, and 5.5V 4 ns tSU2 CLR inactive Setup time before CLK CL = 50pF 3.0V, 4.5V, and 5.5V 4 ns tH3 Data hold time after CLK CL = 50pF 3.0V, 4.5V, and 5.5V 2 ns tW Minimum pulse width CLR low CLK high CLK low CL = 50pF 3.0V, 4.5V, and 5.5V 6 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B. 3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested. 6 MHz Packaging 7 Ordering Information UT54ACS164E/UT54ACTS164E UT54 *** **** - * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Screening: (Note 3) C = Military Temperature Range (-55oC to +125oC) Package Type: U = 14-lead ceramic bottom-brazed dual-in-line Flatpack Part Number: 164E = 8-bit Shift Register I/O Type: ACS = CMOS compatible I/O level ACTS = TTL compatible I/O level Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices have 48 hours of burn-in and are test at -55oC, room temperature, and 125oC. Radiation characterisitics are neither tested nor guaranteed and may not be specified. 8 UT54ACS164E/UTACTS164E: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 14-lead ceramic bottom-brazed dual-in-line Flatpack Class Designator: Q = QML Class Q V = QML Class V Device Type: 02 = TID per MIL-STD-883 TM1019 Condition B 03 = TID per MIL-STD-883 TM1019 Condition A Drawing Number: 96556 = UT54ACS164E 96557 = UT54ACTS164E Total Dose: (Note 3) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML V is not available without radiation testing. 4. Total dose tolerance of 1E6 rads(Si) is only available for device type 02. 9 10