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ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Features Description 8 x 6 Crosspoint Switch Matrix The FMS6502 provides eight inputs that can be routed to any of six outputs. Each input can be routed to one or more outputs, but only one input may be routed to any output. Supports SD, PS, and HD 1080i / 1080p Video Input Clamp and Bias Circuitry Doubly Terminated 75 Cable Drivers Programmable 0dB or 6dB Gain AC- or DC-Coupled Inputs AC- or DC-Coupled Outputs One-to-One or One-to-Many Input-to-Output Switching I2CTM-Compatible Digital Interface, Standard Mode 3.3V or 5V Single Supply Operation Pb-Free TSSOP-24 Package Applications Each input supports an integrated clamp option to set the output sync tip level of video with sync to ~300mV. Alternatively, the input may be internally biased to center output signals without sync (Chroma, Pb, Pr) at ~1.25V. All outputs are designed to drive a 150 DC-coupled load. Each output can be programmed to provide either 0dB or 6dB of signal gain. Input-to-output routing and input bias mode functions are controlled via an I2C-compatible digital interface. Block Diagram Cable and Satellite Set-Top Boxes TV and HDTV Sets IN1 C/B IN2 C/B IN8 C/B A / V Switchers Personal Video Recorders (PVR) Security and Surveillance Video Distribution Automotive (In-Cabin Entertainment) SDA SCL ADDR0 ADDR1 VCC (2) GND (4) OUT1 OUT2 OUT6 Figure 1. Block Diagram Ordering Information Part Number Pb-Free Operating Temperature Range FMS6502MTC24 Yes FMS6502MTC24X Yes (c) 2006 Fairchild Semiconductor Corporation Rev. 1.0.0 Package Packing Method -40C to 85C 24-Lead Thin Shrink Small Ouline Package Rail -40C to 85C 24-Lead Thin Shrink Small Ouline Package Reel www.fairchildsemi.com FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry January 2007 IN1 GND 1 Pin Description 24 2 GND 23 OUT1 22 OUT2 21 OUT3 FAIRCHILD IN2 3 FMS6502 VDD 4 24L TSSOP IN3 5 20 VDD GND 6 19 OUT4 IN4 7 18 OUT5 ADDR1 8 17 OUT6 IN5 9 16 GND 10 15 IN8 ADDR0 IN6 11 14 SDA SCL 12 13 IN7 Figure 2. Pin Configuration (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 Pin# Pin Type Description 1 IN1 Input Input, channel 1 2 GND Output 3 IN2 Input Input, channel 2 4 VDD Input Positive power supply 5 IN3 Input Input, channel 3 6 GND Output Must be tied to ground Must be tied to ground 7 IN4 Input Input, channel 4 8 ADDR1 Input Selects I2C address 9 IN5 Input Input, channel 5 10 ADDR0 Input Selects I2C address 11 IN6 Input Input, channel 6 12 SCL Input Serial clock for I2C port 13 IN7 Input Input, channel 7 14 SDA Input Serial data for I2C port Input, channel 8 15 IN8 Input 16 GND Output Must be tied to ground 17 OUT6 Output Output, channel 6 18 OUT5 Output Output, channel 5 19 OUT4 Output Output, channel 4 20 VDD Input 21 OUT3 Output Output, channel 3 22 OUT2 Output Output, channel 2 23 OUT1 Output Output, channel 1 24 GND Output Must be tied to ground Positive power supply www.fairchildsemi.com 2 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter Min. Max. Unit DC Supply Voltage -0.3 6 V Analog and Digital I/O -0.3 Vcc + 0.3 V 40 mA Output Current Any One Channel, Do Not Exceed Reliability Information Symbol TJ TSTG Parameter Min. Typ. Junction Temperature Storage Temperature Range -65 TL Lead Temperature (Soldering, 10s) JA Thermal Resistance, JEDEC Standard Multi-Layer Test Boards, Still Air Max. Unit 150 C 150 C 300 C 84 C/W Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA VCC Parameter Min. Operating Temperature Range Typ. -40 Supply Voltage Range 3.135 5.0 Max. Unit 85 C 5.25 V Electrostatic Discharge Information Symbol Parameter Value Unit HBM Human Body Model (JEDEC: JESD22-A114) 10 kV CDM Charged Device Model (JEDEC: JESD22-A101) 2 kV (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 3 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Absolute Maximum Ratings The I2C-compatibe interface is used to program output enables, input-to-output routing, and input bias configuration. The I2C address of the FMS6502 is 0x06 (0000 0110) with the ability to offset based upon the values of the ADDR0 and ADDR1 inputs. Offset addresses are defined below: ADDR1 ADDR0 Binary Hex 0 0 0000 0110 0x06 0 1 0100 0110 0x46 1 0 1000 0110 0x86 1 1 1100 0110 0xC6 Data and address data of eight bits each are written to the FMS6502 I2C address register to access control functions. The clamp / bias control bits are written to their own internal address since they should remain the same regardless of signal routing. They are set based on the input signal that is connected to the FMS6502. For efficiency, a single data register is shared between two outputs for input selection. More than one output can select the same input channel for one-to-many routing. All undefined addresses may be written without effect. Output Control Register Contents and Defaults Control Name Width Type Default Bit(s) Description In-A 4 bits Write 0 3:0 Input selected to drive this output: 0000=OFF1, 0001=IN1, 0010=IN2, 1000=IN8 In-B 4 bits Write 0 7:4 Input selected to drive this output: 0000=OFF1, 0001=IN1, 0010=IN2, 1000=IN8 Bit 7 Bit 6 Output Control Register MAP Name Address Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OUT1,2 0x00 B3-Out2 B2-Out2 B1-Out2 B0-Out2 B3-Out1 B2-Out1 B1-Out1 B0-Out1 OUT3,4 0x01 B3-Out4 B2-Out4 B1-Out4 B0-Out4 B3-Out3 B2-Out3 B1-Out3 B0-Out3 OUT5,6 0x02 B3-Out6 B2-Out6 B1-Out6 B0-Out6 B3-Out5 B2-Out5 B1-Out5 B0-Out5 Clamp Control Register Contents and Defaults Control Name Width Type Default Bit(s) Description Clmp 1 bit Write 0 7:0 Clamp / Bias selection: 1 = Clamp, 0 = Bias Clamp Control Register Map Name Address Bit 7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLAMP 0x03 Clmp8 Clmp7 Clmp6 Clmp5 Clmp4 Clmp3 Clmp2 Clmp1 Gain Control Register Contents and Defaults Control Name Width Type Default Bit(s) Description Gain 1 bit Write 0 7:0 Output Gain selection: 0 = 6dB, 1 = 0dB Gain Control Register Map Name Address Bit 7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 GAIN 0x04 Unused Unused Gain6 Gain5 Gain4 Gain3 Gain2 Gain1 Note: 1. When the OFF input selection is used, the output amplifier is powered down and enters a high-impedance state. (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 4 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Digital Interface TA = 25C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC-coupled with 0.1F, unused inputs AC-terminated through 75 to GND, all outputs AC-coupled with 220F into 150, referenced to 400kHz unless otherwise noted. Symbol ICC VOUT Parameter PSRR Typ. Max. Unit 55 75 mA 2.8 (1) Vpp Clamp Mode, All Gain Settings 0.10 0.15 0.20 V (1) Clamp Mode, 0dB Gain Setting 0.10 0.15 0.20 V DC Output Level(1) Clamp Mode, 6dB Gain Setting 0.20 0.30 0.40 V DC Output Level DC Input Level Vbias Min. No Load, All Outputs Enabled Video Output Range DC Input Level Vclamp Conditions Supply Current(1) (1) Bias Mode, All Gain Settings 0.575 0.625 0.675 V DC Output Level (1) Bias Mode, 0dB Gain Setting 0.575 0.625 0.700 V DC Output Level (1) Bias Mode, 6dB Gain Setting 1.150 1.250 1.400 Power Supply Rejection Ratio All Channels, DC 90 V dB Note: 1. 100% tested at 25C. AC Electrical Characteristics TA= 25C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC-coupled with 0.1F, unused inputs AC-terminated through 75 to GND, all outputs AC-coupled with 220F into 150, referenced to 400kHz unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit DC, All Channels, 0dB Gain Setting -0.2 0 +0.2 dB DC, All Channels, 6dB Gain Setting 5.8 6 6.2 dB Channel Gain(1) AV6dB Channel Gain(1) f+1dB +1dB Peaking Bandwidth VOUT = 1.4Vpp 65 MHz f-1dB -1dB Bandwidth VOUT = 1.4Vpp 90 MHz fC -3dB Bandwidth VOUT = 1.4Vpp 115 MHz dG Differential Gain VCC = 5.0V , 3.58MHz 0.1 % d AV0dB Differential Phase VCC = 5.0V , 3.58MHz 0.2 THDSD SD Output Distortion VOUT = 1.4Vpp, 5MHz, VCC = 5.0V 0.05 % THDHD HD Output Distortion VOUT = 1.4Vpp, 22MHz, VCC = 5.0V 0.4 % XTALK1 Input Crosstalk -77 dB XTALK2 Input Crosstalk -62 dB XTALK3 Output Crosstalk -81 dB XTALK4 Output Crosstalk 1MHz, VOUT = 2Vpp(2) 15MHz, VOUT = 2Vpp(2) 1MHz, VOUT = 2Vpp(3) 15MHz, VOUT = 2Vpp(3) -62 dB -50 dB NTC-7 Weighting, 4.2MHz LP, 100kHz HP 78 dB 400kHz to 100MHz, Input Referred 20 nV/ Hz 300 ns XTALK5 Multi-Channel Crosstalk SNRSD Signal-to-Noise Ratio (5) VNOISE Channel Noise AMPON Amplifier Recovery Time Standard Video, VOUT = 2Vpp Post I 2C Programming (4) Notes: 1. 100% tested at 25C. 2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch. 3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch. 4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output. 5. SNR = 20 * log (714mV / rms noise). (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 5 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry DC Electrical Characteristics TA = 25C, Vcc = 5V unless otherwise noted. Symbol Max. Unit Vil Digital Input Low1 Parameter SDA,SCL,ADDR Conditions Min. 0 Typ. 1.5 V Vih 1 Digital Input High SDA,SCL,ADDR 3.0 Vcc V fSCL Clock Frequency SCL 100 kHz tr Input Rise Time 1.5V to 3V 1000 ns tf Input Fall Time 1.5V to 3V 300 ns tlow Clock Low Period 4.7 s thigh Clock High Period 4.0 s tSU,DAT Data Set-up Time 300 ns tHD,DAT Data Hold Time 0 ns tSU,STO Set-up Time from Clock High to Stop 4 s 4.7 s tBUF Start Set-up Time following a Stop tHD,STA Start Hold Time tSU,STA Start Set-up Time following Clock Low to High 4 s 4.7 s Note: 1. 100% tested at 25C. SDA t BUF t LOW tf SCL t HD,STA t tr HD,DAT t t SU,DAT HIGH SDA t SU,STA t SU,STO Figure 3. I2C Bus Timing (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 6 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry I2C BUS Characteristics Operation The I2C-compatible interface conforms to the I2C specification for Standard Mode. Individual addresses may be written, but there is no read capability. The interface consists of two lines: a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply through an external resistor. Data transfer may be initiated only when the bus is not busy. Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line during this time are interpreted as control signals. SCL SDA Data line stable; data valid Figure 4. Change of data allowed Bit Transfer Start and Stop conditions A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as stop condition (P). Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as start condition (S). SCL S P SDA STOP condition START condition Figure 5. START and STOP conditions (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 7 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry I2C Interface The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter while the master generates an extra acknowledge-related clock pulse. The slave receiver addressed must generate an acknowledge after the reception of each byte. A master receiver must generate an acknowledge after the reception of each byte clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. START condition clock pulse for acknowledgement SCL FROM MASTER 1 2 8 9 DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER Figure 6. Acknowledgement on the I2C Bus I2C Bus Protocol Before any data is transmitted on the I2C bus, the device which is to respond is addressed first. The addressing is always carried out with the first byte transmitted after the 1 start procedure. The I2C bus configuration for a data write to the FMS6502 is shown in Figure 7. 9 1 9 SCL SDA A6 START BY MASTER A5 A4 A3 A2 A1 A0 FRAME1 SERIAL BUS ADDRESS BYTE R/W D7 D6 ACK. BY FMS6502 D5 D4 D3 D2 D1 D0 ACK. BY FMS6502 FRAME 2 ADDRESS POINTER REGISTER BYTE 9 1 SCL(CONTINUED) SDA(CONTINUED) D7 D6 D5 D4 D3 D2 FRAME 3 DATA BYTE D1 D0 ACK. BY FMS6502 STOP BY MASTER Figure 7. Write Register Address to Pointer Register; Write Data to Selected Register 3.3V Operation The FMS6502 operates from a single 3.3V supply. With Vcc = 3.3V, the digital input low (Vil) is 0V to 1V and the digital input high (Vih) is 1.8V to 2.9V. (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 8 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Acknowledge Input Clamp / Bias Circuitry Output Configuration The FMS6502 can accommodate AC- or DC-coupled inputs. Internal clamping and bias circuitry are provided to support AC-coupled inputs. These are selectable through the CLMP bits via the I2C-compatible interface. For DC-coupled inputs, the device should be programmed to use the 'bias' input configuration. In this configuration, the input is internally biased to 625mV through a 100k resistor. Distortion is optimized with the output levels set between 250mV above ground and 500mV below the power supply. The FMS6502 outputs may be AC or DC-coupled. DCcoupled loads can drive a 150 load. AC-coupled outputs are capable of driving a single, doubly terminated video load of 150. An external transistor is needed to drive DC low-impedance loads. DC-coupled outputs should be connected as indicated in Figure 10. 75 FMS6502 Output Amplifier With AC-coupled inputs, the FMS6502 uses a simple clamp rather than a full DC-restore circuit. For video signals with and without sync; (Y,CV,R,G,B), the lowest voltage at the output pins is clamped to approximately 300mV above ground. If symmetric AC-coupled input signals are used (Chroma,Pb,Pr,Cb,Cr), the bias circuit can be used to center them within the input common range. The average DC value at the output is approximately 1.27V. Figure 10. DC-Coupled Load Connection Configure AC-coupled loads as shown in Figure 11. Figure 8 shows the clamp mode input circuit and the internally controlled voltage at the input pin for AC-coupled inputs. FMS6502 Output Amplifier Lowest voltage set to 125mV 0.1F Video source must be AC coupled 75 220F 75 75 FMS6502 Input Clamp 75 Figure 11. AC-Coupled Load Connection When an output channel is not connected to an input, the input to that particular channel's amplifier is forced to approximately 150mV. The output amplifier is still active unless specifically disabled by the I2C interface. Voltage output levels depend on the programmed gain for that channel. Figure 8. Clamp Mode Input Circuit Figure 9 shows the bias mode input circuit and the internally controlled voltage at the input pin for AC-coupled inputs. Driving Capacitive Loads Average voltage set to 625mV 0.1F Video source must be AC coupled When driving capacitive loads, use a 10-series resistance to buffer the output, as indicated in Figure 12. FMS6502 Input Bias FMS6502 Output Amplifier 75 10 CL Figure 9. Bias Mode Input Circuit Figure 12. Driving Capacitive Loads (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 9 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Applications Information Crosstalk is an important consideration when using the FMS6502. Input and output crosstalk represent the two major coupling modes that may be present in a typical application. Input crosstalk is crosstalk in the input pins and switches when the interfering signal drives an open switch. It is dominated by inductive coupling in the package lead frame between adjacent leads. It decreases rapidly as the interfering signal moves further away from the pin adjacent to the input signal selected. Output crosstalk is coupling from one driven output to another active output. It decreases with increasing load impedance as it is caused mainly by ground and power coupling between output amplifiers. If a signal is driving an open switch, its crosstalk is mainly input crosstalk. If it is driving a load through an active output, its crosstalk is mainly output crosstalk. Crosstalk from multiple sources into a given channel is measured with the setup shown in Figure 14. Input In1 is driven with a 1Vpp pulse source and connected to outputs Out1 to Out8. Input In9 is driven with a secondary, asynchronous gray field video signal and is connected to Out9. All other inputs are AC terminated with 75. Crosstalk effects on the gray field are measured and calculated with respect to a standard 1Vpp output measured at the load. If not all inputs and outputs are needed, avoid using adjacent channels to reduce crosstalk. TERMINATION IN1 Input and output crosstalk measurements are performed with the test configuration shown in Figure 13. Bias IN1 driven with SD video 1VPP. IN6 driven with asynchronous SD video 1VPP. IN2,3,4,5,7,8 are AC-term to GND with 75 . TERMINATION Bias IN1 IN2 - IN8 are AC-Term to Ground w/75 IN1 = 1VPP IN6 Bias Open switch for input crosstalk. IN8 Bias Close switch for output crosstalk. Measure crosstalk from channels 1-5 into channel 6 OUT1 IN8 Bias OUT6 Figure 14. Test Configuration for Multi-Channel Crosstalk Gain = 6dB Out1 = 2.0VPP Input Crosstalk from IN1 to OUTx OUT1 Output Crosstalk from OUT1 to OUTx OUT6 Figure 13. Test Configuration for Crosstalk For input crosstalk, the switch is open and all inputs are in bias mode. Channel 1 input is driven with a 1Vpp signal, while all other inputs are AC terminated with 75. All outputs are enabled and crosstalk is measured from IN1 to any output. For output crosstalk, the switch is closed. Crosstalk from OUT1 to any output is measured. (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 10 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Crosstalk General layout and supply bypassing play a major role in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board to guide layout and aid device evaluation. The demo board is a fourlayer board with full power and ground planes. Following this layout configuration provides optimum performance and thermal characteristics for the device. For the best results, follow the steps and recommended routing rules listed below. * Make the PCB as thin as possible by reducing FR4 thickness. * Use vias in power pad to tie adjacent layers together. * Remember that baseline temperature is a function of board area, not copper thickness. * Modeling techniques can provide a first-order approximation. Power Dissipation Recommended Routing/Layout Rules Worst-case, additional die power due to DC loading can be estimated at Vcc2/4Rload per output channel. This assumes a constant DC output voltage of Vcc/2. For 5V Vcc with a dual DC video load, add 25/(4*75) = 83mW, per channel. * Do not run analog and digital signals in parallel. * Use separate analog and digital power planes to supply power. * Traces should run on top of the ground plane at all times. Applications for the FMS6502 Video Switch Matrix * No trace should run over ground/power splits. The increased demand for consumer multimedia systems has created a large challenge for system designers to provide cost-effective solutions to capitalize on the growth potential in graphics display technologies. These applications require cost-effective video switching and filtering solutions to deploy high-quality display technologies rapidly and effectively to the target audience. Areas of specific interest include HDTV, media centers, and automotive infotainment (such as navigation, in-cabin entertainment, and back-up cameras). In all cases, the advantages the integrated video switch matrix provides are high-quality video switching specific to the application, as well as video input clamps and on-chip, lowimpedance output cable drivers with switchable gain. * Avoid routing at 90-degree angles. * Minimize clock and video data trace length differences. * Include 10F and 0.1F ceramic power supply bypass capacitors. * Place the 0.1F capacitor within 0.1 inches of the device power pin. * Place the 10F capacitor within 0.75 inches of the device power pin. * For multilayer boards, use a large ground plane to help dissipate heat. * For two-layer boards, use a ground plane that extends beyond the device body by at least 0.5 inches on all sides. Include a metal paddle under the device on the top layer. Generally the largest application for a video switch is for the front-end of an HDTV. This is used to take multiple inputs and route them to their appropriate signal paths (main picture and picture-in-picture, or PiP). These are normally routed into ADCs that are followed by decoders. Technologies for HDTV include LCD, plasma, and CRT, which have similar analog switching circuitry. * Minimize all trace lengths to reduce series inductance. Thermal Considerations Since the interior of most systems, such as set-top boxes, TVs, and DVD players, are at +70C; consideration must be given to providing an adequate heat sink for the device package for maximum heat dissipation. When designing a system board, determine how much power each device dissipates. Ensure that devices of high power are not placed in the same location, such as directly above (top plane) or below (bottom plane) each other on the PCB. VIPDEMOTM Control Software The FMS6502 is configured via an I2C-compatible digital interface. To facilitate demonstration, Fairchild Semiconductor had developed the VIPDEMOTM GUI-based control software to write to the FMS6502 register map. This software is included in the FMS6502DEMO kit. A parallel port I2C adapter and an interface cable to connect to the demo board are also included. Besides using the full FMS6502 interface, the VIPDEMOTM can also be used to control single register read and writes for I2C. PCB Thermal Layout Considerations * Understand the system power requirements and environmental conditions. * Maximize thermal performance of the PCB. * Consider using 70m of copper for high-power designs. (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 11 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Layout Considerations FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 15. 24-Lead Thin Shrink Small Outline Package (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.com 12 FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry 13 www.fairchildsemi.com (c) 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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