ICE3AR0680JZXKLA1 - INFINEON TECHNOLOGIES AG

N e v e r s t o p t h i n k i n g .

Version 2.1a, 11 Jan 2012

Edition 2012-1-11

Published by

Infineon Technologies AG

81726 München, Germany

©Infineon Technologies AG 1/11/12.

Attention please!

The information given in this data sheet shall in no event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values

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CoolSET®-F3R80

ICE3AR0680JZ

Revision History: 2012-1-11 Datasheet Version 2.1a

Previous Version: 2.1

Page Subjects (major changes since last revision)

30 revised outline dimension for PG-DIP-7

7, 17, 18 revise typo

Type Package Marking VDS FOSC RDSon

1) typ @ T=25°C

230VAC ±15%2)

2) Calculated maximum input power rating at Ta=50°C, Ti=125°C and without copper area as heat sink.

85-265 VAC2)

ICE3AR0680JZ PG-DIP-7 3AR0680JZ 800V 100kHz 0.62 82W 52W

ICE3AR0680JZ

Version 2.1a 3 11 Jan 2012

Off-Line SMPS Current Mode Controller with

integrated 800V CoolMOS®and Startup cell

(brownout & frequency jitter) in DIP-7

PG-DIP7

Features

• 800V avalanche rugged CoolMOS®with Startup Cell

• Active Burst Mode for lowest Standby Power

• Selectable entry and exit burst mode level

• 100kHz internally fixed switching frequency with

jittering feature

• Auto Restart Protection for Over load, Open Loop,

VCC Under voltage & Over voltage and Over

temperature

• External auto-restart enable pin

• Over temperature protection with 50°C hysteresis

• Built-in 10ms Soft Start

• Built-in 20ms and extendable blanking time for short

duration peak power

• Propagation delay compensation for both maximum

load and burst mode

• Adjustable brownout feature

• Overall tolerance of Current Limiting <±5%

• BiCMOS technology for low power consumption and

wide VCC voltage range

• Soft gate drive with 50Wturn on resistor

Description

The ICE3AR0680JZ (CoolSET®-F3R80) is an enhanced

800V MOSFET version of ICE3BRxx65J (CoolSET®-F3R

650V) in DIP-7 package. The PWM controller is based on

F3R 650V with some new and enhanced features. In

particular it is a device running at 100KHz, implemented

with brownout features, installing 800V CoolMOS®with

startup cell and packaged into DIP-7. It targets for the low

power SMPS with increased MOSFET voltage margin

requirement such as Off-Line battery adapters, DVD R/W,

DVD Combi, Blue ray, set top box, auxiliary power supply

for PC and server, etc. In summary, the CoolSET®F3R80

provides good voltage margin of MOSFET, lowest

standby power, selectable burst level, reduced output

ripple during burst mode, reliable output with brownout

feature, accurate maximum power control for both

maximum power and burst power, low EMI with frequency

jittering and soft gate drive, built-in and flexible

protections, etc. Therefore, CoolSET®F3R80 is a

Product Highlights

• 800V avalanche rugged CoolMOS®with startup cell

• Active Burst Mode to reach the lowest Standby Power <100mW

• Selectable entry and exit burst mode level

• Adjustable blanking Window for high load jumps

• Frequency jitter and soft driving for low EMI

• Adjustable brownout feature

• Auto Restart protection for over load, over temperature, over voltage and

external protection enable function

• Pb-free lead plating; RoHS compliant

CVCC

CBulk Converter

DC Output

Snubber

Power Management

PWM Controller

Current Mode

85 ... 270 VAC

Typical Application

RSense

FBB

Control Unit

VCC

Startup Cell

Precise Low Tolerance Peak

Current Limitation

Drain

CoolSET®-F3R80

(Brownout & Jitter)

CoolMOS®

GND

RBO2

RBO1 Active Burst Mode

Auto Restart Mode

Brownout mode

BBA

CoolSET®-F3R80

ICE3AR0680JZ

Table of Contents Page

Version 2.1a 4 11 Jan 2012

1 Pin Configuration and Functionality .............................6

1.1 Pin Configuration with PG-DIP-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2 Representative Blockdiagram ..................................7

3 Functional Description ........................................8

3.1 Introduction ..................................................8

3.2 PowerManagement............................................8

3.3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.3.1 PWM-OP .................................................10

3.3.2 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.4 StartupPhase ...............................................10

3.5 PWMSection ................................................12

3.5.1 Oscillator .................................................12

3.5.2 PWM-LatchFF1............................................12

3.5.3 GateDriver ...............................................12

3.6 CurrentLimiting ..............................................13

3.6.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.6.2 Propagation Delay Compensation (patented) . . . . . . . . . . . . . . . . . . . . .13

3.7 ControlUnit .................................................14

3.7.1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.7.2 Active Burst Mode (patented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7.2.1 Selectable burst entry level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7.2.2 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.7.2.3 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.7.2.4 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.7.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.7.3.1 Vcc OVP, OTP, external protection enable and Vcc under voltage . . .18

3.7.3.2 Over load, open loop protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.7.4 BrownoutMode ............................................19

3.7.5 Action sequence at BBA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4 Electrical Characteristics .....................................22

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.2 OperatingRange .............................................23

4.3 Characteristics ...............................................23

4.3.1 SupplySection.............................................23

4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.3.3 PWMSection ..............................................24

4.3.4 SoftStarttime .............................................24

4.3.5 ControlUnit ...............................................25

4.3.6 CurrentLimiting ............................................26

4.3.7 CoolMOS®Section .........................................26

CoolSET®-F3R80

ICE3AR0680JZ

Version 2.1a 5 11 Jan 2012

5 CoolMOS®Performance Characteristic ..........................27

6 Input Power Curve ...........................................29

7 Outline Dimension ...........................................30

8 Marking ....................................................31

9 Schematic for recommended PCB layout ........................32

Version 2.1a 6 11 Jan 2012

CoolSET®-F3R80

ICE3AR0680JZ

Pin Configuration and Functionality

1 Pin Configuration and Functionality

1.1 Pin Configuration with PG-DIP-7

Figure 1 Pin Configuration PG-DIP-7 (top view)

1.2 Pin Functionality

BBA (Brownout, extended Blanking time & Auto-

restart enable)

The BBA pin combines the functions of brownout,

extendable blanking time for over load protection and

the external auto-restart enable. The brownout feature

is to stop the switching pulse when the input voltage is

dropped to a preset low level. The extendable blanking

time function is to extend the built-in 20 ms blanking

time for over load protection by adding an external

capacitor to ground. The external auto-restart enable

function is an external access to stop the gate

switching and force the IC to enter auto-restart mode.

It is triggered by pulling the pin voltage to less than

0.4V.

FBB (Feedback & Burst entry control)

The FBB pin combines the feedback function and the

burst entry/exit control. The regulation information is

provided by the FBB pin to the internal Protection Unit

and the internal PWM-Comparator to control the duty

cycle. The FBB-signal is the only control signal in case

of light load at the Active Burst Mode. The burst entry/

exit control provides an access to select the entry/exit

burst mode level.

CS (Current Sense)

The Current Sense pin senses the voltage developed

on the shunt resistor inserted in the source of the

integrated CoolMOS®. If CS reaches the internal

threshold of the Current Limit Comparator, the Driver

output is immediately switched off. Furthermore the

current information is provided for the PWM-

Comparator to realize the Current Mode.

Drain (Drain of integrated CoolMOS®)

Pin Drain is the connection to the Drain of the

integrated CoolMOS®.

VCC (Power Supply)

The VCC pin is the positive supply of the IC. The

operating range is between 10.5V and 25V.

GND (Ground)

The GND pin is the ground of the controller.

Pin Symbol Function

1 BBA Brownout, extended Blanking

time & Auto-restart enable

2 FBB Feedback & Burst entry/exit con-

trol

3 CS Current Sense/

800V CoolMOS®Source

4 n.c. not connected

5 Drain 800V CoolMOS®Drain

6 - (no pin)

7 VCC Controller Supply Voltage

8 GND Controller Ground

Package PG-DIP-7

GNDBBA

FBB

VCC

n.c. Drain

CoolSET®-F3R80

ICE3AR0680JZ

Representative Blockdiagram

Version 2.1a 7 11 Jan 2012

2 Representative Blockdiagram

Figure 2 Representative Blockdiagram

Version 2.1a 8 11 Jan 2012

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

3 Functional Description

All values which are used in the functional description

are typical values. For calculating the worst cases the

min/max values which can be found in section 4

Electrical Characteristics have to be considered.

3.1 Introduction

CoolSET®-F3R80 brownout and jitter 800V version

(ICE3AR0680JZ) is the enhanced version of the

CoolSET®-F3R 650V version (ICE3BRxx65J). It is

particular good for high voltage margin low power

SMPS application such as auxiliary power supply for

PC and server. The major characteristics are that the

IC is developed with 800V CoolMOS®with start up cell,

having adjustable brownout feature, running at 100KHz

switching frequency and packed in DIP-7 package. It is

derived from F3R 650V version. Thus most of the good

features are retained. Besides, it includes some

enhanced features and new features.

The retained good features include BiCMOS

technology to reduce power consumption and increase

the Vcc voltage range, cycle by cycle current mode

control, built-in 10ms soft start to reduce the stress of

switching elements during start up, built-in 20ms and

extended blanking time for short period of peak power

before entering protection, active burst mode for lowest

standby power and propagation delay compensation

for close power limit between high line and low line,

frequency jittering for low EMI performance, the built-in

auto-restart mode protections for open loop, over load,

Vcc OVP, Vcc under voltage, etc. and also the most

flexible external auto-restart enable, etc.

The enhanced features include narrowing the feedback

voltage swing from 0.5V to 0.3V during burst mode so

that the output voltage ripple can be reduced by 40%,

reduction of the fast voltage fall time of the MOSFET by

increasing the soft turn-on time and addition of 50W

turn-on resistor, faster start up time by optimizing the

Vcc capacitor to 10uF and over temperature protection

with 50°C hysteresis.

The new features include adjustable brownout for

reliable output performance, selectable entry and exit

burst mode so that smaller entry/exit power to burst

mode or even no burst mode is possible and the

propagation delay compensation for burst mode so that

the entry/exit burst mode power is close between high

line and low line.

In summary, the CoolSET®F3R80 provides good

voltage margin of MOSFET, lowest standby power,

flexible burst level, reduced output ripple during burst

mode, reliable output with brownout feature, accurate

power limit for both maximum power and burst power,

low EMI with frequency jittering and soft gate drive,

built-in and flexible protections, etc. Therefore,

CoolSET®F3R80 is a complete solution for the low

power SMPS application.

3.2 Power Management

Figure 3 Power Management

The Undervoltage Lockout monitors the external

supply voltage VVCC. When the SMPS is plugged to the

main line the internal Startup Cell is biased and starts

to charge the external capacitor CVCC which is

connected to the VCC pin. This VCC charge current is

controlled to 0.9mA by the Startup Cell. When the VVCC

exceeds the on-threshold VCCon=17V the bias circuit

are switched on. Then the Startup Cell is switched off

by the Undervoltage Lockout and therefore no power

losses present due to the connection of the Startup Cell

to the Drain voltage. To avoid uncontrolled ringing at

switch-on, a hysteresis start up voltage is implemented.

The switch-off of the controller can only take place

when VVCC falls below 10.5V after normal operation

was entered. The maximum current consumption

before the controller is activated is about 200mA.

When VVCC falls below the off-threshold VCCoff=10.5V,

the bias circuit is switched off and the soft start counter

is reset. Thus it ensures that at every startup cycle the

soft start starts at zero.

The internal bias circuit is switched off if Auto Restart

Mode is entered. The current consumption is then

reduced to 320mA.

Internal Bias

Voltage

Reference

Power Management

5.0V

Undervoltage Lockout

17V

10.5V

Power-Down Reset

Active Burst

Mode

Auto Restart

Mode

Startup Cell

VCCDrain

CoolMOS®

Soft Start block

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 9 11 Jan 2012

Once the malfunction condition is removed, this block

will then turn back on. The recovery from Auto Restart

Mode does not require re-cycling the AC line.

When Active Burst Mode is entered, the internal Bias is

switched off most of the time but the Voltage Reference

is kept alive in order to reduce the current consumption

below 620mA.

3.3 Improved Current Mode

Figure 4 Current Mode

Current Mode means the duty cycle is controlled by the

slope of the primary current. This is done by comparing

the FBB signal with the amplified current sense signal.

Figure 5 Pulse Width Modulation

In case the amplified current sense signal exceeds the

FBB signal the on-time ton of the driver is finished by

resetting the PWM-Latch (Figure 5).

The primary current is sensed by the external series

resistor RSense inserted in the source of the integrated

CoolMOS®. By means of Current Mode regulation, the

secondary output voltage is insensitive to the line

variations. The current waveform slope will change with

the line variation, which controls the duty cycle.

The external RSense allows an individual adjustment of

the maximum source current of the integrated

CoolMOS®.

To improve the Current Mode during light load

conditions the amplified current ramp of the PWM-OP

is superimposed on a voltage ramp, which is built by

the switch T2, the voltage source V1 and a resistor R1

(see Figure 6). Every time the oscillator shuts down for

maximum duty cycle limitation the switch T2 is closed

by VOSC. When the oscillator triggers the Gate Driver,

T2 is opened so that the voltage ramp can start.

Figure 6 Improved Current Mode

In case of light load the amplified current ramp is too

small to ensure a stable regulation. In that case the

Voltage Ramp is a well defined signal for the

comparison with the FBB-signal. The duty cycle is then

controlled by the slope of the Voltage Ramp.

By means of the time delay circuit which is triggered by

the inverted VOSC signal, the Gate Driver is switched-off

until it reaches approximately 156ns delay time (Figure

x3.25

PWM OP

Improved

Current Mode

0.6V

C8 PWM-Latch

FBB R

Driver

Soft-Start Comparator

FBB

Amplified Current Signal

ton

0.6V

Driver

PWMOP

0.6V

10k

Oscillator

T2R1

FBB

PWM-Latch

GateDriver

VoltageRamp

VOSC

Soft-Start Comparator

timedelay

circuit (156ns)

X3.25

PWMComparator

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 10 11 Jan 2012

7). It allows the duty cycle to be reduced continuously

till 0% by decreasing VFBB below that threshold.

Figure 7 Light Load Conditions

3.3.1 PWM-OP

The input of the PWM-OP is applied over the internal

leading edge blanking to the external sense resistor

RSense connected to pin CS. RSense converts the source

current into a sense voltage. The sense voltage is

amplified with a gain of 3.25 by PWM OP. The output

of the PWM-OP is connected to the voltage source V1.

The voltage ramp with the superimposed amplified

current signal is fed into the positive inputs of the PWM-

Comparator C8 and the Soft-Start-Comparator (Figure

8).

3.3.2 PWM-Comparator

The PWM-Comparator compares the sensed current

signal of the integrated CoolMOS®with the feedback

signal VFBB (Figure 8). VFBB is created by an external

optocoupler or external transistor in combination with

the internal pull-up resistor RFB and provides the load

information of the feedback circuitry. When the

amplified current signal of the integrated CoolMOS®

exceeds the signal VFBB the PWM-Comparator

switches off the Gate Driver.

Figure 8 PWM Controlling

3.4 Startup Phase

Figure 9 Soft Start

VOSC

0.6V

FBB

max.

Duty Cycle

Gate

Driver

Voltage

Ramp

156ns time delay

X3.25

PWM OP

Improved

Current Mode

PWM Comparator

Soft-Start Comparator

0.6V

FBB

Optocoupler

RFB

PWM-Latch

Soft-Start

Comparator

Soft Start

C7 Gate Driver

0.6V

x3.25

PWM OP CS

Soft Start counter

Soft Start

Soft Start finish

SoftS

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 11 11 Jan 2012

In the Startup Phase, the IC provides a Soft Start

period to control the primary current by means of a duty

cycle limitation. The Soft Start function is a built-in

function and it is controlled by an internal counter.

Figure 10 Soft Start Phase

When the VVCC exceeds the on-threshold voltage, the

IC starts the Soft Start mode (Figure 10).

The function is realized by an internal Soft Start

resistor, an current sink and a counter. And the

amplitude of the current sink is controlled by the

counter (Figure 11).

Figure 11 Soft Start Circuit

After the IC is switched on, the VSoftS voltage is

controlled such that the voltage is increased step-

wisely (32 steps) with the increase of the counts. The

Soft Start counter would send a signal to the current

sink control in every 300us such that the current sink

decrease gradually and the duty ratio of the gate drive

increases gradually. The Soft Start will be finished in

10ms (tSoft-Start) after the IC is switched on. At the end of

the Soft Start period, the current sink is switched off.

Within the soft start period, the duty cycle is increasing

from zero to maximum gradually (see Figure 12).

Figure 12 Gate drive signal under Soft-Start Phase

In addition to Start-Up, Soft-Start is also activated at

each restart attempt during Auto Restart.

Figure 13 Start Up Phase

VSoftS

VSoftS2

VSoftS1

RSoftS

Soft Start

Counter I

SoftS

32I

VSOFTS32

VSoftS

Gate

Driver

tSoft-Start

VSoftS

VSOFTS32

4.5V

tSoft-Start

VOUT

VFB

VOUT

tStart-Up

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 12 11 Jan 2012

The Start-Up time tStart-Up before the converter output

voltage VOUT is settled, must be shorter than the Soft-

Start Phase tSoft-Start (Figure 13). By means of Soft-Start

there is an effective minimization of current and voltage

stresses on the integrated CoolMOS®, the clamp circuit

and the output rectifier and it helps to prevent

saturation of the transformer during Start-Up.

3.5 PWM Section

Figure 14 PWM Section Block

3.5.1 Oscillator

The oscillator generates a fixed frequency of 100KHz

with frequency jittering of ±4% (which is ±4KHz) at a

jittering period of 4ms.

A capacitor, a current source and current sink which

determine the frequency are integrated. The charging

and discharging current of the implemented oscillator

capacitor are internally trimmed in order to achieve a

very accurate switching frequency. The ratio of

controlled charge to discharge current is adjusted to

reach a maximum duty cycle limitation of Dmax=0.75.

Once the Soft Start period is over and when the IC goes

into normal operating mode, the switching frequency of

the clock is varied by the control signal from the Soft

Start block. Then the switching frequency is varied in

range of 100KHz ± 4KHz at period of 4ms.

3.5.2 PWM-Latch FF1

The output of the oscillator block provides continuous

pulse to the PWM-Latch which turns on/off the

integrated CoolMOS®. After the PWM-Latch is set, it is

reset by the PWM comparator, the Soft Start

comparator or the Current -Limit comparator. When it is

in reset mode, the output of the driver is shut down

immediately.

3.5.3 Gate Driver

Figure 15 Gate Driver

The driver-stage is optimized to minimize EMI and to

provide high circuit efficiency. This is done by reducing

the switch on slope when exceeding the integrated

CoolMOS®threshold. This is achieved by a slope

control of the rising edge at the driver’s output (Figure

16) and adding a 50Wgate turn on resistor (Figure 15).

Thus the leading switch on spike is minimized.

Figure 16 Gate Rising Slope

Furthermore the driver circuit is designed to eliminate

cross conduction of the output stage.

Oscillator

Duty Cycle

max

Gate Driver

0.75

Clock

PWM Section

FF1

Soft Start

Comparator

PWM

Comparator

Current

Limiting

CoolMOS®

Gate

Frequency

Jitter

Soft Start

Block

VCC

PWM-Latch

CoolMOS®

Gate Driver

Gate

50

(internal)

VGate

4.6V

typ. t = 160ns

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 13 11 Jan 2012

During power up, when VCC is below the undervoltage

lockout threshold VVCCoff, the output of the Gate Driver

is set to low in order to disable power transfer to the

secondary side.

3.6 Current Limiting

Figure 17 Current Limiting Block

There is a cycle by cycle peak current limiting operation

realized by the Current-Limit comparator C10. The

source current of the integrated CoolMOS®is sensed

via an external sense resistor RSense. By means of

RSense the source current is transformed to a sense

voltage VSense which is fed into the pin CS. If the voltage

VSense exceeds the internal threshold voltage Vcsth, the

comparator C10 immediately turns off the gate drive by

resetting the PWM Latch FF1.

A Propagation Delay Compensation is added to

support the immediate shut down of the integrated

CoolMOS®with very short propagation delay. Thus the

influence of the AC input voltage on the maximum

output power can be reduced to minimal. This

compensation applies to both the peak load and burst

mode.

In order to prevent the current limit from distortions

caused by leading edge spikes, a Leading Edge

Blanking (LEB) is integrated in the current sense path

for the comparators C10, C12 and the PWM-OP.

The output of comparator C12 is activated by the Gate

G10 if Active Burst Mode is entered. When it is

activated, the current limiting is reduced to Vcsth_burst.

This voltage level determines the maximum power

level in Active Burst Mode.

3.6.1 Leading Edge Blanking

Figure 18 Leading Edge Blanking

Whenever the integrated CoolMOS®is switched on, a

leading edge spike is generated due to the primary-

side capacitances and reverse recovery time of the

secondary-side rectifier. This spike can cause the gate

drive to switch off unintentionally. In order to avoid a

premature termination of the switching pulse, this spike

is blanked out with a time constant of tLEB = 220ns for

normal load and tLEB = 180ns for burst mode.

3.6.2 Propagation Delay Compensation

(patented)

In case of overcurrent detection, there is always

propagation delay to switch off the integrated

CoolMOS®. An overshoot of the peak current Ipeak is

induced to the delay, which depends on the ratio of dI/

dt of the peak current (Figure 19).

Figure 19 Current Limiting

The overshoot of Signal2 is larger than of Signal1 due

to the steeper rising waveform. This change in the

slope is depending on the AC input voltage.

Propagation Delay Compensation is integrated to

CurrentLimiting

C10

C12

G10

Propagation-Delay

Compensation

Vcsth

PWMLatch

FF1

10kD1 1pF

PWM-OP

Propagation-Delay

Compensation-Burst

VCSth_burst

LEB

220ns

LEB

180ns

VFB_burst

FBB

G13

ActiveBurst

Mode

VSense

Vcsth tLEB = 220ns/180ns

ISense

ILimit

tPropagation Delay

IOvershoot1

Ipeak1

Signal1Signal2

IOvershoot2

Ipeak2

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 14 11 Jan 2012

reduce the overshoot due to dI/dt of the rising primary

current. Thus the propagation delay time between

exceeding the current sense threshold Vcsth and the

switching off of the integrated CoolMOS®is

compensated over temperature within a wide input

range. Current Limiting is then very accurate.

For example, Ipeak = 0.5A with RSense = 2. The current

sense threshold is set to a static voltage level Vcsth=1V

without Propagation Delay Compensation. A current

ramp of dI/dt = 0.4A/µs, or dVSense/dt = 0.8V/µs, and a

propagation delay time of tPropagation Delay =180ns leads

to an Ipeak overshoot of 14.4%. With the propagation

delay compensation, the overshoot is only around 2%

(Figure 20).

Figure 20 Overcurrent Shutdown

The Propagation Delay Compensation is realized by

means of a dynamic threshold voltage Vcsth (Figure 21).

In case of a steeper slope the switch off of the driver is

earlier to compensate the delay.

Figure 21 Dynamic Voltage Threshold Vcsth

Similarly, the same concept of propagation delay

compensation is also implemented in burst mode with

reduced level, Vcsth_burst (Figure 17). With this

implementation, the entry and exit burst mode power

can be very close between low line and high line input

voltage.

3.7 Control Unit

The Control Unit contains the functions for Active Burst

Mode and Auto Restart Mode. The Active Burst Mode

and the Auto Restart Mode both have 20ms internal

blanking time. For the over load Auto Restart Mode, the

20ms blanking time can be further extended by adding

an external capacitor at BBA pin. With the blanking

time, the IC avoids entering into those two modes

accidentally. Those buffer time is very useful for the

application which works in short duration of peak power

occasionally.

3.7.1 Basic and Extendable Blanking Mode

Figure 22 Basic and Extendable Blanking Mode

There are 2 kinds of Blanking mode; basic mode and

the extendable mode. The basic mode is a built-in

20ms blanking time while the extendable mode can

extend this blanking time by connecting an external

capacitor to the BBA pin. For the extendable mode, the

gate G5 remains blocked even though the 20ms

blanking time is reached. After reaching the 20ms

blanking time the counter is activated and the switch S1

is turned on to charge the voltage of BBA pin by the

constant current source, Ichg_EB. When the voltage of

BBA pin hits 4.5V, which is sensed by comparator C11,

the counter will increase the counter by 1. Then it

0,9

0,95

1,05

1,1

1,15

1,2

1,25

1,3

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

with compensation without compensation

dVSense s



Sense

Vcsth

VOSC

Signal1 Signal2

VSense Propagation Delay

max. Duty Cycle

off time

C11

4.5V

0.9V

4.5V

Control Unit

Auto

Restart

Mode

5.0V

FBB

CBK

Spike

Blanking

30us

Ichg_EB

BBA Counter &

20ms

Blanking

Time

RBO2

500CT1

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 15 11 Jan 2012

switches off the switch S1 and turns on the switch S2.

The voltage at BBA pin will be discharged through a

500Wresistor. When the voltage drops to 0.9V which is

sensed by comparator C3, the switch S2 will be turned

off and the switch S1 will be turned on. Then the

constant current Ichg_EB will charge the CBK capacitor

again. When the voltage at BBA hits 4.5V which is

sensed by comparator C11, the counter will increase

the count to 2. The process repeats until it reaches total

count of 256 (Figure 23). Then the counter will release

a high output signal. When the AND gate G5 detects

both high signals at the inputs, it will activate the 30ms

spike blanking circuit and finally the auto-restart mode

will be activated.

Figure 23 Waveform at extended blanking time

For example, if CBK=0.1

F, Ichg_EB=720

Extended blanking time = 256*(CBK*(4.5V-0.9V)/Ichg_EB +

CBK*500*ln(4.5/0.9)) = 148.6ms

Total blanking time = 20ms+ 148.6ms =168.6ms

If there is a resistor RBO2 connected to BBA pin, the

effective charging current will be reduced. The blanking

time will be increased.

For example, if CBK=0.1

F, Ichg_EB=720

A, RBO2=12.8K

Ichg_EB’=Ichg_EB-(4.5V+0.9V)/(2*RBO2)=509

Extended blanking time = 256*(CBK*(4.5V-0.9V)/Ichg_EB’ +

CBK*500*ln(4.5/0.9)) = 201.6ms

Total blanking time = 20ms+201.6 = 221.6ms

where Ichg_EB’=net charging current to CBK

Note: The above calculation does not include the effect of the

brownout circuit where there is extra biasing current flowing from

the input. That means the extended blanking time will be

shortened with the line voltage change if brownout circuit is

implemented.

3.7.2 Active Burst Mode (patented)

To increase the efficiency of the system at light load,

the most effective way is to operate at burst mode.

Starting from CoolSET®F3, the IC has been employing

the active burst mode and it can achieve the lowest

standby power. F3R80 adopts the same concept with

some more innovative improvements to the feature. It

includes the adjustable entry burst level, close power

control between high line and low line and the smaller

output ripple during burst mode.

Most of the burst mode design in the market will

provide a fixed entry burst mode level which is a ratio

to the maximum power of the design. F3R80 provides

a more flexible level which can be selected externally.

The provision also includes not entering burst mode.

Propagation delay is the major contributor for the

power control variation for DCM flyback converter. It is

proved to be effective in the maximum power control.

F3R80 also apply the same concept in the burst mode.

Therefore, the entry and exit burst mode power is also

finely controlled during burst mode.

The feedback control swing during burst mode will

affect the output ripple voltage directly. F3R80 reduces

the swing from 0.5V to 0.3V. Therefore, it would have

around 40% improvement for the output ripple.

Figure 24 Active Burst Mode

The Active Burst Mode is located in the Control Unit.

Figure 24 shows the related components.

3.7.2.1 Selectable burst entry level

The burst mode entry level can be selected by

changing the different capacitor CFB at FBB pin. There

are 4 levels to be selected with different capacitor

which are targeted for 10%, 6.67%, 4.38% and 0% of

the maximum input power. At the same time, the exit

burst level are targeted to 20%, 13.3%, 9.6% and 0%

of the maximum power accordingly. The corresponding

capacitance range is from 6.8nF to 100pF. The below

table is the recommended capacitance range for the

entry and exit level with the CFB capacitor.

normal

operation extendedblankingtime

auto

restart

VBBA

0.9V

4.5V 256counts

C6a

3.5V

C13

4.0V

Control Unit

Internal

Bias

C6b

3.2V

G11

Active Burst

Mode

C5 20msBlanking

Time

CFB

C12

CS Vcsth_burst

VFB_burst

G10 &FF1

FBB

Current Limiting

Burst detect

andadjust

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 16 11 Jan 2012

The selection is at the 1st 1ms of the UVLO “ON” (Vcc

> 17V) during the 1st start up but it does not detect in

the subsequent re-start due to auto-restart protection.

In case there is protection triggered such as auto

restart enable or brownout before starts up, the

detection will be held until the protection is removed.

When the Vcc reaches the UVLO “ON” in the 1st start

up, the capacitor CFB at FBB pin is charged by a 5V

voltage source through the RFB resistor. When the

voltage at FBB pin hits 4.5V, the FF4 will be set, the

switch S9 is turned “ON” and the counter will increase

by 1. Then the CFB is discharged through a 500W

resistor. After reaching 0.5V, the FF4 is reset and the

switch S9 is turned “OFF”. Then the CFB capacitor is

charged by the 5V voltage source again until it reaches

4.5V. The process repeats until the end of 1ms. Then

the detection is ended. After that, the total number of

count in the counter is compared and the VFB-burst and

the Vcs_burst are selected accordingly (Figure 25).

Figure 25 Entry burst mode detection

3.7.2.2 Entering Active Burst Mode

The FBB signal is kept monitoring by the comparator

C5 (Figure 24). During normal operation, the internal

blanking time counter is reset to 0. When FBB signal

falls below VFB_burst, it starts to count. When the counter

reaches 20ms and FBB signal is still below VFB_burst, the

system enters the Active Burst Mode. This time window

prevents a sudden entering into the Active Burst Mode

due to large load jumps.

After entering Active Burst Mode, a burst flag is set and

the internal bias is switched off in order to reduce the

current consumption of the IC to about 620uA.

It needs the application to enforce the VCC voltage

above the Undervoltage Lockout level of 10.5V such

that the Startup Cell will not be switched on

accidentally. Or otherwise the power loss will increase

drastically. The minimum VCC level during Active Burst

Mode depends on the load condition and the

application. The lowest VCC level is reached at no load

condition.

3.7.2.3 Working in Active Burst Mode

After entering the Active Burst Mode, the FBB voltage

rises as VOUT starts to decrease, which is due to the

inactive PWM section. The comparator C6a monitors

the FBB signal. If the voltage level is larger than 3.5V,

the internal circuit will be activated; the Internal Bias

circuit resumes and starts to provide switching pulse. In

Active Burst Mode the gate G10 is released and the

current limit is reduced to Vcsth_burst (Figure 2 and

24). In one hand, it can reduce the conduction loss and

the other hand, it can reduce the audible noise. If the

load at VOUT is still kept unchanged, the FBB signal

will drop to 3.2V. At this level the C6b deactivates the

internal circuit again by switching off the Internal Bias.

The gate G11 is active again as the burst flag is set

after entering Active Burst Mode. In Active Burst Mode,

the FBB voltage is changing like a saw tooth between

3.2V and 3.5V (Figure 26).

3.7.2.4 Leaving Active Burst Mode

The FBB voltage will increase immediately if there is a

high load jump. This is observed by the comparator

C13 (Figure 24). Since the current limit is reduced to

31%~45% of the maximum current during active burst

mode, it needs a certain load jump to rise the FBB

signal to exceed 4.0V. At that time the comparator C5

resets the Active Burst Mode control which in turn

blocks the comparator C12 by the gate G10. The

maximum current can then be resumed to stabilize

VOUT.

Entry level Exit level

CFB % of

Pin_max

VFB_burst % of

Pin_max

Vcsth_burst

>=6.8nF

(5%,X7R)

10% 1.60V 20% 0.45V

1nF~2.2nF

(1%,COG)

6.67% 1.42V 13.3% 0.37V

220pF~470pF

(1%,COG)

4.38% 1.27V 9.6% 0.31V

<=100pF

(1%,COG)

0% never 0% always

C19

CFB C20

0.5V

4.5V

ControlUnit

FBB

500

RFB

counter

Comparator

logic

VCSth_burst

VFB_burst

1ms

timer

UVLOduring

1st startup

S Q

UVLO

FF4

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 17 11 Jan 2012

Figure 26 Signals in Active Burst Mode

3.7.3 Protection Modes

The IC provides Auto Restart mode as the major

protection feature. Auto Restart mode can prevent the

SMPS from destructive states. There are 3 kinds of

auto restart mode; normal auto restart mode, odd skip

auto restart mode and non switch auto restart mode.

Odd skip auto restart mode is that there is no detect of

fault and no switching pulse for the odd number restart

cycle. At the even number of restart cycle the fault

detect and soft start switching pulses maintained. If the

fault persists, it would continue the auto-restart mode.

However, if the fault is removed, it can release to

normal operation only at the even number auto restart

cycle (Figure 27).

Figure 27 Odd skip auto restart waveform

Non switch auto restart mode is similar to odd skip auto

restart mode except the start up switching pulses are

also suppressed at the even number of the restart

cycle. The detection of fault still remains at the even

number of the restart cycle. When the fault is removed,

the IC will resume to normal operation at the even

number of the restart cycle (Figure 28).

Figure 28 non switch auto restart waveform

The main purpose of the odd skip auto restart is to

extend the restart time such that the power loss during

auto restart protection can be reduced. This feature is

particularly good for smaller Vcc capacitor where the

restart time is shorter.

The following table lists the possible system failures

and the corresponding protection modes.

VFB_burst

3.5V

4.0V

VFBB

Vcsth_burst

Vcsth

VCS

10.5V

VVCC t

620uA

IVCC

5.7mA

VOUT

20ms Blanking Time

Current limit level

during Active Burst

Mode

3.2V

Entering

Active Burst

Mode

Blanking Timer

Leaving

Active Burst

Mode

VCC Over voltage (1) Odd skip Auto Restart Mode

VCC Over voltage (2) Odd skip Auto Restart Mode

Over load Odd skip Auto Restart Mode

Open Loop Odd skip Auto Restart Mode

10.5V

VCS

VVCC

17V

Fault

detected No detect Startupanddetect

No detect

10.5V

VCS

VVCC

17V

Fault

detected No detect Startupanddetect

No detect

No switching

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 18 11 Jan 2012

3.7.3.1 Vcc OVP, OTP, external protection

enable and Vcc under voltage

Figure 29 Vcc OVP, OTP, external protection

enable

There are 2 types of Vcc over voltage protection; Vcc

OVP (1) and Vcc OVP (2). The Vcc OVP (1) takes

action only during the soft start period. The Vcc OVP

(2) takes the action in any conditions.

Vcc OVP (1) condition is when VVCC voltage is > 20.5V,

VFBB voltage is > 4.5V and during soft start period, the

IC enters into odd skip Auto Restart Mode. This

condition likely happens during start up at open loop

fault. (Figure 29).

Vcc OVP (2) condition is when VVCC voltage is > 25.5V,

the IC enters into odd skip Auto Restart Mode (Figure

29).

The over temperature protection OTP is sensed inside

the controller IC. The Thermal Shutdown block keeps

on monitoring the junction temperature of the

controller. After detecting a junction temperature higher

than 130°C, the IC will enter into the non switch Auto

Restart mode. The F3R80 has also implemented with

a 50°C hysteresis. That means the IC can only be

recovered when the controller junction temperature is

dropped 50°C lower than the over temperature trigger

point (Figure 29).

The external auto restart enable feature can provide a

flexibility to a customer’s self-defined protection

feature. This function can be triggered by pulling down

the VBBA voltage to < 0.4V. Or it can simply trigger the

base pin of an external transistor, TAE at the BBA pin.

When this function is enabled, it will enter into the non

switch auto restart mode. The gate drive is stopped and

there is no switching pulse before it is recovered

(Figure 29).

The Vcc undervoltage and short opto-coupler will go

into the normal auto restart mode inherently.

In case of VCC undervoltage, the Vcc voltage drops

indefinitely. When it drops below the Vcc under voltage

lock out “OFF” voltage (10.5V), the IC will turn off the

IC and the startup cell will turn on again. Then the Vcc

voltage will be charged up to UVLO “ON” voltage (17V)

and the IC turns on again provided the startup cell

charge up current is not drained by the fault. If the fault

is not removed, the Vcc will continue to drop until it hits

UVLO “OFF” voltage and the restart cycle repeats.

Short Optocoupler can lead to Vcc undervoltage

because once the opto-coupler (transistor side) is

shorted, the feedback voltage will drop to zero and

there will be no switching pulse. Then the Vcc voltage

will drop same as the Vcc undervoltage.

3.7.3.2 Over load, open loop protection

Figure 30 Over load, open loop protection

In case of Overload or Open Loop, the FBB exceeds

4.5V which will be observed by comparator C4. Then

the built-in blanking time counter starts to count. When

it reaches 20ms, the extended blanking time counter

CT1 is activated. The switch S2 is turned on and the

voltage at the BBA pin will be discharged through 500W

resistor. When it drops to 0.9V, the switch S2 is turned

off and the Switch S1 is turned on. Then a constant

current source Ichg_EB will start to charge up BBA pin.

When the voltage hits 4.5V which is monitored by

comparator C11, the switch S1 is turned off and the

VCC Undervoltage Normal Auto Restart Mode

Short Optocoupler Normal Auto Restart Mode

Over temperature Non switch Auto Restart Mode

External protection enable Non switch Auto Restart Mode

20.5V

4.5V

Voltage

Reference

Control Unit

AutoRestart

Mode Reset

VVCC <10.5V

FBB

softs_period

Auto-

restart

Enable

Signal

TAE

0.4V

Stop

gate

drive

Spike

Blanking

30µs

Thermal Shutdown

Tj>130°C

BBA

AutoRestart

mode

VCC

C2 120µs blanking

time

25.5V

C11

4.5V

0.9V

4.5V

Control Unit

5.0V

FBB

CBK Spike

Blanking

30us

Ichg_EB

BBA

counter

20ms

Blanking

Time

Voltage

Reference

Auto Restart

Mode Reset

VVCC < 10.5V Auto

Restart

Mode

RBO2

#500CT1

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 19 11 Jan 2012

count will increase by 1. Then the switch S2 will turn on

again and the voltage will drop to 0.9V and rise to 4.5V

again. The count will then increase by 1 again. When

the total count reaches 256, the counter CT1 will stop

and it will release a high output signal. When both the

input signals at AND gate G5 is high, the odd skip Auto

Restart Mode is activated after the 30us spike blanking

time (Figure 30).

The total blanking time depends on the addition of the

built-in and the extended blanking time. If there is no

CBK capacitor at BBA pin, the count will finish within

0.1ms and the equivalent blanking time is just the built-

in time of 20ms. However, if the CBK capacitor is big

enough, it can be as long as 1s. If CBK is 0.1uF and

Ichg_EB is 720uA, the extendable blanking time is around

148.6ms and the total blanking time is 168.6ms.

Since the BBA pin is a multi-function pin, it would share

with different functions. The resistor RBO2 from

brownout feature application may however affect the

extendable blanking time (Figure 30). Thus it should

take the RBO2 into the calculation of the extendable

blanking time. For example the extended blanking time

may be changed from 148.6ms to 201.6ms for without

and having the 12.8KWRBO2 resistor. The list below

shows one particular CBK, RBO2 vs blanking time.

Another factor to affect the extended blanking time is

the input voltage through the RB01 and RB02. It would, on

the contrary, reduce the extended blanking time.

3.7.4 Brownout Mode

When the AC input voltage is removed, the voltage at

the bulk capacitor will fall. When it reaches a point that

the system is greater than the system allowed

maximum power, the system may go into over load

protection. However, this kind of protection is not

welcome for some of the applications such as auxiliary

power for PC/server system because the output is in

hiccup mode due to over load protection (auto restart

mode). The brownout mode is to eliminate this

phenomenon. The IC will sense the input voltage

through the bulk capacitor to the BBA pin by 2 potential

divider resistors, RBO1 and RBO2 (Figure 31).

When the system is powered up, the bulk capacitor and

the Vcc capacitor are charged up at the same time.

When the Vcc voltage is charged to >7V, the brownout

circuit start to operate (Figure 31). Since the UVLO is

still at low level as the Vcc voltage does not reach the

17V UVLO “ON” voltage. The NAND gate G20 will

release a low signal to the flip flop FF5 and the negative

output of FF5 will release a high signal to turn on the

switch S3. The constant load LD6 will start to draw

constant current Ichg_BO from the BBA pin. That means

the brownout mode is default “ON” during the system

starts up.

Figure 31 Brownout detection circuit

Once the system enters the brownout mode, there will

be no switching pulse and the IC enters into another

type auto-restart mode which is similar to the protection

auto-restart mode but the IC will monitor the BBA signal

in each restart cycle (Figure 32).

Figure 32 Brownout mode waveform

The voltage at bulk capacitor Vbulk continues to

increase and so is the voltage at BBA. When the BBA

voltage reaches 0.9V, the output of OPAMP C14 will

become low. Through the inverter gate G21, the “S”

input of the flip flop FF5 is changed to high. Then the

negative output of FF5 is low. The brownout mode is

then “OFF” and the constant current load LD6 is also

“OFF” through the turn-off of the S3. The system will

CBK RBO2 Extended

blanking time

Overall blanking

time

0.1uF - 148.6ms 168.6ms

0.1uF 37.5KW162.8ms 182.8ms

0.1uF 12.8KW201.6ms 221.6ms

C14

0.9V

Control Unit

Brownout

mode

BBA

RBO1

RBO2

Vbulk

Ichg_BO

30µs~60µs

blanking time

UVLO

5µs

blanking

time

FF5

G20

G22

G21

LD6

10.5V

VCS

VVCC

17V

Brownout

detected StartupanddetectBBAvoltage

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 20 11 Jan 2012

turn on with soft start in the coming restart cycle when

Vcc reaches the Vcc “ON” voltage 17V.

When there is an input voltage drop, the BBA voltage

also drops. When the voltage at BBA pin falls below

0.9V, the output of OPAMP C14 is changed to high.

The inverter gate G22 will change the high input to low

output. Then the NAND gate G22 will have a high

output. The negative output of the flip flop FF5 is then

become high. The constant load LD6 is “ON” again and

the IC enters the brownout mode where the Vcc swings

between 10.5V and 17V without any switching pulse.

The formula to calculate the RBO1 and RBO2 are as

below.

RBO1=Vhys/Ichg_BO

RBO2=Vref_BO*RBO1/(VBO_l -Vref_BO)

where VBO_l: input brownout voltage (low point); Vhys:

input brownout hysteresis voltage; Vref_BO: IC reference

voltage for brownout; RBO1 and RBO2: resistors divider

from input voltage to BBA pin

For example,

Ichg_BO=10uA, Vref_BO=0.9V,

Case 1:

if brownout voltage is 70Vac on and 100Vac off,

then brownout voltage, VBO_l=100Vdc,

hysteresis voltage, VBO_hys=43Vdc,

RBO1=4.3MW, RBO2=39KW

Case 2:

if brownout voltage is 100Vac on and 120Vac off,

then brownout voltage, VBO_l=141Vdc,

hysteresis voltage, VBO_hys=28Vdc,

RBO1=2.8MW, RBO2=18KW

Case 3:

if brownout voltage is 120Vac on and 160Vac off,

then brownout voltage, VBO_l=169Vdc,

hysteresis voltage, VBO_hys=56Vdc,

RBO1=5.6MW, RBO2=30KW

The summary is listed below.

Note: The above calculation assumes the tapping point

(bulk capacitor) has a stable voltage with no ripple

voltage. If there is ripple in the input voltage, it should

take the highest voltage for the calculation; VBO_l +

ripple voltage. Besides that the low side brownout

voltage VBO_l added with the ripple voltage at the

tapping point should always be lower than the high side

brownout voltage (VBO_h); VBO_h > VBO_l + ripple

voltage. Otherwise, the brownout feature cannot work

properly. In short, when there is a high load running in

system before entering brownout, the input ripple

voltage will increase and the brownout voltage will

increase (VBO_l = VBO_l + ripple voltage) at the same

time. If the VBO_hys is set too small and is close to the

ripple voltage, then the brownout feature cannot work

properly (VBO_l = VBO_h).

If the brownout feature is not needed, it needs to tie the

BBA pin to the Vcc pin through a current limiting

resistor, 500KW~1MW. The BBA pin cannot be in

floating condition. If the brownout feature is disabled

with a tie up resistor, there is a limitation of the

capacitor CBK at the BBA pin. It is as below.

3.7.5 Action sequence at BBA pin

Since there are 3 functions at the same BBA pin;

brownout, extended blanking time and the auto-restart

enable, the actions of sequence are set as per the

below table in case of several features happens

simultaneously.

The top row of the table is the first happened feature

and the left column is the second happened feature.

For example,

Case 1:

The “Auto-restart enable” feature happened first and it

follows with the “Extended blanking time” feature. Then

the “Auto-restart enable” feature will continue to hold

and the “Extended blanking time” feature is ignored.

Case VBO_l VBO_h VBO_hys RBO1 RBO2

1 100V 143V 43V 4.3MW39KW

2 141V 169V 28V 2.8MW18KW

3 169V 225V 56V 5.6MW30KW

Vcc tie up resistor CBK_max

1 500KW0.47uF

2 1MW0.22uF

1st

2nd

Auto-restart

enable

Extended

blanking time

Brownout

Auto-restart

enable

Auto-restart

enable

Auto-restart

enable

Brownout

Extended

blanking time

Auto-restart

enable

Extended

blanking time

Brownout

Brownout Auto-restart

enable

Extended

blanking time

Brownout

CoolSET®-F3R80

ICE3AR0680JZ

Functional Description

Version 2.1a 21 11 Jan 2012

Case 2:

The “Extended blanking time” feature happened first

and it follows with the “Auto-restart enable” feature.

Then the “Auto-restart enable” feature will take the

priority and the “Extended blanking time” feature is

overridden.

Case 3:

The “Extended blanking time” feature happened first

and it follows with the “Brownout” feature. Then the

“Extended blanking time” feature will continue to work

until it ends. After that if the over load fault is removed

the “Brownout” feature takes the action.

Case 4:

The “Brownout” feature happened first and it follows

with the “Auto-restart enable” feature. Then the

“Brownout” feature will continue to work and the “Auto-

restart enable” feature is ignored.

One typical case happened is that the “Extended

blanking time” feature happened first and it follows with

the “Brownout” feature. If, however, the over load fault

is removed before the end of the extended blanking

time, the “Brownout” feature can take action only after

20ms buffer time.

CoolSET®-F3R80

ICE3AR0680JZ

Electrical Characteristics

Version 2.1a 22 11 Jan 2012

4 Electrical Characteristics

Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are

not violated.

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction

of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7

(VCC) is discharged before assembling the application circuit. Ta=25°C unless otherwise specified.

Parameter Symbol Limit Values Unit Remarks

min. max.

Drain Source Voltage VDS - 800 V

Pulse drain current, tplimited by Tjmax ID_Puls - 20 A

Avalanche energy, repetitive tAR limited by

max. Tj=150°C1)

1) Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f

EAR - 0.17 mJ

Avalanche current, repetitive tAR limited by

max. Tj=150°C

IAR - 4 A

VCC Supply Voltage VVCC -0.3 27 V

FBB Voltage VFBB -0.3 5.5 V

BBA Voltage VBBA -0.3 5.5 V

CS Voltage VCS -0.3 5.5 V

Junction Temperature Tj-40 150 °C Controller & CoolMOS®

Storage Temperature TS-55 150 °C

Thermal Resistance

Junction -Ambient

RthJA - 96 K/W

Soldering temperature, wavesoldering

only allowed at leads

Tsold - 260 °C 1.6mm (0.063in.) from

case for 10s

ESD Capability (incl. Drain Pin) VESD - 2 kV Human body model2)

2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kWseries resistor)

CoolSET®-F3R80

ICE3AR0680JZ

Electrical Characteristics

Version 2.1a 23 11 Jan 2012

4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

4.3 Characteristics

4.3.1 Supply Section

Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction

temperature range TJfrom – 25 °C to 125 °C. Typical values represent the median values, which are

related to 25°C. If not otherwise stated, a supply voltage of VCC = 17 V is assumed.

Parameter Symbol Limit Values Unit Remarks

min. max.

VCC Supply Voltage VVCC VVCCoff 25 V Max value limited due to Vcc OVP

Junction Temperature of

Controller

TjCon -25 130 °C Max value limited due to thermal

shut down of controller

Junction Temperature of

CoolMOS®

TjCoolMOS -25 150 °C

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Start Up Current IVCCstart - 200 300 mAVVCC =16V

VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V

IVCCcharge2 0.55 0.9 1.60 mA VVCC = 1V

IVCCcharge3 0.38 0.7 - mA VVCC =16V

Leakage Current of

Start Up Cell and CoolMOS®

IStartLeak - 0.2 50 mAVDrain = 650V

at Tj=100°C1)

1) The parameter is not subjected to production test - verified by design/characterization

Supply Current with

Inactive Gate IVCCsup1 - 1.9 3.2 mA

Supply Current with Active Gate IVCCsup2 - 5.7 7.8 mA IFBB = 0A

Supply Current in

Auto Restart Mode with Inactive

Gate

IVCCrestart - 320 - mAIFBB = 0A

Supply Current in Active Burst

Mode with Inactive Gate IVCCburst1 - 620 950 mAVFBB = 2.5V

IVCCburst2 - 620 950 mAVVCC = 11.5V, VFBB =

2.5V

VCC Turn-On Threshold

VCC Turn-Off Threshold

VCC Turn-On/Off Hysteresis

VVCCon

VVCCoff

VVCChys

16.0

9.8

17.0

10.5

6.5

18.0

11.2

CoolSET®-F3R80

ICE3AR0680JZ

Electrical Characteristics

Version 2.1a 24 11 Jan 2012

4.3.2 Internal Voltage Reference

4.3.3 PWM Section

4.3.4 Soft Start time

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FBB

IFBB = 0

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Fixed Oscillator Frequency fOSC1 87 100 113 kHz

fOSC2 92 100 108 kHz Tj= 25°C

Frequency Jittering Range fjitter -±4.0 -kHz Tj= 25°C

Frequency Jittering period Tjitter - 4.0 - ms Tj= 25°C

Max. Duty Cycle Dmax 0.70 0.75 0.80

Min. Duty Cycle Dmin 0 - - VFBB < 0.3V

PWM-OP Gain AV3.05 3.25 3.45

Voltage Ramp Offset VOffset-Ramp - 0.60 - V

VFBB Operating Range Min

Level

VFBmin - 0.7 - V

VFBB Operating Range Max

level

VFBmax - - 4.3 V CS=1V, limited by

Comparator C41)

1) The parameter is not subjected to production test - verified by design/characterization

FBB Pull-Up Resistor RFB 9.0 15.4 22.0 kW

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Soft Start time tSS - 10 - ms

CoolSET®-F3R80

ICE3AR0680JZ

Electrical Characteristics

Version 2.1a 25 11 Jan 2012

4.3.5 Control Unit

Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Brownout reference voltage for

comparator C14

VBO_ref 0.80 0.90 1.00 V

Blanking time voltage lower limit for

Comparator C3

VBKC3 0.80 0.90 1.00 V

Blanking time voltage upper limit for

Comparator C11

VBKC11 4.28 4.50 4.72 V

Over Load Limit for Comparator C4 VFBC4 4.28 4.50 4.72 V

Entry Burst select High level for

Comparator C19

VFBC19 4.28 4.50 4.72 V

Entry Burst select Low level for

Comparator C20

VFBC20 0.40 0.50 0.60 V

Active Burst Mode

Entry Level for

Comparator C5

10% Pin_max VFB_burst1 1.51 1.60 1.69 V < 7 counts

6.67% Pin_max VFB_burst2 1.34 1.42 1.50 V 8 ~ 39 counts

4.38% Pin_max VFB_burst3 1.20 1.27 1.34 V 40 ~ 191 counts

Active Burst Mode High Level for

Comparator C6a

VFBC6a 3.35 3.50 3.65 V In Active Burst Mode

Active Burst Mode Low Level for

Comparator C6b

VFBC6b 3.06 3.20 3.34 V

Active Burst Mode Level for

Comparator C13

VFBC13 3.85 4.00 4.15 V

Overvoltage Detection Limit for

Comparator C1

VVCCOVP1 19.5 20.5 21.5 V VFBB = 5V, during soft

start

Overvoltage Detection Limit for

Comparator C2

VVCCOVP2 25.0 25.5 26.3 V

Auto-restart enable reference voltage

for Comparator C9

VAE 0.25 0.40 0.45 V

Charging current for extended

blanking time

Ichg_EB 480 720 864 mA

Charging current for brownout Ichg_BO 9.0 10.0 10.8 mA

Thermal Shutdown1)

1) The parameter is not subjected to production test - verified by design/characterization. The thermal shutdown

temperature refers to the junction temperature of the controller.

TjSD 130 140 150 °C Controller

Hysteresis for thermal Shutdown1) TjSD_hys - 50 - °C

Built-in Blanking Time for Overload

Protection or enter Active Burst Mode

tBK - 20 - ms

Timer for entry burst select tEBS - 1 - ms

Spike Blanking Time for Auto-Restart

Protection

tSpike - 30 - ms

CoolSET®-F3R80

ICE3AR0680JZ

Electrical Characteristics

Version 2.1a 26 11 Jan 2012

and VVCCPD

4.3.6 Current Limiting

4.3.7 CoolMOS®Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Peak Current Limitation

(incl. Propagation Delay)

Vcsth 0.99 1.06 1.13 V dVsense / dt= 0.6V/ms

(Figure 20)

Peak Current

Limitation during

Active Burst Mode

20% Pin_max Vcsth_burst1 0.39 0.45 0.51 V < 7 counts

13.3% Pin_max Vcsth_burst2 0.32 0.37 0.44 V 8 ~ 39 counts

9.6% Pin_max Vcsth_burst3 0.25 0.31 0.37 V 40 ~ 191 counts

Leading Edge

Blanking

Normal mode tLEB_normal - 220 - ns

Burst mode tLEB_burst - 180 - ns

CS Input Bias Current ICSbias -1.5 -0.2 - mAVCS =0V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Drain Source Breakdown Voltage V(BR)DSS 800

870

Tj= 25°C

Tj= 110°C1)

Drain Source On-Resistance RDSon -

0.62

1.36

1.67

0.71

1.58

1.93

Tj= 25°C

Tj=125°C1)

Tj=150°C1)

at ID= 2.2A

1) The parameter is not subjected to production test - verified by design/characterization

Effective output capacitance, energy

Co(er) - 40.9 - pF VDS = 0V to 480V

Rise Time trise - 302)

2) Measured in a Typical Flyback Converter Application

- ns

Fall Time tfall - 302) - ns

CoolSET®-F3R80

ICE3AR0680JZ

CoolMOS®Performance Characteristic

Version 2.1a 27 11 Jan 2012

5 CoolMOS®Performance Characteristic

Figure 33 Safe Operating Area (SOA) curve for ICE3AR0680JZ

Figure 34 SOA temperature derating coefficient curve

CoolSET®-F3R80

ICE3AR0680JZ

CoolMOS®Performance Characteristic

Version 2.1a 28 11 Jan 2012

Figure 35 Power dissipation; Ptot=f(Ta)

Figure 36 Drain-source breakdown voltage; VBR(DSS)=f(Tj), ID=0.25mA

CoolSET®-F3R80

ICE3AR0680JZ

Input Power Curve

Version 2.1a 29 11 Jan 2012

6 Input Power Curve

Two input power curves giving the typical input power versus ambient temperature are showed below;

Vin=85Vac~265Vac (Figure 37) and Vin=230Vac+/-15% (Figure 38). The curves are derived based on a typical

discontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum secondary

to primary reflected voltage (higher priority). The calculation is based on no copper area as heatsink for the device.

The input power already includes the power loss at input common mode choke, bridge rectifier and the

CoolMOS.The device saturation current (ID_Puls @ Tj=125°C) is also considered.

To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient

temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 37),

operating temperature is 50°C, estimated efficiency is 85%, then the estimated output power is 44W (52W * 85%).

Figure 37 Input power curve Vin=85~265Vac; Pin=f(Ta)

Figure 38 Input power curve Vin=230Vac+/-15%; Pin=f(Ta)

CoolSET®-F3R80

ICE3AR0680JZ

Outline Dimension

Version 2.1a 30 11 Jan 2012

7Outline Dimension

Figure 39 PG-DIP-7 (Pb-free lead plating Plastic Dual-in-Line Outline)

PG-DIP-7

(Plastic Dual In-Line Outline)

CoolSET®-F3R80

ICE3AR0680JZ

Marking

Version 2.1a 31 11 Jan 2012

8 Marking

Figure 40 Marking for ICE3AR0680JZ

Marking

CoolSET®-F3R80

ICE3AR0680JZ

Schematic for recommended PCB layout

Version 2.1a 32 11 Jan 2012

9 Schematic for recommended PCB layout

Figure 41 Schematic for recommended PCB layout

General guideline for PCB layout design using F3 CoolSET (refer to Figure 41):

1. “Star Ground “at bulk capacitor ground, C11:

“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11

separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device

effectively. The primary DC grounds include the followings.

a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.

b. DC ground of the current sense resistor, R12

c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of

IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.

d. DC ground from bridge rectifier, BR1

e. DC ground from the bridging Y-capacitor, C4

2. High voltage traces clearance:

High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.

a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm

b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm

3. Filter capacitor close to the controller ground:

Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin

as possible so as to reduce the switching noise coupled into the controller.

Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 41):

1. Add spark gap

Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated

charge during surge test through the sharp point of the saw-tooth plate.

a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:

Gap separation is around 1.5mm (no safety concern)

CoolSET®-F3R80

ICE3AR0680JZ

Schematic for recommended PCB layout

Version 2.1a 33 11 Jan 2012

b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.

230Vac input voltage application, the gap separation is around 5.5mm

115Vac input voltage application, the gap separation is around 3mm

2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input

3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:

The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and

reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.

The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the

sensitive components such as the primary controller, IC11.

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