Philips Semiconductors Product specification
74LV123
Dual retriggerable monostable multivibrator
with reset
2
1998 Apr 28 853–1911 19290
FEATURES
•Optimized for Low V oltage applications: 1.0 to 5.5V
•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C
•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C
•DC triggered from active HIGH or active LOW inputs
•Retriggerable for very long pulses up to 100% duty factor
•Direct reset terminates output pulses
•Schmitt-trigger action on all inputs except for the reset input
•Output capability: standard (except for nREXT/CEXT)
•ICC category: MSI
DESCRIPTION
The 74LV123 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT123.
The 74LV123 is a dual retriggerable monostable multivibrator with
output pulse width control by three methods. The basic pulse time is
programmed by selection of an external resistor (REXT) and
capacitor (CEXT). They are normally connected as shown in
Figure 1. Once triggered, the basic output pulse width may be
extended by retriggering the gated active LOW-going edge input
(nA) or the active HIGH-going edge input (nB). By repeating this
process, the output pulse period (nQ = HIGH, nQ = LOW) can be
made as long as desired. Alternatively, an output delay can be
terminated at any time by a LOW-going edge on input nRD, which
also inhibits the triggering. Figures 1 and 2 illustrate pulse control by
retriggering and early reset. The basic output pulse width is
essentially determined by the values of the external timing
components REXT and CEXT. For pulse width when CEXT <10000pF,
see Figure 5. When CEXT 10,000pF, the typical output pulse
width is defined as: tW = 0.45 REXT CEXT (typ.), where
tW= pulse width in ns; REXT = external resistor in KΩ; and
CEXT = external capacitor in pF. Schmitt-trigger action in the nA and
nB inputs makes the circuit highly tolerant of slower input rise and
fall times.
QUICK REFERENCE DATA
GND = 0V ; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH Propagation delay
nA, nB to nQ, nQ
nRD to nQ, nQ
CL = 15pF
VCC = 3.3V
REXT = 5KΩ
CEXT = 0pF 25
20 ns
ns
CIInput capacitance 3.5 pF
CPD Power dissipation capacitance per monost-
able VCC = 3.3V, VI = GND to VCC160 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL VCC2 fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C74LV123 N 74LV123 N SOT38-1
16-Pin Plastic SO –40°C to +125°C74LV123 D 74LV123 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C74LV123 DB 74LV123 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C74LV123 PW 74LV123PW DH SOT403-1