EM78P142 - ELAN Microelectronics - Datasheet.Directory

EM78P142

8-Bit Microprocessor

with OTP ROM

Product

Specification

DOC. VERSION 1.0

ELAN MICROELECTRONICS CORP.

January 2008

T radem ark Acknowledgments:

IBM is a registered trademark and PS/2 is a trademark of IBM.

Windows is a trademark of Microsoft Corporation.

ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.

Printed in Taiwan

The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no

responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics

makes no commitment to update, or to keep current the information and material contained in this specification.

Such information and material may change to conform to each confirmed order.

In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omis sions, or

other inaccuracies in the information or material con tained in this specification. ELAN Microelectronics shall not

be liable for direct, in direct, special in cident al, or consequen tial damages arising from the use of s uch inf ormation

or material.

The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and

may be used or copied only in accordance with the terms of such agreement.

ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of

ELAN Microelectronics product in such applications is not supported and is prohibited.

NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY

ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELE CTRONICS.

ELAN MICROELECTRONICS CORPORATION

Headquarters:

No. 12, Innovat ion Ro ad 1

Hsinchu Science Park

Hsinchu, Taiwan 308

Tel: +886 3 563- 9 97 7

Fax: +886 3 563-996 6

http://www.emc.com.tw

Hong Kong:

Elan (HK) Microelectronics

Corporation, Ltd.

Flat A, 19F., World Tech Centre

95 How Ming Street, Kwun Tong

Kowloon, HONG KONG

Tel: +852 2723-3376

Fax: +852 2723-7780

elanhk@emc.com.hk

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Elan Information

Technology Group (USA)

P.O. Box 601

Cupertino, CA 95015

USA

Tel: +1 408 366-8225

Fax: +1 408 366-8225

Shenzhen:

Elan Mi croele ctroni cs

Shenzhen, Ltd.

3F, SSMEC Bldg., Gaoxin S. Ave. I

Shenzhen Hi-tech Industrial Park

(South Area), Shenzhen

CHINA 518057

Tel: +86 755 2601 -0565

Fax: +8 6 755 26 01-0500

Shanghai:

Elan Microelectronics

Shanghai, Ltd.

#23, Zone 115, Lane 572, Bibo Rd.

Zhangj iang Hi-Tech Park

Shanghai, CHINA 201203

Tel: +86 21 5080-3866

Fax: +86 21 5080-4600

Contents

Product Specification (V1.0) 01.25.2008 • iii

Contents

1 General Description................................................................................................1

2 Features...................................................................................................................1

3 Pin Assignment .......................................................................................................2

4 Pin Description........................................................................................................3

4.1 EM78P142SS10 ............................................................................................... 3

5 Block Diagram.........................................................................................................4

6 Function Description ..............................................................................................5

6.1 Operational Registers....................................................................................... 5

6.1.1 R0 (Indirect Address Register) .......................................................................... 5

6.1.2 R1 (Time Clock).................................................................................................. 5

6.1.3 R2 (Program Counter) and Stack ....................................................................... 5

6.1.3.1 Data Memory Configuration................................................................. 7

6.1.4 R3 (Status Register) ........................................................................................... 8

6.1.5 R4 (RAM Select Register) .................................................................................. 8

6.1.6 R5 ~ R6 (Port 5 ~ Port 6).................................................................................... 8

6.1.7 R7 (Port 7) .......................................................................................................... 9

6.1.8 R8 (AISR: ADC Input Select Register) ............................................................. 10

6.1.9 R9 (ADCON: ADC Control Register) ................................................................ 12

6.1.10 RA (ADOC: ADC Offset Calibration Register) .................................................. 13

6.1.11 RB (ADDATA: Converted Value of ADC) .......................................................... 13

6.1.12 RC (ADDATA1H: Converted Value of ADC) ..................................................... 13

6.1.13 RD (ADDATA1L: Converted Value of ADC) ...................................................... 14

6.1.14 RE (Interrupt Status 2 and Wake-up Control Register) .................................... 14

6.1.15 RF (Interrupt Status 2 Register)........................................................................ 15

6.1.16 R10 ~ R3F ........................................................................................................ 15

6.2 Special Purpose Registers.............................................................................. 16

6.2.1 A (Accumulator) ................................................................................................ 16

6.2.2 CONT (Control Register) .................................................................................. 16

6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)...................................................... 16

6.2.4 IOC80 (TCCA Control Register) ....................................................................... 17

6.2.5 IOC90 (TCCB and TCCC Control Register) ..................................................... 17

6.2.6 IOCA0 (IR and TCCC Scale Control Register)................................................. 18

6.2.7 IOCB0 (Pull-down Control Register)................................................................. 19

6.2.8 IOCC0 (Open-drain Control Register) .............................................................. 19

6.2.9 IOCD0 (Pull-high Control Register) .................................................................. 19

6.2.10 IOCE0 (WDT Control Register and Interrupt Mask Register 2)........................ 20

6.2.11 IOCF0 (Interrupt Mask Register) ...................................................................... 21

6.2.12 IOC51 (TCCA Timer) ........................................................................................ 21

6.2.13 IOC61 (TCCB Timer) ........................................................................................ 22

6.2.14 IOC71 (TCCBH/MSB Timer)............................................................................. 22

Contents

iv • Product Specification (V1.0) 01.25.2008

6.2.15 IOC81 (TCCC Timer)........................................................................................ 22

6.2.16 IOC91 (Low-Time Register).............................................................................. 23

6.2.17 IOCA1 (High Time Register)............................................................................. 23

6.2.18 IOCB1 High/Low Time Scale Control Register)................................................ 23

6.2.19 IOCC1 (TCC Prescaler Timer).......................................................................... 24

6.2.20 IOCD1 (LVD Control Register) ......................................................................... 25

6.2.21 IOCE1 (Output Sink Select Control Register) .................................................. 26

6.2.22 IOCF1 (Pull-high Control Register)................................................................... 27

6.3 TCC/WDT and Prescaler ................................................................................ 27

6.4 I/O Ports ......................................................................................................... 28

6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function ............................. 30

6.5 Reset and Wake-up ........................................................................................ 31

6.5.1 Reset and Wake-up Operation ......................................................................... 31

6.5.1.1 Wake-up and Interrupt Modes Operation Summary.......................... 33

6.5.1.2 Register Initial Values after Reset ..................................................... 38

6.5.1.3 Controller Reset Block Diagram ........................................................ 43

6.5.2 The T and P Status under Status Register ....................................................... 43

6.6 Interrupt .......................................................................................................... 44

6.7 Analog-To-Digital Converter (ADC) ................................................................. 46

6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)............................... 46

6.7.1.1 R8 (AISR: ADC Input Select Register) .............................................. 46

6.7.1.2 R9 (ADCON: ADC Control Register) ................................................. 47

6.7.1.3 RA (ADOC: AD Offset Calibration Register) ...................................... 48

6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) ............. 49

6.7.3 ADC Sampling Time ......................................................................................... 49

6.7.4 AD Conversion Time......................................................................................... 49

6.7.5 ADC Operation during Sleep Mode.................................................................. 49

6.7.6 Programming Process/Considerations ............................................................. 50

6.7.6.1 Programming Process ....................................................................... 50

6.7.6.2 Sample Demo Programs ................................................................... 51

6.8 Infrared Remote Control Application/PWM Waveform Generation .................. 53

6.8.1 Overview........................................................................................................... 53

6.8.2 Function Description ......................................................................................... 54

6.8.3 Programming the Related Registers ................................................................ 56

6.9 Timer .............................................................................................................. 57

6.9.1 Overview........................................................................................................... 57

6.9.2 Function Description ......................................................................................... 57

6.9.3 Programming the Related Registers ................................................................ 59

6.10 Oscillator ........................................................................................................ 60

6.10.1 Oscillator Modes ............................................................................................... 60

6.10.2 Crystal Oscillator/Ceramic Resonators (Crystal).............................................. 61

6.10.3 External RC Oscillator Mode ............................................................................ 64

6.10.4 Internal RC Oscillator Mode ............................................................................. 65

Contents

Product Specification (V1 .0) 01.25.2008 • v

6.11 Power-on Considerations................................................................................ 66

6.11.1 Programmable WDT Time-out Period .............................................................. 66

6.11.2 External Power-on Reset Circuit ...................................................................... 66

6.11.3 Residual Voltage Protection ............................................................................. 67

6.12 Code Option ................................................................................................... 68

6.12.1 Code Option Register (Word 0) ........................................................................ 68

6.12.2 Code Option Register (Word 1) ........................................................................ 70

6.12.3 Customer ID Register (Word 2) ........................................................................ 71

6.13 Low Voltage Detector/Low Voltage Reset ....................................................... 72

6.13.1 Low Voltage Reset............................................................................................ 72

6.13.2 Low Voltage Detector........................................................................................ 72

6.13.2.1 IOCD1 (LVD Control Register) .......................................................... 72

6.13.2.2 RE (Interrupt Status 2 & Wake-up Control Register) ......................... 73

6.13.3 Programming Process ...................................................................................... 74

6.14 Instruction Set................................................................................................. 75

7 Absolute Maximum Ratings..................................................................................77

8 DC Electrical Characteristics................................................................................77

8.1 AD Converter Characteristic ........................................................................... 79

8.2 Device Characteristics .................................................................................... 80

9 AC Electrical Characteristic..................................................................................81

10 Timing Diagrams...................................................................................................82

APPENDIX

A Package Type ........................................................................................................83

B Packaging Configuration......................................................................................84

B.1 EM78P142SS10 ............................................................................................. 84

C Quality Assurance and Reliability........................................................................85

C.1 Address Trap Detect....................................................................................... 85

D How to Use the ICE 341N......................................................................................86

E Comparison between V-Package and U-Package Version..................................89

EM78P142-V Package ............................................................................................ 89

EM78P142-U Package............................................................................................ 89

Contents

vi • Product Specification (V1.0) 01.25.2008

Specification Revision History

Doc. Version Revision Description Date

1.0 Initial released version 2008/01/25

Item EM78P142

Level Voltage Reset 4.0V, 3.5V, 2.4V

Crystal mode

Operating frequency range at 0°C~ 70°C

DC ~ 16MHz, 4.5V

DC ~ 8MHz, 3.0V

DC ~ 4MHz, 2.1V

IRC mode wake-up time

( Sleep → Normal )

Condition: 5V, 4MHz

10µs

Code Option Added a Code Option NRM

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 1

(This specification is subject to change without further notice)

1 General Description

The EM78P142 is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology.

The series have an on-chip 2K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a

protection bit to prevent intrusion of user’s OTP memory code. Three Code option bits are also available to meet user’s

requirements.

With enhanced OTP-ROM features, the EM78P142 provide a convenient way of developing and verifying user’s

programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development

and programming tools. User can avail of the ELAN Writer to easily program his development code.

2 Features

 CPU configuration

• 2K×13 bits on-chip ROM

• 80×8 bits on-chip registers (SRAM)

• 8-level stacks for subroutine nesting

• 4 programmable Level Voltage Detector

(LVD) : 4.5V, 4.0V, 3.3V, 2.2V

• 3 programmable Level Voltage Reset

(LVR) : 4.0V, 3.5V, 2.4V

• Less than 1.5 mA at 5V/4MHz

• Typically 15 µA, at 3V/32kHz

• Typically 2 µA, during sleep mode

 I/O port configuration

• 3 bidirectional I/O ports: P5, P6, P7

• 8 I/O pins

• Wake-up port : P5

• 5 programmable pull-down I/O pins

• 6 programmable pull-high I/O pins

• 1 programmable open-drain I/O pins

 Operating voltage range:

• 2.1V~5.5V at 0°C~70°C (commercial)

• 2.3V~5.5V at -40°C~85°C (industrial)

 Operating frequency range (base on 2 clocks):

• Crystal mode: DC ~ 16MHz, 4.5V;

DC ~ 8MHz, 3V; DC ~ 4MHz, 2.1V

• ERC mode: DC ~ 16MHz, 4.5V;

DC ~ 125ns inst. cycle, 4.5V

DC ~ 8MHz, 3V; DC ~ 250ns inst. cycle, 3V

• IRC mode

Oscillation mode: 16MHz, 4MHz, 1MHz, 455kHz

Drift Rate

Internal RC

Frequency Temperature

(-40°C~85°C)Voltage

(2.3V~5.5V) Process Total

4 MHz ±5% ±5% ±4% ±14%

16 MHz ±5% ±5% ±4% ±14%

1 MHz ±5% ±5% ±4% ±14%

455kHz ±5% ±5% ±4% ±14%

 All the four main frequencies can be trimmed by

programming with four calibrated bits in the ICE341N

Simulator. OTP is auto trimmed by ELAN Writer.

 Fast set-up time requires only 0.8ms (VDD: 5V

Crystal: 4MHz, C1/C2: 30pF) in HXT2 mode and 10µs

in IRC mode (VDD: 5V, IRC: 4 MHz)

 Peripheral configuration

• Easily implemented IR (infrared remote control)

• 8-bit real time clock (TCC) with overflow interrupt

• 8-bit real time clock (TCCA, TCCC) and 16-bit real

time clock (TCCB) with overflow interrupt

• 7-bit multi-channel Analog-to-Digital Converter with

12-bit resolution in Vref mode

 Five available interrupts

• TCC, TCCA, TCCB, TCCC overflow interrupt

• Input-port status changed interrupt (wake up from

sleep mode)

• ADC completion interrupt

• IR/PWM period match completion

• Low voltage detect (LVD) interrupt

 Special Features:

• Programmable free running Watchdog Timer

(4.5 ms : 18 ms)

• Power saving Sleep mode

• Selectable Oscillation mode

• Power-on voltage detector available (1.7V ± 0.1V)

• High EFT immunity (better performance at 4 MHz or

below)

 Package Type:

• 10 pin SSOP 150mil : EM78P142SS10J/S

Note: Green products do not contain hazardous .substances.

EM78P142

8-Bit Microprocessor with OTP ROM

2 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

3 Pin Assignment

Figure 3-1 EM78P142SS10

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 3

(This specification is subject to change without further notice)

4 Pin Description

4.1 EM78P142SS10

Symbol Pin No. Type Function

P50~P53

P55 1~3, 9~10 I/O

5-bit General purpose input/output pins

Pull-high/Pull-down Function

Wake up from Sleep/Idle mode when the pin status

changes

Default value at power-on reset

P67 6 I/O

1-bit General purpose input/output pin

Pull-high/Open-drain Function

Default value at power-on reset

P70~P71 8, 4 I/O

2-bit General purpose input/output pins

Default value at power-on reset

When P71 is used as output function, it is an open drain

ADC0~ADC6 1~3, 6

8~10 I

7-bit channel Analog-to-Digital Converter with 12-bit

resolution.

Defined by ADCON (R9)<1:0>

/RESET 4 I

If it remains at logic low, the device will be reset

Wake-up from Sleep/Idle mode when pin status

changes

Voltage on /RESET must not exceed Vdd during normal

mode

OSCI 9 I

Crystal type: Crystal input terminal.

RC type: RC oscillator input pin

OSCO 8 O

Crystal type: Output terminal for crystal oscillator.

RC type: Clock output with a duration of one instruction

cycle time.

External clock signal input.

VDD 7 –

Power supply

VSS 5 –

Ground

EM78P142

8-Bit Microprocessor with OTP ROM

4 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

5 Block Diagram

Figure 5 EM78P142 Block Diagram

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 5

(This specification is subject to change without further notice)

6 Function Description

6.1 Operational Registers

6.1.1 R0 (Indirect Address Register)

R0 is not a physically implemented register. It is used as an indirect address pointer.

Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM

Select Register (R4).

6.1.2 R1 (Time Clock)

 Incremented by the instruction cycle clock.

 Writable and readable as any other registers.

 The TCC prescaler counter (IOCC1) is assigned to TCC

 The contents of the IOCC1 register is cleared whenever –

• a value is written to the TCC register.

• a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of the CONT register)

• there is power-on reset, /RESET, or WDT time out reset.

6.1.3 R2 (Program Counter) and Stack

A7 ~ A0

On-chip Program

Memory

000H

7FFH

003H

Hardware Interrupt Vector

User Memory Space

Reset Vector

A9 A8 A10

Stack Level 1

Stack Level 3

Stack Level 2

Stack Level 4

Stack Level 5

CALL

0 PAGE0 0000~03FF

1 PAGE1 0400~07FF

RET

RETL

RETI

Stack Level 6

Stack Level 7

Stack Level 8

021H

Figure 6-1 Program Counter Organization

 R2 and hardware stacks are 11-bit wide. The structure is depicted in the table

under Section 6.1.3.1 Data Memory Configuration.

 The configuration structure generates 2K×13 bits on-chip ROM addresses to the

relative programming instruction codes. One program page is 1024 words long.

 The contents of R2 are all set to "0"s when a reset condition occurs.

EM78P142

8-Bit Microprocessor with OTP ROM

6 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

 "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,

"JMP" allows PC to jump to any location within a page.

 "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into

the stack. Thus, the subroutine entry address can be located anywhere within a

page.

 "LJMP" instruction allows direct loading of the program counter bits (A0~A10).

Therefore, "LJMP" allows PC to jump to any location within 2K (211).

 "LCALL" instruction loads the program counter bits (A0 ~A10), and then PC+1 is

pushed into the stack. Thus, the subroutine entry address can be located

anywhere within 2K (211)

 "RET" ("RETL k", "RETI") instruction loads the program counter with the contents

of the top of stack.

 "ADD R2, A" allows a relative address to be added to the current PC, and the ninth

and above bits of the PC will increase progressively.

 "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of

the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.

 Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC

R2, 6", etc.) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain

unchanged.

 All instructions are single instruction cycle (fclk/2) except “LCALL” and “LJMP”

instructions. The “LCALL” and “LJMP” instructions need two instructions cycle.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 7

(This specification is subject to change without further notice)

6.1.3.1 Data Memory Configuration

Address R Page Registers IOCX0 Page Registers

00 R0 (Indirect Addressing Register) Reserve

01 R1 (Timer Clock)

02 R2 (Program Counter) Reserve

03 R3 (Status Register) Reserve

04 R4 (RAM Select Register) Reserve

05 R5 (Port 5) IOC50 (I/O Port Control Register)

06 R6 (Port 6) IOC60 (I/O Port Control Register)

07 R7 (Port 7) IOC70 (I/O Port Control Register)

08 (ADC Input Select Register

0B IOCB0 (Pull-down Control

0F IOCF0 (Interrupt Mask Register 1)

︰

General Registers

：

Bank 0 Bank 1

IOCX1 Page Registers

IOC80 (TCCA Control Register)

IOC90 (TCCB and TCCC

Control Register)

IOCA0 (IR and TCCC Scale

Control Register)

IOCC0 (Open-drain Control

IOCD0 (Pull-high Control Register)

IOCE0 (WDT Control Register and

Interrupt Mask Register 2)

IOC51 (TCCA Timer)

IOC61 (TCCB LSB Timer)

IOC71 (TCCB HSB Timer)

IOC81 (TCCC Timer)

IOC91 (Low-Time Register)

IOCA1 (High-Time Register)

IOCB1 (High-Time and Low-Time

Scale Control Register)

Reserve

(LVD Control Register)

(High Output Sink Current)

(Pull-high Control Register)

(ADC Control Register)

(ADC Offset Calibration

(Converted value

AD11~AD4 of ADC)

(Converted value

AD11~AD8 of ADC)

(Converted value

AD7~AD0 of ADC)

(Interrupt Status 2 and

Wake-up Control Register

(Interrupt Status Register 1)

IOCC1 (TCC Prescaler Control)

IOCD1

IOCE1

IOCF1

Reserve

EM78P142

8-Bit Microprocessor with OTP ROM

8 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.1.4 R3 (Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RST IOCS - T P Z DC C

Bit 7 (RST): Bit of reset type

Set to “1” if wake-up from sleep on pin change, comparator status

change, or AD conversion completed. Set to “0” if wake-up from other

reset types.

Bit 6 (IOCS): Select the Segment of IO control register

0 = Segment 0 (IOC50 ~ IOCF0) selected

1 = Segment 1 (IOC51 ~ IOCC1) selected

Bit 5: Not used (reserved)

Bit 4 (T): Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during

power on, and reset to “0” by WDT time-out (for more details see Section

6.5.2, The T and P Status under Status Register).

Bit 3 (P): Power-down bit. Set to “1” during power-on or by a "WDTC" command

and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P

Status under Status Register for more details).

Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is

zero.

Bit 1 (DC): Auxiliary carry flag

Bit 0 (C): Carry flag

6.1.5 R4 (RAM Select Register)

Bit 7: Set to “0” all the time

Bit 6: Used to select Bank 0 or Bank 1 of the register

Bits 5~0: Used to select a register (Address: 00~0F, 10~3F) in indirect addressing

mode.

See table under Section 6.1.3.1 Data Memory Configuration.

6.1.6 R5 ~ R6 (Port 5 ~ Port 6)

R5 & R6 are I/O registers.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 9

(This specification is subject to change without further notice)

6.1.7 R7 (Port 7)

Bit 7 6 5 4 3 2 1 0

EM78P142 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ I/O I/O

ICE341N C3 C2 C1 C0 RCM1 RCM0 I/O I/O

Note: R7 is an I/O register.

Bit 7 ~ Bit 2:

[With EM78P142]: Unimplemented, read as ‘0’.

[With Simulator (C3~C0, RCM1, and RCM0)]: IRC calibration bits in IRC oscillator

mode. In IRC oscillator mode of ICE341N simulator, these

are the IRC mode selection bits and IRC calibration bits.

Bit 7 ~ Bit 4 (C3 ~ C0): Calibrator of internal RC mode

C3 C2 C1 C0 Frequency (MHz)

0 0 0 0 (1-36%) × F

0 0 0 1 (1-31.5%) × F

0 0 1 0 (1-27%) × F

0 0 1 1 (1-22.5%) × F

0 1 0 0 (1-18%) × F

0 1 0 1 (1-13.5%) × F

0 1 1 0 (1-9%) × F

0 1 1 1 (1-4.5%) × F

1 1 1 1 F (default)

1 1 1 0 (1+4.5%) × F

1 1 0 1 (1+9%) × F

1 1 0 0 (1+135%) × F

1 0 1 1 (1+18%) × F

1 0 1 0 (1+22.5%) × F

1 0 0 1 (1+27%) × F

1 0 0 0 (1+31.5%) × F

Note: 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode.

Hence, they are shown for reference only. Definite values depend on the actual process.

2. Similar way of calculation is also applicable for low frequency mode.

Bit 3 and Bit 2 (RCM1, RCM0): IRC mode selection bits

RCM 1 RCM 0 Frequency (MHz)

1 1 4 (default)

1 0 16

0 1 1

0 0 455kHz

EM78P142

8-Bit Microprocessor with OTP ROM

10 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.1.8 R8 (AISR: ADC Input Selec t Register)

The AISR register individually defines the I/O Port as analog input or as digital I/O.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

‘0’ ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

Bit 7: This bit must be set to “0” all the time.

Bit 6 (ADE6): AD converter enable bit of P55 pin

0 = Disable ADC6, P55 functions as I/O pin

1 = Enable ADC6 to function as analog input pin

Bit 5 (ADE5): AD converter enable bit of P70 pin

0 = Disable ADC5, P70 functions as I/O pin

1 = Enable ADC5 to function as analog input pin

Bit 4 (ADE4): AD converter enable bit of P67 pin

0 = Disable ADC4, P67 functions as I/O pin

1 = Enable ADC4 to function as analog input pin

Bit 3 (ADE3): AD converter enable bit of P53 pin

0 = Disable ADC3, P53 functions as I/O pin

1 = Enable ADC3 to function as analog input pin

Bit 2 (ADE2): AD converter enable bit of P52 pin

0 = Disable ADC2, P52 functions as I/O pin

1 = Enable ADC2 to function as analog input pin

Bit 1 (ADE1): AD converter enable bit of P51 pin

0 = Disable ADC1, P51 functions as I/O pin

1 = Enable ADC1 to function as analog input pin

Bit 0 (ADE0): AD converter enable bit of P50 pin

0 = Disable ADC0, P50 functions as I/O pin

1 = Enable ADC0 to function as analog input pin

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 11

(This specification is subject to change without further notice)

NOTE

The P55/OSCI/ADC6 pin cannot be applied to OSCI and ADC6 at the same time.

If P55/OSCI/ADC6 functions as OSCI oscillator input pin, then ADE6 bit for R8 must

be ”0” and ADIS2~0 do not select “ 1 10” . The P55/OS CI/ADC6 pin priority is as f oll ows:

The P70/OSCO/ADC5 pin cannot be applied to OSCO and ADC5 at the same time.

If P70/OSCO/AD C5 acts as O SCO oscilla tor input pi n, then ADE5 bit for R8 must be ” 0”

and ADIS2~0 do not select “101”. The P70/OSCO/ADC5 pin priority is as follows:

The P67/IR OUT/ADC4 pin cannot be applied to IR OUT and ADC4 at the same time.

If P67/IR OUT/ADC4 functions as ADC4 analog input pin, then IROUTE bit for IOCA0

must be “0”..

If P67/IR OUT/ADC4 functions as IR OUT analog in put pin, t hen ADE4 bit for R 8 must

be ”0” and ADIS2~0 do not select “100”.

The P67/IR OUT/ADC4 pin priority is as follows:

P55/OSCI/ADC6 Pin Priority

High Medium Low

OSCI ADC6 P55

P67/IR OUT/ADC4 Pin Priority

High Medium Low

ADC4 IR OUT P67

P70/OSCO/ADC5 Pin Priority

High Medium Low

OSCO ADC5 P70

EM78P142

8-Bit Microprocessor with OTP ROM

12 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.1.9 R9 (ADCON: ADC Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

“0” CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0

Bit 7: This bit must be set to “0” all the time

Bit 6 and Bit 5 (CKR1 and CKR0): The prescaler of the ADC oscillator clock rate

00 = 1: 16 (default value)

01 = 1: 4

10 = 1: 64

11 = 1: 8

CPUS CKR1:CKR0 Operation Mode Max. Operation Frequency

1 00 Fosc/16 4 MHz

1 01 Fosc/4 1 MHz

1 10 Fosc/64 16 MHz

1 11 Fosc/8 2 MHz

0 ×× Internal RC −

Bit 4 (ADRUN): ADC starts to RUN.

1 = an AD conversion is started. This bit can be set by software

0 = Reset upon completion of the conversion. This bit cannot be

reset through software

Bit 3 (ADPD): ADC Power-down mode

1 = ADC is operating

0 = Switch off the resistor reference to save power even while the

CPU is operating.

Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select

000 = ADIN0/P50

001 = ADIN1/P51

010 = ADIN2/P52

011 = ADIN3/P53

100 = ADIN4/P67

101 = ADIN5/P70

110 = ADIN6/P55

111 = not used

These bits can only be changed when the ADIF bit and the ADRUN bit are both low.

See Section 6.1.14, RE (Interrupt Status 2 and Wake-up Control Register).

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 13

(This specification is subject to change without further notice)

6.1.10 RA (ADOC: ADC Offset Calibration Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CALI SIGN VOF[2] VOF[1] VOF[0] “0” “0” “0”

Bit 7 (CALI): Calibration enable bit for ADC offset

0 = disable Calibration

1 = enable Calibration

Bit 6 (SIGN): Polarity bit of offset voltage

0 = Negative voltage

1 = Positive voltage

Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits

VOF[2] VOF[1] VOF[0] EM78P142 ICE341

0 0 0 0LSB 0LSB

0 0 1 2LSB 2LSB

0 1 0 4LSB 4LSB

0 1 1 6LSB 6LSB

1 0 0 8LSB 8LSB

1 0 1 10LSB 10LSB

1 1 0 12LSB 12LSB

1 1 1 14LSB 14LSB

Bit 2 ~ Bit 0: Unimplemented, read as ‘0’

6.1.11 RB (ADDATA: Converted Value of ADC)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4

When the AD conversion is completed, the result is loaded into the ADDATA. The

ADRUN bit is cleared and the ADIF is set. See Section 6.1.14, RE (Interrupt Status 2

and Wake-up Control Register).

RB is read only.

6.1.12 RC (ADDATA1H: Converted Value of ADC)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

“0” “0” “0” “0” AD11 AD10 AD9 AD8

When the AD conversion is completed, the result is loaded into the ADDATA1H. The

ADRUN bit is cleared and the ADIF is set. See Section 6.1.14, RE (Interrupt Status 2

and Wake-up Control Register).

RC is read only.

EM78P142

8-Bit Microprocessor with OTP ROM

14 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.1.13 RD (ADDATA1L: Converted Value of ADC)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

When the AD conversion is completed, the result is loaded into the ADDATA1L. The

ADRUN bit is cleared and the ADIF is set. See Section 6.1.14, RE (Interrupt Status 2

and Wake-up Control Register).

RD is read only

6.1.14 RE (Interrupt Status 2 and Wake-up Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

/LVD LVDIF ADIF “0” ADWE “0” ICWE LVDWE

Note: 1. RE <6, 5> can be cleared by instruction but cannot be set.

2. IOCE0 is the interrupt mask register.

3. Reading RE will result to “logic AND” of the RE and IOCE0.

Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD

pin voltage is lower than LVD voltage interrupt level (selected by

LVD1 and LVD0), this bit will be cleared.

0 = low voltage is detected

1 = low voltage is not detected or LVD function is disabled

Bit 6 (LVDIF): Low Voltage Detector interrupt flag

LVDIF is reset to “0” by software.

Bit 5 (ADIF): Interrupt flag for analog to digital conversion. Set when AD

conversion is completed. Reset by software.

0 = no interrupt occurs

1 = interrupt request

Bit 4: This bit must be set to “0” all the time.

Bit 3 (ADWE): ADC wake-up enable bit

0 = Disable ADC wake-up

1 = Enable ADC wake-up

When AD Conversion enters sleep/idle mode, this bit must be set to “Enable“.

Bit 2: This bit must be set to “0” all the time.

Bit 1 (ICWE): Port 5 input change to wake-up status enable bit

0 = Disable Port 5 input change to wake-up status

1 = Enable Port 5 input change to wake-up status

When Port 5 change enters sleep/idle mode, this bit must be set to “Enable“.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 15

(This specification is subject to change without further notice)

Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit

0 = Disable Low Voltage Detect wake-up

1 = Enable Low Voltage Detect wake-up

When the Low Voltage Detect is used to enter an interrupt vector or to

wake-up the IC from sleep/idle with Low Voltage Detect running, the

LVDWE bit must be set to “Enable“.

6.1.15 RF (Interrupt Status 2 Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF “0” ICIF TCIF

Note: 1. “1” means there is interrupt request, “0”

2. RF can be cleared by instruction but cannot be set.

3. IOCF0 is the interrupt mask register.

4. Reading RF will result to “logic AND” of the RF and IOCF0

Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM

function. Reset by software.

Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM

function. Reset by software.

Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by

software.

Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCB overflows. Reset by

software.

Bit 3 (TCCAIF): TCCA overflow interrupt flag. Set when TCCA overflows. Reset by

software.

Bit 2: This bit must be set to “0” all the time.

Bit 1 (ICIF): Port 5 input status change interrupt flag. Set when Port 5 input

changes. Reset by software.

Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by

software.

6.1.16 R10 ~ R3F

All of these are 8-bit general-purpose registers.

EM78P142

8-Bit Microprocessor with OTP ROM

16 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.2 Special Purpose Registers

6.2.1 A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the

temporary storage function of the Accumulator, which is not an addressable register.

6.2.2 CONT (Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

“0” INT “0” “0” PSTE PST2 PST1 PST0

Note: The CONT register is both readable and writable.

Bit 6 is read only.

Bit 7: This bit must be set to “0” all the time.

Bit 6 (INT): Interrupt enable flag

0 = masked by DISI or hardware interrupt

1 = enabled by the ENI/RETI instructions

This bit is readable only.

Bit 5 ~ Bit 4 : These bits must set to “0” all the time.

Bit 3 (PSTE): Prescaler enable bit for TCC

0 = prescaler disable bit. TCC rate is 1:1.

1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.

Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits

PST2 PST1 PST0 TCC Rate

0 0 0 1:2

0 0 1 1:4

0 1 0 1:8

0 1 1 1:16

1 0 0 1:32

1 0 1 1:64

1 1 0 1:128

1 1 1 1:256

Note: Tcc time-out period [1/Fosc x prescaler x (256 − Tcc cnt) x 1

6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)

"0" defines the relative I/O pin as output

"1" sets the relative I/O pin into high impedance

IOC50 <7, 6, 4>, IOC60 <6~0> :

These bits must set to “0” all the time,

Other bits could be readable and writable.

IOC70 registers are all readable and writable

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 17

(This specification is subject to change without further notice)

6.2.4 IOC80 (TCCA Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

– – – “0” “0” TCCAEN “0” “0”

Note: Bit 2 of the IOC80 register is both readable and writable.

Bits 7 ~ 5: Not used

Bits 4 ~ 3: These bits must set to “0” all the time.

Bit 2 (TCCAEN): TCCA enable bit

0 = disable TCCA

1 = enable TCCA

Bits 1 ~ 0: These bits must set to “0” all the time.

6.2.5 IOC90 (TCCB and TCCC Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCCBHE TCCBEN “0” “0” – TCCCEN “0” “0”

Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of the timer

1 = Enable the most significant byte of TCCBH

TCCB is a 16-bit timer.

0 = Disable the most significant byte of TCCBH (default value)

TCCB is an 8-bit timer.

Bit 6 (TCCBEN): TCCB enable bit

0 = disable TCCB

1 = enable TCCB

Bits 5 ~ 4: These bits must set to “0” all the time.

Bit 3: Not used.

Bit 2 (TCCCEN): TCCC enable bit

0 = disable TCCC

1 = enable TCCC

Bits 1 ~ 0: These bits must set to “0” all the time.

EM78P142

8-Bit Microprocessor with OTP ROM

18 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.2.6 IOCA0 (IR and TCCC Sca le Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCCCSE TCCCS2 TCCCS1 TCCCS0 IRE HF LGP IROUTE

Bit 7 (TCCCSE): Scale enable bit for TCCC

An 8-bit timer is provided as scale for TCCC and IR-Mode. When in

IR-Mode, TCCC timer scale uses the low-time segments of the

pulse generated by Fcarrier frequency modulation (see Figure 6-11

in Section 6.8.2, Function Des c ripti on).

0 = scale disable bit, TCCC rate is 1:1

1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4

Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits

The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to

determine the scale ratio of TCCC as shown below:

TCCCS2 TCCCS1 TCCCS0 TCCC Rate

0 0 0 1:2

0 0 1 1:4

0 1 0 1:8

0 1 1 1:16

1 0 0 1:32

1 0 1 1:64

1 1 0 1:128

1 1 1 1:256

Bit 3 (IRE): Infrared Remote Enable bit

0 = Disable IRE, i.e., disable H/W Modulator Function. The IROUT

pin is fixed at a high level and the TCCC is an Up Timer.

1 = Enable IRE, i.e., enable H/W Modulator Function. Pin 67 is

defined as IROUT. If HF=1, the TCCC timer scale uses the

low-time segments of the pulse generated by the Fcarrier

frequency modulation (see Figure 6-11 in Section 6.8.2,

Function Description). When HF=0, the TCCC is an Up Timer

Bit 2 (HF): High Frequency bit

0 = PWM application. IROUT waveform is achieved base on the

high-pulse width timer and low-pulse width timer which

determine the high time width and low time width respectively.

1 = IR application mode. The low-time segments of the pulse

generated by the Fcarrier frequency modulation (see Figure

6-11 in Section 6.8.2, Funct ion Desc r ipt ion)

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 19

(This specification is subject to change without further notice)

Bit 1 (LGP): Long Pulse.

0 = The high-time and low-time registers are valid

1 = The high-time register is ignored. A single pulse is generated.

Bit 0 (IROUTE): Control bit used to define the P67 (IROUT) pin function

0 = P67 defined as bi-directional I/O pin

1 = P67 defined as IROUT. Under this condition, the I/O control bit

of P67 (Bit 7 of IOC60) must be set to “0”

6.2.7 IOCB0 (Pull-down Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

“1” “1” /PD55 “1” /PD53 /PD52 /PD51 /PD50

The IOCB0 register is both readable and writable.

Bits 7 ~ 6 and Bit 4: These bits must set to “1” all the time.

Bit 5 (/PD55): Control bit is used to enable the pull-down function of the P55 pin

0 = Enable internal pull-down

1 = Disable internal pull-down

Bit 3 (/PD53): Control bit is used to enable the pull-down function of the P53 pin

Bit 2 (/PD52): Control bit is used to enable the pull-down function of the P52 pin

Bit 1 (/PD51): Control bit is used to enable the pull-down function of the P51 pin

Bit 0 (/PD50): Control bit is used to enable the pull-down function of the P50 pin.

6.2.8 IOCC0 (Open-drain Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

/OD67 “1” “1” “1” “1” “1” “1” “1”

The IOCC0 register is both readable and writable.

Bit 7 (/OD67): Control bit is used to enable the open-drain output of the P67 pin

0 = Enable open-drain output

1 = Disable open-drain output

Bits 6 ~ 0: These bits must set to “1” all the time

6.2.9 IOCD0 (Pull-high Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

“1” “1” /PH55 “1” /PH53 /PH52 /PH51 /PH50

The IOCD0 register is both readable and writable.

EM78P142

8-Bit Microprocessor with OTP ROM

20 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Bits 7 ~ 6 and Bit 4: These bits must set to “1” all the time.

Bit 5 (/PH55): Control bit is used to enable the pull-high function of the P55 pin

0 = Enable internal pull-high

1 = Disable internal pull-high

Bit 3 (/PH53): Control bit is used to enable the pull-high function of the P53 pin.

Bit 2 (/PH52): Control bit is used to enable the pull-high function of the P52 pin.

Bit 1 (/PH51): Control bit is used to enable the pull-high function of the P51 pin.

Bit 0 (/PH50): Control bit is used to enable the pull-high function of the P50 pin.

6.2.10 IOCE0 (WDT Control Register and Interrupt Mask Register 2)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WDTE “0” ADIE “0” PSWE PSW2 PSW1 PSW0

Bit 7 (WDTE): Control bit used to enable Watchdog Timer

0 = Disable WDT

1 = Enable WDT

WDTE is both readable and writable.

Bit 6: This bit must be set to “0” all the time.

Bit 5 (ADIE): ADIF interrupt enable bit

0 = disable ADIF interrupt

1 = enable ADIF interrupt

Bit 4: This bit must be set to “0” all the time.

Bit 3 (PSWE): Prescaler enable bit for WDT

0 = prescaler disable bit, WDT rate is 1:1

1 = prescaler enable bit, WDT rate is set as Bit 2 ~ Bit 0

Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits

PSW2 PSW1 PSW0 WDT Rate

0 0 0 1:2

0 0 1 1:4

0 1 0 1:8

0 1 1 1:16

1 0 0 1:32

1 0 1 1:64

1 1 0 1:128

1 1 1 1:256

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 21

(This specification is subject to change without further notice)

6.2.11 IOCF0 (Interrupt Mask Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

LPWTIE HPWTIE TCCCIE TCCBIE TCCAIE “0” ICIE TCIE

Note: The IOCF0 register is both readable and writable.

Individual interrupt is enabled by setting to “1” its associated control bit in the IOCF0 and in IOCEO

Bits 4 and 5.

Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to

Figure 6-7 Int errupt Input Circuit under Section 6 Interrupt.

Bit 7 (LPWTIE): LPWTIF interrupt enable bit

0 = Disable LPWTIF interrupt

1 = Enable LPWTIF interrupt

Bit 6 (HPWTIE): HPWTIF interrupt enable bit

0 = Disable HPWTIF interrupt

1 = Enable HPWTIF interrupt

Bit 5 (TCCCIE): TCCCIF interrupt enable bit

0 = Disable TCCCIF interrupt

1 = Enable TCCCIF interrupt

Bit 4 (TCCBIE): TCCBIF interrupt enable bit

0 = Disable TCCBIF interrupt

1 = Enable TCCBIF interrupt

Bit 3 (TCCAIE): TCCAIF interrupt enable bit

0 = Disable TCCAIF interrupt

1 = Enable TCCAIF interrupt

Bit 2: This bit must be set to “0” all the time.

Bit 1 (ICIE): ICIF interrupt enable bit

0 = Disable ICIF interrupt

1 = Enable ICIF interrupt

Bit 0 (TCIE): TCIF interrupt enable bit.

0 = Disable TCIF interrupt

1 = Enable TCIF interrupt

6.2.12 IOC51 (TCCA Timer)

The IOC51 (TCCA) is an 8-bit clock timer. It is also an Up Timer and it can be read,

written to, and cleared on any reset condition.

()

1256

×−×

=cntTCCAF

periodTimeoutTCCA

OSC

EM78P142

8-Bit Microprocessor with OTP ROM

22 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.2.13 IOC61 (TCCB Timer)

The IOC61 (TCCB) is an 8-bit clock timer for the least significant byte of TCCBX

(TCCB). It is also an Up Timer, and it can be read, written to, and cleared on any reset

condition.

6.2.14 IOC71 (TCCBH/MSB Timer)

The IOC71 (TCCBH/MSB) is an 8-bit clock Timer for the most significant byte of

TCCBX (TCCBH). It can be read, written to, and cleared on any reset condition.

When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,” then

TCCB is a 16-bit timer.

When TCCBH is disabled:

()

1256

×−×

=cntTCCBF

periodTimeoutTCCB

OSC

When TCCBH is enabled:

()

[]

125665536

×+×−×

=cntTCCBTCCBHF

periodTimeoutTCCB

OSC

6.2.15 IOC81 (TCCC Timer)

IOC81 (TCCC) is an 8-bit clock timer that can be extended to 16-bit timer. It can be

read, written to and cleared on any reset condition.

If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC timer scale uses the

low-time segments of the pulse generated by the Fcarrier frequency modulation (see

Figure 6-11 in Section 6.8.2, Function Description). Then the TCCC value will be

TCCC predicted value.

When HF = 0 or IRE = 0, the TCCC is an Up Timer.

In TCCC Up Timer mode:

()

12560

×−××

=cntTCCCIOCAScalerF

periodTimeoutTCCC

OSC

When HF = 1 and IRE = 1, TCCC timer scale uses the low-time segments of the pulse

generated by the Fcarrier frequency modulation.

In IR mode:

()

[]

()

{}

08112 IOCAScaleTCCCIOCValueTCCCDecimal

Fcarrier ×+

where 1

OSC

FT =

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 23

(This specification is subject to change without further notice)

6.2.16 IOC91 (Low-Time Register)

The 8-bit Low-time register controls the active or Low segment of the pulse.

The decimal value of its contents determines the number of oscillator cycles and verifies

that the IR OUT pin is active. The active period of IR OUT can be calculated as follows:

()

[]

()

{

}

TIOCBScaleTimeLowIOCValueTimeLowDecimal

WidthTimeLow 1911×+

where 1

OSC

FT =

When an interrupt is generated by the Low time down counter underflow (when

enabled), the next instruction will be fetched from Address 015H (Low time).

6.2.17 IOCA1 (High Time Register)

The 8-bit High-time register controls the inactive or High period of the pulse.

The decimal value of its contents determines the number of oscillator cycles and

verifies that the IR OUT pin is inactive. The inactive period of IR OUT can be calculated

as follows:

()

[]

()

{

}

TIOCBScaleTimeHighIOCAValueTimeHighDecimal

WidthTimeHigh 111 ×+

where 1

OSC

FT =

When an interrupt is generated by the High time down counter underflow (when

enabled), the next instruction will be fetched from Address 012H (High time).

6.2.18 IOCB1 High/Low Time Scale Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

HTSE HTS2 HTS1 HTS0 LTSE LTS2 LTS1 LTS0

Bit 7 (HTSE): High-time scale enable bit

0 = scale disable bit, High-time rate is 1:1

1 = scale enable bit, High-time rate is set as Bit 6~Bit 4.

EM78P142

8-Bit Microprocessor with OTP ROM

24 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High-time scale bits:

HTS2 HTS1 HTS0 High-time Rate

0 0 0 1:2

0 0 1 1:4

0 1 0 1:8

0 1 1 1:16

1 0 0 1:32

1 0 1 1:64

1 1 0 1:128

1 1 1 1:256

Bit 3 (LTSE): Low-time scale enable bit.

0 = scale disable bit, Low-time rate is 1:1

1 = scale enable bit, Low-time rate is set as Bit 2~Bit 0.

Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low-time scale bits:

LTS2 LTS1 LTS0 Low-time Rate

0 0 0 1:2

0 0 1 1:4

0 1 0 1:8

0 1 1 1:16

1 0 0 1:32

1 0 1 1:64

1 1 0 1:128

1 1 1 1:256

6.2.19 IOCC1 (TCC Prescaler Timer)

TCC prescaler timer can be read and written to:

PST2 PST1 PST0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCC

Rate

0 0 0 - - - - - - - V 1:2

0 0 1 - - - - - - V V 1:4

0 1 0 - - - - - V V V 1:8

0 1 1 - - - - V V V V 1:16

1 0 0 - - - V V V V V 1:32

1 0 1 - - V V V V V V 1:64

1 1 0 - V V V V V V V 1:128

1 1 1 V V V V V V V V 1:256

V = valid value

The TCC prescaler timer is assigned to TCC (R1).

The contents of the IOCC1 register are cleared when one of the following occurs:

 a value is written to the TCC register

 a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of CONT)

 power-on reset, /RESET

 WDT time out reset

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 25

(This specification is subject to change without further notice)

6.2.20 IOCD1 (LVD Control Register)

Bit 7 6 5 4 3 2 1 0

EM78P142 - - - - LVDIE LVDEN LVD1 LVD0

ICE341N TYPE1 TYPE0 LVR1 LVR0 LVDIE LVDEN LVD1 LVD0

Bits 7~6 (Type 1 ~ Type 0): Type selection for EM78P142.

Type 1, Type 0 MCU Type

11 No use

10 No use

01 EM78P142 – 10Pin

00 No use

Bits 5~4 (LVR1 ~ LVR0): Low Voltage Reset enable bits.

LVR1, LVR0 VDD Reset Level VDD Release Level

11 NA (Power-on Reset)

10 2.4V 2.6V

01 3.5V 3.7V

00 4.0V 4.2V

Note: The IOCD1 <3> register is both readable and writable.

Individual interrupt is enabled by setting to “1” its associated control bit in the IOCD1 <4>.

Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to

Figure 6-8 Interrupt Input Circuit under Section 6.6 Interrupt.

Bit 3 (LVDIE): Low voltage Detector interrupt enable bit.

0 = Disable Low voltage Detector interrupt.

1 = Enable Low voltage Detector interrupt.

When a Low Voltage Detect is used to enter an interrupt vector or enter

next instruction, the LVDIE bit must be set to “Enable“.

Bit 2 (LVDEN): Low Voltage Detector enable bit

0 = Low voltage detector disable

1 = Low voltage detector enable

Bits 1~0 (LVD1:0): Low Voltage Detector level bits.

LVDEN LVD1, LVD0 LVD Voltage Interrupt Level /LVD

Vdd ≤ 2.2V 0

1 11

Vdd > 2.2V 1

Vdd ≤ 3.3V 0

1 10 Vdd > 3.3V 1

Vdd ≤ 4.0V 0

1 01 Vdd > 4.0V 1

Vdd ≤ 4.5V 0

1 00 Vdd > 4.5V 1

0 ×× NA 0

EM78P142

8-Bit Microprocessor with OTP ROM

26 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.2.21 IOCE1 (Output Sink Select Control Register)

Bit 7 6 5 4 3 2 1 0

EM78P142 - TIMERSC CPUS IDLE “0” “0” “0” “0”

ICE341N WDTPS TIMERSC CPUS IDLE “0”

“0” “0” “0”

Bit 7 (WDTPS): WDT time-out period select bit.

0 : 4.5 ms

1 : 18 ms

Bit 6 (TIMERSC): TCC, TCCA, TCCB, TCCC clock sources select 0/1 → Fs/Fm*

Fs: sub frequency for WDT internal RC time base 15kHz ± 30%

Fm: main-oscillator clock

Bit 5 (CPUS): CPU Oscillator Source Select

0 : sub-oscillator (fs)

1 : main oscillator (fosc)

When CPUS=0, the CPU oscillator select sub-oscillator and the

main oscillator is stopped.

Bit 4 (IDLE): Idle Mode Enable Bit. From SLEP instruction, this bit will determine

as to which mode to go.

0 : Idle=”0”+SLEP instruction → sleep mode

1 : Idle=”1”+SLEP instruction → idle mode

CPU Operation Mode

Green Mode

fosc:stop

fs: oscillation

CPU: u si n g fs

Norm al Mo de

fosc:oscillation

fs: oscillation

CPU : using fosc

IDLE Mode

fosc:stop

fs: oscillation

CPU: stop

SLEEP Mode

fosc:stop

fs: stop

CPU: stop

IDLE="1

"+SLEP

IDLE="0"

+ SLEP wake up

RESET

CPUS="1" CPUS="0" IDLE="1"

+SLEP

wake up

IDLE="0"

+SLEP

Wake up

Figure 6-2 CPU Operation Mode

Bits 3 ~ 0: These bits must set to “0” all the time.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 27

(This specification is subject to change without further notice)

6.2.22 IOCF1 (Pull-high Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

/PH67 “1” “1” “1” “1” “1” “1” “1”

Note: The IOCD0 register is both readable and writable.

Bit 7 (/PH67): Control bit is used to enable the pull-high function of the P67 pin.

0 = Enable internal pull-high

1 = Disable internal pull-high

Bit 6 ~ 0: These bits must set to “1” all the time.

6.3 TCC/WDT and Prescaler

There are two 8-bit timers available as prescalers that can be extended to 16-bit timer

for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT register are

used to determine the ratio of the TCC prescaler, and the PSW2 ~ PSW0 bits of the

IOCE0 register are used to determine the prescaler of WDT. The prescaler timer is

cleared by the instructions each time such instructions are written into TCC. The WDT

and prescaler will be cleared by the “WDTC” and “SLEP” instructions. Figure 6-3

depicts the block diagram of TCC/WDT.

TCC (R1) is an 8-bit timer. The TCC clock source can be internal clock (Fosc).

NOTE

The internal TCC will stop running when in sleep mode. However, during AD

conversion, when TCC is set t o “SLEP” instructi on, if the AD WE bit o f the RE r egister is

enabled, the TCC will keep on running.

The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on

running even when the oscillator driver has been turned off (i.e., in sleep mode).

During normal operation or in sleep mode, a WDT time-out (if enabled) will cause the

device to reset. The WDT can be enabled or disabled any time during normal mode

through software programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10

IOCE0 (WDT Control and Interrupt Mask Registers 2). With no prescaler, the WDT

time-out period is approximately 18ms1 or 4.5ms2.

1 VDD=5V, WDT time-out period = 16.5ms ± 30%

VDD=3V, WDT time-out period = 18ms ± 30%

2 VDD=5V, WDT time-out period = 4.2ms ± 30%

VDD=3V, WDT time-out period = 4.5ms ± 30%

EM78P142

8-Bit Microprocessor with OTP ROM

28 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

8-Bit counterWDT

Prescaler8 to 1 MUX

WDT Time out

WDTE

(IOCE0)

TCC Pin MUX

Fosc/2

8-Bit Counter (IOCC1)

8 to 1 MUX

TE (CONT)

Data Bus

TCC overflow

interrupt

TS (CONT)

TCC (R1)

PSW2~0

(IOCE0)

Prescaler

PST2~0

(CONT)

Figure 6-3 TCC and WDT Block Diagram

6.4 I/O Ports

The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5

is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain

output set through software. Port 5 features an input status changed interrupt (or

wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O

control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both

readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are

illustrated in Figures 6-4, 6-5, and 6-6.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 29

(This specification is subject to change without further notice)

PORT

PCWR

PDWR

IOD

PDRD

PCRD

CLK

Note: Pull-high and Open-drain are not shown in the figure.

Figure 6-4 I/O Port and I/O Control Register Circuit for Port 6 and Port 7

PCRD

IOD

PDRD

P50 ~ P57

PCWR

_CLK

PDWR

_CLK

CLK

TI n

PORT

Note: Pull-high (down) and Open-drain are not shown in the figure.

Figure 6-5 I/O Port and I/O Control Register Circuit for Ports 50~57

EM78P142

8-Bit Microprocessor with OTP ROM

30 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

TI 1

TI 8

IO C F.1

TI 0

RF.1

….

Figure. 6-6 Port 5 Block Diagram with Input Change Interrupt/Wake-up

6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function

(1) Wake-up (2) Wake-up and Interrupt

(a) Before Sleep (a) Before Sleep

1. Disable W DT 1. Disable W DT

2. Read I/O Port 5 (MOV R5, R5) 2. Read I/O Port 5 (MOV R5, R5)

3. Execute "ENI" or "DISI" 3. Execute "ENI" or "DISI"

4. Enable wake-up bit (Set RE ICWE =1) 4. Enable wake-up bit (Set RE

ICWE =1)

5. Execute "SLEP" instruction 5. Enable interrupt (Set IOCF ICIE =1)

(b) After wake-up 6. Execute "SLEP" instruction

→ Next instruction (b) After wake-up

1. IF "ENI" → Interrupt vector (008H)

2. IF "DISI" → Next instruction

(3) Interrupt

(a) Before Port 5 pin change

1. Read I/O Port 5 (MOV R5,R5)

2. Execute "ENI" or "DISI"

3. Enable interrupt (Set IOCF ICIE =1)

(b) After Port 5 pin changed (interrupt)

1. IF "ENI" → Interrupt vector (006H)

2. IF "DISI" → Next instruction

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 31

(This specification is subject to change without further notice)

6.5 Reset and Wake-up

6.5.1 Reset and Wake-up Operation

A reset is initiated by one of the following events:

1. Power-on reset

2. /RESET pin input "low"

3. WDT time-out (if enabled)

The device is kept in reset condition for a period of approximately 18ms3 (except in LXT

mode) after the reset is detected. When in LXT2 mode, the reset time is 500 ms. Two

choices (18 ms3 or 4.5 ms4) are available for WDT-time out period. Once a reset occurs,

the following functions are performed (the initial Address is 000h):

 The oscillator continues running, or will be started (if in sleep mode).

 The Program Counter (R2) is set to all "0".

 All I/O port pins are configured as input mode (high-impedance state)

 The Watchdog Timer and prescaler are cleared

 When power is switched on, the upper three bits of R3 is cleared

 The IOCB0 register bits are set to all "1"

 The IOCC0 register bits are set to all "1"

 The IOCD0 register bits are set to all "1"

 Bits 7, 5, and 4 of the IOCE0 register are cleared

 Bits 5 and 4 of the RE register are cleared

 RF and IOCF0 registers are cleared

Executing the “SLEP” instruction will assert the sleep (power down) mode (When

IDLE=”0”.). While entering into sleep mode, the Oscillator, TCC, TCCA, TCCB, and

TCCC are stopped. The WDT (if enabled) is cleared but keeps on running.

During AD conversion, when “SLEP” instruction is set; the Oscillator, TCC, TCCA,

TCCB, and TCCC keep on running. The WDT (if enabled) is cleared but keeps on

running.

The controller can be awakened by:

Case 1 External reset input on /RESET pin

Case 2 WDT time-out (if enabled)

Case 3 Port 5 input status changes (if ICWE is enabled)

3 VDD=5V, Setup time period = 16.5ms ± 30%.

VDD=3V, Setup time period = 18ms ± 30%.

4 VDD=5V, Setup time period = 4.2ms ± 30%.

VDD=3V, Setup time period = 4.5ms ± 30%.

EM78P142

8-Bit Microprocessor with OTP ROM

32 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Case 4 AD conversion completed (if ADWE is enabled)

Case 5 Low Voltage Detector (if LVDWE is enabled)

The first two cases (1 and 2) will cause the EM78P142 to reset. The T and P flags of

R3 can be used to determine the source of the reset (wake-up). Cases 3, 4, and 5 are

considered the continuation of program execution and the global interrupt ("ENI" or

"DISI" being executed) determines whether or not the controller branches to the

interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will

begin to execute from Address 0x06 (Case 3), 0x0C (Case 4), and 0x21 (Case 5) after

wake-up. If DISI is executed before SLEP, the execution will restart from the instruction

next to SLEP after wake-up.

Only one of Cases 2 to 5 can be enabled before entering into sleep mode. That is:

Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the

EM78P142 can be awakened only with Case 1 or Case 2. Refer to the

section on Interrupt (Section 6.6) for further details.

Case [b] If Port 5 Input Status Change is used to wake up the EM78P142 and the

ICWE bit of the RE register is enabled before SLEP, and WDT must be

disabled. Hence, the EM78P142 can be awakened only with Case 3.

Wake-up time is dependent on the oscillator mode. In RC mode, Wake-up

time is 10µs (for stable oscillators). In HXT2 (4 MHz) mode, Wake-up time is

800 µs (for stable oscillators), and in LXT2 mode, Wake-up time is 2s ~ 3s.

Case [c] If AD conversion completed is used to wake-up the EM78P142 and ADWE bit

of RE register is enabled before SLEP, WDT must be disabled by software.

Hence, the EM78P142 can be awakened only with Case 4. The wake-up

time is 15 TAD (ADC clock period).

Case[d] If Low voltage detector is used to wake-up the EM78P142 and the LVDWE bit

of Bank 0-RE register is enabled before SLEP, WDT must be disabled by

software. Hence, the EM78P142 can be awakened only with Case 5.

Wake-up time is dependent on the oscillator mode.

If Port 5 Input Status Change Interrupt is used to wake up the EM78P142 (as in Case

[b] above), the following instructions must be executed before SLEP:

BC R3, 6 ; Select Segment 0

MOV A, @00xx1110b ; Select WDT prescaler and Disable WDT

IOW IOCE0

WDTC ; Clear WDT and prescaler

MOV R5, R5 ; Read Port 5

ENI (or DISI) ; Enable (or disable) global interrupt

MOV A, @xxxxxx1xb ; Enable Port 5 input change wake-up bit

MOV RE

MOV A, @xxxxxx1xb ; Enable Port 5 input change interrupt

IOW IOCF0

SLEP ; Sleep

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 33

(This specification is subject to change without further notice)

6.5.1.1 Wake-up and Interrupt Modes Operation Summary

The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as

follows.

Wake-up

Signal Sleep Mode Idle Mode Green Mode Normal Mode

Port 5 pin

change

If enable ICWE bit

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

If enable ICWE bit

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Interrupt

(if interrupt is enabled)

or next instruction

TCC overflow

interrupt x

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Interrupt

(if interrupt is enabled)

or next instruction

conversion

complete

interrupt

If enable ADWE bit

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Fs and Fm don’t stop

If enable ADWE bit

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Fs and Fm don’t stop

Interrupt

(if interrupt is enabled)

or next instruction

High-pulse

width timer

underflow

interrupt

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Low-pulse

width timer

underflow

interrupt

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Interrupt

(if interrupt is enabled)

or next instruction

TCCA

overflow

interrupt

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Interrupt

(if interrupt is enabled)

or next instruction

TCCB

overflow

interrupt

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Interrupt

(if interrupt is enabled)

or next instruction

TCCC

overflow

interrupt

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Low Voltage

Detector

interrupt

If Enable LVDWE bit

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

If Enable LVDWE bit

Wake-up + interrupt

(if interrupt is enabled)

+ next instruction

Interrupt

(if interrupt is enabled)

or next instruction

Interrupt

(if interrupt is enabled)

or next instruction

WDT

Time out Reset Reset

Low Voltage

Reset Reset Reset

After wake up:

1. If interrupt is enabled → interrupt+ next instruction

2. If interrupt is disabled → next instruction

EM78P142

8-Bit Microprocessor with OTP ROM

34 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Signal Sleep Mode Idle Mode* Normal Mode Green Mode

RE (ICWE) Bit 1=0,

IOCF0 (ICIE) Bit 1=0

RE (ICWE) Bit 1=0, IOCF0

(ICIE) Bit 1=0 IOCF0 (ICIE) Bit 1=0 IOCF0 (ICIE) Bit 1=0

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Port 5 input status

changed wake-up is

invalid.

TCC, TCCX and IR/PWM

keep on running.

Port5 input status changed

wake-up is invalid.

Port 5 input status change

interrupted is invalid

Port 5 input status

change interrupted is

invalid

RE (ICWE) Bit 1=0,

IOCF0 (ICIE) Bit 1=1

RE (ICWE) Bit 1=0, IOCF0

(ICIE) Bit 1=1 NA NA

Set RF (ICIF)=1,

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Port 5 input status

changed wake-up is

invalid.

Set RF (ICIF)=1,

TCC, TCCX and IR/PWM

keep on running.

Port5 input status changed

wake-up is invalid.

NA NA

RE (ICWE) Bit 1=1,

IOCF0 (ICIE) Bit 1=0

RE (ICWE) Bit 1=1, IOCF0

(ICIE) Bit1=0 NA NA

Wake-up + Next

Instruction

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Wake-up + Next Instruction

TCC, TCCX and IR/PWM

keep on running.

NA NA

RE (ICWE) Bit1=1, DISI

+ IOCF0 (ICIE) Bit 1=1

RE (ICWE) Bit 1=1, DISI +

IOCF0 (ICIE) Bit 1=1

DISI + IOCF0 (ICIE)

Bit 1=1

DISI + IOCF0 (ICIE)

Bit 1=1

Wake-up + Next

Instruction + Set RF

(ICIF)=1

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Wake-up + Next Instruction

+ Set RF (ICIF)=1

TCC, TCCX and IR/PWM

keep on running.

Next Instruction

+ Set RF (ICIF)=1

Next Instruction

+ Set RF (ICIF)=1

RE (ICWE) Bit 1=1, ENI

+ IOCF0 (ICIE) Bit 1=1

RE (ICWE) Bit 1=1, ENI +

IOCF0 (ICIE) Bit 1=1

ENI + IOCF0 (ICIE)

Bit 1=1

ENI + IOCF0 (ICIE)

Bit 1=1

Port 5 Input

Status

Change

Wake-up + Interrupt

Vector (006H) + Set RF

(ICIF)=1

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Wake-up + Interrupt Vector

(006H) + Set RF (ICIF)=1

TCC, TCCX and IR/PWM

keep on running.

Interrupt Vector(006H)

+ Set RF (ICIF)=1

Interrupt Vector(006H)

+ Set RF (ICIF)=1

DISI+IOCF0(TCIE) Bit 0 =1 DISI + IOCF0 (TCIE)

Bit 0=1

DISI + IOCF0 (TCIE)

Bit 0=1

Wake-up + next instruction

Set RF (TCIF)=1

Next Instruction + Set RF

(TCIF)=1

Next Instruction + Set

RF (TCIF)=1

ENI + IOCF0(TCIE)

Bit 0 =1

ENI + IOCF0 (TCIE)

Bit 0=1

ENI + IOCF0 (TCIE)

Bit 0=1

TCC

Overflow NA

Wake-up + Interrupt Vector

(009H) + Set RF (TCIF)=1

Interrupt Vector (009H) +

Set RF (TCIF)=1

Interrupt Vector (009H)

+ Set RF (TCIF)=1

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 35

(This specification is subject to change without further notice)

Signal Sleep Mode Idle Mode* Normal Mode Green Mode

RE (ADWE) Bit 3=0,

IOCE0 (ADIE) Bit 5=0

RE (ADWE) Bit 3=0, IOCE0

(ADIE) Bit 5=0 IOCE0 (ADIE) Bit 5=0 IOCE0 (ADIE) Bit 5=0

Clear R9 (ADRUN)=0,

ADC is stopped,

AD conversion wake-up

is invalid.

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Clear R9 (ADRUN)=0, ADC

is stopped,

AD conversion wake-up is

invalid.

Oscillator, TCC, TCCX and

IR/PWM keep on running.

AD conversion interrupted

is invalid

AD conversion

interrupted is invalid

RE (ADWE) Bit 3=0,

IOCE0 (ADIE) Bit 5=1

RE (ADWE) Bit 3=0, IOCE0

(ADIE) Bit 5=1 NA NA

Set RF (ADIF)=1, R9

(ADRUN)=0, ADC is

stopped,

AD conversion wake-up

is invalid.

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Set RF (ADIF)=1, R9

(ADRUN)=0, ADC is

stopped,

AD conversion wake-up is

invalid.

Oscillator, TCC, TCCX and

IR/PWM keep on running.

NA NA

RE (ADWE) Bit 3=1,

IOCE0 (ADIE) Bit 5=0

RE (ADWE) Bit 3=1, IOCE0

(ADIE) Bit 5=0 NA NA

Wake-up + Next

Instruction,

Oscillator, TCC, TCCX

and IR/PWM keep on

running.

Wake-up when ADC

completed.

Wake-up + Next Instruction,

Oscillator, TCC, TCCX and

IR/PWM keep on running.

Wake-up when ADC

completed.

NA NA

RE (ADWE) Bit 3=1,

DISI + IOCE0 (ADIE)

Bit 5=1

RE (ADWE) Bit 3=1, DISI +

IOCE0 (ADIE) Bit 5=1

DISI + IOCE0 (ADIE)

Bit 5=1

DISI + IOCE0 (ADIE)

Bit 5=1

Wake-up + Next

Instruction + RE

(ADIF)=1,

Oscillator, TCC, TCCX

and IR/PWM keep on

running.

Wake-up when ADC

completed.

Wake-up + Next Instruction

+ RE (ADIF)=1,

Oscillator, TCC, TCCX and

IR/PWM keep on running.

Wake-up when ADC

completed.

Next Instruction

+ RE (ADIF)=1

Next Instruction

+ RE (ADIF)=1

RE (ADWE) Bit 3=1, ENI

+ IOCE0 (ADIE) Bit 5=1

RE (ADWE) Bit 3=1, ENI +

IOCE0 (ADIE) Bit 5=1

ENI + IOCE0 (ADIE)

Bit 5=1

ENI + IOCE0 (ADIE)

Bit 5=1

Conversion

Wake-up + Interrupt

Vector (00CH)+ RE

(ADIF)=1,

Oscillator, TCC, TCCX

and IR/PWM keep on

running.

Wake-up when ADC

completed.

Wake-up + Interrupt Vector

(00CH)+ RE (ADIF)=1,

Oscillator, TCC, TCCX and

IR/PWM keep on running.

Wake-up when ADC

completed.

Interrupt Vector (00CH)

+ Set RE (ADIF)=1

Interrupt Vector (00CH)

+ Set RE (ADIF)=1

EM78P142

8-Bit Microprocessor with OTP ROM

36 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Signal Sleep Mode Idle Mode* Normal Mode Green Mode

DISI + IOCF0 (HPWTIE)

Bit 6=1

DISI + IOCF0 (HPWTIE)

Bit 6=1

DISI + IOCF0 (HPWTIE)

Bit 6=1

Wake-up +Next Instruction

+ Set RF (HPWTIF)=1

Next Instruction

+ Set RF (HPWTIF)=1

Next Instruction

+ Set RF (HPWTIF)=1

ENI

+ IOCF0 (HPWTIE) Bit 6 =1

ENI

+ IOCF0 (HPWTIE)

Bit 6 =1

ENI

+ IOCF0 (HPWTIE)

Bit 6 =1

IR/PWM

underflow

interrupt

(High-pulse

width timer

underflow

interrupt)

Wake-up +Interrupt Vector

(012H)

+ Set RF (HPWTIF)=1

Interrupt Vector (012H)

+ Set RF (HPWTIF)=1

Interrupt Vector (012H)

+ Set RF (HPWTIF)=1

DISI + IOCF0 (LPWTIE)

Bit 7=1

DISI + IOCF0 (LPWTIE)

Bit 7=1

DISI + IOCF0 (LPWTIE)

Bit 7=1

Wake-up +Next Instruction

+ Set RF (LPWTIF)=1

Next Instruction

+ Set RF (LPWTIF)=1

Next Instruction

+ Set RF (LPWTIF)=1

ENI + IOCF0 (LPWTIE)

Bit 7 =1

ENI + IOCF0 (LPWTIE)

Bit 7 =1

ENI + IOCF0 (LPWTIE)

Bit 7 =1

IR/PWM

underflow

interrupt

(Low-pulse

width timer

underflow

interrupt)

Wake-up +Interrupt Vector

(015H)

+ Set RF (LPWTIF)=1

Interrupt Vector (015H)

+ Set RF (LPWTIF)=1

Interrupt Vector (015H)

+ Set RF (LPWTIF)=1

DISI + IOCF0 (TCCAIE)

Bit 3=1

DISI + IOCF0 (TCCAIE)

Bit 3=1

DISI + IOCF0 (TCCAIE)

Bit 3=1

Wake-up +Next Instruction

+ Set RF (TCCAIF)=1

Next Instruction

+ Set RF (TCCAIF)=1

Next Instruction

+ Set RF (TCCAIF)=1

ENI + IOCF0 (TCCAIE)

Bit 3=1

ENI + IOCF0 (TCCAIE)

Bit 3=1

ENI + IOCF0 (TCCAIE)

Bit 3=1

TCCA Over

Flow NA

Wake-up +Interrupt Vector

(018H)

+ Set RF (TCCAIF)=1

Interrupt Vector (018H)

+ Set RF (TCCAIF)=1

Interrupt Vector (018H)

+ Set RF (TCCAIF)=1

DISI + IOCF0 (TCCBIE)

Bit 4=1

DISI + IOCF0 (TCCBIE)

Bit 4=1

DISI + IOCF0 (TCCBIE)

Bit 4=1

Wake-up +Next Instruction

+ Set RF (TCCBIF)=1

Next Instruction

+ Set RF (TCCBIF)=1

Next Instruction

+ Set RF (TCCBIF)=1

ENI + IOCF0 (TCCBIE)

Bit 4=1

ENI + IOCF0 (TCCBIE)

Bit 4=1

ENI + IOCF0 (TCCBIE)

Bit 4=1

TCCB Over

Flow NA

Wake-up +Interrupt Vector

(01BH) + Set RF(TCCBIF)=1

Interrupt Vector (01BH)

+ Set RF (TCCBIF)=1

Interrupt Vector (01BH)

+ Set RF (TCCBIF)=1

DISI + IOCF0 (TCCCIE)

Bit 5=1

DISI + IOCF0 (TCCCIE)

Bit 5=1

DISI + IOCF0 (TCCCIE)

Bit 5=1

Wake-up +Next Instruction

+ Set RF (TCCCIF)=1

Next Instruction

+ Set RF (TCCCIF)=1

Next Instruction

+ Set RF (TCCCIF)=1

ENI + IOCF0 (TCCCIE)

Bit 5=1

ENI + IOCF0 (TCCCIE)

Bit 5=1

ENI + IOCF0 (TCCCIE)

Bit 5=1

TCCC Over

Flow NA

Wake-up +Interrupt Vector

(01EH) + Set RF

(TCCCIF)=1

Interrupt Vector (01EH)

+ Set RF (TCCCIF)=1

Interrupt Vector (01EH)

+ Set RF (TCCCIF)=1

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 37

(This specification is subject to change without further notice)

Signal Sleep Mode Idle Mode* Normal Mode Green Mode

RE (LVDWE) Bit 0=0,

IOCD1 (LVDIE) Bit 3=0

RE (LVDWE) Bit 0=0, IOCD1

(LVDIE) Bit 3=0 IOCD1 (LVDIE) Bit 3=0 IOCD1 (LVDIE) Bit 3=0

Low voltage detector

wake-up is invalid.

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Low voltage detector

wake-up is invalid.

TCC, TCCX and IR/PWM

keep on running.

Low voltage detector

interrupted is invalid.

Low voltage detector

interrupted is invalid.

RE (LVDWE) Bit 0=0,

IOCD1 (LVDIE) Bit 3=1

RE (LVDWE) Bit 0=0, IOCD1

(LVDIE) Bit 3=1 NA NA

Set RE (LVDIF)=1,

Low voltage detector

wake-up is invalid.

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Set RE (LVDIF)=1,

Low voltage detector

wake-up is invalid.

TCC, TCCX and IR/PWM

keep on running.

NA NA

RE (LVDWE) Bit 0=1,

IOCD1 (LVDIE) Bit 3=0

RE (LVDWE) Bit 0=1, IOCD1

(LVDIE) Bit 3=0 NA NA

Wake-up + Next

Instruction,

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Wake-up + Next Instruction,

TCC, TCCX and IR/PWM

keep on running.

NA NA

RE (LVDWE) Bit =1,

DISI + IOCD1 (LVDIE)

Bit 3=1

RE (LVDWE) Bit 0=1, DISI +

IOCD1 (LVDIE) Bit 3=1

DISI + IOCD1 (LVDIE)

Bit 3=1

DISI + IOCD1 (LVDIE)

Bit 3=1

Wake-up + Next

Instruction + Set RE

(LVDIF)=1,

Oscillator, TCC, TCCX

and IR/PWM are

stopped.

Wake-up + Next Instruction

+ Set RE (LVDIF)=1,

TCC, TCCX and IR/PWM

keep on running.

Next Instruction

+ Set RE (LVDIF)=1

Next Instruction

+ Set RE (LVDIF)=1

RE (LVDWE) Bit 2=1,

ENI + IOCD1 (LVDIE)

Bit 3=1

RE (LVDWE) Bit0=1, ENI +

IOCD1 (LVDIE) Bit 3=1

ENI + IOCD1 (LVDIE)

Bit 3=1

ENI + IOCD1 (LVDIE)

Bit 3=1

Low Voltage

Detector

interrupt

Wake-up + Interrupt

Vector (021H) + Set RE

(LVDIF)=1,Oscillator,

TCC, TCCX and

IR/PWM are stopped.

Wake-up + Interrupt Vector

(021H) + Set RE (LVDIF)=1,

TCC, TCCX and IR/PWM

keep on running.

Interrupt Vector (021H)

+ Set RE (LVDIF)=1

Interrupt Vector (021H)

+ Set RE (LVDIF)=1

WDT

Timeout

IOCE (WDTE)

Bit 7=1

Wake-up + Reset

(Address 0x00)

Wake-up + Reset

(Address 0x00) Reset (Address 0x00) Reset (Address 0x00)

Low voltage

reset

Wake-up + Reset

(Address 0x00)

Wake-up + Reset

(Address 0x00) Reset (Address 0x00) Reset (Address 0x00)

EM78P142

8-Bit Microprocessor with OTP ROM

38 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.5.1.2 Register Initial Values after Reset

The following summarizes the initialized values for registers.

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit Name – – C55 – C53 C52 C51 C50

Type 1 1 1 1 1 1 1 1

Power-on 1 1 1 1 1 1 1 1

/RESET and WDT P P P P P P P P

NA IOC50

Wake-up from Pin

Change 1 1 1 1 1 1 1 1

Bit Name C67 – – – – – – –

Type 1 1 1 1 1 1 1 1

Power-on 1 1 1 1 1 1 1 1

/RESET and WDT P P P P P P P P

NA IOC60

Wake-up from Pin

Change 1 1 1 1 1 1 1 1

Bit Name × × × × × × C71 C70

Power-on 0 0 0 0 0 0 1 1

/RESET and WDT 0 0 0 0 0 0 1 1

NA IOC70

Wake-up from Pin

Change P P P P P P P P

Bit Name × × – – – TCCAEN – –

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOC80

Wake-up from Pin

Change P P P P P P P P

Bit Name TCCBHE TCCBEN – – × TCCCEN – –

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOC90

Wake-up from Pin

Change P P P P P P P P

Bit Name TCCCSE TCCCS2 TCCCS1 TCCCS0 IRE HF LGP IROUTE

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOCA0

(IRCR)

Wake-up from Pin

Change P P P P P P P P

Bit Name – – /PD55 – /PD53 /PD52 /PD51 /PD50

Power-on 1 1 1 1 1 1 1 1

/RESET and WDT 1 1 1 1 1 1 1 1

NA IOCB0

(PDCR)

Wake-up from Pin

Change P P P P P P P P

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 39

(This specification is subject to change without further notice)

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit Name /OD67 – – – – – – –

Power-on 1 1 1 1 1 1 1 1

/RESET and WDT 1 1 1 1 1 1 1 1

NA IOCC0

(ODCR)

Wake-up from Pin

Change P P P P P P P P

Bit Name – – /PH55 – /PH53 /PH52 /PH51 /PH50

Power-on 1 1 1 1 1 1 1 1

/RESET and WDT 1 1 1 1 1 1 1 1

NA IOCD0

(PHCR1)

Wake-up from Pin

Change P P P P P P P P

Bit Name WDTC – ADIE – PSWE PSW2 PSW1 PSW0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOCE0

Wake-up from Pin

Change P P P P P P P P

Bit Name LPWTIE HPWTIE TCCCIE TCCBIE TCCAIE – ICIE TCIE

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOCF0

Wake-up from Pin

Change P P P P P P P P

Bit Name TCCA7 TCCA6 TCCA5 TCCA4 TCCA3 TCCA2 TCCA1 TCCA0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOC51

(TCCA)

Wake-up from Pin

Change P P P P P P P P

Bit Name TCCB7 TCCB6 TCCB5 TCCB4 TCCB3 TCCB2 TCCB1 TCCB0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOC61

(TCCB)

Wake-up from Pin

Change P P P P P P P P

Bit Name TCCBH7 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 TCCBH0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOC71

(TCCBH)

Wake-up from Pin

Change P P P P P P P P

Bit Name TCCC7 TCCC6 TCCC5 TCCC4 TCCC3 TCCC2 TCCC1 TCCC0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOC81

(TCCC)

Wake-up from Pin

Change P P P P P P P P

Bit Name LTR7 LTR6 LTR5 LTR4 LTR3 LTR2 LTR1 LTR0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOC91

(LTR)

Wake-p from Pin

Change P P P P P P P P

EM78P142

8-Bit Microprocessor with OTP ROM

40 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit Name HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOCA1

(HTR)

Wake-up from Pin

Change P P P P P P P P

Bit Name HTSE HTS2 HTS1 HTS0 LTSE LTS2 LTS1 LTS0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOCB1

(HLTS)

Wake-up from Pin

Change P P P P P P P P

Bit Name TCCPC7 TCCPC6 TCCPC5 TCCPC4 TCCPC3 TCCPC2 TCCPC1 TCCPC0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

NA IOCC1

(TCCPC)

Wake-up from Pin

Change P P P P P P P P

Bit Name TYPE1 TYPE0 LVR1 LVR0 LVDIE LVDEN LVD1 LVD0

Power-on 1 1 1 1 0 0 1 1

/RESET and WDT P P P P 0 P 1 1

IOCD1

(LVD CR)

(ROMLESS) Wake-up from Pin

Change P P P P P P P P

HS1 WDPTS TIMERSC CPUS IDLE – – – –

Power-on 1 1 1 1 0 0 0 0

/RESET and WDT P 1 1 1 0 0 0 0

IOCE1

(HSC)

(ROMLESS) Wake-up from Pin

Change P P P P P P P P

Bit Name /PH67 – – – – – – –

Power-on 1 1 1 1 1 1 1 1

/RESET and WDT 1 1 1 1 1 1 1 1

NA IOCF1

(PHCR2)

Wake-up from Pin

Change P P P P P P P P

Bit Name – INT – – PSTE PST2 PST1 PST0

Power-on 1 0 1 1 0 0 0 0

/RESET and WDT 1 0 1 1 0 0 0 0

NA CONT

Wake-up from Pin

Change P P P P P P P P

Bit Name – – – – – – – –

Power-on U U U U U U U U

/RESET and WDT P P P P P P P P

0x00 R0 (IAR)

Wake-up from Pin

Change P P P P P P P P

Bit Name – – – – – – – –

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 00 0

0x01 R1 (TCC)

Wake-up from Pin

Change P P P P P P P P

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 41

(This specification is subject to change without further notice)

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit Name – – – – – – – –

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

0x02 R2 (PC)

Wake-up from Pin

Change Jump to Address 0x06 or continue to execute next instruction

Bit Name RST IOCS – T P Z DC C

Power-on 0 0 0 1 1 U U U

/RESET and WDT 0 0 0 T t P P P

0x03 R3 (SR)

Wake-up from Pin

Change P P P T t P P P

Bit Name × BS – – – – – –

Power-on 0 0 U U U U U U

/RESET and WDT 0 0 P P P P P P

0x04 R4 (RSR)

Wake-up from Pin

Change 0 P P P P P P P

Bit Name – – P55 – P53 P52 P51 P50

Power-on 1 1 1 1 1 1 1 1

/RESET and WDT 1 1 1 1 1 1 1 1

0x05 R5

Wake-up from Pin

Change P P P P P P P P

Bit Name P67 – – – – – – –

Power-on 1 1 1 1 1 1 1 1

/RESET and WDT 1 1 1 1 1 1 1 1

0x06 R6

Wake-up from Pin

Change P P P P P P P P

Bit Name – – – – – – P71 P70

Power-on 0 0 0 0 0 0 1 1

/RESET and WDT 0 0 0 0 0 0 1 1

0x7 R7

Wake-up from Pin

Change P P P P P P P P

Bit Name – ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

0x8 R8

(AISR)

Wake-up from Pin

Change 0 0 0 0 P P P P

Bit Name – CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

0x9 R9

(ADCON)

Wake-up from Pin

Change P P P P P 0 P P

Bit Name CALI SIGN VOF[2] VOF[1] VOF[0] – – –

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

0xA RA

(ADOC)

Wake-up from Pin

Change P P P P P P P P

EM78P142

8-Bit Microprocessor with OTP ROM

42 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit Name AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4

Power-on U U U U U U U U

/RESET and WDT U U U U U U U U

0XB RB

(ADDATA)

Wake-up from Pin

Change P P P P P P P P

Bit Name “0” “0” “0” “0” AD11 AD10 AD9 AD8

Power-on 0 0 0 0 U U U U

/RESET and WDT 0 0 0 0 U U U U

0XC RC

(ADDATA1H)

Wake-up from Pin

Change 0 0 0 0 P P P P

Bit Name AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Power-on U U U U U U U U

/RESET and WDT U U U U U U U U

0XD RD

(ADDATA1L)

Wake-up from Pin

Change P P P P P P P P

Bit Name /LVD LVDIF ADIF – ADWE – ICWE LVDWE

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

0xE RE

(ISR2)

Wake-up from Pin

Change P P P P P P P P

Bit Name LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF – ICIF TCIF

Power-on 0 0 0 0 0 0 0 0

/RESET and WDT 0 0 0 0 0 0 0 0

0xF RF

(ISR1)

Wake-up from Pin

Change P P P P P P P P

Bit Name – – – – – – – –

Power-on U U U U U U U U

/RESET and WDT P P P P P P P P

0x10~0x3F R10~R3F

Wake-up from Pin

Change P P P P P P P P

Legend: “×” = not used “P” = previous value before reset

“u” = unknown or don’t care “t” = check “Reset Type” Table in Section 6.5.2

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 43

(This specification is subject to change without further notice)

6.5.1.3 Controller Reset Block Diagram

WDT Timeout

Oscillator

D Q

CLK

CLR

WDT

VDD

Setu p time Reset

CLK

/RESET

Power-on Reset

Voltage

Detector

ENWDTB

Figure 6-7 Controller Reset Block Diagram

6.5.2 The T and P Status under Status Register

A reset condition is initiated by one of the following events:

1. Power-on reset

2. /RESET pin input "low"

3. WDT time-out (if enabled)

The values of T and P as listed in the table below, are used to check how the processor

wakes up.

Reset Type RST T P

Power-on 0 1 1

/RESET during Operating mode, 0 *P *P

/RESET wake-up during Sleep mode 0 1 0

LVR during Operating mode, 0 *P *P

LVR wake-up during Sleep mode 0 1 0

WDT during Operating mode 0 0 1

WDT wake-up during Sleep mode 0 0 0

Wake-up on pin change during Sleep mode 1 1 0

*P: Previous status before reset

The following shows the events that may affect the status of T and P.

Event RST T P

Power-on 0 1 1

WDTC instruction *P 1 1

WDT time-out 0 0 *P

SLEP instruction *P 1 0

Wake-up on pin changed during Sleep mode 1 1 0

*P: Previous value before reset

EM78P142

8-Bit Microprocessor with OTP ROM

44 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.6 Interrupt

The EM78P142 has five interrupts enumerated below:

1. TCC, TCCA, TCCB, TCCC overflow interrupt

2. Port 5 Input Status Change Interrupt

3. Analog to Digital conversion completed

4. IR/PWM underflow interrupt

5. Low voltage detector interrupt

Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV

R5, R5") is necessary. Each Port 5 pin will have this feature if its status changes. The

Port 5 Input Status Change Interrupt will wake up the EM78P142 from sleep mode if it is

enabled prior to going into sleep mode by executing SLEP instruction. When wake up

occurs, the controller will continue to execute program in-line if the global interrupt is

disabled. If enabled, the global interrupt will branch out to the Interrupt Vector 006H.

RF and RE are the interrupt status register that records the interrupt requests in the

relative flags/bits. IOCF0 and IOCE0 are interrupt mask registers. The global interrupt

is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the

interrupt service routine, the source of an interrupt can be determined by polling the flag

bits in RF. The interrupt flag bit must be cleared by instructions before leaving the

interrupt service routine to avoid recursive interrupts.

When interrupt mask bits is “Enable”, the flag in the Interrupt Status Register (RF) is set

regardless of the ENI execution. Note that the result of RF will be the logic AND of RF

and IOCF0 (refer to figure below). The RETI instruction ends the interrupt routine and

enables the global interrupt (the ENI execution).

When an interrupt is generated by the Timer clock (when enabled), the next instruction

will be fetched from Address 009, 018, 01B, and 01EH (TCC, TCCA, TCCB, and TCCC

respectively).

When an interrupt generated by the AD conversion is completed (when enabled), the

next instruction will be fetched from Address 00CH

When an interrupt is generated by the High time / Low time down counter underflow

(when enabled), the next instruction will be fetched from Addresses 012 and 015H

(High time and Low time respectively).

When an interrupt is generated by the Low Voltage Detect (when enabled), the next

instruction will be fetched from Address 021 (Low Voltage Detector interrupt).

Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4

registers are saved first by the hardware. If another interrupt occurs, the ACC, R3, and

R4 will be replaced by the new interrupt. After an interrupt service routine is completed,

the ACC, R3, and R4 registers are restored.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 45

(This specification is subject to change without further notice)

INT

ENI/DISI

IOD

RFWR

IOCFRD

IOCFWR

IRQn

IRQm

RFRD

IOCF

/RESET

/IRQn

VCC

CLK

Interrupt sources

Interrupt

occurs

ENI/DISI Stack ACC

Stack R3

RETI

ACC

R3 (7~5, 2~0)

R4 (6~0) Stack R4

Figure 6-8 Interrupt Back-up Diagram

In EM78P142, each individual interrupt source has its own interrupt vector as depicted

in the table below.

Interrupt Vector Interrupt Status Priority*

003H NA −

006H Port 5 pin change 2

009H TCC overflow interrupt 3

00CH AD conversion complete interrupt 4

00FH NA −

012H High-pulse width timer underflow interrupt 5

015H Low-pulse width timer underflow interrupt 6

018H TCCA overflow interrupt 7

01BH TCCB overflow interrupt 8

01EH TCCC overflow interrupt 9

021H Low Voltage Detector interrupt 1

Note: *Priority: 1 = highest ; 9 = lowest priority

EM78P142

8-Bit Microprocessor with OTP ROM

46 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.7 Analog-To-Digital Conv erter (ADC)

The analog-to-digital circuitry consists of an 8-bit analog multiplexer; three control

registers (AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA1/RB,

ADDATA1H/RC, and ADDATA1L/RD) and an ADC with 12-bit resolution as shown in

the functional block diagram below. The analog reference voltage (Vref) and the

analog ground are connected via separate input pins.

The ADC module utilizes successive approximation to convert the unknown analog

signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and

ADDATA1L. Input channels are selected by the analog input multiplexer via the

ADCON register Bits ADIS1 and ADIS0.

ADDATA1H

DAT A B U S

Vref

Power-Down

Fsco

Internal RC

4-1

MUX

7 ~ 0 34

ADC

( successive approximation )

ADCON RF

AISR ADCON

Start to Convert

ADCON

01234567891011

ADDATA1L

ADC3

ADC2

ADC1

ADC0

ADC7

ADC6

ADC5

ADC4

Figure 6-9 Analog-to-Digital Conversion Functional Block Diagram

6.7.1 ADC Control Register (AISR/R8, ADCON/R9 , ADOC/RA)

6.7.1.1 R8 (AISR: ADC Input Select Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

“0” ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

The AISR register individually defines the P5, P6 and P7 pins as analog inputs or as

digital I/O.

Bit 7: This bit must be set to “0” all the time.

Bit 6 (ADE6): AD converter enable bit of P55 pin

0 : Disable ADC6, P55 functions as I/O pin

1 : Enable ADC6 to function as analog input pin

Bit 5 (ADE5): AD converter enable bit of P70 pin

0 : Disable ADC5, P70 functions as I/O pin

1 : Enable ADC5 to function as analog input pin

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 47

(This specification is subject to change without further notice)

Bit 4 (ADE4): AD converter enable bit of P67 pin

0 = Disable ADC4, P67 functions as I/O pin

1 = Enable ADC4 to function as analog input pin

Bit 3 (ADE3): AD converter enable bit of P53 pin

0 = Disable ADC3, P53 functions as I/O pin

1 = Enable ADC3 to function as analog input pin

Bit 2 (ADE2): AD converter enable bit of P52 pin

0 = Disable ADC2, P53 functions as I/O pin

1 = Enable ADC2 to function as analog input pin

Bit 1 (ADE1): AD converter enable bit of P51 pin

0 = Disable ADC1, P51 acts as I/O pin

1 = Enable ADC1 acts as analog input pin

Bit 0 (ADE0): AD converter enable bit of P50 pin

0 = Disable ADC0, P50 functions as I/O pin

1 = Enable ADC0 to function as analog input pin

6.7.1.2 R9 (ADCON: ADC Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

“0” CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0

The ADCON register controls the operation of the AD conversion and decides which

pin should be currently active.

Bit 7: This bit must be set to “0” all the time

Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The prescaler of ADC oscillator clock rate

00 = 1: 16 (default value)

01 = 1: 4

10 = 1: 64

11 = 1: 8

CPUS CKR1: CKR0 Operation Mode Max. Operation Frequency

1 00 Fosc/16 4 MHz

1 01 Fosc/4 1 MHz

1 10 Fosc/64 16 MHz

1 11 Fosc/8 2 MHz

0 ×× Internal RC −

Bit 4 (ADRUN): ADC starts to RUN

0 : reset upon completion of the conversion. This bit cannot be reset

though software.

1 : an AD conversion is started. This bit can be set by software.

EM78P142

8-Bit Microprocessor with OTP ROM

48 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Bit 3 (ADPD): ADC Power-down mode

0 : switch off the resistor reference to conserve power even while the

CPU is operating

1 : ADC is operating

Bit 2 ~ Bit 0 (ADIS2 ~ ADIS0): Analog Input Select

000 = ADIN0/P50

001 = ADIN1/P51

010 = ADIN2/P52

011 = ADIN3/P53

100 = ADIN4/P67

101 = ADIN5/P70

110 = ADIN6/P55

111 = not used

These bits can only be changed when the ADIF bit and the ADRUN bit

are both LOW

6.7.1.3 RA (A DOC: AD Offset Calibration Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CALI SIGN VOF[2] VOF[1] VOF[0] “0” “0” “0”

Bit 7 (CALI): Calibration enable bit for ADC offset

0 = disable Calibration

1 = enable Calibration

Bit 6 (SIGN): Polarity bit of offset voltage

0 = Negative voltage

1 = Positive voltage

Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits.

VOF[2] VOF[1] VOF[0] EM78P142 ICE341N

0 0 0 0LSB 0LSB

0 0 1 2LSB 2LSB

0 1 0 4LSB 4LSB

0 1 1 6LSB 6LSB

1 0 0 8LSB 8LSB

1 0 1 10LSB 10LSB

1 1 0 12LSB 12LSB

1 1 1 14LSB 14LSB

Bit 2 ~ Bit 0: Unimplemented, read as ‘0’.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 49

(This specification is subject to change without further notice)

6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC,

ADDATA1L/RD)

When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H

and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.

6.7.3 ADC Sampling Time

The accuracy, linearity, and speed of the successive approximation of the AD converter

are dependent on the properties of the ADC and the comparator. The source

impedance and the internal sampling impedance directly affect the time required to

charge the sample holding capacitor. The application program controls the length of

the sample time to meet the specified accuracy. Generally speaking, the program

should wait for 2µs for each KΩ of the analog source impedance and at least 2µs for

the low-impedance source. The maximum recommended impedance for analog

source is 10KΩ at Vdd=5V. After the analog input channel is selected, this acquisition

time must be done before the conversion is started.

6.7.4 AD Conversion Time

CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This

allows the MCU to run at the maximum frequency without sacrificing the AD conversion

accuracy. For the EM78P142, the conversion time per bit is about 4µs. The table

below shows the relationship between Tct and the maximum operating frequencies.

CKR1:CKR0 Operation

Mode Max. Operation

Frequency Max. Conversion

Rate/B it Max. Conversion Rate

00 Fosc/16 4 MHz 250kHz (4µs) 15×4µs=60µs (16.7kHz)

01 Fosc/4 1 MHz 250kHz (4µs) 15×4µs=60µs (16.7kHz)

10 Fosc/64 16 MHz 250kHz ( 4µs) 15×4µs=60µs (16.7kHz)

11 Fosc/8 2 MHz 250kHz ( 4µs) 15×4µs=60µs (16.7kHz)

NOTE

■ Pin not used as an analog input pin can be used as regular input or output pin.

■ During conversion, do not perform output instruction to maintain precision for all of

the pins.

6.7.5 ADC Operation during Sleep Mode

In order to obtain a more accurate ADC value and reduce power consumption, the AD

conversion remains operational during sleep mode. As the SLEP instruction is

executed, all the MCU operations will stop except for the Oscillator, TCC, TCCA,

TCCB, TCCC, and AD conversion.

EM78P142

8-Bit Microprocessor with OTP ROM

50 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

The AD Conversion is considered completed as determined by:

1. The ADRUN bit of the R9 register is cleared to “0”.

2. The ADIF bit of the RE register is set to “1”.

3. The ADWE bit of the RE register is set to “1.” Wakes up from ADC conversion

(where it remains in operation during sleep mode).

4. Wake up and execution of the next instruction if the ADIE bit of the IOCE0 is

enabled and the “DISI” instruction is executed.

5. Wake up and enters into Interrupt vector (Address 0x00C) if the ADIE bit of the

IOCE0 is enabled and the “ENI” instruction is executed.

6. Enters into Interrupt vector (Address 0x00C) if the ADIE bit of the IOCE0 is enabled

and the “ENI” instruction is executed.

The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the

conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise,

the AD conversion will be shut off, no matter what the status of the ADPD bit is.

6.7.6 Programming Process/Considerations

6.7.6.1 Programming Process

Follow these steps to obtain data from the ADC:

1. Write to the eight bits (ADE7: ADE0) on the R8 (AISR) register to define the

characteristics of R5 (digital I/O, analog channels, or voltage reference pin)

2. Write to the R9/ADCON register to configure the AD module:

a) Select the ADC input channel ( ADIS2 : ADIS0 )

b) Define the AD conversion clock rate ( CKR1 : CKR0 )

c) Select the VREFS input source of the ADC

d) Set the ADPD bit to 1 to begin sampling

3. Set the ADWE bit, if the wake-up function is employed

4. Set the ADIE bit, if the interrupt function is employed

5. Write “ENI” instruction, if the interrupt function is employed

6. Set the ADRUN bit to 1

7. Write “SLEP” instruction or Polling.

8. Wait for wake-up or for the ADRUN bit to be cleared to “0” , interrupt flag (ADIF) is

set “1,” or ADC interrupt occurs.

9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the

ADC input channel changes at this time, the ADDATA, ADDATA1H, and

ADDATA1L values can be cleared to ‘0’.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 51

(This specification is subject to change without further notice)

10. Clear the interrupt flag bit (ADIF).

11. For next conversions, go to Step 1 or Step 2 as required. At least two Tct is

required before the next acquisition starts.

NOTE

In order to obtain accurate values, it is necessary to avoid any data transition on I/O

pins during AD conversion

6.7.6.2 Sample Demo Programs

R_0 == 0 ; Indirect addressing register

PSW == 3 ; Status register

PORT5 == 5

PORT6 == 6

R_E== 0XE ; Interrupt status register

B. Define a Control Register

IOC50 == 0X5 ; Control Register of Port 5

IOC60 == 0X6 ; Control Register of Port 6

IOCE0== 0XE ; Interrupt Mask Register 2

C_INT== 0XF ; Interrupt Mask Register

C. ADC Control Register

ADDATA == 0xB ; The contents are the results of ADC

AISR == 0x08 ; ADC input select register

ADCON == 0x9 ; 7 6 5 4 3 2 1 0

; - CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0

D. Define Bits in ADCON

ADRUN == 0x4 ; ADC is executed as the bit is set

ADPD == 0x3 ; Power Mode of ADC

E. Program Starts

ORG 0 ; Initial address

JMP INITIAL ;

ORG 0x0C ; Interrupt vector

JMP CLRRE

;

;(User program section)

;

CLRRE:

MOV A,RE

AND A, @0BXX0XXXXX ; To clear the ADIF bit, “X” by application

MOV RE,A

BS ADCON, ADRUN ; To start to execute the next AD conversion

; if necessary

RETI

EM78P142

8-Bit Microprocessor with OTP ROM

52 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

INITIAL:

MOV A,@0B00000001 ; To define P50 as an analog input

MOV AISR,A

MOV A,@0B00001000 ; To select P50 as an analog input channel, and

AD power on

MOV ADCON,A ; To define P50 as an input pin and set clock

rate at fosc/16

En_ADC:

MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others

; are dependent on applications

IOW PORT5

MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, “X”

; by application

MOV RE,A

MOV A, @0BXX1XXXXX ; Enable the ADIE interrupt function of ADC,

; “X” by application

IOW IOCE0

ENI ; Enable the interrupt function

BS ADCON, ADRUN ; Start to run the ADC

; If the interrupt function is employed, the following three lines

may be ignored

;If Sleep:

SLEP

;

;(User program section)

;

;If Polling:

POLLING:

JBC ADCON, ADRUN ; To check the ADRUN bit continuously;

JMP POLLING ; ADRUN bit will be reset as the AD conversion

; is completed

;

;(User program section)

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1 .0) 01.25.2008 • 53

(This specification is subject to change without further notice)

6.8 Infrared Remote Control Application/PWM W aveform

Generation

6.8.1 Overview

This LSI can easily output infrared carrier or PWM standard waveform. As illustrated

below, the IR and PWM waveform generation function include an 8-bit down count

timer/counter, high-time, low-time, and IR control register. The IROUT pin waveform is

determined by IOCA0 (IR and TCCC scale control register), IOCB1 (high-time rate,

low-time rate control register), IOC81 (TCCC timer), IOCA1 (high-time register), and

IOC91 (low-time register).

H/W Modulator

IROUT pin

IRE

Fcarrier

Fosc

LGP

8-bit counter

8-to-1 MUX

8-bit binary

down counter

Auto-reload buffer

(TCCC)(IOC81)

8-bit counter

8-to-1 MUX

8-bit counter

8-to-1 MUX

8-bit binary

down counter

8-bit binary

down counter

Auto-reload buffer

(High-time)(IOCA1)

Auto-reload buffer

(Low-time) (IOC91)

8 8

Scale

(IOCB 1)

Scale

(IOCB1)

Scale

(IOCA0)

8 8

Underflow Interrupt

HPWTIF

LPWTIF

Figure 6-10 IR/PWM System Block Diagram

Details of the Fcarrier High Time Width and Low Time Width are shown below:

()

[]

()

{}

08112 IOCAScaleTCCCIOCValueTCCCDecimal

Fcarrier ×+

where 1

OSC

FT =

()

[]

()

{

}

TIOCBScaleTimeHighIOCAValueTimeHighDecimal

WidthTimeHigh 111 ×+

()

[]

()

{

}

TIOCBScaleTimeLowIOCValueTimeLowDecimal

WidthTimeLow 1911×+

When an interrupt is generated by the High time down counter underflow (when

enabled), the next instruction will be fetched from Address 018 and 01BH (High time

and Low time respectively).

EM78P142

8-Bit Microprocessor with OTP ROM

54 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.8.2 Function Description

The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the

Fcarrier waveform at low-time segments of the pulse.

low time width high time width low time width high time width

Fcarrier

IROUT

IRE Start

Figure 6-11a LGP=0, HF=1, IROUT Pin Output Waveform

The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate

the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is

determined by the high time width and low time width instead. This mode can produce

standard PWM waveform.

low time width high time w idth low time width high time w idth

Fcarrier

IROUT

IRE Start

Figure 6-11b LGP=0, HF=0, IROUT Pin Output Waveform

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 55

(This specification is subject to change without further notice)

The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the

Fcarrier waveform at low-time segments of the pulse. When IRE goes low from high,

the output waveform of IROUT will keep transmitting until high-time interrupt occurs.

low time width hi gh time width l ow ti me w i dth high time width

Fcarrier

IROUT

IRE IR disab l e

Start

Alw ays hig h - level

Figure 6-11c LGP=0, HF=1, When IRE goes Low from High, IROUT Pin Outputs Waveform

The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate

the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is

determined by high time width and low time width. This mode can produce standard

PWM waveform when IRE goes low from high. The output waveform of IROUT will

keep on transmitting until high-time interrupt occurs.

low time width high tim e wid th low time width hi gh t im e w idt h

Fcarrier

IROUT

IRE IR disable

Start

Alw ays high-level

Figure 6-11d LGP=0, HF=0, W hen IRE goes Low from High, Irout Pin Output Waveform

EM78P142

8-Bit Microprocessor with OTP ROM

56 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

The following figure shows LGP=1 and HF=1. When this bit is set to high level, the

high-time segment of the pulse is ignored. So, IROUT waveform output is determined

by low-time width.

low time width low ti me wi dth low t im e w i dth

Fcarrier

IROUT

IRE

IR disable

Start

Alwa ys high- level

Figure 6-11e LGP=1 and HF=1, IROUT Pin Output Waveform

6.8.3 Programming the Related Registers

When defining IR/PWM, refer to the operation of the related registers as shown in the

tables below.

IR/PWM Related Control Registers

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x09 IOC90 TCCBHE/0TCCBEN/0 “0” “0” “0”

CCCEN/0 “0” “0”

0X0A IR CR

/IOCA0 TCCCSE/0 TCCCS2/0 TCCCS1/0 TCCCS0/0 IRE/0 HF/0 LGP/0 IROUTE/0

0x0F IMR

/IOCF0 LPWTIE/0 HPWTIE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0 “0” ICIE/0 TCIE/0

0X0B HLTS

/IOCB1 HTSE/0 HTS2/0 HTS1/0 HTS0/0 LTSE/0 LTS2/0 LTS1/0 LTS0/0

IR/PWM Related Status/Data Registers

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x0F ISR/RF LPWTIF/0 HPWTIF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0 “0” ICIF/0 TCIF/0

0x06 TCCC

/IOC81 TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0

0X09 LTR

/IOC91 LTR7/0 LTR6/0 LTR5/0 LTR4/0 LTR3/0 LTR2/0 LTR1/0 LTR0/0

0X0A HTR

/IOCA1 HTR7/0 HTR6/0 HTR5/0 HTR4/0 HTR3/0 HTR2/0 HTR1/0 HTR0/0

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 57

(This specification is subject to change without further notice)

6.9 Timer

6.9.1 Overview

Timer A (TCCA) is an 8-bit clock timer. Timer B (TCCB) is a 16-bit clock timer. Timer C

(TCCC) is an 8-bit clock timer that can be extended to 16-bit clock timer with

programmable scalers. TCCA, TCCB, and TCCC can be read and written to, and are

cleared at every reset condition.

6.9.2 Function Description

Set predict value

Fosc

TCCC

Set TCCCIF

TCCCEN

Overflow

TCCA

Set TCCAIF

TCCAEN

Overflow

TCCB

Set TCCBIF

TCCBEN

Overflow

Set predict value Set predict value

8-to-1 MUX

8 Bit

counter

Fosc

TCCCS1 ~ TCCCS0

Figure 6-12 Timer Block Diagram

Each signal and block of the above Timer block diagram is described as follows:

TCCX: Timer A~C register. TCCX is incremented until it matches with zero, and then

reloads the predicted value. When writing a value to TCCX, the predicted

value and TCCX value become the set value. When reading from TCCX, the

value will be the TCCX direct value. When TCCXEN is enabled, the reloading

of the predicted value to TCCX, TCCXIE is also enabled. TCCXIF will be set at

the same time. It is an up timer.

TCCA Timer (IOC51):

IOC51 (TCCA) is an 8-bit clock timer. It can be read, written to, and cleared on

any reset condition and it is also an Up Timer.

()

1256

×−×

=cntTCCAF

periodTimeoutTCCA

OSC

TCCB Timer (IOC61):

IOC61 is an 8-bit clock timer for the least significant byte of TCCBX (TCCB). It

can be read, written, and cleared on any reset condition and it is also an Up

Timer.

EM78P142

8-Bit Microprocessor with OTP ROM

58 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

TCCBH / MSB Timer (IOC71):

IOC71 is an 8-bit clock timer for the most significant byte of TCCBX (TCCBH).

It can be read, written to, and cleared on any reset condition.

When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,”

then TCCB is a 16-bit length timer.

When TCCBH is disabled:

()

1256

×−×

=cntTCCBF

periodTimeoutTCCB

OSC

When TCCBH is enabled:

()

[]

125665536

×+×−×

=cntTCCBTCCBHF

periodTimeoutTCCB

OSC

TCCC Timer (IOC81):

IOC81 (TCCC) is an 8-bit clock timer. It can be read, written to, and cleared on

any reset condition.

If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC timer scale uses

the low-time segments of the pulse generated by Fcarrier frequency

modulation (see Figure 6-11 in Section 6.8.2, Function Description). The

TCCC value will then be the TCCC predicted value.

When HF = 0 or IRE = 0. The TCCC is an Up Timer.

In TCCC Up Timer mode:

()

12560

×−××

=cntTCCCIOCAScalerF

periodTimeoutTCCC

OSC

When HF = 1 and IRE = 1, TCCC timer scale uses the low-time segments of

the pulse generated by the Fcarrier frequency modulation.

In IR mode:

()

[]

()

{}

08112 IOCAScaleTCCCIOCValueTCCCDecimal

Fcarrier ×+

where 1

OSC

FT =

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 59

(This specification is subject to change without further notice)

6.9.3 Programming the Related Registers

When defining TCCX, refer to the operation of its related registers as shown in the

tables below.

TCCX Related Control Registers:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x08 IOC80 - - - “0” “0” TCCAEN/0 “0” “0”

0x09 IOC90 TCCBHE/0 TCCBEN/0 “0” “0” “0” TCCCEN/0 “0” “0”

0x0A IR CR

/IOCA0 TCCCSE/0 TCCCS2/0 TCCCS1/0 TCCCS0/0 IRE/0 HF/0 LGP/0 IROUTE/0

0x0F IMR

/IOCF0 LPWTE/0 HPWTE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0 “0” ICIE/0 TCIE/0

Related TCCX Status/Data Registers:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x0F ISR/RF LPWTF/0 HPWTF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0 “0” ICIF/0 TCIF/0

0x05 TCCA

/IOC51 TCCA7/0 TCCA6/0 TCCA5/0 TCCA4/0 TCCA3/0 TCCA2/0 TCCA1/0 TCCA0/0

0x06 TCCB

/IOC61 TCCB7/0 TCCB6/0 TCCB5/0 TCCB4/0 TCCB3/0 TCCB2/0 TCCB1/0 TCCB0/0

0x07 TCCBH

/IOC71 TCCBH7/0 TCCBH6/0 TCCBH5/0 TCCBH4/0 TCCBH3/0 TCCBH2/0 TCCBH1/0 TCCBH0/0

0x08 TCCC

/IOC81 TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0

EM78P142

8-Bit Microprocessor with OTP ROM

60 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.10 Oscillator

6.10.1 Oscillator Modes

The EM78P142 can be operated in six different oscillator modes, such as High Crystal

Oscillator Mode 1 (HXT1), High Crystal Oscillator Mode 2 (HXT2), Low Crystal

Oscillator Mode 1 (LXT1), Low Crystal Oscillator Mode 2 (LXT2), External RC

Oscillator Mode (ERC), and RC Oscillator Mode with Internal RC Oscillator Mode

(IRC). You can select one of them by programming the OSC2, OCS1, and OSC0 in the

Code Option register.

The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.

Oscillator Mode s OSC2 OSC1 OSC0

ERC1 (External RC oscillator mode); P70/OSCO acts as P70 0 0 0

ERC1 (External RC oscillator mode); P70/OSCO acts as OSCO 0 0 1

IRC2 (Internal RC oscillator mode); P70/OSCO acts as P70 0 1 0

IRC2 (Internal RC oscillator mode); P70/OSCO acts as OSCO 0 1 1

LXT13 (Frequency range of XT mode is 1MHz ~ 100kHz) 1 0 0

HXT13 (Frequency range of XT mode is 16 MHz ~ 6 MHz) 1 0 1

LXT23 (Frequency range of XT mode is 32kHz) 1 1 0

HXT23 (Frequency range of XT mode is 6 MHz ~ 1 MHz) (default) 1 1 1

1 In ERC mode, OSCI is used as oscillator pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4.

2 In IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4.

3 In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot

and should not be defined as normal I/O pins.

The maximum operating frequency limit of crystal/resonator at different VDDs, are as

follows:

Conditions VDD Max. Freq. (MHz)

2.1V 4

3.0V 8

Two clocks

4.5V 16

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 61

(This specification is subject to change without further notice)

6.10.2 Crystal Oscillator/Ceramic Resonators (Crystal)

The EM78P142 can be driven by an external clock signal through the OSCI pin as

illustrated below.

OSCI

OSCO

Figure 6-13 External Clock Input Circuit

In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or

ceramic resonator to generate oscillation. Figure 6-14 below depicts such a circuit.

The same applies to the HXT1 mode, HTX2 mode, LXT1 mode and LXT2 mode.

OSCI

OSCO

Crystal

RS C2

Figure 6-14 Crystal/Resonator Circuit

The following table provides the recommended values for C1 and C2. Since each

resonator has its own attribute, user should refer to the resonator specifications for the

appropriate values of C1 and C2. RS, a serial resistor, maybe required for AT strip cut

crystal or low frequency mode. Figure 6-17 is PCB layout suggestion. When the

system works in Crystal mode (16MHz), a 10KΩ is connected between OSCI and

OSCO.

EM78P142

8-Bit Microprocessor with OTP ROM

62 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Capacitor selection guide for crystal oscillator or ceramic resonators:

Oscillator Type Frequency Mode Frequency C1(pF) C2(pF)

100kHz 67pF 67pF

200kHz 30pF 30pF

455kHz 30pF 30pF

LXT

(100K~1 MHz)

1MHz 30pF 30pF

1.0 MHz 30pF 30pF

2.0 MHz 30pF 30pF

Ceramic Resonators

MXT

(1M~6 MHz)

4.0 MHz 30pF 30pF

LXT2 (32.768kHz) 32.768kHz 40pF 40pF

100kHz 67pF 67pF

200kHz 30pF 30pF

455kHz 30pF 30pF

LXT1

(100K~1 MHz)

1MHz 30pF 30pF

455kHz 30pF 30pF

1.0 MHz 30pF 30pF

2.0 MHz 30pF 30pF

4.0 MHz 30pF 30pF

HXT2

(1~6 MHz)

6.0 MHz 30pF 30pF

8.0 MHz 30pF 30pF

10.0 MHz 30pF 30pF

12.0 MHz 30pF 30pF

Crystal Oscillator

HXT1

(6~16 MHz)

16.0 MHz 15pF 15pF

Circuit diagrams for serial and parallel modes Crystal/Resonator:

OSCI

7404

330 330

Crystal

7404 7404

Figure 6-15 Serial Mode Crystal/Resonator Circuit Diagram

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 63

(This specification is subject to change without further notice)

OSCI

7404

C1 C2

10K4.7K Vdd

10K

Crystal

Figure 6-16 Parallel Mode Crystal/Resonator Circuit Diagram

Figure 6-17 Parallel Mode Crystal/Resonator Circuit Diagram

EM78P142

8-Bit Microprocessor with OTP ROM

64 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.10.3 External RC Oscillator Mode

For some applications that do not require

precise timing calculation, the RC

oscillator (Figure 6-18) could offer an

effective cost savings. Nevertheless, it

should be noted that the frequency of the

RC oscillator is influenced by the supply

voltage, the values of the resistor (Rext),

the capacitor (Cext), and even by the

operation temperature. Moreover, the

frequency also changes slightly from one

chip to another due to the manufacturing

process variation.

OSCI

Vcc

Rext

Cext

Figure 6-18 External RC Oscillator Mode

Circuit

In order to maintain a stable system frequency, the values of the Cext should be no less

than 20 pF, and the value of Rext should not be greater than 1 MΩ. If the frequency

cannot be kept within this range, the frequency can be affected easily by noise,

humidity, and leakage.

The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the

contrary, for very low Rext values, for instance, 1 KΩ, the oscillator will become

unstable because the NMOS cannot correctly discharge the capacitance current.

Based on the above reasons, it must be kept in mind that all supply voltage, the

operation temperature, the components of the RC oscillator, the package types, and

the way the PCB is layout, have certain effect on the system frequency.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 65

(This specification is subject to change without further notice)

The RC Oscillator frequencies:

Cext Rext Average Fosc 5V, 25°C Average Fosc 3V, 25°C

3.3k 3.5 MHz 3.0 MHz

5.1k 2.4 MHz 2.2 MHz

10k 1.27 MHz 1.24 MHz

20 pF

100k 140kHz 143kHz

3.3k 1.21 MHz 1.18 MHz

5.1k 805kHz 790kHz

10k 420kHz 418kHz

100 pF

100k 45kHz 46kHz

3.3k 550kHz 526kHz

5.1k 364kHz 350kHz

10k 188kHz 185kHz

300 pF

100k 20kHz 20kHz

Note: 1: Measured based on DIP packages.

2: The values are for design reference only.

3: The frequency drift is ± 30%

6.10.4 Internal RC Oscillator Mode

The EM78P142 offers a versatile internal RC mode with default frequency value of

4MHz. Internal RC oscillator mode has other frequencies (16MHz, 1MHz, and 455kHz)

that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below

describes the EM78P142 internal RC drift with voltage, temperature, and process

variations.

Internal RC Drift Rate (Ta=25°C, VDD=5V±5%, VSS=0V)

Drift Rate

Internal

RC Frequency Temperature

(-40°C ~+85°C) Voltage

(2.3V~3.9V~5.5V) Process Total

4 MHz ±5% ±5% ±4% ±14%

16 MHz ±5% ±5% ±4% ±14%

1 MHz ±5% ±5% ±4% ±14%

455kHz ±5% ±5% ±4% ±14%

Note: Theoretical values are for reference only. Actual values may vary depending on the actual process.

EM78P142

8-Bit Microprocessor with OTP ROM

66 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.11 Power-on Considerations

Any microcontroller is not warranted to start operating properly before the power supply

stabilizes in steady state. The EM78P142 POR voltage range is 1.6V ~ 1.8V. Under

customer application, when power is switched OFF, Vdd must drop below 1.6V and

remains at OFF state for 10µs before power can be switched ON again. Subsequently,

the EM78P142 will reset and work normally. The extra external reset circuit will work

well if Vdd rises fast enough (50ms or less). However, under critical applications, extra

devices are still required to assist in solving power-on problems.

6.11.1 Programmable WDT Time-out Period

The Option word (WDTPS) is used to define the WDT time-out period (18ms5 or

4.5ms6). Theoretically, the range is from 4.5ms or 18ms. For most crystal or ceramic

resonators, the lower the operation frequency is, the longer is the required set-up time.

6.11.2 External Power-on Reset Circuit

The circuit shown in the

following figure implements

an external RC to produce a

reset pulse. The pulse

width (time constant) should

be kept long enough to

allow the Vdd to reach the

minimum operating voltage.

This circuit is used when the

power supply has a slow

power rise time. Because

/RESET

VDD

Rin C

Figure 6-19 External Power-on Reset Circuit

the current leakage from the /RESET pin is about ±5µA, it is recommended that R

should not be greater than 40K. This way, the voltage at Pin /RESET is held below 0.2V.

The diode (D) functions as a short circuit at power-down. The “C” capacitor is

discharged rapidly and fully. Rin, the current-limited resistor, prevents high current

discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.

5 VDD=5V, WDT time-out period = 16.5ms ± 30%.

VDD=3V, WDT time-out period = 18ms ± 30%.

6 VDD=5V, WDT time-out period = 4.2ms ± 30%.

VDD=3V, WDT time-out period = 4.5ms ± 30%.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 67

(This specification is subject to change without further notice)

6.11.3 Residual Voltage Pro t ection

When the battery is replaced, device power (Vdd) is removed but residual voltage

remains. The residual voltage may trip below Vdd minimum, but not to zero. This

condition may cause a poor power-on reset. Figure 6-20 and Figure 6-21 show how to

create a protection circuit against residual voltage.

/RESET

VDD

100K

1N4684

10K

33K

VDD

Figure 6-20 Residual Voltage Protection Circuit 1

/RESET

VDD

R3 R2

Figure 6-21 Residual Voltage Protection Circuit 2

EM78P142

8-Bit Microprocessor with OTP ROM

68 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.12 Code Option

EM78P142 has two CODE option words and one Customer ID word that are not part of

the normal program memory.

Word 0 Word1 Word 2

Bit 12 ~ Bit 0 Bit 12 ~ Bit 0 Bit12 ~ Bit 0

6.12.1 Code Option Register (Word 0)

Word 0

Bit Bit 12 Bi t 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bit 1 Bit 0

Mne

monic LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0 − Protect

1 High High High High 4

clocks Disable High High High − Disable

0 Low Low Low Low 2

clocks Enable Low Low Low − Enable

Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits

LVR1, LVR0 VDD Reset Level VDD Release Level

11 NA (Power-on Reset) (Default)

10 2.4V 2.6V

01 3.5V 3.7V

00 4.0V 4.2V

Bits 10~9 (TYPE1 ~ TYPE0): Type selection for EM78P142.

TYPE 1, TYPE 0 MCU Type

00 Not used

01 EM78P142 – 10Pin

10 Not used

11 Not used

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 69

(This specification is subject to change without further notice)

Bit 8 (CLKS): Instruction period option bit

0 = two oscillator periods

1 = four oscillator periods (default)

Refer to Section 6.15 for Instruction Set

Bit 7 (ENWDTB): Watchdog timer enable bit

0 = Enable

1 = Disable (default)

Bits 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Modes Selection bits

Oscillator Mode s OSC2 OSC1 OSC0

ERC1 (External RC oscillator mode); P70/OSCO acts as P70 0 0 0

ERC1 (External RC oscillator mode); P70/OSCO acts as OSCO 0 0 1

IRC2 (Internal RC oscillator mode); P70/OSCO acts as P70 0 1 0

IRC2 (Internal RC oscillator mode); P70/OSCO acts as OSCO 0 1 1

LXT13 (Frequency range of XT, mode is 1MHz ~ 100kHz) 1 0 0

HXT13 (Frequency range of XT mode is 16MHz ~ 6MHz) 1 0 1

LXT23 (Frequency range of XT mode is 32kHz) 1 1 0

HXT23 (Frequency range of XT mode is 6MHz ~ 1MHz) (default) 1 1 1

1 In ERC mode, OSCI is used as oscillator pin. OSCO/P54 is defined by code option Word 0 Bit 6 ~ Bit 4.

2 In IRC mode, P54 is normal I/O pin. OSCO/P54 is defined by code option Word 0 Bit 6 ~ Bit 4.

3 In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot

and should not be defined as normal I/O pins.

Bit 3: Not used, (reserved). This bit is set to “0” all the time.

Bits 2 ~ 0 (Protect): Protect Bits

Protect Bits Protect

0 Enable

1 Disable (default)

EM78P142

8-Bit Microprocessor with OTP ROM

70 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.12.2 Code Option Register (Word 1)

Word 1

Bit Bit 12 Bit 11 Bi t 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mne

monic – – – RCOUT – – – C3 C2 C1 C0 RCM1 RCM0

1 – – –

System

_clk – – – High High High High High High

0 – – –

Open_

drain – – – Low Low Low Low Low Low

Bit 12: Not used, (reserved). This bit is set to “0” all the time.

Bits 11~10: Not used, (reserved). These bits are set to “1” all the time.

Bit 9 (RCOUT): Instruction clock output enable bit in IRC or ERC mode

0 = OSCO pin is open drain

1 = OSCO output instruction clock (default)

Bit 8 & Bit 7: These bits must set to “0” all the time

Bit 6: Not used, (reserved). This bit is set to “1” all the time.

Bit 5, 4, 3, & Bit 2 (C3, C2, C1, C0): Calibrator of internal RC mode

C3, C2, C1, and C0 must be set to “1” only (auto-calibration).

Bit 1 & Bit 0 (RCM1, RCM0): RC mode selection bits

RCM 1 RCM 0 Frequency (MHz)

1 1 4 (Default)

1 0 16

0 1 1

0 0 455kHz

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 71

(This specification is subject to change without further notice)

6.12.3 Customer ID Register (Word 2)

Word 2

Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mne

monic – – – NRM RESET

ENB – WDTPS ID5 ID4 ID3 ID2 ID1 ID0

1 – – – MOD1 P71 – 18ms High High High High High High

0 – – – MOD2 /RESET – 4.5ms Low Low Low Low Low Low

Bits 12 ~ 11: Not used (reserved). These bits are set to “1” all the time.

Bit 10: Not used, (reserved). This bit is set to “0” all the time.

Bit 9 (N RM): 0 = Noise reject Mode 2,

For multi-time circuit use, such as key scan and LED output.

1 = Noise reject Mode 1. For General input or output use

(Default)

Bit 8 (RESETENB): RESET/P71 pin select bit

0 = P71 set to /RESET pin

1 = P71 is general purpose input pin or open-drain for output

Port (default)

Bit 7: Not used (reserved). This bit is set to “1” all the time.

Bit 6 (WD TPS): WDT Time-out Period Selection bit

WDT Time Watchdog Timer*

1 18 ms (Default)

0 4.5 ms

*Theoretical values, for reference only

Bits 5 ~ 0: Customer’s ID code

EM78P142

8-Bit Microprocessor with OTP ROM

72 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.13 Low Voltage Detector/Low Voltage Reset

The low voltage reset (LVR) and the low voltage detector (LVD) are designed for

unstable power situation, such as external power noise interference or in EMS test

condition.

When LVR is enabled, the system supply voltage (Vdd) drops below Vdd reset level

(VRESET) and remains at 10µs, the system reset will occur and the system will keep on

reset status. The system will remain at reset status until Vdd voltage rises above Vdd

release level. Refer to Figure 6-26.

If Vdd drops below low voltage detector level, /LVD (the Bit 7 of RE) is cleared to “0’ to

show low voltage signal when LVD is enabled. This signal can be used for low voltage

detection.

6.13.1 Low Voltage Reset

LVR property is set at Bits 12, 11 of Code Option Word 0. The detailed operation mode

is as follows:

Word 0

Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0 − Protect

Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits.

LVR1, LVR0 VDD Reset Level VD D Release Level

11 NA (Power-on Reset)

10 2.4V 2.6V

01 3.5V 3.7V

00 4.0V 4.2V

6.13.2 Low Voltage Detector

LVD property is set at the register, detailed operation mode is as follows:

6.13.2.1 IOCD1 (LVD Control Register)

Bit 7 6 5 4 3 2 1 0

EM78P142 - - - - LVDIE LVDEN LVD1 LVD0

ICE341N TYPE1 TYPE0 LVR1 LVR0 LVDIE LVDEN LVD1 LVD0

NOTE

■ IOCD1< 3 > register is both readable and writable

■ Individual interrupt is enabled by setting its associated control bit in the IOCD1< 4 >

to "1."

■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI

instruct ion. Refer to Figure 6-8 (Interrupt Input Circuit) und er Section 6.6 (I nterru pt).

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 73

(This specification is subject to change without further notice)

Bit 3 (LVDIE): Low voltage Detector interrupt enable bit.

0 = Disable Low voltage Detector interrupt

1 = Enable Low voltage Detector interrupt

When the detect-low-level-voltage state is used to enter an interrupt

vector or enter next instruction, the LVDIE bit must be set to “Enable“.

Bit 2 (LVDEN): Low Voltage Detector Enable bit

0 = Low voltage detector disable

1 = Low voltage detector enable

Bits 1~0 (LVD1:0): Low Voltage Detector level bits.

LVDEN LVD1, LVD0 LVD voltage Interrupt Level /LVD

Vdd ≤ 2.2V 0

1 11 Vdd > 2.2V 1

Vdd ≤ 3.3V 0

1 10 Vdd > 3.3V 1

Vdd ≤ 4.0V 0

1 01 Vdd > 4.0V 1

Vdd ≤ 4.5V 0

1 00 Vdd > 4.5V 1

0 ×× NA 0

6.13.2.2 RE (Interrupt Status 2 & Wake-up Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

/LVD LVDIF ADIF “0” ADWE “0” ICWE LVDWE

NOTE

■ RE < 6, 5 > can be cleared by instruction but cannot be set.

■ IOCE0 is the interrupt mask register.

■ Reading RE will result to "logic AND" of RE and IOCE0.

Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin

voltage is lower than LVD voltage interrupt level (selected by LVD1 and

LVD0), this bit will be cleared.

0 = Low voltage is detected.

1 = Low voltage is not detected or LVD function is disabled.

Bit 6 (LVDIF): Low Voltage Detector interrupt flag

LVDIF reset to “0” by software or hardware.

Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit.

0 = Disable Low Voltage Detect wake-up.

1 = Enable Low Voltage Detect wake-up.

When the Low Voltage Detect is used to enter an interrupt vector or to

wake up the IC from sleep/idle with Low Voltage Detect running, the

LVDWE bit must be set to “Enable“.

EM78P142

8-Bit Microprocessor with OTP ROM

74 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

6.13.3 Programming Process

Follow these steps to obtain data from the LVD:

1. Write to the two bits (LVD1: LVD0) on the LVDCR register to define the LVD level.

2. Set the LVDWE bit, if the wake-up function is employed.

3. Set the LVDIE bit, if the interrupt function is employed.

4. Write “ENI” instruction, if the interrupt function is employed.

5. Set LVDEN bit to 1

6. Write “SLEP” instruction or Polling /LVD bit.

7. Clear the low voltage detector interrupt flag bit (LVDIF) when Low Voltage Detector

interrupt occurred.

The LVD module uses the internal circuit. When LVDEN (Bit 2 of IOCD1) is set to “1”,

the LVD module is enabled.

When LVDWE (bit 0 of RE) is set to “1”, the LVD module will continue to operate during

sleep/idle mode. If Vdd drops slowly and crosses the detect point (VLVD), the LVDIF

(Bit 6 of RE) will be set to ”1”, the /LVD (Bit 7 of RE) will be cleared to “0”, and the

system will wake up from Sleep/Idle mode. When a system reset occurs, the LVDIF will

be cleared.

When Vdd remains above VLVD, LVDIF is kept at “0” and /LVD is kept at “1”. When

Vdd drops below VLVD, LVDIF is set to “1” and /LVD is kept at “0”. If ENI instruction is

executed, LVDIF will be set to “1”, and the next instruction will branch to interrupt Vector

021H. The LVDIF is cleared to “0” by software. Refer Figure 6-24 below.

Vdd

LVDIF

Internal

Reset

VLVD

VRESET

LVDIF is cleared by

software

Vdd < Vreset not longer than 10us, the system still keeps on operating

<LVR Voltage drop

18ms

System occur reset

>LVR Voltage drop

Figure 6-22 LVD/LVR Waveform Situation

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 75

(This specification is subject to change without further notice)

6.14 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and one

or more operands. Normally, all instructions are executed within one single instruction

cycle (one instruction consists of two oscillator time periods), unless the program

counter is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of

arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.).

In addition, the instruction set has the following features:

1. Every bit of any register can be set, cleared, or tested directly.

2. The I/O registers can be regarded as general registers. That is, the same

instruction can operate on I/O registers.

The following symbols are used in the Instruction Set table:

Convention:

R = Register designator that specifies which one of the registers (including operation and general purpose

registers) is to be utilized by the instruction.

Bits 6 and 7 in R4 determine the selected register bank.

b = Bit field designator that selects the value for the bit located in the register R and which affects the

operation.

k = 8 or 10-bit constant or literal value

Binary Instruction Hex Mnemonic Operation Status Affected

0 0000 0000 0000 0000 NOP No Operation None

0 0000 0000 0001 0001 DAA Decimal Adjust A C

0 0000 0000 0010 0002 CONTW A → CONT None

0 0000 0000 0011 0003 SLEP 0 → WDT, Stop oscillator T, P

0 0000 0000 0100 0004 WDTC 0 → WDT T, P

0 0000 0000 rrrr 000r IOW R A → IOCR None1

0 0000 0001 0000 0010 ENI Enable Interrupt None

0 0000 0001 0001 0011 DISI Disable Interrupt None

0 0000 0001 0010 0012 RET [Top of Stack] → PC None

0 0000 0001 0011 0013 RETI [Top of Stack] → PC,

Enable Interrupt None

0 0000 0001 0100 0014 CONTR CONT → A None

0 0000 0001 rrrr 001r IOR R IOCR → A None1

0 0000 01rr rrrr 00rr MOV R,A A → R None

0 0000 1000 0000 0080 CLRA 0 → A Z

0 0000 11rr rrrr 00rr CLR R 0 → R Z

0 0001 00rr rrrr 01rr SUB A,R R-A → A Z, C, DC

0 0001 01rr rrrr 01rr SUB R,A R-A → R Z, C, DC

0 0001 10rr rrrr 01rr DECA R R-1 → A Z

0 0001 11rr rrrr 01rr DEC R R-1 → R Z

0 0010 00rr rrrr 02rr OR A,R A ∨ VR → A Z

0 0010 01rr rrrr 02rr OR R,A A ∨ VR → R Z

EM78P142

8-Bit Microprocessor with OTP ROM

76 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Binary Instruction Hex Mnemonic Operation Status Affected

0 0010 10rr rrrr 02rr AND A,R A & R → A Z

0 0010 11rr rrrr 02rr AND R,A A & R → R Z

0 0011 00rr rrrr 03rr XOR A,R A ⊕ R → A Z

0 0011 01rr rrrr 03rr XOR R,A A ⊕ R → R Z

0 0011 10rr rrrr 03rr ADD A,R A + R → A Z, C, DC

0 0011 11rr rrrr 03rr ADD R,A A + R → R Z, C, DC

0 0100 00rr rrrr 04rr MOV A,R R → A Z

0 0100 01rr rrrr 04rr MOV R,R R → R Z

0 0100 10rr rrrr 04rr COMA R /R → A Z

0 0100 11rr rrrr 04rr COM R /R → R Z

0 0101 00rr rrrr 05rr INCA R R+1 → A Z

0 0101 01rr rrrr 05rr INC R R+1 → R Z

0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None

0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None

0 0110 00rr rrrr 06rr RRCA R R(n) → A(n-1), R(0) → C,

C → A(7) C

0 0110 01rr rrrr 06rr RRC R R(n) → R(n-1), R(0) → C,

C → R(7) C

0 0110 10rr rrrr 06rr RLCA R R(n) → A(n+1), R(7) → C,

C → A(0) C

0 0110 11rr rrrr 06rr RLC R R(n) → R(n+1), R(7) → C,

C → R(0) C

0 0111 00rr rrrr 07rr SWAPA R R(0-3) → A(4-7),

R(4-7) → A(0-3) None

0 0111 01rr rrrr 07rr SWAP R R(0-3) ↔ R(4-7) None

0 0111 10rr rrrr 07rr JZA R R+1 → A, skip if zero None

0 0111 11rr rrrr 07rr JZ R R+1 → R, skip if zero None

0 100b bbrr rrrr 0xxx BC R,b 0 → R(b) None 2

0 101b bbrr rrrr 0xxx BS R,b 1 → R(b) None 3

0 110b bbrr rrrr 0xxx JBC R,b if R(b)=0, skip None

0 111b bbrr rrrr 0xxx JBS R,b if R(b)=1, skip None

1 00kk kkkk kkkk 1kkk CALL k PC+1 → [SP], (Page, k) →

PC None

1 01kk kkkk kkkk 1kkk JMP k (Page, k) → PC None

1 1000 kkkk kkkk 18kk MOV A,k k → A None

1 1001 kkkk kkkk 19kk OR A,k A ∨ k → A Z

1 1010 kkkk kkkk 1Akk AND A,k A & k → A Z

1 1011 kkkk kkkk 1Bkk XOR A,k A ⊕ k → A Z

1 1100 kkkk kkkk 1Ckk RETL k k → A, [Top of Stack] → PC None

1 1101 kkkk kkkk 1Dkk SUB A,k k-A → A Z, C, DC

1 1110 1001 000k 1E9k BANK k k →R4(6) None

1 1110 1010 kkkk

k kkkk kkkk kkkk 1EAK LCALL k PC+1→[SP], k→PC None

1 1110 1011 kkkk

k kkkk kkkk kkkk 1EBK LJMP k k→PC None

Note: 1 This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only.

2 This instruction is not recommended for RF operation.

3 This instruction cannot operate under RF.

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 77

(This specification is subject to change without further notice)

7 Absolute Maximum Ratings

Items Rating

Temperature under bias -40°C to 85°C

Storage temperature -65°C to 150°C

Input voltage Vss-0.3V to Vdd+0.5V

Output voltage Vss-0.3V to Vdd+0.5V

Working Voltage 2.3V to 5.5V

Working Frequency DC to 16MHz

8 DC Electrical Characteristics

Ta= 25°C, VDD= 5.0V, VSS= 0V

Sy mbol Parameter Condition Min. Typ. Max. Unit

FXT Crystal: VDD to 5V Two cycle with two clocks 32.768k 4 16 MHz

ERC ERC: VDD to 5V R: 5.1KΩ, C: 100 pF 760 950 1140 kHz

VIHRC Input High Threshold

Voltage (Schmitt Trigger) OSCI in RC mode 3.9 4 4.1 V

IERC1 Sink current VI from low to high, VI=5V 21 22 23 mA

VILRC Input Low Threshold

Voltage (Schmitt Trigger) OSCI in RC mode 1.7 1.8 1.9 V

IERC2 Sink current VI from high to low, VI=2V 16 17 18 mA

IIL Input Leakage Current for

input pins VIN = VDD, VSS -1 0 1 µA

VIH1 Input High Voltage

(Schmitt Trigger) Ports 5, 6, 7 0.7Vdd − Vdd+0.3V V

VIL1 Input Low Voltage

(Schmitt Trigger ) Ports 5, 6, 7 -0.3V − 0.3Vdd V

VIHT1 Input High Threshold

Voltage (Schmitt Trigger) /RESET 0.7Vdd − Vdd+0.3V V

VILT1 Input Low Threshold

Voltage (Schmitt trigger) /RESET -0.3V − 0.3Vdd V

VIHT2 Input High Threshold

Voltage (Schmitt Trigger) TCC,INT 0.7Vdd − Vdd+0.3V V

VILT2 Input Low Threshold

Voltage (Schmitt Trigger) TCC,INT -0.3V − 0.3Vdd V

VIHX1 Clock Input High Voltage OSCI in crystal mode 2.9 3.0 3.1 V

VILX1 Clock Input Low Voltage OSCI in crystal mode 1.7 1.8 1.9 V

IOH1 Output High Voltage

(Ports 5, 6, 7) VOH = 0.9VDD − -10 − mA

EM78P142

8-Bit Microprocessor with OTP ROM

78 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

Sy mbol Parameter Condition Min. Typ. Max. Unit

IOL1 Output Low Voltage

(Ports 5, 6,7) VOL = 0.1VDD − 20 − mA

IPH Pull-high current Pull-high active, input pin at VSS -50 − -90 µA

IPL Pull-low current Pull-low active, input pin at Vdd 20 − 60 µA

ISB1 Power down current All input and I/O pins at VDD,

output pin floating, WDT disabled − − 2.0 µA

ISB2 Power down current All input and I/O pins at VDD,

output pin floating, WDT enabled − − 10 µA

ICC1 Operating supply current

at two clocks

/RESET= 'High', Fosc=32kHz

(Crystal type, CLKS="0"),

Output pin floating, WDT disabled

− 15 20 µA

ICC2 Operating supply current

at two clocks

/RESET= 'High', Fosc=32kHz

(Crystal type,CLKS="0"), output

pin floating, WDT enabled

− 15 25 µA

ICC3 Operating supply current

at two clocks

/RESET= 'High', Fosc=4MHz

(Crystal type, CLKS="0"), output

pin floating, WDT enabled

− 1.5 1.7 mA

ICC4 Operating supply current

at two clocks

/RESET= 'High', Fosc=10MHz

(Crystal type, CLKS="0"),

Output pin floating, WDT enabled

− 2.8 3.0 mA

Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.

2. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical results at 25°C.

These data are for design reference only.

Internal RC Electrical Characteristics (Ta=25°C, VDD=5 V, VSS=0V)

Drift Rate

Internal RC Temperature Voltage Min. Typ. Max.

4 MHz 25°C 5V 3.84 MHz 4 MHz 4.16 MHz

16 MHz 25°C 5V 15.36 MHz 16 MHz 16.64 MHz

1 MHz 25°C 5V 0.96 MHz 1 MHz 1.04 MHz

455kHz 25°C 5V 436.8kHz 455kHz 473.2kHz

Internal RC Electrical Characteristics (Ta=-40 ~85°C, VDD=2.2~5.5 V, VSS=0V)

Drift Rate

Internal RC Temperature Voltage Min. Typ. Max.

4 MHz -40°C ~85°C 2.2V~5.5V 3.44 MHz 4 MHz 4.56 MHz

16 MHz -40°C ~85°C 2.2V~5.5V 13.76 MHz 16 MHz 18.24 MHz

1 MHz -40°C ~85°C 2.2V~5.5V 0.86 MHz 1 MHz 1.14 MHz

455kHz -40°C ~85°C 2.2V~5.5V 391.3kHz 455kHz 518.7kHz

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 79

(This specification is subject to change without further notice)

8.1 AD Con verter Characteristic

Vdd=2.5V to 5.5V, Vss=0V, Ta=-40 to 85°C

Sy mbol Parameter Condition Min. Typ. Max. Unit

VAREF 2.5 − Vdd V

VASS Analog reference voltage VAREF - VASS ≥ 2.5V Vss − Vss V

VAI Analog input voltage − VASS − VAREF V

Ivdd 750 850 1000 µA

IAI1 Ivref Analog supply current VDD=VAREF=5.0V, VASS = 0.0V

(V reference from Vdd) -10 0 +10 µA

Ivdd 500 600 820 µA

IAI2 IVref Analog supply current VDD=VAREF=5.0V, VASS = 0.0V

(V reference from VREF) 200 250 300 µA

IOP OP current

VDD=5.0V, OP used

Output voltage swing from 0.2V

to 4.8V

450 550 650 µA

RN1 Resolution ADREF=0, Internal VDD

VDD=5.0V, VSS = 0.0V − 9

−10 Bits

RN2 Resolution ADREF=1, External VREF

VDD=VREF=5.0V, VSS = 0.0V − 11

12 Bits

LN1 Linearity error VDD = 2.5 to 5.5V Ta=25°C 0 ±4 ±8 LSB

LN2 Linearity error VDD= 2.5 to 5.5V Ta=25°C 0 ±2 ±4 LSB

DNL Differential nonlinear error VDD = 2.5 to 5.5V Ta=25°C 0 ±0.5 ±0.9 LSB

FSE1 Full scale error VDD=VAREF=5.0V, VASS = 0.0V ±0 ±4 ±8 LSB

FSE2 Full scale error VDD=VREF=5.0V, VSS = 0.0V ±0 ±2 ±4 LSB

OE Offset error VDD=VAREF=5.0V, VASS = 0.0V ±0 ±2 ±4 LSB

ZAI Recommended impedance of

analog voltage source − 0 8 10 KΩ

TAD ADC clock duration VDD=VAREF=5.0V, VASS = 0.0V 4 − − µs

TCN AD conversion time VDD=VAREF=5.0V, VASS = 0.0V 15 − 15 TAD

ADIV ADC OP input voltage range VDD=VAREF=5.0V, VASS = 0.0V 0 − V

AREF V

0 0.2 0.3

ADOV ADC OP output voltage swing VDD=VAREF=5.0V, VASS =0.0V,

RL=10KΩ 4.7 4.8 5 V

ADSR ADC OP slew rate VDD=VAREF=5.0V, VASS = 0.0V 0.1 0.3 − V/µs

PSR Power Supply Rejection VDD=5.0V±0.5V ±0 − ±2 LSB

Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.

2. There is no current consumption when ADC is off other than minor leakage current.

3. AD conversion result will not decrease when an increase of input voltage and no missing code will result.

4. These parameters are subject to change without further notice.

EM78P142

8-Bit Microprocessor with OTP ROM

80 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

8.2 Device Characteristics

The graphs below were derived based on a limited number of samples and they are

provided for reference only. Hence, the device characteristic shown herein cannot be

guaranteed as fully accurate. In these graphs, the data may be out of the specified

operating warranted range.

IRC OSC Frequency (VDD=3V)

-40-200 25705085

Temperature oC

Frequency (MHz) .

Figure 8-1 Internal RC OSC Frequency vs. Temperature, VDD=3V

IRC OSC Frequency (VDD=5 V)

-40-200 25507085

Temperature (℃)

Frequency (M Hz) .

Figure 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 81

(This specification is subject to change without further notice)

9 AC Electrical Characteristic

Ta=-40 to 85°C, VDD=5V±5%, VSS=0V

Sy mbol Parameter Conditions Min Type Max Unit

Dclk Input CLK duty cycle – 45 50 55 %

Crystal type 100 – DC ns

Tins Instruction cycle time

(CLKS="0") RC type 500 – DC ns

Ttcc TCC input time period – (Tins+20)/N*– – ns

Tdrh Device reset hold time Ta = 25°C 11.3 16.2 21.6 ms

Trst /RESET pulse width Ta = 25°C 2000 – – ns

Twdt Watchdog timer duration Ta = 25°C 11.3 16.2 21.6 ms

Tset Input pin setup time – – 0 – ns

Thold Input pin hold time – 15 20 25 ns

Tdelay Output pin delay time Cload = 20 pF 45 50 55 ns

Tdrc ERC delay time Ta = 25°C 1 3 5 ns

Note:1. *N = selected prescaler ratio

2. Twdt1: The Option Word 1 (WDTPS) is used to define the oscillator set-up time. WDT timeout

length is the same as set-up time (18ms).

3. Twdt2: The Option Word 1 (WDTPS) is used to define the oscillator set-up time. WDT timeout

length is the same as set-up time (4.5ms).

4. These parameters are hypothetical (not tested) and are provided for design reference only.

5. Data under Minimum, Typical, and Maximum (Min, Typ, and Max) columns are based on

hypothetical results at 25°C. These data are for design reference use only.

6. The Watchdog timer duration is determined by code option Word1 (WDTPS).

EM78P142

8-Bit Microprocessor with OTP ROM

82 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

10 Timing Diagrams

RESET Timing (CLK="0")

CLK

/RESET

NOP Instruction 1

Executed

Tdrh

TCC Input Timing (CLKS="0")

CLK

TCC

Ttcc

Tins

AC T esting : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing

measurements are m ade at 0.75VDD for log ic "1",and 0.25VDD for logic "0".

AC Test Input/Output W aveform

VDD-0.5V

GND+0.5V

0.75VDD

0.25VDDTEST PO INTS

0.75VDD

0.25VDD

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 83

(This specification is subject to change without further notice)

APPENDIX

A Package Type

OTP MCU Package Type Pin Count Package Size

EM78P142SS10J/S SSOP 10 150 mil

Green products do not contain hazardous substances.

The third edition of Sony SS-00259 standard.

Pb contents should be less the 100ppm

Pb contents comply with Sony specs.

Part No. EM78P142xJ /xS

Electroplate type Pure Tin

Ingredient (%) Sn: 100%

Melting point (°C) 232°C

Electrical resistivity

(µΩ-cm) 11.4

Hardness (hv) 8~10

Elongation (%) >50%

EM78P142

8-Bit Microprocessor with OTP ROM

84 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

B Packaging Configuration

B.1 EM78P142SS10

TITLE:

SSOP 10L (150MIL)PACKAGE

OUTLINE DIMENSION

Unit : mm

Scale: Free

File :

SSOP 10 L

Material:

Edtion: A

Sheet:1 of 1

Symbal Min Normal Max

A1.35 1.55 1.75

A1 0.075 0.175 0.275

A2 1.18 1.38 1.58

D4.7 4.9 5.1

E5.8 6.0 6.2

E1 3.7 3.9 4.1

b0.406 0.496

b1 0.406 0.456

c0.178 0.278

c1 0.178 0.228

L0.55 0.65 0.75

θ0° - 7°

1.00TYP

Figure B-1 EM78P142 10-pin SSOP Package Type

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 85

(This specification is subject to change without further notice)

C Quality Assurance and Reliability

Test Category Test Conditions Remarks

Solderability Solder temperature=245 ± 5°C, for 5 seconds up to the

stopper using a rosin-type flux −

Step 1: TCT, 65°C (15mins)~150°C (15mins), 10 cycles

Step 2: Bake at 125°C, TD (durance)=24 hrs

Step 3: Soak at 30°C /60% , TD (durance)=192 hrs

Pre-condition Step 4: IR flow 3 cycles

(Pkg thickness ≥ 2.5mm or

Pkg volume ≥ 350mm3 ----225 ± 5°C)

(Pkg thickness ≤ 2.5mm or

Pkg volume ≤ 350mm3 ----240 ± 5°C )

For SMD IC (such as

SOP, QFP, SOJ, etc)

Temperature cycle test -65° (15mins)~150°C (15mins), 200 cycles −

Pressure cooker test TA =121°C, RH=100%, pressure=2 atm,

TD (durance) = 96 hrs −

High temperature /

High humidity test TA=85°C , RH=85% , TD (durance)=168 , 500 hrs −

High-temperature

storage life TA=150°C, TD (durance)=500, 1000 hrs −

High-temperature

operating life

TA=125°C, VCC=Max. operating voltage,

TD (durance) =168, 500, 1000 hrs −

Latch-up TA=25°C, VCC=Max. operating voltage, 150mA/20V −

ESD (HBM) TA=25°C, ≥ | ± 3KV |

ESD (MM) TA=25°C, ≥ | ± 300V |

IP_ND,OP_ND,IO_ND

IP_NS,OP_NS,IO_NS

IP_PD,OP_PD,IO_PD,

IP_PS,OP_PS,IO_PS,

VDD-VSS(+),VDD_VSS

(-)mode

C.1 Address Trap Detect

An address trap detect is one of the MCU embedded fail-safe functions that detects

MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an

instruction from a certain section of ROM, an internal recovery circuit is auto started. If

a noise-caused address error is detected, the MCU will repeat execution of the

program until the noise is eliminated. The MCU will then continue to execute the next

program.

EM78P142

8-Bit Microprocessor with OTP ROM

86 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

D How to Use the ICE 341N

ICE 341 for EM78P142

W1 P55/OSCI Pin Select

OSCI P55

I/O Port (P55)

OSCI P55

Crystal, ERC (OSCI)

Oscillator IRC Modes select I/O Port (P55)

Oscillator Crystal, ERC Modes select Crystal (OSCI)

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 87

(This specification is subject to change without further notice)

JP3

P56 P52 P53 P54

P57 P51 P50 P55

RESE

T/P71 GND

P60 P61

P70

VDD

P67 P66 P64P65

P63P62

202

EM78P142

8-Bit Microprocessor with OTP ROM

88 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)

DIP IDC PLUG

P56

P51

P50

P55

P57

P52

P53

P54

P70

VDD

P67

P66

RESE

T/P71

GND

P60

P61

P63

P62

P64

P65

201

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V 1 .0) 01.25.200 8 • 89

(This specification is subject to change without further notice)

E Comparison between V- Pa ckage an d U-Pa ckage Versio n

This microcontroller device is comprised of the older V-package version and the newer

U-package version. In the newer U-package version, a Code Option NRM is added

and various features such as Crystal mode Operating frequency range and IRC mode

wake-up time from sleep mode to normal mode, have been modified to favorably meet

users’ requirements. The following table is provided for quick comparison between the

two package version and for user convenience in the choice of the most suitable

product for their application.

Item EM78P142-V EM78P142-U

Level Voltage Reset 4.0V, 3.5V, 2.7V 4.0V, 3.5V, 2.4V

Crystal mode

Operating frequency range

at 0°C~ 70°C

DC ~ 12 MHz, 4.5V

DC ~ 8 MHz, 3.0V

DC ~ 4 MHz, 2.1V

DC ~ 16 MHz, 4.5V

DC ~ 8 MHz, 3.0V

DC ~ 4 MHz, 2.1V

IRC mode wake-up time

( Sleep → Normal )

Condition: 5V, 4 MHz

80µs 10µs

Code Option × Added a Code Option NRM

EM78P142-V Package EM78P142-U Package

EM78P142

8-Bit Microprocessor with OTP ROM

90 • Product Specification (V1.0) 01.25.2008

(This specification is subject to change without further notice)