NJU3711
- 1 -
Ver.2003-11-18
8-BIT SERIAL TO PARALLEL CONVERTER
GENERAL DESCRIPTION
The NJU3711 is an 8-bit serial to parallel converter
especially applying to MPU outport expander.
The effec tive outport ass ignment of MPU is availa ble
as the connection between NJU3711 and MPU using
only 4 lines.
The serial data synchronizing with 5MHz or more
clock can be input to the serial data input terminal and
the data are output from parallel output buffer through
serial in parallel out shift register and parallel data
latches.
The hysteresis input circuit realizes wide noise
margin and the high drive-ability output buffer (25mA)
can drive LED directly.
FEATURES
8-Bit Serial In Parallel Out
Hysteresis Input 0.5V typ
Operating Voltage 5V±10%
Maximum Operating Frequency 5MHz and more
Output Current 25mA
C-MOS Technology
Package Outline DIP14/DMP14/SSOP14
BLOCK DIAGRAM
PACKAGE OUTLINE
NJU3711M
NJU3711D
NJU3711V
PIN CONFIGURATION
P3 1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
P2
P1
CLR
STB
CLK
DATA
P4
P5
VSS
P6
P7
P8
NJU3711D/M/V
P1
Shift Register
Controller Circuit
Latch Circuit
P2
P3
P7
P8
DAT
A
CL
K
STB
CLR
NJU3711
- 2 - Ver.2003-11-18
TERMINAL DESCRI PTION
No. SYMBOL I/O FUNCTION
1 P3 O
2 P4 O
3 P5 O
Parallel Conversion Data Output Terminals
4 VSS - GND
5 P6 O
6 P7 O
7 P8 O
Parallel Conversion Data Output Terminals
8 DATA I Serial Data Input Terminal
9 CLK I Clock Signal Input Terminal
10 STB I Strobe Signal Input Terminal
11 CLR I Clear Signal Input Terminal
12 P1 O
13 P2 O
Parallel Conversion Data Output Terminals
14 VDD - Power Supply Terminal (4.5 to 5.5V)
NJU3555 NJU3555 NJU3711
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Ver.2003-11-18
FUNCTIONAL DESCRI PTION
(1) Reset
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
output are "L" level.
Normally, the CLR terminal should be "H" level.
(2) Data Transmission
In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
latches.
Even if the STB t er mina l is "L" lev el, the input cloc k signal sh i fts the data in t he shift regist er, theref ore,
the clock signal should be controlled for data order.
Furthermor e, t he 4 input circuits provide a hy st eresi s characteristics usin g t he schmit t t r igger st ruct ure
to protect the noise.
CLK STB CLR OPERATION
X X L
All of latches are reset (the data in t he shift regist er is no change).
All of parallel conversion outputs are "L".
H H
The serial data into the DATA terminal are inputted to t he shift regist er.
In this stage, t he dat a in t he latch is not changed.
L
H The data in the shift register is transferred to the latch. And the data in the
latch is output from the parallel conversion output terminals.
L H
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is also changed in accordance with the shift regist er.
Note 1) X: Don’t care
NJU3711
- 4 - Ver.2003-11-18
TIMING CHART
CL
K
CLR
STB
DATA
P1
P2
P3
P4
P5
P6
P7
P8
NJU3555 NJU3555 NJU3711
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Ver.2003-11-18
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage Range VDD -0.5 ~ +7.0 V
Input Voltage Range VI V
SS-0.5 ~ VDD+0.5 V
Output Voltage Range VO V
SS-0.5 ~ VDD+0.5 V
Output Current IO ±25 mA
VO=7V, VI=0V 20 (max)
Output Short Current
(P1~P8 Terminals) (Note 5) IOSD VO=0V, VI=7V -20 (max) mA
Power Dissipation PD 700 (DIP)
300 (DMP)
300 (SSOP) mW
Operating Temperature Range Topr -25 ~ +85 °C
Storage Temperature Range Tstg -65 ~+150 °C
Note 2) All voltage are relative to VSS=0V reference.
Note 3) Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also
recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause
malfunc tions and impact on the reliability.
Note 4) To stabilize the IC operation, plac e decoupling capacitor between VDD and VSS.
Note 5) VDD=7V, VSS=0V, less t han 1 second per pin.
DC ELECTRICAL CHARACTERISTICS
(VDD=4.5~5.5V, VSS=0V, Ta=25°C, unless otherwise noted)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT
Operating Voltage VDD 4.5 -
5.5
V
Operating Current IDDS V
IH=VDD, VIL=VSS - -
0.1
mA
High-level Input Voltage VIH 0.7VDD - VDD V
Low-level Input Voltage VIL VSS - 0.3VDD V
Input Leakage Current ILI V
I=0~VDD -10 - 10 µA
IOH=-25mA VDD-1.5 - VDD
IOH=-15mA VDD-1.0 - VDD
High-level Output Voltage
(Note 6) VOHD
IOH=-10mA
P1~P8
Terminals VDD-0.5 - VDD
V
IOL=+25mA VSS - 1.5
IOL=+15mA VSS - 0.8
Low-level Output Voltage
(Note 6) VOLD
IOL=+10mA
P1~P8
Terminals VSS - 0.4
V
Note 6) Specified val ue represent output current per pin. When use, total current considerat ion and less than power diss ipation in rati ng
operation shoul d be requi red.
NJU3711
- 6 - Ver.2003-11-18
SWITCHING CHARACTERISTICS
(VDD=4.5~5.5V, VSS=0V, Ta=25°C, unless otherwise noted)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT
Set-Up Time tSD DATA-CLK 20 -
-
ns
Hold Time tHD CLK-DATA 20 - - ns
Set-Up Time tSSTB
STB-CLK 30 - - ns
Hold Time tHSTB
CLK-STB 30 - - ns
tpd PCK CLK-P1~P8 - - 100 ns
tpd PSTB
STB-P1~P8 - - 80 ns
Output Delay Time
tpd PCLR
CLR-P1~P8 - - 80 ns
Maximum Operat i ng Frequency fMAX 5 - - MHz
Note 7) COUT=50pF
NJU3555 NJU3555 NJU3711
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Ver.2003-11-18
SWITCHING CHARACTERISTICS TEST WAVEFORM
fMAX
CL
K
tSSTB
tSD
tHD
tHSTB
DAT
A
STB
CL
K
P1~P8
STB
tpd PCK L
H
P1~P8
tpd PSTB
CL
K
STB
H
P1~P8
tpd PCLR
CLR
DAT
A
NJU3711
- 8 - Ver.2003-11-18
APPLICATION CIRCUIT
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
applicatio n circuits in thi s databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
MPU
NJU3711
DATA
CLK
STB
CLR
P1 P2 P3 P4 P5 P6 P7 P8
