SZESD7361XV2T1G - ON SEMICONDUCTOR

August, 2018 − Rev. 5 1Publication Order Number:

ESD7361/D

ESD7361, SZESD7361

ESD Protection Diode

Low Capacitance ESD Protection Diode

for High Speed Data Line

The ESD7361 Series ESD protection diodes are designed to protect

high speed data lines from ESD. Ultra−low capacitance make this

device an ideal solution for protecting voltage sensitive high speed

data lines.

Features

•Low Capacitance (0.55 pF Max, I/O to GND)

•Protection for the Following IEC Standards:

♦IEC61000−4−2 (ESD): Level 4 ±15 kV Contact

♦IEC61000−4−4 (EFT): 40 A −5/50 ns

♦IEC61000−4−5 (Lightning): 1 A (8/20 ms)

•ISO 10605 (ESD) 330 pF/2 kW ±15 kV Contact

•SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and

PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•Wireless Charger

•Near Field Communications

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit

Operating Junction Temperature Range TJ−55 to +125 °C

Storage Temperature Range Tstg −55 to +150 °C

Lead Solder Temperature −

Maximum (10 Seconds) TL260 °C

IEC 61000−4−2 Contact (ESD)

IEC 61000−4−2 Air (ESD)

ISO 10605 330 pF/2 kW Contact (ESD)

ESD

±15

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

MARKING

DIAGRAMS

PIN CONFIGURATION

AND SCHEMATIC

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X, XX = Specific Device Code

M = Date Code

Cathode 2

Anode

SOD−323

CASE 477

SOD−523

CASE 502

SOD−923

CASE 514AB

27H

27X

2 M

See detailed ordering and shipping information on page 6 o

this data sheet.

ORDERING INFORMATION

ESD7361, SZESD7361

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ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Uni−Directional

IPP

VRWM

VCVBR VF

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage VRWM 5 16 V

Breakdown Voltage VBR IT = 1 mA; pin 1 to pin 2 16.5 V

Reverse Leakage Current IRVRWM = 5.0 V

VRWM = 15 V <1

20 1000

1000 nA

Clamping Voltage (Note 2) VCIPP = 8 A 31 V

Clamping Voltage (Note 2) VCIPP = 16 A 34 V

Junction Capacitance CJVR = 0 V, f = 1 MHz

VR = 0 V, f < 1 GHz 0.55

0.55 pF

Dynamic Resistance RDYN TLP Pulse 0.735 W

Insertion Loss f = 1 MHz

f = 5 GHz 0.01

2dB

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. For test procedure see Figures 9 and 10 and application note AND8307/D.

2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.

TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

Figure 1. Typical IV Characteristics Figure 2. Typical CV Characteristics

1.E−03

1.E−04

1.E−05

1.E−06

1.E−07

1.E−08

1.E−09

1.E−10

1.E−11

1.E−12

1.E−130 5 10 15 20 25 30

VOLTAGE (V)

CURRENT (A)

VBias (V)

CAPACITANCE (pF)

0.8

0.6

0.4

0.2

004814 182 6101216

ESD7361, SZESD7361

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Figure 3. Typical Insertion Loss

ESD7361HT1G (SOD323) Figure 4. Typical Capacitance Over Frequency

ESD7361HT1G (SOD323)

S21 (dB)

FREQUENCY (Hz)

CAPACITANCE (pF)

FREQUENCY (Hz)

1.E+07 1.E+08 1.E+09

1.E+07 5.E+08 1.E+09 2.E+09 2.E+09 3.E+09

Figure 5. Typical Insertion Loss

ESD7361XV2T1G (SOD523) Figure 6. Typical Capacitance Over Frequency

ESD7361XV2T1G (SOD523)

CAPACITANCE (pF)

FREQUENCY (Hz)

S21 (dB)

FREQUENCY (Hz)

1.E+07 1.E+08 1.E+09

1.E+07

Figure 7. Typical Insertion Loss

ESD7361P2T5G (SOD923)

S21 (dB)

FREQUENCY (Hz) Figure 8. Typical Capacitance Over Frequency

ESD7361P2T5G (SOD923)

CURRENT (A)

FREQUENCY (Hz)

0.5

−0.5

−1

−1.5

−2

−2.5

−3

−3.5

−4

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.5

−0.5

−1

−1.5

−2

−2.5

−3

−3.5

−4

1.E+07 1.E+09 2.E+09 3.E+09

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

04.E+09

0.5

−0.5

−1

−1.5

−2

−2.5

−3

−3.5

−4 1.E+08 1.E+09

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1.E+07 1.E+09 2.E+09 3.E+09 4.E+09

ESD7361, SZESD7361

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IEC 61000−4−2 Spec.

Level Test Volt-

age (kV)

First Peak

Current

(A) Current at

30 ns (A) Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 W aveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 9. IEC61000−4−2 Spec

Figure 10. Diagram of ESD Clamping Voltage Test Setup

50 W

Cable

Device

Under

Test Oscilloscope

ESD Gun

50 W

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

ESD7361, SZESD7361

www.onsemi.com

Figure 11. Positive TLP I−V Curve Figure 12. Negative TLP I−V Curve

TLP CURRENT (A)

VC, VOLTAGE (V)

040353051015 2520

TLP CURRENT (A)

VC, VOLTAGE (V)

−25

0 −14−12−10−2 −4 −6 −8

NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage

stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description

below for more information.

−20

−15

−10

−5

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 13. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 14 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels.

Figure 13. Simplified Schematic of a Typical TLP

System

DUT

LS÷

Oscilloscope

Attenuator

10 MW

50 W Coax

Cable

50 W Coax

Cable

Figure 14. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

ESD7361, SZESD7361

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ORDERING INFORMATION

Device Package Shipping†

ESD7361HT1G SOD−323

(Pb−Free) 3000 / Tape & Reel

SZESD7361HT1G*

ESD7361XV2T1G

SOD−523

(Pb−Free)

3000 / Tape & Reel

SZESD7361XV2T1G*

ESD7361XV2T5G 8000 / Tape & Reel

SZESD7361XV2T5G*

ESD7361P2T5G SOD−923

(Pb−Free) 8000 / Tape & Reel

SZESD7361P2T5G*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP

Capable.

ESD7361, SZESD7361

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PACKAGE DIMENSIONS

SOD−323

CASE 477−02

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. LEAD THICKNESS SPECIFIED PER L/F DRAWING

WITH SOLDER PLATING.

4. DIMENSIONS A AND B DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

5. DIMENSION L IS MEASURED FROM END OF RADIUS.

NOTE 3

12bE

CNOTE 5

DIM MIN NOM MAX

MILLIMETERS

A0.80 0.90 1.00

A1 0.00 0.05 0.10

A3 0.15 REF

b0.25 0.32 0.4

C0.089 0.12 0.177

D1.60 1.70 1.80

E1.15 1.25 1.35

0.08

2.30 2.50 2.70

0.031 0.035 0.040

0.000 0.002 0.004

0.006 REF

0.010 0.012 0.016

0.003 0.005 0.007

0.062 0.066 0.070

0.045 0.049 0.053

0.003

0.090 0.098 0.105

MIN NOM MAX

INCHES

1.60

0.063

0.63

0.025 0.83

0.033

2.85

0.112

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ESD7361, SZESD7361

www.onsemi.com

PACKAGE DIMENSIONS

SOD−523

CASE 502

ISSUE E

NOTES:

6. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

7. CONTROLLING DIMENSION: MILLIMETERS.

8. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.

MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF

BASE MATERIAL.

9. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-

TRUSIONS, OR GATE BURRS.

D−X−

−Y−

0.08 X Y

DIM MIN NOM MAX

MILLIMETERS

D1.10 1.20 1.30

E0.70 0.80 0.90

A0.50 0.60 0.70

b0.25 0.30 0.35

c0.07 0.14 0.20

L0.30 REF

H1.50 1.60 1.70

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

RECOMMENDED

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.48 0.40

1.80

DIMENSION: MILLIMETERS

PACKAGE

OUTLINE

L2 0.15 0.20 0.25

ESD7361, SZESD7361

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PACKAGE DIMENSIONS

SOD−923

CASE 514AB

ISSUE C

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.

MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF

BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-

TRUSIONS, OR GATE BURRS.

DIM MIN NOM MAX

MILLIMETERS

A0.34 0.37 0.40

b0.15 0.20 0.25

c0.07 0.12 0.17

D0.75 0.80 0.85

E0.55 0.60 0.65

0.95 1.00 1.05

L0.19 REF

0.013 0.015 0.016

0.006 0.008 0.010

0.003 0.005 0.007

0.030 0.031 0.033

0.022 0.024 0.026

0.037 0.039 0.041

0.007 REF

MIN NOM MAX

INCHES

−Y−

−X−

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

See Application Note AND8455/D for more mounting details

1.20 2X

0.25

0.36

PACKAGE

OUTLINE

b2X

0.08 XY TOP VIEW

SIDE VIEW

BOTTOM VIEW

L2 0.05 0.10 0.15 0.002 0.004 0.006

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ESD7361/D

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